Assignment – 2

Topics – Differential Amplifiers, Operational Amplifiers, and Noise

1. Find the voltage gain Av given that vin1 and vin2 are anti-symmetric.
2. The circuit is symmetric and the inputs are anti-symmetric. Find Av.
3. The circuit is symmetric and the inputs are anti-symmetric. Find Av.
4. A MOS differential pair is driven with an input common mode of 1.6V, if Iss=0.5mA, Vth=0.5V
and VDD=1.8V, what is the maximum allowed load resistance?
5. Design an NMOS differential pair for a voltage gain of 5 and a power budget of 2mW subject
to the condition that the stage following the differential pair requires at least an input common
𝜇𝐴
mode level of 1.6V. Assume 𝜇𝑛 Cox = 100 𝑉2 and VDD =1.8V.
6. 6. Design an NMOS differential pair for a power budget of 3mW and
𝜇𝐴
(∆Vin)max = 500mV. Assume 𝜇𝑛 Cox = 100 𝑉2 and VDD =1.8V.

7. Calculate the differential voltage gain Av. Assume inputs are anti-symmetric.

8. Calculate the differential voltage gain Av. Assume inputs are anti-symmetric.
9. Find the differential gain and CMRR of the following circuit.
 𝜇𝐴
10. An active loaded MOS differential pair with (W/L)n = 100 and (W/L)p = 200, 𝜇𝑛 Cox = 200 𝑉2
,
𝜇𝐴
𝜇𝑝 Cox = 200 𝑉2, VAN = |VAP| = 20V (Early voltage), ISS = 0.8mA, Rss = 25kΩ. Calculate Gm, Rout,
Ad, ACM, CMRR.
11. Calculate the input common-mode voltage range and the closed-loop output impedance of the
unity-gain buffer depicted in the below Fig. (Given - If each device (including the current source)
has a threshold voltage of 0.3 V and an overdrive of 0.1 V).

12. Design a fully differential telescopic op amp with the following specifications: VDD = 3 V, peak-
to-peak differential output swing = 3V, power dissipation = 10 mW, voltage gain = 2000. Assume
that μnCox=60 μA/V2, μpCox = 30μA/V2, λn = 0.1V−1, λp = 0.2V−1 (for an effective channel
length of 0.5μm), γ = 0, and VTHN = |VTHP| = 0.7V.
13. Determine the resistance seen at the source of M2 in the below Fig. if γ = 0
14. Calculate the small-signal differential voltage gain Av for the n-channel input, differential amplifier
when ISS = 50 µA, Kn=110 µA/V2, Kp=50 µA/V2 and W1/L1 = W2/L2 = W3/L3 = W4/L4= 2, λn=0.04,
λp=0.05. Assuming that all channel lengths are equal and have a value of 1 µm.
15. Design an NMOS differential pair for a power budget of 3mW and 𝛥𝑣𝑖𝑛𝑚𝑎𝑥 = 500mV. Assume 𝜇𝑛𝐶𝑜𝑥
𝜇𝐴
= 100 𝑉2 , 𝑉𝐷𝐷 = 1.8𝑉.
Repeated problem 6.

16. Given that for an op-amp the gain is 103, the slew rate is 1.5V/μsec. Input is 5×10-3sinωt, calculate
maximum frequency to prevent distortion.
17. Calculate Δ VBE in the circuit, where Q2 is formed as the parallel combination of m units, each
identical to Q1.

18. Due to a manufacturing error, in the circuit, M2 is twice as wide as M1. Calculate the small-signal gain
if the dc levels of Vin1 and Vin2 are equal.
19. For a differential amplifier ISS = 10 µA, Kn=110 µA/V, Kp=50 µA/V and W1/L1 = W2/L2 = W3/L3=
W4/L4 = 8 , λn=0.04, λp=0.05,CL=100pF Find Slew rate.

20. Assume that VDD=4V, VSS= 0, and Vtp=-0.85, Vtn=0.55 to calculate the ICMR of the
circuit given in Question 14. Assume that ISS is 100 µA, W1/L1 = W2/L2= 5 , W3/L3=
W4/L4 = 1, and VDSS(sat) = 0.2 V. µnCox = 90 µA/V, µpCox = 45 µA/V.
21. A NMOS differential pair is biased by a current source of I = 0.2 mA having an output
resistance RSS=100 kΩ. The amplifier has drain resistance RD = 10 kΩ, using transistors with
kn’W/L = 3mA/V2 , and ro that is large . If the output is taken differentially and there is a
1% mismatch between the drain resistances, find the CMRR.
22. In the circuit shown below, transistors Q1 and Q2 have Vth = 1V, and the process
transconductance parameter kn’ = 100 μA/V2 , (W/L)1 = (W/L)2 = 20. Assuming λ = 0, find
V1, V2.

23. Due to a manufacturing error, M2 is twice as wide as M1. What will be the small-signal gain
if the dc levels of Vin1 and Vin2 are equal.
 Repeated problem 18.

24. The circuit of Fig given below uses a resistor rather than a current source to define a tail current
of 1 mA. Assume that (W/L)1,2 = 25/0.5, μnCox = 50 μA/V2, Vth = 0.6V, λ = γ = 0, and VDD
= 3V. What is the required input CM voltage for which RSS sustains 0.5 V?
25. Calculate RD for a differential gain of 5. In the given circuit at Question no. 24.
26. What happens at the output if the input CM level is 50 mV higher than the value calculated in
Q. 24?

27. In the circuit of Fig. given below, assume that ISS = 1mA and W/L = 50/0.5 for all the transistors.
Determine the voltage gain. Given VDD=3V, vth= 0.6V, µpCox= 25µA/V2 , ,µnCox= 50µA/V2
and lambda = 0.01.
28. Calculate Vb such that ID5 = ID6 = 0.8(ISS/2) as given in the circuit of Question no. 27.
given that VDD=3V, vth= 0.6V, µpCox= 25µA/V2, µnCox= 50µA/V2

29. In this circuit given below having (W/L)1−4 = 50/0.5 and ISS = 1 mA. What is the small-signal
differential gain?
30. For Vin, CM = 1.5 V, what is the maximum allowable output voltage swing? For the circuit
given in Question no. 29.

31. In the given Fig in Question no. 27, assume that M5 and M6 have a small threshold voltage
mismatch of V and ISS has an output impedance RSS. Calculate the CMRR.
32. For the two-stage Op-amp shown below, find W1/L1, W6/L6, and Cc if GB = 6.28 MHz, non-
dominant pole = 5 MHz, zero = 3 MHz and CL = C2 = 20 pF, Kn=110 µA/V2, Kp=50 µA/V2
and consider only the two-pole model of the Op-amp. The bias current in M5 is 40 µA and in
M7 is 320 µA.
33. Design the currents and W/L values of the current-mirror load
differential amplifier to satisfy the following specifications: VDD=
-VSS =2.5 V, SR ≥10 V/µs (CL =5 pF), f-3 dB = 100 kHz, a small-signal
differential voltage gain of 100 V/V, -2.5 ≤ ICMR ≤ 2 V, and Pdiss ≤
1 mW. Use the model parameters of KN = 110 µA/V2 , KP = 50 µA/V2 , VTN =
0.7 V, VTP = -0.7 V, λn=0.04V-1, λp=0.05V-1.
34. Suppose in the circuit shown below, (W/L)1,2 = 50/0.5 and ID1 = |ID2| = 0.5 mA, T=300K,
KN = 134 µA/V2 , KP = 38 µA/V2 What is the input-referred thermal noise voltage?
35. For the amplifier shown below, assume that all transconductances are equal. Find (a) the
equivalent input noise voltage in units of V2/Hz considering only Thermal noise. (b) the
equivalent input noise voltage in units of V2/Hz considering only 1/f noise [Here,
mean square 1/f noise voltage per unit bandwidth = BN,P/ (WLf) ; BN =
8x10-22 (V-m)2 and BP = 2x10-22 (V-m)2], and (c) the noise corner
frequency in Hz. Using, ∫𝑎 𝑓 𝑑𝑓, find the rms noise voltage in a bandwidth of 1Hz to
100kHz in V(rms).
36. Explain the operation of a Folded Cascode differential amplifier with a suitable circuit diagram.
Draw the small signal model and find Rout (output impedance), DC voltage gain, output voltage
swing and location of poles and zeroes?
37. Design a Miller compensated, two-stage Operational amplifier using the model parameters
shown in Table 1. Assume minimum channel length as 1 µm, load capacitance of 10 pF and
supply voltage of 5 V. Determine W, L for all devices and the value of compensation capacitor
(Cc) for the following specifications:

Open loop gain > 60 dB

Phase Margin > 60°
Gain Bandwidth Product > 10 MHz
Static power dissipation < 5mW
Slew rate > 25 V/µs
VDD=5V, Vss=0V
ICMR: 1.5 V to 4.5 V
Qutput voltage swing: 0.5 V to 4.5 V
38. What is KT/C noise? Derive the expression of total output thermal noise in a PMOS current
source load common source amplifier driving a load capacitance, CL?

39. Calculate the equivalent noise voltage of two parallel resistors R1 and R2.
40. A transistor of width W is laid out with one gate finger and exhibits a total gate resistance of R G [Fig.
(a)]. Now, we reconfigure the device into four equal gate fingers[Fig. (b)]. Determine the total gate
resistance thermal noise spectrum of the new structure.