HDL

(Hardware Description Language)

Presented by:
Ms.Sejal Rathod
Masters of Engineering,
Electronics & Communication
BINARY TO GREY
Xor gate entity arechitecture……
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY bin2grey IS
PORT (bin : IN std_logic_vector(3 DOWNTO 0);
grey : OUT std_logic_vector(3 DOWNTO 0));
END bin2grey;

ARCHITECTURE exam OF bin2grey IS

BEGIN
WITH bin SELECT
grey <= "0000" WHEN "0000",
"0001" WHEN "0001",
"0011" WHEN "0010",
"0010" WHEN "0011",
"0110" WHEN "0100",
"0111" WHEN "0101",
"0101" WHEN "0110",
"0100" WHEN "0111",
"1100" WHEN "1000",
"1101" WHEN "1001",
"1111" WHEN "1010",
"1110" WHEN "1011",
"1010" WHEN "1100",
"1011" WHEN "1101",
"1001" WHEN "1110",
"1000" WHEN OTHERS;
END exam;
GREY TO BINARY
ACTIVE LOW OUTPUT DECODER
 HDL Models of Combinational Circuits
Verilog (Dataflow: Two-to-Four Line Decoder)
// Dataflow description of two-to-four-line decoder
// Note: The figure uses symbol E, but the
// Verilog model uses enable to clearly indicate functionality.

module decoder_2x4_df ( output [0: 3] D,input A, B,enable);

assign D[0] = !((!A) && (!B) && (!enable)),

D[1] = !((!A) && B && (!enable)),
D[2] = !((A) && (! B) && (!enable)),
D[3] = !(A && B && (!enable));
endmodule
 HDL Models of Combinational Circuits
Gate Level Modelling
Two-to-Four-Line Decoder
// Gate-level description of two-to-four-line decoder In the Verilog model three not gates
// Refer to Fig. with symbol E replaced by enable, for clarity. produce the complement of the inputs,
module decoder_2x4_gates (D, A, B, enable); and four nand gates provide the outputs
output [0: 3] D; for the bits of D.
input A, B; Remember that the output is always
input enable; listed first in the port list of a primitive,
wire A_not, B_not, enable_not; followed by the inputs.
not
G1 (A_not, A), // Comma-separated list of primitives
G2 (B_not, B),
Note that the keywords not and nand are
G3 (enable_not, enable);
written only once and do not have to be
nand repeated for each instance of the nand gate,
G4 (D[0], A_not, B_not, enable_not), but commas must be inserted at the end of
G5 (D[1], A_not, B, enable_not), each instantiation of the gates in the series,
except for the last statement, which must be
G6 (D[2], A, B_not, enable_not),
terminated by a semicolon.
G7 (D[3], A, B, enable_not); The wire declaration is for internal
endmodule connections.

assign D[0] = !((!A) && (!B) && (!enable));

 HDL Models of Combinational Circuits

VHDL (Dataflow: Two-to-Four Line Decoder)

-- Dataflow description of two-to-four-line decoder. Note: The figure uses
-- symbol E, but the VHDL model uses enable to clearly indicate functionality.
entity decoder_2x4_df_vhdl is
port (D: out Std_Logic_Vector (3 downto 0); A, B, enable: in Std_Logic);
end decoder_2x4_df_vhdl;
Architecture Dataflow of decoder_2x4_df_vhdl is
begin
D(0) <= not ((not A) and (not B) and (not enable));
D(1) <= not (not A) and B and not (enable);
D(2) <= not (A and (not B) and (not enable));
D(3) <= not (A and B and (not enable));
end Dataflow;
 HDL Models of Combinational Circuits
Gate Level Modelling Two-to-Four-Line Decoder
library ieee; VHDL entity decoder_2x4_gates_vhdl is
use ieee.std_logic_1164.all; port (A, B, enable: in std_logic;
D: out std_logic_vector (3 down to 0);
-- Model for inverter component end decoder_2x4_gates_vhdl;
entity inv_gate is
architecture Structure of decoder_2x4_gates_vhdl is
port (B: out std_logic; A: in std_logic);
component inv_gate
end inv_gate;
port (B: out std_logic; A: in std_logic);
architecture Boolean_Equation of inv_gate is
end component;
begin
component nand3_gate
B <= not A;
port (D: out std_logic; A, B, C: in std_logic);
end Boolean_Equation;
end component;
entity nand3_gate is
signal A_not, B_not, enable_not; -- Internal signals
port (D: out std_logic; A, B, C: in std_logic);
begin -- Instantiate components and connect ports via port maps
end nand3_gate;
G1: inv_gate port map (A_not, A);
architecture Boolean_Eq of nand2_gate
G2: inv_gate port map (B_not, B);
begin
G3: inv_gate port map (enable_not, enable);
C <= not (A and B and C); G4: nand3_gate port map (D(0), A_not, B_not, enable_not);
end Boolean_Eq; G5: nand3_gate port map (D(1), A_not, B, enable_not);
G6: nand3_gate port map (D(2), A, B_not, enable_not);
G7: nand3_gate port map (D(3), A, B, enable_not);
end Structure
8x3 priority
ENCODER
// Code your design here
module priorityenoder83_dataflow(en,i,y);
// declare port list via input and output
input en;
input [7:0]i;
output [2:0]y;

// check the logic diagram and assign the

outputs
assign y[2]=i[4] | i[5] | i[6] | i[7] &en;
assign y[1]=i[2] | i[3] | i[6] | i[7] &en;
assign y[0]=i[1] | i[3] | i[5] | i[7] &en;

endmodule
// Code your testbench // since en and i are input values,
module tb; en=1;i=128;#5
reg en; en=1;i=64;#5
reg [7:0]i; en=1;i=32;#5
wire [2:0]y; en=1;i=16;#5
en=1;i=8;#5
// instantiate the model: creating en=1;i=4;#5
priorityenoder83_dataflow dut(en,i,y); en=1;i=2;#5
initial en=1;i=1;#5
begin en=0;i=8'bx;#5
$dumpfile("dump.vcd");$dumpvars(1); $finish;
$monitor("en=%b i=%b y=%b",en,i,y); end
endmodule
VHDL (Dataflow: Four-Bit Adder)
-- Dataflow description of four-bit adder

entity binary_adder is
port (Sum: out Std_Logic_Vector (3 downto 0);
C_out: out Std_Logic; A, B: in Std_Logic_Vector (3 downto 0); C_in: in Std_Logic);
end binary_adder;

architecture Dataflow of binary_adder is

begin
C_out & Sum <= A + B + ('000' & C_in); -- Compatible word sizes
end Dataflow;
 VHDL Code for 4-bit full adder/ 4 bit Ripple Carry Adder
library ieee;
use ieee.std_logic_1164.all;
entity Full_Adder_vhdl_code is
port( A,B, Cin : in std_logic;
s, Cout : out std_logic);
end Full_Adder_vhdl_code;
architecture bhv of Full_Adder is
begin
sum <= (X xor Y) xor Cin;
Cout <= (X and (Y or Cin)) or (Cin and Y);
end bhv;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ripple_Adder is
Port ( A,B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC; Cout : out STD_LOGIC;
S : out STD_LOGIC_VECTOR (3 downto 0)
);
end Ripple_Adder;
architecture Behavioral of Ripple_Adder is
-- Full Adder VHDL Code Component Decalaration
component full_adder_vhdl_code
Port ( A,B,Cin : in STD_LOGIC;
S,cout : out STD_LOGIC);
end component;
-- Intermediate Carry declaration
signal c1,c2,c3: STD_LOGIC;
begin
-- Port Mapping Full Adder 4 times
FA1: full_adder_vhdl_code
port map( A(0), B(0), Cin, S(0), c1);
FA2: full_adder_vhdl_code
port map( A(1), B(1), c1, S(1), c2);
FA3: full_adder_vhdl_code
port map( A(2), B(2), c2, S(2), c3);
FA4: full_adder_vhdl_code
port map( A(3), B(3), c3, S(3), Cout);
end Behavioral;