Candidate Name DUNNA SRIKANTH

DOB 03/01/1997
Total Experience 1.9
Relevant Experience 1.9 (Skills- PV Engineer)
Current Location Hyderabad, 500075
Preferred Location Hyderabad
Bench Profile/ Market (If Market Notice Period) Bench – Avail Imm.
Current Company Capgemini India
Current Client / Project Intel
Primary Skill (Hands on Experience) Having Experty in Physical Verification, worked multiple blocks, for
signoff LV clean-up and strong experience in Intel 7nm 22nm and
TSMC N6/3 LV flows and worked on LV flows for Implementing
Functional ECOs and Timing Closure ECOs (Setup & Hold Timing
Violation fixing, Net Improvement, Net degradation, Cell Swaps,
upsizing/downsizing cells, RV and Calibre Fix's) using Synopsys IC
Compiler & IC Validator
Tools: ICC2,ICV,IC workbench,
Technology: Intel 7nm 22nm and TSMC N6/N3 nodes
Additional Skills
Worked at QC before No
Education & Certification B-Tech - Gokaraju Rangaraju Institute of Engineering under JNTUH &
PD Certificate SumedhaIT
Any additional Comments for candidate (Relevant exp within the Intel 7nm,22nm Tsmc 3nm 6nm : worked for all LV/PV flows which
industry) include LVS , Density fixes , Antenna fixes, ECO implementation and
all other LV Bundle flows, Synopsys, DRV

1|P age
 CURRICULUM VITAE
DUNNA SRIKANTH
EMPLOYEE ID: 46210827

SUMMARY
 Overall 1 years 9 months of experience in Physical verification with Intel

HIGHLIGHTS  Intel 7nm 22nm, Tsmc 3nm 6nm : worked for all LV/PV flows which include LVS ,
Density fixes , Antenna fixes, ECO implementation and all other LV Bundle flows,
Synopsys, Calibre/DRV

SKILLS AND
COMPETENCIES

Current Role PHYSICAL VERIFICATION ENGINEEER(ASSOCIATE )

Domain Experience
1.9 years of Physical Verification Engineer.
Areas

Skills
 Implemented EC0’s(Size cells , Buffer addition , net improvements etc.)
 Good hands on experience in fixing all PV flows
 Fixed violations related to IR and cross talk
 Proficient in tools like ICC II, ICV – synposys tools
 Good Knowledge on PD Flow and IC Fabrication Process
 Implentation of Setup and Hold fixes.

2|P age
EMPLOYMENT
HISTORY

Since 24th July, 2021 to ALTRAN/CAPGEMINI – Consultant – PV Engineer

Present  Physical Verification Engineer

ACHIEVEMENTS/
AWARDS/
PUBLICATIONS

 Multiple Appreciations in recognition of Dedication,Passion and Hard

work in Intel_PVCOE projecs.

EDUCATION

Year BACHELORS OF TECHNOLOGY (ELECTRICAL AND ELECTRONICS

ENGINEERING , GRIET ,JNTUH 2020

PROJECT
EXPERIENCE

Project Title ARLC N3

3|P age
 Project Timeline Sep 2022 – Present (9 months)
Technology Nodes TSMC 3nm
Role Worked as a physical verification Engineer
Responsibilities  Cleaned PV flows like DRC, LVS, Extraction, hold and setup fixes, ECOs (Timing
and RV Checks), PMJ checks, dfi_integra , Density and Antenna violations (Critical
blocks)

Key skills/Tools Synopsys IC Compiler, IC Validator, IC workbench

Project Title MTLSOC

Project Timeline July 2022 - Aug 2022 ( 2 months)
Technology Nodes TSMC 6nm
Role Worked as a physical verification Engineer
Responsibilities  LV quality Reviews, Cleaned PV flows like DRC, LVS, Extraction, hold and setup
fixes, ECOs (Timing and RV Checks), PMJ checks, dfi_integra , Density and
Antenna violations (Critical blocks)

Key skills/Tools Cadence Innovus, Calibre, Synopsys IC Compiler, IC Validator, IC workbench

Project Title MTLB A0

Project Timeline April 2022 - June 2022 ( 3 months)
Technology Nodes TSMC 22nm
Role Worked as a physical verification Engineer
Responsibilities  Power layout, Cleaned PV flows like DRC, LVS,MIM generation
Key skills/Tools Synopsys IC Compiler, IC Validator, IC workbench

Project Title MTLC P0/R0/J0/S0

Project Timeline Nov 2021 -Jan 2022 (3 months)
Technology Nodes Intel 7nm
Role Worked as a physical verification Engineer
Responsibilities  LV quality Reviews, Cleaned PV flows like DRC, LVS, Extraction, hold and setup
fixes, ECOs (Timing and RV Checks), PMJ checks, dfi_integra , Density and
Antenna violations (Critical blocks)

4|P age
 Key skills/Tools Synopsys IC Compiler, IC Validator, IC workbench

LANGUAGES

Speak ENGLISH , TELUGU, HINDI

Read ENGLISH,TELUGU, HINDI

Write ENGLISH,TELUGU, HINDI

5|P age