The Islamia University of Bahawalpur

Department of Electronic Engineering

Complex Engineering Problem

Course: Digital System Design – ES423 Instructor: Dr. Abid Munir

BSc. Electronic Engineering, Session 2021-2025 Max. Marks: 20

6th Semester (Spring-2024) Submission deadline: 1 Week before Final exams

Submission guidelines:
a) Implementation on Xilinx FPGA trainer.
b) Submission will be group-wise.
c) IUB plagiarism policy will be observed for the CEP report.

Design a vending machine for a supermarket with cash receipt and return of remaining amounts
after dispensing the desired products. Implement on Xilinx FPGA.

1. Problem Statement:

“Vending Machines are one of practical scenarios where the concepts of Finite state machines can be used for
solving the real engineering problems. Vending Machine assigned for this task is required to process inputs of
currency, inputs from keyboard to indicate the options and deliver the selected product along with dispensing the
remaining amounts”.

2. Project Objectives:

a) Design of a Finite State Machine to perform the task of a vending machine

b) Develop the synthesizable HDL code
c) Analyze the synthesized circuit in simulator
d) Implementation on FPGA
3. Background and Getting Knowledge of:
Sequential logic circuits are key components for development of solutions to address real engineering
problems. The concept of Finite State Machines helps to translate the requirement of project into state diagrams
followed by the design steps required for gate level manifestation of the required circuit. We can use HDL to
program the FSM which subsequently translated into RTL for implementation on an FPGA. This project
requires design skills, HDL programming and implementation on FPGA. This project can be approached using
following steps:

- Design a state diagram to represent a vending machine

- Develop its HDL description
- Test and synthesize the code for FPGA
- Implement the solution on FPGA development board
4. Justification of CEP attributes

Complex Problems
Sr. Complex Problems Description
Definitions
a. In depth knowledge of sequential logic circuits and Finite State
Depth of Knowledge Required Machines. ( WK4,WK5)
1
(WP1) b. Knowledge HDL and simulation ( WK2)
c. Knowledge of handling the FPGA development Board (WK6)
 Range of conflicting a. There are various possible conceptual models from input to display.
2.
requirements (WP2) b. There are different HDL coding options to implement the FSM.

a. Analysis of the problem statement to determine the design

Depth of Analysis Required parameter
3.
(WP3) b. Analysis of state diagram to seek optimal design.
c. Analysis of RTL to find optimum implementation on FPGA.

a. Analysis of problem statement, design parameters and

4. Interdependence (WP7)
implementation are interdependent.

5. Outcomes and mapping with PLOs

CLOs Description Domain PLOs

Analyze and troubleshoot digital systems by identifying issues in
CLO1 circuit diagrams, timing diagrams, or HDL code C4 2

Design custom digital systems for specific applications,

incorporating advanced components and optimizing
CLO2 C6 3
performance.

To use/operate modern tools of Xilinx / cadence for development and

CLO6 P5 5
testing of digital systems.

To communicate effectively about laboratory work in written and

CLO7 P4 10
document the laboratory procedures.

To apply engineering principles to manage the semester project from the

CLO9 A4 11
area of embedded system.

6. Deliverables

Final deliverables are as follows;

a) Implementation on FPGA board
b) Report
c) Power point presentation

---------------------------------------------
Acronyms:
WPs: Attributes for CEP in OBE
WKs: Attributes for Knowledge profiles in OBE
WK2: Mathematics, Numerical Analysis, Statistics, Computer & Information Science
WK4: Engineering Specialist Knowledge
WK5: Engineering Design
WK6: Engineering Practice