Yang 2020

This article has been accepted for publication in a future issue of this journal, but has not been
fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2020.2986804, IEEE Journal
of Emerging and Selected Topics in Power Electronics
IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE
A Low-Loss Z-Source Circuit Breaker for LVDC

Systems
Yachao Yang, Chun Huang
Abstract—Conventional bidirectional Z-source circuit an unfavorable factor in such case. In order to overcome the
breakers (Bi-ZSBs) require at least two semiconductor tubes to limitations of the traditional DCCBs, a new solid-state circuit
be turned on during normal operation, which is typical a series breaker called Z-source circuit breaker (ZSB) is designed and
connection of a thyristor (SCR) and a power diode. The introduced in [6, 7], which has many advantages, such as small
conduction loss of the semiconductor tube is not negligible in the size, low cost, strong over-current capability and so on [8]. The
case of dc high power, since it is approximately proportional to
the current flowing through the semiconductor tube. Therefore,
ZSB is mainly composed of thyristors and an LC resonance
this paper presents a new low-loss Z-source circuit breaker for circuit, and it can actively cut off the main circuit current
LVDC Systems. In normal operation, the proposed topology has through the LC resonance circuit in the fault transient [9]. At
only one thyristor turned on, so it further reduces the conduction present, the ZSB is mainly divided into two types, namely
loss of the Bi-ZSB compared to the conventional Bi-ZSBs. In unidirectional Z-source circuit breaker (Uni-ZSB) and
addition, the proposed topology uses a coupled inductor with two bidirectional Z-source circuit breaker (Bi-ZSB).
windings, which has the characteristics of simple structure, small Generally, the Uni-ZSB has three structures, that is, cross
volume, common ground and so on. The working principle and structure, parallel structure and series structure. In [10], a ZSB
power loss of the proposed topology is analyzed in detail, and the
with cross-connection structure is proposed, which can quickly
circuit design is given. Finally, the performance of the proposed
topology is verified by MATLAB simulation and hardware
cut off the fault current, but it has the problem that the power
experiment. supply and load do not share the ground, which is not
applicable to the dc system that requires common ground. In
Index Terms—Low loss circuit breaker, Z-source circuit breaker, [11], a parallel ZSB with common ground characteristics is
coupled inductor, fault current limiting. proposed. However, the parallel ZSB will reflect a large fault
current on the power supply side during the fault. To overcome
the problems mentioned above, a modified ZSB in series is
I. INTRODUCTION1 proposed in [12], but its loss is still high. In addition, the ZSBs
mentioned above adopt separate inductors in LC resonance
I N recent years, with the in-depth development of new energy
and the development of power electronics technology, dc
part, so their volume is large and cost is high. Therefore,
references [13, 14] use the coupled inductor instead of the
power system has become a hot research topic, such as dc
separate inductor to improve the performance of the ZSB,
transmission system, dc distribution network and dc microgrid
including simplifying the structure, reducing the cost and
[1]. In addition, it is also the development direction of future
volume of the ZSB, and so on. In DC microgrid or distribution
power system. Compared with ac system, dc system has many
network, the Uni-ZSB is restricted for such occasions due to
advantages [2]. However, there is no natural zero crossing
that the energy needs flow in both directions.
characteristic of dc current, which is a big challenge for dc
The Bi-ZSB can overcome the shortcoming of the Uni-ZSB,
circuit breaker (DCCB) to realize fast tripping. Therefore,
and realize bi-direction flow of energy, so it has a good
research on DCCB has important engineering value and
application prospect in the field of DC microgrid or
application prospects [3].
distribution network. In [15], a Bi-ZSB is proposed, but it is
Conventional DCCBs with full-controlled semiconductor,
still non-common ground between the power supply and the
such as IGBT, IGCT, etc., have no fault detection capability,
load, while its cost is high. Two new kinds of Bi-ZSB are
and they can be only passively tripped by an external trigger
proposed in [16], i.e. separate-inductor-based Bi-ZSB and
signal [4, 5]. When a short-circuit fault occurs, due to the
coupled-inductor-based Bi-ZSB. In order to reduce the number
inherent response time of the detection system and DCCB, the
of the separate inductors, references [17, 18] simplify the
converter and DCCB may still have to bear a large fault current,
design of the Bi-ZSB proposed in [16], using only two separate
which may cause damage to dc equipment. Therefore, the
inductors in LC resonance part, which greatly reduces the
conventional DCCBs with full-controlled semiconductor have
volume and weight of the Bi-ZSB. Similarly, in order to reduce
the number of the coupled inductor, reference [19] uses a
This work was supported by National Natural Science Foundation of China three-winding coupled inductor instead of two independent
under Grant 51677060. coupled inductors in [16] to further optimize the structure of
Yachao Yang is with the College of Electrical and Information Engineering, the Bi-ZSB. At present, the research on the Bi-ZSB has made
Hunan University, Changsha, China (e-mail: yachaoyang@foxmail.com). some progress by peers. Each of them has its own advantages
Chun Huang is with the College of Electrical and Information Engineering,
Hunan University, Changsha, China (e-mail: yellowpure@hotmail.com, and drawbacks in certain aspects. However, it is important to
Corresponding Author). note that the conduction losses of the Bi-ZSB are rarely
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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/JESTPE.2020.2986804, IEEE Journal
considered in existing references [20, 21]. Moreover, it also consists of four thyristors SCR1~SCR4, a coupled inductor
has some other problems, such as low utilization rate of the with two coils L1 and L2, a capacitor C, a current limiting
coupled coil, many windings and so on. resistor R1 and RD snubber circuits. M is the mutual
This paper presents a low-loss Z-source circuit breaker for inductance of the coupled inductor. In normal operation, the
LVDC systems. The proposed topology can realize conduction loss of the proposed topology is only the loss of the
bidirectional energy flow and cut off the fault current quickly SCR1 or SCR3. The capacitor C, the SCR2 and SCR4, and the
during the fault. In normal operation, only one thyristor of the coupled inductor constitute LC resonance circuit. In addition,
proposed topology flows through the load current, which the current limiting resistor R1 only provides a charging path
greatly reduces the conduction loss, improves the efficiency for the capacitor C in the initial stage of power on, and its
and power density of the Bi-ZSB. In addition, the proposed power loss is very low.
topology uses a coupled inductor with two windings in the LC
resonance part, so it improves the utilization ratio of the SCR SCR
+
coupled coil and reduces the volume of the Bi-ZSB. In this
C1 C2
paper, we briefly analyze the conduction losses associated with RL
these Bi-ZSBs and give a qualitative comparison between
them in many aspects. The performance of the Bi-ZSB is _
SCR SCR
verified by MATLAB simulation and hardware experiment.
(a)
The remainder of this paper is organized as follows. In the
Section II, existing topologies, the proposed topology and their L1
D1
comparison are introduced. Then in the Section III, the LL
D3
operation principle of the proposed topology is analyzed in SCR

+
detailed. The proposed topology is tested on a hardware D2
C1
D4
experiment platform in the Section IV. In the end, Section V is L2
CL RL
the conclusion of this paper.
_ C2
II. EXISTING TOPOLOGIES, PROPOSED TOPOLOGY AND THEIR
(b)
COMPARISON C1
L1 L2
A. Existing Topologies of the Bi-ZSB SCR1 SCR2
+
The Bi-ZSB can be obtained by modifying the structure of D1 D2
the Uni-ZSB. Therefore, the Bi-ZSB uses approximately twice C2
C0 CL RL
as many components as the Uni-ZSB. Generally, the Uni-ZSB
needs one semiconductor tube to be turned on during normal _
operation, whereas the Bi-ZSB requires at least two
(c)
semiconductor tubes to be turned on in the existing topologies. D2 D1
We only consider the Bi-ZSB in this paper. The existing
topologies of the Bi-ZSB are shown in Fig. 1. + SCR1 L1 L3 SCR2
In Fig. 1(a), the topology has a high conduction loss, and it L2
also has many disadvantages, such as non-common ground, RL
large number of components, and so on. The topology shown C
in Fig. 1(b) inserts one thyristor and two inductors in the _
middle of the rectifier bridge, so it greatly reduces the number (d)

of the thyristor and is simple to control, but the topology Fig. 1. The existing topologies of the Bi-ZSB, (a) topology proposed in [15], (b)
required three semiconductor tubes to be turned on during topology proposed in [17], (c) topology proposed in [18], (d) topology
normal operation. In Fig. 1(c) and Fig. 1(d), the topologies proposed in [19].
reduce the losses of the Bi-ZSB to some extent. However, M
when the SCR1 or SCR2 shown in Fig. 1(c) is turned off during
L1 SCR1 R1 L2
the fault, the fault current will oscillate due to freewheeling
effect of the reverse parallel connection the diode D1 or D2, + SCR4 SCR2
which is unfavorable for dc system. In Fig. 1(d), only the coil D1 Rlimit Rlimit D2
L1 or L3 is used during normal operation, which is determined SCR3
by the current direction, and the coupled coil L2 only works C
during the fault, so the coils are redundant and its utilization _
rate is low.
Fig. 2. The proposed topology.
B. Proposed topology The control method of the proposed topology is simple.
Based on the above considerations, this paper presents a When the current flows from left to right, the SCR1 needs a
new Bi-ZSB. The proposed topology is shown in Fig. 2, it trigger signal, while the SCR2 needs a continuous high-level

TABLE I
COMPARISON OF THE DIFFERENT TOPOLOGIES
Category In [15] In [17] In [18] In [19] The proposed topology
1 Common groung? No Yes Yes Yes Yes
2 Number of power tubes when conducting 4 3 2 2 1
3 Number of passive components 4 4 5 4 4
4 Number of power diodes 0 4 2 2 0
5 Number of thyristors 8 1 2 2 4
6 Number of coils 2 2 2 3 2
7 Volume Medium Medium Medium Small Small
8 Utilization rate of coils Low Low Low Low High
9 Fault current is reflected to the source side? Yes Yes Yes No No
signal at its gate, which is to make the capacitor C discharge coupled inductor is used, the proposed topology will not reflect
quickly at the moment of the fault. Conversely, the SCR3 and the fault current on the power supply side during the fault. In
SCR4 are triggered in the same way as the SCR1 and SCR2. addition, it can be seen from Tab I that the topology in Fig.1 (d)
uses two power diodes, two thyristors and three windings, and
C. Comparison of the Different topologies
its cost is clearly indicated as low in [19]. However, the
In this paper, the power loss of the thyristor or diode is proposed topology uses four thyristors and two windings.
mainly the conduction loss, the conduction loss of the thyristor Compared with the topology in Fig. 1(d), the proposed
or diode can be expressed as: topology may have a higher cost in power tubes, but lower in
PLoss = VF  I (1) coupled inductor. Therefore, the proposed topology is about
where, PLoss is the loss of the thyristor or diode, VF is the the same as that of Fig. 1 (d) in terms of cost.
forward voltage drop, and I is the current flowing through the
thyristor or diode. III. PROPOSED TOPOLOGY AND OPERATION PRINCIPLE
The forward voltage drop of the thyristor or diode is This section includes the working principle and detailed
determined by its PN junction characteristics, which is affected analysis process of the proposed topology, the minimum
by many factors, such as positive current amplitude, detectable fault conductance, the minimum required fault
temperature, etc. Generally, under the same working conductance ramp rate and transfer function. In order to
conditions, the forward voltage drop of thyristor is greater than express clearly, the working principle of the proposed
that of diode, so the power loss of diode is less than that of topology will be analyzed in combination with the simulation
thyristor. When the loss of the Bi-ZSB is high, the heat results, and the specific simulation parameters are shown in
generated by itself is also high, which may lead to aging or Table II.
thermal failure of components. In practical application, the TABLE II
thyristor and diode with low on voltage drop should be SIMULATION PARAMETERS
selected as much as possible, but its cost is high. Therefore, the Parameters Values
topology of the Bi-ZSB should be further improved to reduce DC voltage 30V
the loss. In this paper, the proposed topology is compared with Coil turn ratio 1:1
the existing topologies advised in [15], [17], [18] and [19] in Coil inductance 1000μH
many aspects. A qualitative comparison of the different Load 10Ω
topologies is shown in Tab I. Step load 5.5Ω/4.6Ω
As can be seen from Tab I, except for the topology proposed Fault resistance 0.01Ω
in [15], all other Bi-ZSBs are common ground between power Capacitance 470μF
supply and load. Under the same working conditions, since
there is only one thyristor in the load current path, the proposed A. Analysis of the Operation Principle
topology has the lowest conduction loss among the topologies The specific working principle is shown in Fig. 3, and
in Tab I, which improves the efficiency and power density of analysis process is as follows:
the Bi-ZSB. Generally, the volume of the Bi-ZSB with When the energy flows from left to right, the current path is
separate inductor structure is larger than that with coupled shown in Fig. 3(a). In addition, when the voltage of the
inductor, and the number of components required is more [22]. capacitor C is charged to the supply voltage, the current
The inductor size is reduced by 50% compared with limiting resistor R1 will no longer generate loss. At this time,
non-couple-inductor Bi-ZSB [23]. Therefore, compared with the load current and the voltage of the capacitor are as below:
other Bi-ZSBs, the topologies proposed in this paper and in Us
reference [19] have smaller volume and fewer components. I L = I SCR1 = (2)
RL
However, the coupled coils in [19] have the problems of
redundancy and low utilization rate. The proposed topology UC = U s (3)
further simplifies the design of the coupled inductor. Since the where, IL is the load current, ISCR1 is the thyristor SCR1 current,

40
uL (V), iL (A)
SCR1 Load voltage uL
L1 R1 L2 20
Load current iL
+ SCR4 SCR2 IL 0
D1 Rlimit D2 + (a)
Rlimit 4
Us SCR3 RL uL
iSCR1 (A)
C _ 2
_ t0
0
(a) (b)
100
uSCR1 (V)
L1 SCR1 R1 L2 50
iL1 iL2 0
+ SCR4 SCR2 iF
-50
D1 Rlimit Rlimit D2 + (c)
iC SCR3 uL 40
Us RFault RL
UC 20
uC (V)
_
_ 0
-20
(b) (d)
1
L1 SCR1 R1 L2 0.5
iR1 (A)
iL1 iL2 0
+ SCR4 SCR2
-0.5
D1 Rlimit Rlimit D2 + (e)
30
Us SCR3 RL uL
RFault 20
UC _ iC (A)
10
_ 0
-10
(c) (f)
30
Fig. 3. The specific working principle, (a) normal working stage, (b) fault 20
iSCR2 (A)
transient and steady state stage, (c) freewheeling stage. 10

Us is the power supply voltage, RL is the load, UC is the 0
-10
capacitance voltage. (g)
4
The simulation results are shown in Fig. 4. The fault occurs
iL1, iD1 (A)
Coil L1 current iL1

at t0=1ms moment. In Fig. 4, 0<t<t0 represents the normal 2 Diode D1 current iD1
working stage. According to Fig. 4(a) ~ (d), the capacitor
0
voltage is equal to the supply voltage, and the load current is 0m 1m 2m 3m 4m 5m 6m
3A before t0. Time (s)
(h)
The current path during the fault is shown in Fig. 3(b).
Fig. 4. The simulation results of the proposed topology, (a) load voltage and
When a short-circuit fault occurs, the load voltage drops current, (b) SCR1 current, (c) SCR1 voltage, (d) capacitor voltage, (e) R1
rapidly and the fault current rises rapidly. The current of the current, (f) capacitor current, (g) SCR2 current, (h) coil L1 current and
coupled coil L1 will be reflected by the coil L2 to get a reverse freewheeling current.
current with the main circuit, which will make the current of
the main circuit be quickly pulled to zero, and turn off the the turns of the coupled coils L1 and L2.
SCR1. At this time, the relationship between the capacitor Since iL1 is opposite in direction to the main loop current, the
voltage and fault current is as: current flowing through the SCR1 is:
diF U s N2
U C = L2  + RFault  iF (4) iSCR1 = I SCR1 − iL1 =
−  iF (7)
dt RL N1
where, RFault is the fault resistance and iF is the fault current. According to Taylor formula, combined Eq. (5) ~ (7), Eq. (7)
Since the initial value of the fault current is zero, the fault can be rewritten as below:
U R
iSCR1  s − C  (t − t 0 ) + C Fault  (t − t 0 )
current can be obtained as: U U 2
2 (8)
  R  RL L2 2 L2
 1 − exp − Fault  (t − t0 )
UC
iF = (5) After the SCR1 is turned off, the capacitor continues to inject
RFault   L2  current to the fault point. When the fault current reverses, the
The current of the coupled coil L1 reflected by the coil L2 is SCR2 will be turned off and the fault current will be zero.
as below: Therefore, the discharging process of the RLC circuit has only
N2 positive half cycle, as below:
iL1 =  iF (6)
di F
N1 U C = L2  + RFault  i F (9)
where, iL1 is the current of the coupled coil L1, N1 and N2 are dt
According to Eq. (9), if the fault resistance RFault is ignored, B. Minimum Detectable Fault Conductance
the fault current of positive half cycle can be calculated as: The working process of the proposed topology is analyzed
t U t in detail above. However, the tripping condition of the Bi-ZSB
iF = I L cos + C sin (10)
L2C L2 L2C is related to the fault conductance and its ramp rate [24, 25].
In the simulation results, Fig. 4(a) shows the change process Firstly, this paper analyzes the minimum detectable fault
of the load voltage and current when a short-circuit fault conductance under the condition that the fault conductance
occurs. Fig. 4(b) shows that the current flowing through SCR1 ramp rate is large enough. When the fault occurs, the current of
is rapidly pulled to zero at the fault instant. According to Fig. the coil L1 reflected by the coil L2 as:
i = U  2  (G − G )
N (11)
4(c), the SCR1 bears a positive voltage drop during the fault, L1 s F L
N1
which proves that the SCR1 has been reliably turned off. Fig.
4(d) shows the change of the capacitor voltage. In actual where, GF is the fault conductance and GL is the load
application, the capacitor can be connected in anti-parallel conductance.
with a diode in order to achieve the protection of the capacitor The current flowing through the SCR1 is as below:
 (GF − GL )
polarity reversal. The current of the resistor R1 is shown in Fig. N2
iSCR1 = GLU s − U s  (12)
4(e). Since the SCR2 and R1 are shorted, the main current will N1
not flow through the SCR2 and R1. The value of the resistor R1 Eq. (11) and Eq. (12) show the relationship between the
affects the charging time of the capacitor C. The smaller the selection of turn ratio and load and supply voltage. According
resistance is, the shorter the charging time of the capacitor C is; to the characteristics of the SCR, when the current flowing
on the contrary, the longer the charging time is. After the fault, through the SCR is less than or equal to zero, the SCR will be
the resistor R1 will produce a small amplitude current due to turned off. Therefore, the minimum detectable fault
the capacitor over discharging. The current through resistor R1 conductance can be obtained as below:
will go towards zero when the capacitor gets charged to nearly
 N 
the supply voltage Us. The steady-state process of the fault is GF  GF min = 1 + 1   GL = 2GL (13)
shown in Fig. 4(f) and (g), the fault current becomes zero after  N2 
a positive half cycle. The transient process of the fault is given where, GFmin is the minimum detectable fault conductance.
in Fig. 5. Since the supply voltage Us is removed from Eq. (13), the
4 turn ratio is only related to the load. Therefore, changing the
Fault transient process
iSCR1 (A)
turn ratio can change the fault detection threshold [19]. In

2
order to facilitate the calculation and design of the coupled
0
inductor, the turn ratio is considered to be 1:1. Therefore, when
(a) the fault conductance is more than twice the load conductance,
10 the proposed topology considers that the dc line has a fault and
trips immediately. On the contrary, the proposed topology will
iC (A)
5
not be triggered.
0
The current flowing through the SCR1 under different fault
t0-2μ t0 t0+2μt0+4μ t0+6μ t0+8μ conductance is shown in Fig. 6, and the fault conductance is
Time (s) considered as 0.19Ω-1 and 0.21Ω-1 respectively. It can be seen
(b) from Fig. 6 that when the fault conductance is greater than
Fig. 5. The fault transient waveforms, (a) SCR1 current, (b) capacitor current. GFmin, the proposed topology will trip. Conversely, the
Fig. 5(a) shows the turn-off process of the SCR1. According proposed topology will flow through the fault current.
to Eq. (8), the current flowing through the SCR 1 decays 6
linearly due to the fault resistance RFault is very small. The GF=0.21Ω-1>GFmin
4
iSCR1 (A)
transient process is very short, only 5μs, which shows that the
GF=0.19Ω-1<GFmin
proposed topology can cut off the fault current quickly in case 2
of the fault. During the fault transient, the capacitor C supplies
0
current to the fault resistance RFault and the coil L1 respectively,
0m 1m 2m 3m 4m 5m 6m
as shown in Fig. 5(b). In addition, the fault current has no Time (s)
effect on the power supply.
Fig. 6. The current of the SCR1 under different fault conductance.
The freewheeling stage is given in Fig. 3(c). When the fault
current disappears, there is still energy left in the coupled In addition, if the fault is permanent, the proposed topology
inductor. At this time, the coupled inductor will release its may not be able to be interrupted again after reclosing, due to
energy through the RD snubber circuits. that the fault conductance does not meet Eq. (13). However, it
In Fig. 4(f)~(h), when the capacitor current iC exceeds its is also a common phenomenon for all Z-source DC circuit
peak value and starts to decrease, the snubber circuit of the breakers. Generally, the fault protection method and the fault
coupled inductor starts to work. When the fault current is zero, location method are used together in DC system [26].
the current of the coupled inductor begins to decay until it is Reference [2] introduces in detail that the probe method can
zero. not only locate the fault point accurately, but also discriminate
between transient and permanent faults. If the fault is where, KFrrmin is the minimum required fault conductance ramp
eliminated, DCCB will be reclosed; on the contrary, DCCB rate.
will not be reclosed. The probe method ensures that the success Therefore, the proposed topology can actively trip only
rate of reclosing operation reaches 100%, and avoids the when the fault conductance and its ramp rate simultaneously
damage of DC equipment. Therefore, if the proposed topology satisfy Eq. (13) and Eq. (21). On the contrary, the proposed
is used in combination with the probe method, it can also topology will not trip. The current of the SCR1 under different
achieve good results. fault conductance ramp rates is shown in Fig. 7.
30
C. Minimum Required Fault Conductance Ramp Rate
20 KFrr>KFrrmin
When the fault conductance satisfies Eq. (13) and has a
iSCR1 (A)
KFrr<KFrrmin
sufficiently large ramp rate, the proposed topology will trip in 10
time. However, when the fault conductance ramp rate is small,
the proposed topology may not actively trip, even if the fault 0
current is large enough. Therefore, the proposed topology has a 0m 1m 3m 2m 4m 5m 6m
requirement for the minimum fault conductance ramp rate. Time (s)
Assuming that the load conductance GL changes to the fault Fig. 7. The current of the SCR1 under different fault ramp rates.
conductance GF is a linear process, the expression of the fault D. Analysis of the Impedance Network
conductance ramp rate can be written as:
G − GL
As discussed in [17], [18] regarding the filter characteristics
K Frr = F (14) of the Bi-ZSB, this paper considers the transfer function of the
Δt
proposed topology. The equivalent circuit of the proposed
where, KFrr is the fault conductance ramp rate, and △t is the
topology is shown in Fig. 8.
climbing time.
s(L1+M) s(L2+M)
During the fault conductance climbing, the expression of
fault current is as below: +
• •
+
uL dU C I1 I3
i F = iC = = −C = u L  (G L + K Frr t ) (15) sM
RFault dt • • •
Ui I2 RL Uo
where, uL is the load voltage. R1
The initial value of the load voltage is the supply voltage. If
the voltage drop across the coil L2 is ignored and the variables _
1/sC _
uL and UC are considered equal, Eq. (15) can be further derived
as follows: Fig. 8. The equivalent circuit of the proposed topology.
 G t K t2  In Fig. 8, the mutual inductance is written as:
u L = U s  exp − L − Frr  (16)
 C 2C  M = k L1  L2 (k  1) (22)
where, M is the mutual inductance, and k is the coupled
 G t K t2 
iF = U s  (GL + K Frr t )  exp − L − Frr  (17) coefficient.
 C 2C  Therefore, the transfer function of the proposed topology
According to Eq. (17), the peak value of the fault current can can be derived as below:
be obtained as below:
• (sM + R + 1 sC ) || (sL2 + sM + RL ) RL
K Frr C  exp(GL K Frr C )
2 Uo ( sL2 + sM + RL ) (23)
iFmax = U s (18) =
e U
•
s ( L
i
2 + M ) + ( sM + R + 1 sC ) || ( sL2 + sM + RL )
where, iFmax is the peak value of the fault current.
Assuming that the coupled coefficient k is equal to 1, the
According to Taylor formula, Eq. (18) can be solved as
current limiting resistance R1 and load RL are considered as
following:
10Ω, and the coils L1 and L2 are taken to be 1000μH, then Eq.
K Frr C + GL
2
(23) can be derived as:
iFmax  U s (19)
•
e
Uo s 2 RLC + sR 2C + R
Since the turn off of the main circuit SCR1 depends on the •
= (24)
amplitude of the coupled current, the peak value of the fault Ui 8s 3 L2C + 7 s 2 RLC + s( R 2C + 4 L) + R
current should satisfy the following condition:
In Eq. (24), other parameter values are given in Tab II.
iFmax − I L  GLU s (20) Therefore, the Bode diagram of the proposed Bi-ZSB is easily
Therefore, the required fault conductance ramp rate can be obtained by Eq. (24), as shown in Fig. 9.
obtained by Eq. (20) is as below: As shown in Fig. 9, the proposed topology has low-pass
2 2 filtering characteristics, and the passband cut-off frequency is
 (4e − 1) = 9.873 L
GL G
K Frr  K Frrmin = (21) about 1100Hz. In addition, the value of the resistor R1 affects
C C the transmission characteristics of the proposed topology. The
smaller the resistance is, the narrower the pass band of the As can be seen from Eq. (5), the value of the capacitor C
filter is; on the contrary, the wider the pass band is. Therefore, affects the duration of the fault current. If the capacitance is
the proposed topology is helpful to reduce the harmonic reduced, the duration and amplitude of the fault current will be
component in dc system. reduced. Conversely, the duration and amplitude will increase.
20 In addition, the capacitance is inversely proportional to the
minimum fault conductance ramp rate according to Eq. (21).
Amplitude (dB)
0
The capacitance can be selected according to three factors,
-20 R1=1Ω including DC voltage, the fault current duration and the
-40
R1=10Ω minimum fault conductance ramp rate. The simulation results
R1=50Ω of the capacitor C with different values are shown in Fig. 11.
-60 40
(a)
0 C=100μF
iF (A)
20 C=470μF
Phase (deg)
-50 C=1000μF
R1=1Ω 0
-100 R1=10Ω
0m 1m 2m 3m 4m 5m 6m
R1=50Ω Time (s)
-150
100 101 102 103 104 105 106 Fig. 11. The simulation results of the capacitor C with different values.
Frequency (Hz)
(b)
The design parameters of the proposed topology are
Fig. 9. The Bode diagram of the proposed topology, (a) amplitude frequency
discussed above. The inductance and capacitance affect the
response, (b) phase frequency response. magnitude and duration of the fault current respectively, but
have little effect on the trip performance. Therefore, the
E. Discussion on Design Parameters parameters of the coupled inductor and capacitor need to be
The design parameters of the proposed topology are mainly selected according to the actual application.
the coupled inductor and capacitor. In addition, the selection of
the thyristor needs to be based on specific voltage and power IV. EXPERIMENTAL VERIFICATION AND ANALYSIS
levels. The design parameters of the coupled inductor include
the inductance and the turn ratio. According to Eq. (10), the A. Design of the Circuit
inductance of the secondary coil is related to the magnitude In order to verify the above theoretical analysis, this paper
and duration of the fault current. Eq. (5) can be simplified as builds a scale-down hardware platform. The dc voltage is 30V
below: and the load is about 10Ω during normal operation. According
to Eq. (13), when the change of the fault conductivity is greater
iF 
UC
(t − t0 ) (25) than 0.2Ω-1, the proposed topology will trip. Therefore, in
L2 order to ensure that the proposed topology does not trip, the
As can be seen from Eq. (10) and Eq. (25), if the inductance fault resistance should change from 10Ω to 5Ω. At this time,
of the secondary coil is reduced, the amplitude of the fault the maximum value of the load current can reach 6A, so the
current will increase, but the duration of the fault current will maximum load power is 180W. In order to ensure the
decrease. Conversely, the amplitude will decrease, and the reliability of the components, the selection of the thyristor
duration will increase. Therefore, the inductance of the should leave a margin. The thyristor selected in this paper is
secondary coil should be selected according to the DC system MCR25D. In addition, according to the load power and the
power and components. The simulation results of the L2 with datasheet of the TDK magnetic core, the core of the coupled
different inductance are shown in Fig. 10. inductor selected in this paper is EE40, the core material is
40 PC40, and the diameter of the copper wire is 1.2mm. The
L2=200μH parameters of the hardware experiment are shown in Tab III.
iF (A)
20 L2=500μH
TABLE III
L2=1000μH
PARAMETERS OF EXPERIMENT
0 Parameters Values
0m DC voltage 30V
1m 2m 3m 4m 5m 6m
Time (s) Coil inductance 1000μH
Fig. 10. The simulation results of the L2 with different inductance. Coupled core EE40/PC40
SCR MCR25D
According to Eq. (13), the turn ratio of the coupled inductor
Freewheeling diode SS36
is related to the load. Therefore, the proposed topology can
Capacitor 470μF/50V
adjust the fault detection threshold based on the turn ratio.
After the turn ratio and the secondary coil inductance are According to the design formula of inductance, the number
determined, the parameters of the primary coil can also be of the coil turns is calculated as below:
easily obtained. The magnetic core of the coupled inductor L
N= (26)
should also be selected according to the actual situation.
AL
where, N is the number of the coil turns, L is the inductance,

and AL is the inductance coefficient of the magnetic core. Time: 400μs/div
The inductance coefficient AL of the magnetic core EE40 is Ch1: 10V/div
4150nH/N2±25% according to the TDK datasheet. Therefore, Ch2: 1V/div 10mV/A
the number of the coil turns can be calculated to be
Ch1: Voltage of capacitor
approximately 16. The hardware experiment circuit designed
according to the above parameters is shown in Fig. 12. The
platform mainly includes the main circuit and the trigger Ch2: Current of capacitor
control circuit of the thyristor.
(c)
Ch1: Voltage of SCR
Ch2: Current of SCR
Fig. 12. Hardware experiment platform. Time: 1000μs/div

Ch1: 10V/div
B. Experimental Results and Analysis Ch2: 50mV/div 10mV/A
The waveforms on the hardware experimental platform are
shown in Fig. 13.
(d)
It can be seen from Fig. 13(a) and (b) that the load voltage is
equal to the power supply voltage before the short-circuit fault
occurs, and the voltage drop of the thyristor SCR1 is
Ch1: Voltage of SCR
approximately zero. In addition, in the experiment, the load is
connected in parallel with three resistors with a nominal value
Ch2: Current of SCR
of 30Ω. Since the error of the load and sampling circuit, the
actual load current is more than 3A.
Time: 1000μs/div
Time: 400μs/div
Ch1: 10V/div
Ch1: 10V/div
Ch2: 50mV/div 10mV/A
Ch2: 1V/div 50mV/A
Ch1: Voltage of load

(e)
Fig. 13. Hardware experiment, (a) the voltage and current of load, (b) the
Ch2: Current of load voltage and current of SCR1, (c) the voltage and current of capacitor, (d) the
voltage and current of SCR1 under GF < GFmin, (e) the voltage and current of
SCR1 under KFrr < KFrrmin.
In Fig. 13(a) and (c), after the short-circuit fault occurs, and
the fault conductance and its ramp rate meet Eq. (13) and Eq.
(a) (21) respectively, the capacitor voltage and load voltage drop
rapidly, and the fault current rises quickly. Simultaneously, the
Ch1: Voltage of SCR
current flowing through the thyristor SCR1 is rapidly pulled to
Time: 1000μs/div
zero at the fault instant, and the voltage drop of the thyristor
Ch1: 10V/div
SCR1 rises to the power supply voltage, thus the fault current
Ch2: 50mV/div 10mV/A flowing from the power supply is cut off. In addition, the fault
current is not reflected to the power supply side, and there is no
inrush current on the power supply side during the fault.
Ch2: Current of SCR In Fig. 13(d), the fault conductance is about 0.19 Ω -1, but it
does not meet Eq. (13), that is, GF < GFmin, so the proposed
topology is not tripped, even if the fault conductance ramp rate
meets Eq. (21).
(b)
In Fig. 13(e), due to that the fault conductance ramp rate is seen from Fig. 14 that the calculated and measured values of
less than KFrrmin, the proposed topology is also not triggered, the inductor and thyristor losses are almost the same, which
even if the fault current is very large. From the above analysis, proves the correctness of theoretical analysis. In addition, the
it can be seen that the trip conditions of the proposed topology power loss of the inductor is very small, which accounts for
need to meet both Eq. (13) and Eq. (21). In addition, the less than 1% of the total power.
hardware experiments verify the feasibility of the theory. 8
C. Analysis and Measurement of the Loss The calculated PCu
In order to quantitatively describe the performance of the 6 The measured PCu
PCu and PSCR (W)

proposed topology, this paper analyzes the power loss The calculated PSCR
according to the actual components. The thyristor selected in The measured PSCR
this paper is MCR25D, the diameter of the copper wire is 4
1.2mm, and the total turns of the two windings is 32 turns, so
the total length of the copper wire is 2m. The power loss of the
inductor includes copper loss and core loss. In DC system, the 2
core loss of the inductor can be ignored due to the short fault
time. Therefore, the power loss of the inductor is mainly 0
copper loss, which is expressed as: 1 2 3 4 5 6
L Load current (A)
PCu = I L  ρ 
2
(27) Fig. 14. The Calculated and measured values of the coupled inductor and
S thyristor losses.
where, PCu is the copper loss of the inductor, ρ is the resistivity
of copper conductor, L is the length of copper wire, and S is the D. Comparison of the Loss and Efficiency
cross-sectional area of copper wire. In this paper, the power loss and efficiency of the proposed
During normal operation, the thyristor is always on. topology are compared with that of Fig. 1 under the same
Therefore, the power loss of the thyristor is mainly the working conditions, as shown in Tab V. In the experiment, the
conduction loss [27], which can be expressed by Eq. (1). The diode model is MBR30200CT. In addition, the power losses of
forward voltage drop of the thyristor can be obtained according all topologies are shown in Fig. 15.
to the MCR25D datasheet. Therefore, the calculated and As can be seen from Fig. 15, the topology in Fig. 1(a) has the
measured values of the coupled inductor and thyristor losses highest loss, and the loss reaches 26.278W when the load
are given in this paper, as shown in Tab IV, where PSCR is the current is 6A. The loss of the topology in Fig. 1(b) is relatively
conduction loss of the thyristor. In addition, the maximum load moderate compared with that of Fig. 1(a), and the maximum
current is considered to be 6A. loss is 16.420W. Since the loss of the inductor is small, the
For clarity, the calculated and measured values of the difference between the losses of the topology in Fig. 1(c) and
inductor and thyristor losses are shown in Fig. 14. It can be Fig. 1(d) is small, and their losses are 11.980W and 11.333W
TABLE IV
THE CALCULATED AND MEASURED VALUES OF THE COUPLED INDUCTOR AND THYRISTOR LOSSES
Total Power The calculated PCu The measured PCu The calculated PSCR The measured PSCR Load power Efficiency
IL (A)
(W) (W) (W) (W) (W) (W) (%)
1 5.632 0.03 0.035 0.84 0.857 4.729 83.967
2 20.842 0.12 0.140 1.76 1.766 18.856 90.471
3 45.249 0.27 0.316 2.70 2.766 42.054 92.939
4 79.052 0.48 0.579 3.72 3.828 74.454 94.184
5 122.480 0.75 0.904 4.83 4.970 116.260 94.922
6 174.904 1.08 1.294 5.94 6.246 166.880 95.411
TABLE V
THE POWER LOSS AND EFFICIENCY OF ALL TOPOLOGIES
Fig. 1(a) Fig. 1(b) Fig. 1(c) Fig. 1(d) The proposed topology
IL (A) Power loss Efficiency Power loss Efficiency Power loss Efficiency Power loss Efficiency Power loss Efficiency
(W) (%) (W) (%) (W) (%) (W) (%) (W) (%)
1 3.463 38.510 2.132 62.143 1.512 73.151 1.495 73.463 0.903 83.967
2 7.204 65.437 4.506 78.382 3.206 84.620 3.136 84.954 1.986 90.471
3 11.380 74.849 7.132 84.237 5.107 88.713 4.949 89.062 3.195 92.939
4 15.891 79.898 9.967 87.392 7.187 90.908 6.898 91.275 4.598 94.184
5 20.784 83.031 13.024 89.366 9.449 92.285 8.997 92.654 6.220 94.922
6 26.278 84.976 16.420 90.612 11.980 93.151 11.333 93.521 8.026 95.411
respectively. However, the proposed topology has the lowest V. CONCLUSION

loss, only 8.026W, which proves that the proposed topology This paper presents a low-loss Z-source circuit breaker for
has great advantages in terms of low power loss. LVDC systems. The proposed topology has the least power
30 loss during normal steady-state operation, due to that there is
Topology in Fig. 1(a) only one thyristor in the conduction path. Compared with the
25 Topology in Fig. 1(b) proposed topology, the other topologies of the Bi-ZSB have
Topology in Fig. 1(c)
Power loss (W)
20 higher conduction loss, which is due to the presence of extra

Topology in Fig. 1(d) diodes in their circuits. The experimental results also prove
Proposed topology that the proposed topology has advantages in terms of low
15
power loss. In addition, the proposed topology optimizes the
10 design of the coupled inductor, improves the utilization of the
coils, and reduces the cost and volume. Therefore, the
5 proposed topology further overcomes the shortcomings of
conventional Z-source circuit breakers. The effectiveness of
0 the proposed topology is verified by simulation and a
1 2 3 4 5 6
Load current (A) scale-down hardware experiment, and the expected results are
Fig. 15. The power losses of all topologies.
achieved.
The above analysis provides a reference for the loss
REFERENCE
evaluation of the Bi-ZSB under high voltage and high power.
When the proposed topology is used in high voltage [1] S. Beheshtaein, R. M. Cuzner, M. Forouzesh, M. Savaghebi, et al., “DC
Microgrid Protection: A Comprehensive Review,” IEEE Journal of
applications, several thyristors may be needed in the Emerging and Selected Topics in Power Electronics. doi:
conduction path, which will lead to an increase in the loss of 10.1109/JESTPE.2019.2904588.
the proposed topology. Similarly, the losses of the topology in [2] J. Park, J. Candelaria, L. Ma and K. Dunn, “DC Ring-Bus Microgrid
Fig. 1 will also increase. In brief, assuming that n power tubes Fault Protection and Identification of Fault Location,” IEEE
Transactions on Power Delivery, vol. 28, no. 4, pp. 2574-2584, Oct.
are required in the conduction path, the losses of the power 2013.
tubes of the proposed topology and the topology in Fig. 1 will [3] Xue Shimin, Chen Chaochao, Jin Yi, et al.,“A research review of
increase by n times at the same time, so the ratio of the protection technology for DC distribution system,” Proceedings of the
proposed topology to the topology in Fig. 1 is constant in terms CSEE, vol. 34, no. 19, pp. 3114-3122, 2014 (in Chinese).
[4] C. Meyer, S. Schroder, and R. W. De Doncker, “Solid-state circuit
of power tube losses. In addition, since the number of power breakers and current limiters for medium-voltage systems having
tubes in the current path of the proposed topology is always distributed power systems,” IEEE Trans. Power Electron., vol. 19, no.
less than that of other topologies, the proposed topology also 5, pp. 1333-1340, 2004.
has advantages in low power loss in high voltage situations, [5] L. L. Qi, A. Antoniazzi, L. Raciti and D. Leoni, “Design of Solid-State
Circuit Breaker-Based Protection for DC Shipboard Power Systems,”
but the advantage may not be very obvious. IEEE Journal of Emerging and Selected Topics in Power Electronics,
The efficiency of all topologies is shown in Fig. 16 vol. 5, no. 1, pp. 260-268, March 2017.
according to Tab V. [6] P. Prempraneerach, M. Angle, J. Kirtley, et al., “Optimization of a
Z-Source DC Circuit Breaker,” IEEE Electric Ship Technologies
100 Symposium (ESTS), Hilton Arlington, VA, USA, 2013, pp. 4480–486.
[7] A. Maqsood and K. A. Corzine, “Integration of Z-Source Breakers Into
80 Zonal DC Ship Power System Microgrids,” IEEE Journal of Emerging
and Selected Topics in Power Electronics, vol. 5, no. 1, pp. 269-277,
Efficiency (%)
March 2017.
60 [8] Maqsood and K. Corzine, “The Z-source breaker for fault protection in
ship power systems,” in Proc. IEEE Int. Symp. Power Electron. Elect.
Topology in Fig. 1(a) Drives Autom. Motion, 2014, pp. 307–312.
40 [9] S. Mirsaeidi et al., “AC and DC microgrids: A review on protection
Topology in Fig. 1(b)
Topology in Fig. 1(c) issues and approaches,” J. Elect. Eng. Technol., vol. 12, no. 6, pp.
2089–2098, 2017.
20 Topology in Fig. 1(d) [10] K. A. Corzine and R. W. Ashton, “A New Z-Source DC Circuit
Proposed topology Breaker,” IEEE Transactions on Power Electronics, vol. 27, no. 6, pp.
0 2796-2804, June 2012.
1 2 3 4 5 6 [11] K. A. Corzine and R. W. Ashton, “Structure and analysis of the
Load current (A) Z-source MVDC breaker,” 2011 IEEE Electric Ship Technologies
Symp., Alexandria, VA, 2011, pp. 334-338.
Fig. 16. The efficiency of all topologies.
[12] A. H. Chang, B. R. Sennett, A.-T. Avestruz, et al., “Analysis and design
As can be seen from Fig. 16, the efficiency of all topologies of DC system protection using Z-source circuit breaker,” IEEE Trans.
increases with increasing load current. However, the proposed Power Electron., vol. 31, no. 2, pp. 1036–1049, Feb. 2016.
[13] K. A. Corzine, “A New-Coupled-Inductor Circuit Breaker for DC
topology has the highest efficiency. When the load current is Applications,” IEEE Transactions on Power Electronics, vol. 32, no. 2,
6A, the efficiency of the proposed topology is 95.411%, while pp. 1411-1418, Feb. 2017.
the maximum efficiency of the topology in Fig. 1 is 93.521%. [14] W. Li, Y. Wang, X. Wu, et al., “A Novel Solid-State Circuit Breaker for
Therefore, the proposed topology can further improve the On-Board DC Microgrid System,” IEEE Transactions on Industrial
Electronics, vol. 66, no. 7, pp. 5715-5723, July 2019.
efficiency of the Bi-ZSB.

[15] A. Maqsood and K. A. Corzine, “The Z-source breaker for ship power Yachao Yang was born in Hebei, China,
system protection,” 2015 IEEE Electric Ship Technologies Symposium
in 1989. He received the B.Sc. degree in
(ESTS), Alexandria, VA, 2015, pp. 293-298.
[16] S. Savaliya, S. Singh, and B. G. Fernandes, “Protection of DC system Electronic Science and technology from
using bi-directional Z-source circuit breaker,” in Proc. 2016 Conf. Hunan Institute of Engineering in 2010,
IEEE Ind. Electron. Soc., 2016, pp. 4217–4222. Xiangtan, China. He received the M.Sc.
[17] D. J. Ryan, H. D. Torresan and B. Bahrani, “A Bidirectional Series
degree in Electronics and Communication
Z-Source Circuit Breaker,” IEEE Transactions on Power Electronics,
vol. 33, no. 9, pp. 7609-7621, Sept. 2018. Engineering from Hunan University in
[18] D. Keshavarzi, T. Ghanbari and E. Farjah, “A Z-Source-Based 2014, Changsha, China. Currently, he is
Bidirectional DC Circuit Breaker With Fault Current Limitation and pursuing the Ph.D. degree in Electrical
Interruption Capabilities,” IEEE Transactions on Power Electronics,
Engineering at Hunan University.
vol. 32, no. 9, pp. 6813-6822, Sept. 2017.
[19] Y. Wang, W. Li, X. Wu and X. Wu, “A Novel Bidirectional Solid-State His current research interests include fault analysis and
Circuit Breaker for DC Microgrid,” IEEE Transactions on Industrial protection of dc grid.
Electronics, vol. 66, no. 7, pp. 5707-5714, July 2019.
[20] S. Bhatta, Y. Zhang and R. Fu, “Comparative Analysis of Power Loss
Chun Huang was born in Hunan, China,
Associated with Topology of Bi-Directional Z-Source Circuit
Breakers,” Southeast Con 2018, St. Petersburg, FL, 2018, pp. 1-5. in 1966. He received the B.Sc., M.Sc., and
[21] S. Bhatta, Y. Zhang and R. Fu, “Relationship of Steady-State Power Ph.D. degrees in Electrical Engineering
Loss and Configurable Tripping Time in Z-Source Circuit Breakers,” from Hunan University, Changsha, China
2019 IEEE Applied Power Electronics Conference and Exposition
in 1988, 1991, and 2005, respectively.
(APEC), Anaheim, CA, USA, 2019, pp. 3483-3489.
[22] S. G. Savaliya and B. G. Fernandes, “Analysis and Experimental Since 1991, he has been with Hunan
Validation of Bidirectional Z-Source DC Circuit Breakers,” IEEE University, where he is a professor of
Transactions on Industrial Electronics, vol. 67, no. 6, pp. 4613-4622, electrical engineering. His research
June 2020.
interests include power system protection
[23] H. Al-khafaf and J. Asumadu, “Γ-Z-source DC circuit breaker
operation with variable coupling coefficient k,” 2017 IEEE and control, distribution network, and the application of signal
International Conference on Electro Information Technology (EIT), processing technology in electrical engineering.
Lincoln, NE, 2017, pp. 492-496.
[24] Muhammad Waqas Aslam, Nauman Ahmad Zaffar, “A Novel
Bidirectional Z-Source DC Circuit Breaker for DC Microgrids,” SBA
School of Science & Engineering, LUMS , Lahore, Pakistan,2016
IEEE.
[25] A. Maqsood and K. Corzine, “Z-source Dc circuit breakers with
coupled inductors,” 2015 IEEE Energy Conversion Congress and
Exposition (ECCE), Montreal, QC, 2015, pp. 1905-1909.
[26] Y. Yang, C. Huang and Q. Xu, “A Fault Location Method Suitable for
Low-Voltage DC Line,” IEEE Transactions on Power Delivery, vol. 35,
no. 1, pp. 194-204, Feb. 2020.
[27] S. Bhatta, Y. Zhang and R. Fu, “Comparative Analysis of Power Loss
Associated with Topology of Bi-Directional Z-Source Circuit
Breakers,” SoutheastCon 2018, St. Petersburg, FL, 2018, pp. 1-5.

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This article has been accepted for publication in a future issue of this journal, but has not been

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

A Low-Loss Z-Source Circuit Breaker for LVDC

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

operation principle of the proposed topology is analyzed in SCR

middle of the rectifier bridge, so it greatly reduces the number (d)

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

transient and steady state stage, (c) freewheeling stage. 10

Coil L1 current iL1

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

turn ratio can change the fault detection threshold [19]. In

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

where, N is the number of the coil turns, L is the inductance,

Ch1: Voltage of SCR

Ch2: Current of SCR

Fig. 12. Hardware experiment platform. Time: 1000μs/div

Ch1: Voltage of load

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

PCu and PSCR (W)

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

respectively. However, the proposed topology has the lowest V. CONCLUSION

20 higher conduction loss, which is due to the presence of extra

IEEE POWER ELECTRONICS REGULAR PAPER/LETTER/CORRESPONDENCE

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