Digital systems

Chapter 5

1 Compter organization
Dr. Iness NEDJI MILAT (Lecturer)
iness.nedji@ensia.edu.dz

Pr. Nasreddine LAGRAA

Nasredine,lagraa@ensia.edu.dz
First year – 2023/2024
2
Von Neumann Model
3 Von Neumann model
John von Neumann proposed a fundamental model in 1945, for processing computer
programs.

It is also known as the Von Neumann Architecture.

It describes the design architecture for a computer with these

components:

Central processing unit (CPU)

Main memory that stores data and instructions (programs),

Input and output devices,

All these components are connected via buses.

4 Von Neumann model : Two Key Properties
Von Neumann model is also called stored program computer. It has two key
properties:

Stored program

Both Data and Instructions are stored in a same

memory,

Sequential instruction processing

The CPU executes one instruction at a time using the Fetch-Decode-Execute

cycle
Program counter (instruction pointer) identifies the current instruction
Program counter is advanced sequentially except for control transfer
instructions
 Von Neumann model
5
Central processing Unit Monitor,
Processes data and
Printer,
instructions and controls
Manages execution of Disk,… system
the computer
instructions by sending control Control Unit
signals to other parts of the CPU.
Registers
Registers
Temporary
Inputstorage Output
locations within the
CPU(Fast).
Arithmetic and Logic Unit:
Keyboard, carries out arithmetic and
ALU
Mouse, logical operations.
Buses : Wires that are used
Disk,… to transfer data between
components
stores the program
Main Memory
(instructions and data)
6
Buses
7 Von Neumann model : Buses
Buses are a communication system that transfers information (Instruction, data,
address, control signal) between components inside a computer,

CPU Main Memory Input/Output

Buses

Von-Neumann Architecture comprised of three major bus systems for data transfer :
Address bus, Control bus and Data bus
8 Types of Buses

CPU Main Memory Input/Output

Address Bus

Control Bus
1
0

Data Bus 1
0
1
1
1 Parallel lines
0

A bus structure consists of a set of common lines, one for each bit of a binary information.
9 Types of Buses
Data Bus
Carries the data between the CPU, the memory and the Input/Output devices
Bidirectional : Either the CPU writes data to memory, or it read data from
memory
May consist of 32, 64 or more separate lines
The number of lines is referred to as the width of the data bus,
The number of lines determines how many bits can be transferred at a time
The width of the data bus is a key factor in determining overall system
performance
10 Types of Buses
Address Bus
Carries the address of data between the CPU and the memory units,
Unidirectional : the CPU always sets the bus to indicate the address of memory word
being read or written.
Its width determines the maximum possible memory capacity.

Control Bus
Carries control signals (commands) from the CPU in order to control and coordinate
all the activities within the computer,
Unidirectional : the CPU always sets it to indicate operations to be performed.
11
Main Memory
12 Conceptual view of memory
▪ The memory unit that establishes direct communication with the CPU is called Main
Memory. It is often referred to as RAM (Random Access Memory).
▪ A memory unit stores binary information (Instruction or data) in groups of bits called
words.
▪ The data consists of m lines : n address lines
n
Main Memory
▪ Data input lines provide the information to be stored 2n words
(written) into the memory, CS m bits per word
R/W
▪ Data output lines carry the information out (read) from
the memory.
m
▪ The address consists of n lines which specify which word (among
the 2n words available) to be selected for reading or writing.
m data lines

▪ The control line Read/Write (1/0) specifies the direction of transfer of the data (Memory
operation).
▪ The control line Chip Select (CS) selects the chip box to be read from/written to.
13 Array Organization of Memory
Main Memory

2n- 1 Word 2n -1

Address •
•
• n lines
bus •
CS Deepth
R/W • (2n)
Data •
m lines
•
bus
2

1 Word 1

@0 Bm-1 ... B3 B2 B1 B0 Word 0

Width (m)
14 Array Organization of Memories : Example
Address bus : n = 3 lines Main memory
Memory size = 23 words = 8 words 7 0 0 1 1

Data bus : m = 4 lines (word = 4 bits) 6 1 1 1 0

Memory size = 23 × 4 bits = 32 bits 5 1 0 0 0

For example, the 4-bit word stored at address 4 1 0 1 1

Deepth

5 is 1000 3 1 0 1 1

2 1 0 0 0

1 0 1 1 0

0 0 0 0 1

addresses
Width
15 Memory array architecture
Main memory
Memory is a 2D array of bits. Cell
Word 2n -1
Each bit stored in a cell memory.

Address bus
Address Decoder selects a word line

Decoder
R/W selector determines access type

CS selector determines a chip box Word 1

R/W
CS Word 0
Word line is then coupled to the data lines

Data bus
16 Memory: Write and Read Operations

The Write operation:

Transfers the address of the desired word to the address lines
Transfers the data bits (the word) to be stored in memory to the data input lines
Activates the Write control line (set Read/Write to 0)

The Read operation:

Transfers the address of the desired word to the address lines
Activates the Read control line (set Read/Write to 1)
Transfers a copy of the accessed word to the data output lines
17 Implementation of Cells
Modern computer memory is implemented as semiconductor memory, where data
is stored within memory cells built from MOS transistors and other components

DRAM (Dynamic RAM) SRAM (Static RAM)

Main memory Cache memory
18 Memory Technology : SRAM
Static random access memory
Two cross coupled inverters store a single bit
Feedback path enables the stored value to persist in the “cell”
4 transistors for storage
2 transistors for access
19 Memory Technology: DRAM
Dynamic random access memory
Capacitor charge state indicates stored value
Whether the capacitor is charged or discharged indicates storage of 1 or 0
1 capacitor
1 access transistor

The electric charge on the capacitors gradually leaks away

DRAM cell loses charge over time
DRAM cell needs to be refreshed

Refresh : A DRAM controller must periodically rewrites

the data in the capacitors, restoring them to their
original charge

The need to refresh DRAM demands more complicated circuitry and timing than SRAM.
 Tri-State Buffers
If enabled (E=1), then Q = D
Otherwise, Q is not connected
20 DRAM Write operation
Tri-State buffer

Selected word line

=0

=1

Data output line

Data input line

21 DRAM Read operation

Destructive reads
22
Central Processing Unit
23 Central Processing Unit (CPU) : Registers
The CPU is responsible for executing the instructions of a computer programs. Its major
components are : Control Unit, ALU and a variety of registers.

Central processing Unit Program Counter : holds the memory address of the
next instruction to be executed.
How they are
PC organized into the : holds the memory address
Memory Address Register
Control Unit CPU?
of either the data or the instruction.
MAR
Accumulator : holds the results of calculations carried
ACC
Registers out by the ALU

IR Instruction Register : holds the current instruction to

execute
MDR
ALU Memory Data Register : holds the data or instruction
retrieved from main memory.
24 Organization of CPU components n lines
Buses
General Purpose Registers (Reg File) : set of
Central processing
temporary Unit
registers used for any purpose. Ex.
store operands,Program
intermediate results or:arguments Main memory
Status Word set of flag bits
n bits
Processing unit of functions…
(carry, overflow, Interrupt, supervisor flags) @2 -1
n
R1 MAR
and Instruction pointer,..
R2
@
Rn PSW d
PC e
n lines
ACC c
o
Control logic bloc d
16-bit
(FSM) e
r
ALU

m bits
Instr.
IR Decoder @0
m bits
MDR Control unit
m bits

m lines m lines
25 CPU : Control unit vs Processing unit
The control unit allows:
to sequence the execution of the programs’ instructions,
to ensure the fetching and the decoding of the instruction to execute
(which is encoded in binary form)
to organize the execution of the instruction,
to carry out the preparation of the following instruction.

The processing unit allows:

to execute the instruction by performing the operation,
to hold temporally the operands and the results of the operation into
Register File,
26 How to Execute Instructions?

1. First we need to :
Fetch the instruction
2. Then we need to :
Decode instruction / fetch register operands
3. Then we need to :
Do the operation
4. Then we need to :
Write the result into register-file
Store the result into memory
5. Finally we need to :
Calculate the next instruction address
27 FETCH – DECODE – EXECUTE Cycle
As soon as a computer is turned on it starts fetching instructions from memory,
decoding them and executing them.
This process is repeated continuously, therefore it is known as the
Fetch-Decode-Execute Cycle.

Fetch

Execute Decode
 0110 0010 0100

28 Organization of CPU components Buses

Central processing Unit

Main memory
4 bits
R1 Processing unit
MAR1000
0010
0100
R2 8 0110
ADD0010A,B
0100
@
Rn PSW d
PC 1001
1000 e
ACC c
o
000000001100 Control logic bloc d
16-bitB = 4 000000000111
000000000111
(FSM) R/W
R/W == 11 e
+ r 3

ALU A=2 000000000101

000000000101

Instr. 1

IR Decoder
0110 0010 0100 0
m bits

MDR Control unit

12 lines 12 lines
 FETCH - DECODE - EXECUTE (Data path)
29 Buses

R1
PC Memory

51
50 50
R2
MAR ...
R3 50 ADD R4, R1, R2
010110001

IR
R4 MDR 16-bit

010 11 00 01 010110001

B A

ALU

Step 1: Load Step 3: Load IR

Step 2: Access
MAR and with the content Decode Execute
memory
increment PC of MDR
 FETCH - DECODE - EXECUTE (Data path)
30 Buses

R1 10
PC Memory
51 50
R2 30
MAR ...
R3 50 ADD R4, R1, R2

IR (Data path)
R4 40 MDR 16-bit

010 11 00 01 010110001

B A

+
ALU

Step 1: Load Step 3: Load IR

Step 2: Access
MAR and with the content Decode Execute
memory
increment PC of MDR
31
Machine Instruction
32 Converting high-level language to binary machine language
Programs are written in any high-level languages such : C++, Python, Java,..
The CPU can execute only machine instructions in binary
Therefore, all programs in high-level languages, are first translated (compiled) into a
binary machine instructions before the program can run.

High-level language program temp = v[k];

(in C) v[k] = v[k+1];
v[k+1] = temp;
Compiler
lw $15, 0($2)
Assembly language program lw $16, 4($2)
sw $16, 0($2)
sw $15, 4($2)
Assembler
0000 1001 1100 0110 1010 1111 0101 1000
Binary Machine Langage 0000 1001 0101 1000 0000 1001 1100 0110
Program 1100 0110 1010 1111 0101 1000 0000 1001
1100 0110 0000 1001 1100 0110 1010 1111
33 Machine instruction
The machine instruction is simply a sequence of bits that can be directly decodes and
executed by the CPU,
For executing instruction, the CPU needs to know : the operation, the operands and their
addressing modes,
The machine instruction consists of two fields :
Operation Code (Opcode) : specifies the operation to be performed by CPU,
Operand (s) : specifies the data to be operated by the CPU. The operand can either be stored in
main memory or in CPU register.
Constant (immediate addressing mode)

OPCODE OPERAND(s) Address memory (Direct addressing mode)

Machine instruction
Register (Register addressing mode)
Examples : add R3, R1, R2 ; R3= R1+R2
1101 0011 0001 0010
34 Types of machine instructions
Most assembly/machine instructions fall into one of three categories
Arithmetic/Logic
Example: ADD, SUB, MUL, AND, XOR,...
Data Transfer (to and from memory)
Example: LOAD, STORE, MOVE
Control
Example: JUMP, BR, TEST

The number of bits allocated for the opcode can determine the number of machine
instructions

Ex : if Opcode size is 4 bits -> the CPU can execute 16 kind of instructions
35 Addressing mode
Addressing modes specify where an operand is located. They can specify a constant, a register or a
memory location.
Immediate addressing is where the data is part of instruction
add R5 , R3 , 50 ; R5=R3 + 50
add 50 ; ACC=ACC + 50
Direct addressing is where the address of data is given in the instruction
load R5 , 0x1FA5 ; R5= [0x1FA5]
mov R1, [300] ;
Indirect addressing gives the address of the address of the data in the instruction
load R5 , (0x1FA5) ; R5= [[0x1FA5]]
Register addressing is where the data is located in a register
add R3, R1, R2 ; R3= R1+R2
36 Instruction set architecture ISA
Instruction set architecture (ISA) of CPU is a blueprint defining:
the set of machine instructions (Opcode),
the CPU registers (number and size),
the memory size,
the addressing mode,
…

This is the programmer’s view of the machine

It should be able to implement all the programs that users may write.
The CPU can support only machine instructions that can be mapped to its ISA
architecture.
37 Designing an ISA
• Important questions that need to be answered :
• How many instructions should we have ?
• What should they do ?
• How complicated should they be ?

• RISC : (Reduced Instruction Set Computer)

Two
different
paradigms
• CISC : (Complex Instruction Set Computer)

37
38
39 RISC vs. CISC
Complex instruction set computer (CISC):
• Large instruction set;
• Complex operations;
• Complex addressing modes;
• Complex hardware, long execution time;
• Minimum number of instructions needed for
a given task;
• Easy to program, simpler compiler.
Reduced instruction set computer (RISC):
• Small instruction set;
• Simple instructions to allow for fast execution (fewer
steps);
• Large number of registers;
• Only load/store instructions should access the main
memory, one MM access per instruction;
• Simple addressing modes to allow for fast address
computation;
• Fixed-length instructions with few formats and aligned
fields to allow for fast instruction decoding;
• increased compiler complexity and compiling time;
• simpler and faster hardware implementation, pipelined
architecture.