Digital systems

Chapter 4

1 Sequential Circuits
Dr. Iness NEDJI MILAT (Lecturer)
iness.nedji@ensia.edu.dz

Pr. Nasreddine LAGRAA

Nasredine,lagraa@ensia.edu.dz
First year – 2023/2024
2 Sequential vs. combinational circuit
Combinational circuit output depends only on current inputs
How can we design a circuit that stores information?
Use a feedback

Sequential circuit is a combinational n

Combinational
circuit with m
inputs • •
feedbacks (storage elements). • Logic • outputs
• •
EX : Counters and Shift registers.

Some sequential circuits may not Internal input Storage element contain
Internal
combinational circuits, but only (present state) storage elements output (next
Sequential circuit state)
Ex : Registers (set of bits).

The output of a sequential circuit depends not only on current inputs but also on the previous
outputs (states).
3 Storage elements
Internal outputs of a sequential circuit are fed back via storage elements
The storage elements (memory) are circuits that are capable of storing binary
information.
The binary information stored in these memory elements at any given time
defines the state of the sequential circuit at that time.
Each storage element memorize one bit with two states (0 or 1)
4 Types of sequential circuits
Sequential circuits can be Asynchronous or Synchronous.

Asynchronous sequential circuits

change their states and output values whenever

a change in input values occurs.

Synchronous sequential circuits

change their states and output values at fixed
points of time, i.e. clock signals. (Clk = 1)

Clk
5 The clock

In synchronous circuits, state values are controlled by clock signals.

A “clock” is a special circuit that sends electrical pulses through a circuit.
Clocks produce electrical waveforms such as the one shown below.

clock
high rising
fallin
edge
g
1 edge

clock
period clock
low
6 Clock Disciplines
State changes occur in sequential circuits only when the clock ticks.
Level sensitive
State changes when clock is high (or low) Circui
t
CL
K
Edge triggered
State changes at clock edge

Circui
positive edge-triggered t
CL
K

negative edge-triggered
Circui
t
CL
K
7
Basic Storage Element
8 Basic storage elements

Generally, there are two types of storage elements used: Latches, and Flip-Flops.

Latches : A latch is an asynchronous memory element whose excitation signals (inputs)

control the state of the circuit.

A latch has two stages Set and Reset. Set input sets the output to 1. Reset input sets the
output to 0.

Flip-flops : A flip-flop is a synchronous memory element that has clock signals control the
state of the circuit.

Flip-flop is a latch with clock input signal

9 SR Latch
The SR latch is the basic memory element. It has two input signals (S and R) and
two outputs (Q and Q’).
Basic Latches can be constructed using two NAND gates or using two NOR gates

SR
Latch

Active Active
Low High

Two cross-coupled NAND gates Two cross-coupled NOR gates

 A B Or Nor
10 SR Latch 0
0
0
1
0
1
1
0
1 0 1 0
1 1 1 0
Active high
Present Next
10 state state
R 10
Q
S R Q0 Q Q’ Function
0 0 0 0 1 Q = Q0 Store
0 0 1 1 0 Q = Q0 (hold)
0 10 0 1 0 0 1 Q=0
Reset Put 0 in bit
0 1 1 0 1 Q=0
S 10Q
10 1 0 0 1 0 Q=1
1 0 Set Put 1 in bit
1 0 1 Q=1
1 1 0 0 0 Q = Q’
Forbidden
1 1 1 0 0 Q = Q’

To avoid
11 Timing Diagram Representation

R=0 R=0 R=1 R=0

Q Q Q Q
1 1 0 0
0 0 1 1

1 1 0 0
0 Q’ 0 Q’ 1 1
Q’ Q’

S=1 S=0 S=0 S=0

1
R
0
S 1
0
Q 1
0

Q’ 1
0

Gate delay Wire delay + Gate delay Time

Latch delay = wire delay + 2 gate delay

12 SR Latch with NOR
S R Q0 Q Q’
R 0 0 0 0 1
Q 1 0
0 0 1
0 1 0 0 1
0 1 1 0 1
1 0 0 1 0
Q 1 0 1 1 0
S 1 1 0 x x
1 1 1 x x

00 01 11 10
0 0 0 X 1 characteristic equation
1 1 0 X 1 Q(t+1) = S + R’ Q(t)
Next state Present state
Q+ Q
13 SR gated Latch
Similar to the SR latch but with the extra control input EN which enables or disables
the operation of the S and R inputs.
When EN=1, the gated SR latch operates as an SR latch.
When EN=0, S and R are disabled and the circuit persists in the preceding state.

EN S R Q Q+
R
0 x x 0 0
Q 0 x x 1 1
EN 1 0 0 0 0
1 0 0 1 1
Q 1 0 1 x 0
S 1 1 0 x 1
1 1 1 x NA
14 Takeaway
The fact:
Set-Reset (SR) Latch can store one bit and we can change the value of the stored bit.
But,
The problem:
SR Latch has a forbidden state.
Question:
How do we avoid the forbidden state of SR Latch?
Response:
Ensure that inputs S and R How ?

are never equal to 1 at the same time, D Latch

15 D Latch
D latch ensures that inputs S and R never equal to 1 at the same time.
10 R 01
D 10
Q
D Q
D S Q
0 0 1
R Q
S 10 1 1 0
10

Q+ = Q(t+1) = D

D Latch can change a value of bit like an SR Latch while avoiding the forbidden
state.
But, how can it store the bit? By using D Flip-Flop
16 D Latch
• Data (D) Latch D S Q
• Easier to use than an SR latch
R Q
• No possibility of entering an undefined state

• When D changes, Q changes immediately (…after a delay of 1 NOT gate and 2

NORs gates)

• SR latches are useful in control applications

• we often think in terms of setting or resetting a flag to some condition.
• D latches are useful to store bits of information
17 D Flip-Flop (D Latch with Clock)

D S Q
D Q

CLK cl R
k
TruthTable
Excitation Table clk D Q+
CLK D
0 0 Q
Store bit
↑ 0 0 1
0 1 Q
↑ 1 1 0 Reset bit
1 0 0 1
↑ : Rising Edge of Clock Set bit
1 1 1 0
18 D Flip-Flop: Example Timing Diagram
clock
period

1
CLK
0

1
D
0

1
Q
0
Clock to Q time (TC2Q) = Latch delay

Set Reset Reset Set Set Reset Reset

19 J K Latch
The SR latch can be modified to provide a stable state J when
Q both
inputs are 1 : use JK latch.
K
The “JK” is called in honor of his inventor Jack Kilby.

In the JK latch, the inputs J and K behave exactly like inputs S and R, But it provides a
stable state when both inputs are 1 (The output is complemented).
J K Q+
0 0 Qprev No change (hold
/store)
0 1 0 Reset (clear)
1 0 1 Set
1 1 Q Toggle

Q(t + 1) = JQ`(t) + K`Q(t)

20 J K Flip flop
JK Latch with clock J Q
CL
K
K

R clk J K Q+
K
Q 0 x x Q Store
1 0 0 Q Store
CL
K 1 0 1 0 Reset
J 1 1 0 1 Set
S
Q 1 1 1 Q Toggle
21 J/K Flip-Flop : Example Timing

1
CLK 0

1
K 0

1
J 0

1
Q 0

NO
SET TOGGLE TOGGLE CLEAR CHANGE SET
22 T flip-flop

T (Toggle or Trigger) Flip-Flop is a complementing synchronous flip-flop.

It can be designed using :

T
SR (Set-Reset) Flip-Flop
D (Data) Flip-Flop
JK Flip-Flop

T Q(t+1)
0 Q(t) No change
Q(t + 1) = T Q = TQ` + T`Q
1 Complement
23 Implementations of T flip flop
T flip-flop can be implemented using SR flip-flop

R
T Q
C
L
K S Q’

T flip-flop can be constructed with a D flip-flop and a XOR gate.

D Q
T

CL
K
24 Implementations of T flip flop

The T flip-flop can also be obtained from a JK flip-flop when inputs J and K are
tied together.

T J Q

CLK

K
25 Characteristic Equations

SR flip-flop Characteristic Equations

Q(t + 1) = S+ R`Q(t)
D flip-flop Characteristic Equations
Q(t + 1) = D

JK flip-flop Characteristic Equations

Q(t + 1) = JQ`(t) + K`Q(t)

T flip-flop Characteristic Equations

Q(t + 1) = T Q = TQ`(t) + T`Q(t)
26 Sequential circuit timing constraints
The Flip-Flop operates properly if the imput signal (Ex: D) is stable (that is, not
changing) at the time Clk goes from 0 to 1 (if rising edge). But it may lead to
unpredictable results if the input signal also changes at this time.

Constraint 1 : the input signal must be stable between setup time and hold time.
Setup Time (Tsetup): The minimum time duration for which the data input must be valid and stable
before the arrival of the clock edge.

Hold Time (Thold): The minimum time duration for which the data input must not be changed after
the clock transition occurs.
27 Sequential circuit timing constraints
Constraint 2 : (Clock and Setup Times) The following timing constraint is required for
correct operation of the sequential circuit :
Tclk ≥ Tclk2q + TCombinational + Tsetup

IF Tclk < Tclk2q + TCombinational + T setup THEN Setup time violation

Constraint 3 : (Hold Time) The following hold time constraint is required for correct
operation of Flip-Flop:
Thold ≤ Tclk2q + TCombinational

IF Thold > Tclk2q + TCombinational THEN Hold time violation

28 Example
FF A FF B
10 01 10 10 10
Comb
D1 Q1 Logic D2 Q2
CLK Q CLK Q
Timing constraint : ✔a
CLK ClktoQ time Comb Logic time Setup time Tclk = Tclk2q + TCombinational + Tsetup

Time Clock

CLK
Setup time Hold time Setup time Hold time

Stable Stable
D1
FF B Stable
D2
ClktoQ time
ClktoQ time

Q1
ClktoQ time
Q2
29 Setup time violation : Case 1 (FF A) Between Input and First Flip-Flop
FF A FF B
10 0 0 0
Comb
D1 Q1 Logic D2 Q2
CLK Q CLK Q

CLK ClktoQ time Comb Logic time Setup time

Time Clock

CLK
Setup time Hold time Setup time Hold time

D1
FF A Instable : Setup Time Violation
D2
Data stable for a
FF B Stable
period < setup time
Q1
ClktoQ time
Q2
 Low combinational

30 Setup time violation : Case 2 (FF B) Between logic

two Flip-Flops

FF A FF B
10 01 0
1 01 0
Comb
D1 Q1 Logic D2 Q2
CLK Q CLK Q

ClktoQ time Comb Logic time Setup Time violation Violation

CLK

Setup time Tclk < Tclk2q + TCombinational + Tsetup

Time Clock

CLK
Setup time Hold time Setup time Hold time
FF A Stable
D1 FF A Stable

FF B Stable
D2
ClktoQ time FF B Instable : Setup Time violation
Violation
Q1
ClktoQ time
ClktoQ time
Q2
31 Hold time violation : Case 1 (FF A) Between Input and First Flip-Flop
FF A FF B
010 0 0 0
Comb
D1 Q1 Logic D2 Q2
CLK Q CLK Q

CLK ClktoQ time Comb Logic time Setup time

Simulation during the
circuit design phase in
order to configure circuit’s Time Clock
times

CLK
Setup time Hold time Setup time Hold time

D1
FF A Instable : Hold Time Violation
D2
FF B Stable Data stable for a period < hold time (D1
Q1 changed the value before hold slack!!)
ClktoQ time
Q2
 Fast combinational

32 Hold time violation : Case 2 (FF B) Between two Flip-Flops logic

FF A FF B
0 Q1 passes through the fast logic and
10 01 1 01 0
Comb arrives too early at the input D2 of FF
D1 Q1 Logic D2 Q2 B, which leads to hold time violation
CLK Q CLK Q and metastability.

CLK ClktoQ time Comb Logic time Setup time Timing constraint : ✔a
Hold Time violation Violation
TCLK > Tclk2q + TCombinational + Tsetup
Thold > Tclk2q + TCombinational Time Clock

CLK D2 changed the value

Setup time Setup time Hold time
before hold slack
Hold time
(New data arrives early)
FF A Stable
D1 FF A Stable

D2
ClktoQ time FF B Instable : Hold Time violation
Violation
Q1
ClktoQ time

Q2
33
Finite State Machines
34 Finite State Machine
• The behavior of sequential circuits can be expressed by using Finite State Machines
(FSMs).
• FSM is an abstract model for describing a sequential circuit,
• FSM can be represented by :
• States-Transitions table : like truth table (Inputs, Present states, Next states, Outputs)
• States-Transitions diagram: consists of a set of nodes that hold the states of the circuit and a set of arcs
(transitions) that connect the states.
Q Input Q+ Output
Input / Output
Input Output
0 0 0 0
0 1 1 0
Flip-Flop 1 0 0 1
Q 1 1 1 0
State

States-Transitions Diagram States-Transitions table

35 Types of Finite State Machine
There are two types of FSMs : Mealy and Moore machines. They differ only in how they
express the outputs of the machine.

❑ Mealy state machine : the outputs are functions

of both the present state and the inputs of circuit.
• The outputs may change if the inputs change
during the clock pulse period.

❑ Moore state machine : the outputs

are only functions of the present
state of circuit.
36 Mealy FSM : Example
0 0 0
0
0

0
0
0 1 01

1
Mealy State diagram
Nodes : states Q1 Q2 Arcs: X / Y

1/1 0/0
0/0
n
• n Flip-Flops max 2 possible states (nodes)
1/1
0/0
1/1
37 Moore FSM : Example
0 0
0
0

0
0
1 01
1

Nodes : states Q1 Q2 / Y Arcs: X

Moore State diagram

38
Counters
39 Counters
• A counter is a sequential circuit. It just simply counts the clock pulses.

• It cycles through a specified number of states.

• It made up of n flip-flops which are interconnected by

combinatorial logic (gates).

• n-bit counter : n flip-flops, count in binary from 0 to 2ⁿ-1

-1

• Also called a modulus (MOD) m counter (2ⁿ < m ≤ 2ⁿ). (MOD m counter cycles through
m states).

• Ex : 2-bit up counter = MODComplete

4 counter or MOD
cycle
3 counter
Incomplete cycle

Unused state
40 Types of counters
• Two types of counters:
• Synchronous (parallel) counters
• A common clock signal is connected to all flip-flops

• Asynchronous (ripple) counters

• Ripple counters allow some flip-flop outputs to be used as a source of clock
for other flip-flops.
41 Synchronous up counters
The output value increases by one on each clock cycle, After the largest value, the output
If we use D flip-flops, then the D
“wraps around” back to 0. inputs will just be the same as the

• Ex : 2-bits up counter (synchronous counter modulus 4) (2 FF, 2² = 4 statenextnodes)

states

State Excitation
Table Table
Present State Next State Inputs excitation

Q1 Q0
Q+ = D
Q 1+ Q 0+ D1 D0
0 0 0 1 0 1
Q+ = D1= Q1 Q0 + Q1 Q0
0 1 1 0 1 0 1

1 0 1 1 1 1 Q+
0
= D0= Q0
1 1 0 0 0 0
42 Unused states
• The synchronous counter up shown so far is with complete cycle (2n states, n
flip-flops). But sometimes you may have unused states.
• For example, here is a state table and diagram for a 3-bit up counter that repeatedly
counts from 0 (000) to 5 (101)
• What should we put in the table for the two unused states?
Self-starting counter

1 1 0
To get the safest circuit
simplest circuit
1 1 1
43 Asynchronous counters
▪ Asynchronous counter is a set of JK Flip-Flops in toggle mode (j=k=1).
▪ Also known as ripple counter, as the input clock pulse “ripples” through the counter.
▪ The clock signal controls only the first Flip-Flop (LSB), and
▪ Output of the first Flip-Flop (LSB) is connected to the clock input of the next
more-significant Flip-Flop.
▪ And so on..
▪ Ex : 2-bit ripple counter
1
LSB MSB
Q0 Q1
J Q J Q
CLK

K K
44 2-bit ripple counter (Async. MOD 4 counter)
1
LSB MSB

J Q Q0 J Q1
Q
CLK

K K

TCLK
1 2 3 4
Timing diagram : Q 1Q 0
CLK 00 → 01 → 10 → 11 → 00 ...
T Q0
1 2
Q0
0 1 0 1 0 TQ1 = 2TQ0 = 4TCLK
T Q1 1 1/FQ1 = 2/FQ0 = 4/FCLK
Q1 0 0 1 1 0
FQ1 = FQ0 /2 = FCLK /4

▪ Output of the last flip-flop (MSB) divides the input clock frequency by the 2ⁿ (n :
number of FFs), hence a counter is also a frequency divider.
45 3-bit ripple counter (Async. MOD 8 counter)

1 LSB MSB

J Q Q0 J Q Q1 J Q Q2
CLK CLK CLK CLK

K K K

CLK 1 2 3 4 5 6 7 8

Q0

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2
0 0 0 0 1 1 1 1 0

Recycles back to 0
46 Unused states
▪ Also known as Asyn. Counters with MOD number (m) < 2n . States may be skipped
resulting in a truncated sequence.
▪ Technique: force counter to recycle before going through all of the states in the
sequence.
• MOD-6 counter produced by clearing (a 111 000
Temporary 001
MOD-8 binary counter) when count of state
six (110) occurs. 110
010

101 011
100
47
Registers
48 Basic register
A register is a set of Flips-Flops with sharing clock signal.

Each Flips-Flop stores one bit of information.

An n-bit register is built from n-Flips-Flops and stores n-bits of data.

EX : 4-bit Register with parallel Load (Parallel Inputs Parallel Outputs)

MSB LSB
49 Shift registers
• A shift register is a register with serial Load (Introduce bit by bit).
• It can move data from stage (Flip-Flop) to stage within the register, or into or out of
the register upon application of clock pulses.

• The shift register can perform a shift right or a shift left.

• Shift right : Move each bit one position right and Shift in 0 to leftmost bit.

• Shift left : Move each bit one position left and Shift in 0 to rightmost bit.
50 Shift registers : Implementation
• Connect each Flip-Flop’s output to next Flip-Flop’s input

• 4-bit Shift Right Register

MSB LSB
Serial data QA QB QC QD Serial data
input D Q D Q D Q D Q output
FF B FF C FF D
FF A

CLK

• 4-bit Shift Left Register

MSB LSB
QA QB QC QD
Serial data D Q D Q D Q D Q Serial data
output input
FF B FF C FF D
FF A

CLK
51 Bidirectional shift registers
• Data can be shifted either left or right, using a control line RIGHT/LEFT (or
simply RIGHT) to indicate the direction.
52 Universal shift register 74 194
▪ 4-bit bidirectional shift register with parallel load.

▪ Types of shift register :

Mode control

▪ SISO mode (Serial In Serial Out) S1 S0 Register op

0 0 No change

▪ SIPO mode (Serial In Parallel Out) 0 1 Shift right

1 0 Shift left
▪ PISO mode (Parallel In Serial Out) 1 1 Parallel load