EC18601-VLSI Design

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UNIT I
MOS TRANSISTOR PRINCIPLE 9
NMOS, PMOS -Enhancement and depletion MOSFET; MOS
transistor-Ideal I-V characteristics; Fabrication Process - MOSFET,
CMOS- n-well, p-well, Twin tub, SOI; Scaling principles and
fundamental limits; CMOS inverter characteristics; Stick diagram;
Layout diagrams ; Design rules; Layer Representation

UNIT II
COMBINATIONAL LOGIC CIRCUITS 9
Static CMOS Design: Examples of Combinational Logic Design;
Complementary CMOS concept and properties; Ratioed Logic -
DCVSL logic gate; Pass Transistor Logic - Concept, Complementary
PTL and Differential PTL; CMOS transmission gate; Elmores
constant; Dynamic CMOS design: Dynamic Logic - Basic Principles;
Issues in Dynamic Design; Cascading Dynamic Gates
UNIT III
SEQUENTIAL LOGIC CIRCUITS 9
Timing Metrics for Sequential Circuits; Static Latches and Registers;
Bi-stability Principle; Multiplexer Based Latches; Master-Slave based
Edge Triggered Register; Non-ideal clock signals; Dynamic Latches
and Registers; Transmission-Gate Edge-triggered Registers; C2MOS
Register; Dual-Edge Registers; True Single-Phase Clocked Register
(TSPCR) Timing issues; Pipelines; Clock Strategies; Synchronous
and Asynchronous design- Low power design principles

UNIT IV
DESIGNING ARITHMETIC BUILDING BLOCKS 9
Data path circuits; Architectures for Ripple Carry Adders; Carry Look
Ahead Adders; Carry Select Adder; Carry Bypass Adder; High speed
adders - Brunt Kung adder, Kogge Stone; Multipliers - Wallace Tree
multiplier, Booth Multiplier; Barrel shifters; Speed and Area Trade-
off for all above Arithmetic Building Blocks
UNIT V
IMPLEMENTATION STRATEGIES 9
Full custom and Semi-custom design; Standard cell design and
cell libraries; FPGA building block architecture - FPGA
interconnect routing procedures; Design for Testability: Ad Hoc
Testing, Scan Design, BIST
TEXTBOOKS:
1. Jan M Rabaey, Anantha Chandrakasan, B. Nikolic, “Digital
Integrated Circuits: A Design Perspective”, Second Edition,
Prentice Hall of India, 2003. (Unit-1 to Unit-4)

2. M.J. Smith, “Application Specific Integrated Circuits”, Addisson

Wesley, 1997 (Unit-5)

REFERENCES:
3. N.Weste, K.Eshraghian, “Principles of CMOS VLSI Design”,
Second Edition, Addision Wesley 1993 (Unit-1 to Unit-4)

4. R.Jacob Baker, Harry W.LI., David E.Boyee, “CMOS Circuit

Design, Layout and Simulation”, Prentice Hall of India 2005

5. A.Pucknell, Kamran Eshraghian, “BASIC VLSI Design”, Third

Edition, Prentice Hall of India, 2007.
 UNIT I MOS TRANSISTOR PRINCIPLE
Syllabus
- NMOS, PMOS, Enhancement and depletion MOSFET
- MOS transistor-Ideal I-V characteristics
- Fabrication Process - MOSFET, CMOS
- n-well, p-well, Twin tub, SOI,
- CMOS inverter characteristics,
- Stick diagram, Layout diagrams,
- Scaling principles and fundamental limits

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 MOS Transistor

An MOS transistor is a majority-carrier (Unipolar) device, in which

the current in a conducting channel between the source and
drain is modulated by a voltage applied to the gate.

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MOS Transistor Symbols
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

Source Gate Drain

Polysilicon
SiO2

p+ p+

n bulk Si

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V-I Characteristics of MOS Transistor
Drain-to-Source Current Ids versus
Drain-to Source Voltage Vds relationship

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Difference Between Electric field and Electric Potential

1. Electric field is described as the amount of force per charge (that acts
between two charges) while the Electric potential is described as the amount
of energy or work per charge (amount of work to be done to move a charge
from one place to another without causing any acceleration).

2. Electric field is measured in Newtons per Coulomb or Volts per meter

while Electric Potential is measured in unit Volts or Joules per Coulomb

3. Electric field is a vector quantity while Electric potential is a scalar

quantity.

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 Drain-to-Source Current Ids versus
Drain-to Source Voltage Vds relationship (continued…..)

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 Drain-to-Source Current Ids versus
Drain-to Source Voltage Vds relationship (continued…..)

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 Drain-to-Source Current Ids versus
Drain-to Source Voltage Vds relationship (continued…..)

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Drain-to-Source Current Ids versus Drain-to Source Voltage Vds relationship(continued…..)

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 Drain-to-Source Current Ids versus
Drain-to Source Voltage Vds relationship (continued…..)

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 Drain-to-Source Current Ids versus
Drain-to Source Voltage Vds relationship (continued…..)

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 The MOS Device Design Equation

Process
Three regions of operation (Ideal First Orderparameter and
Equations)
Device geometry

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The MOS Device Design Equation

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❖This is called Channel Length Modulation

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 Channel Length Modulation
• Reverse-biased p-n junctions form a depletion region
• Region between n and p with no carriers
• Width of depletion Ld region grows with reverse bias
• Leff = L – Ld
GND VDD VDD
• Shorter Leff gives more current Source Gate Drain
Depletion Region
• Ids increases with Vds increase Width: Ld
• Even in saturation
n L n
+ Leff +
p GND bulk Si

4: Nonideal Transistor Theory 27