STATE INSTITUTE OF ENGINEERING & TECHNOLOGY

NILOKHERI

Laboratory File of
Verilog HDL Lab
(EC-308LA)
Jan-May, 2024

DEPARTMENT OF
ELECTRONICS & COMMUNICATION ENGINEERING

Submitted to:- Submitted by:-

Dr. Shiv Kumar Name:
AP,ECE Department Roll No.
 INDEX

S.No. NameofExperiment DateofExperiment Signature

1. WriteaProgramtoimplementlogicgates and
verify using a test bench.

2. WriteaProgramtoimplementhalf-adder and
verify using a test bench.

3. WriteaProgramtoimplementFull-adder and
verify using a test bench.

4. Write a Program to implement 4 bit

additionandverifyusingatestbenchand
verify using a test bench.

5. Write a Program to implement an 8:1

multiplexerandverifyusingatestbench.

6. Write a Program to implement a 1:8

demultiplexerandverifyusingatestbench.

7. WriteaProgramtoimplementaflip flops.

8. WriteaProgramtoimplementcode
convertors.

9. WriteaProgramtoimplementupdown
counter.

10. WriteaProgramtoimplement4bit ALU.

 ExperimentNo:- 1

Aim:-Writeaprogramtoimplementlogic-gatesandverifyusingatestbench .

SoftwareUsed:-Xilinx

DesignSource Code:
modulelogic_gates(input in1,inputin2,outputout1,output
out2,output out3, output out4, output out5, output out6);and
g1(out1,in1,in2);
or g2(out2,in1,in2);
xor g3(out3,in1,in2);
nandg4(out4,in1,in2);
nor g5(out5,in1,in2);
buf g6(out6,in1);
endmodule

SimulationSourceCode:
moduletest_logicgates();
reg in1,in2;
wire out1,out2,out3,out4,out5,out6;
logic_gatestest(in1,in2,out1,out2,out3,out4,out5,out6);
initial
begin
in1=0;
in2=1;#10i
n1=1;
#15in2=0;
end
initial
$monitor($time,"in1=%b,in2=%b,out1=%b,out2=%b,out3=%b,out4=%b,out5=%b,out6=%b"
,in1,in2,out1,out2,out3,out4,out5,out6);
initial #50 $stop;
endmodule
Schematic Diagram

Waveform

Result:-Wehave verifiedtheoperationsoflogicgates.
 ExperimentNo:- 2

Aim:-Writeaprogramtoimplementhalf-adderand verifyusingatest bench.

SoftwareUsed:-Xilinx

DesignSourceCode:-

modulehalf_adder(inputa,inputb,outputsum,output carry); xor

g1(sum,a,b);
andg2(carry,a,b);
endmodule

SimulationSourceCode:-

modulehalf_adder_sim();
reg a,b;
wiresum,carry;
half_adder_test gates(a,b,sum,carry);
initialbegina=0;b=1;#10a=1;#15b=0; end
initial
$monitor($time,"a=%b,b=%b,sum=%b,carry=%b",a,b,sum,carry);initial#50
$stop;
endmodule

Schematic Diagram:-

Waveform:-
Result:- Wehaveverified theoperationsofhalf-adderusingatestbench.
 ExperimentNo:- 3

Aim:-Writeaprogramtoimplementfull-adderandverifyusingatestbench.

SoftwareUsed:-Xilinx

DesignSourceCode:-modulefull_adder(inputa,inputb, inputc,wirew1,wire w2, wire

w3, output sum, output carry);
xorg1(w1,a,b);
andg2(w2,a,b);
andg3(w3,w1,c);
xorg4(sum,w1,c);
org5(carry,w2,w)
endmodule

Simulationsourcecode:m module
full_adder_sim( );
rega,b,c;
wire sum,carry; full_adder
test1(a,b,c,sum,carry); initial
begina=0;b=0;c=1;#10a=1; #20
b=1;
#30c=1;
end
initial
$monitor($time,"a=%b,b=%b,c=%b,sum=%b,carry=%b",a,b,c,sum,carry);
initial #80 $stop;
endmodule
Schematic Diagram

Waveform:-

Result:-Wehavetheworkingoffulladderusingatestbench.
 ExperimentNo:- 4

Aim:-Writeaprogramtoimplement4bit-adderandverifyusingatestbench.

SoftwareUsed:-Xilinx

DesignSourceCode:
//DesigningfullAdder
modulefull_adder(inputa,inputb,inputc,outputsum,outputcarry); wire w1;
wire w2;
wirew3;
xorg1(w1,a,b);
andg2(w2,a,b);
andg3(w3,w1,c);
xor g4(sum,w1,c);
org5(carry,w2,w3);
endmodule

//Designing4bit-adderUsingfulladder
module four_bit_adder( input [3:0] a,
input [3:0] b, input cin, output [3:0] sum,
output cout);
wirec1,c2,c3;
full_adderfa0(a[0],b[0],cin,sum[0],c1);
full_adderfa1(a[1],b[1],c1,sum[0],c2);
full_adderfa2(a[2],b[2],c2,sum[0],c3);
full_adderfa3(a[3],b[3],c3,sum[0],cout);
endmodule

SimulationSourceCode:
modulesim_four_bit();
reg [3:0] a;
reg [3:0] b;reg
cin;
wire[3:0]sum;
wire Cout;
four_bit_adderdut(a,b,Cin,sum,cout);
initial
begin
a=4'b0011;b=4'b0011;cin=1'b0;#10; a
=4'b1011;b=4'b0111;cin = 1'b1; #15;
a=4'b1111;b=4'b1111;cin=1'b1;#120;
end
endmodule
Schematic Diagram:-

Simulation Waveform:-

Result:-Wehavetheworkingof4bit-adderusingfulladderandverified usingatest bench.

 ExperimentNo:- 5

Aim:-Writeaprogramtoimplementan8:1multiplexerandverifyusingTest-bench.

SoftwareUsed:-Xilinx

DesignSourceCode:-module mux_8to1(input D0,D1,D2,D3,D4,D5,D6,D7,S0, S1, S2,

output out);
wireT1,T2,T3,T4,T5, T6,T7,T8,T9,T10T11; not(T1, S0);
not(T2, S1); not(T3, S2);
and(T4,D0,T1,T2,T3),(T5,D1,S0,T2,T3);
and(T6,D2,T1,S1,T3),(T7,D3,S0,S1,T3);
and(T8,D4,T1,T2,S2),(T9,D5,S0,T2,S2);
and(T10,D6,T1,S1,S2),(T11,D7,S0,S1,S2);
or(out,T4,T5,T6,T7,T8,T9,T10, T11);
endmodule

SimulationSourceCode:-module
sim_mux();
wireout;
regD0,D1, D2, D3, D4,D5, D6, D7,S0, S1,S2;
mux_8to1mux(D0,D1,D2,D3,D4,D5,D6,D7,S0,S1,S2,out);
initial
begin
D0=1'b0;D1=1'b0;D2=1'b0;D3=1'b0;D4=1'b0;D5=1'b0;D6=1'b0;D7=1'b0;S0=1'b0; S1=1'b0;
S2=1'b0;
#500$finish;
end
always#1 D0=~D0;
always#2D1=~D1;
always#3 D2=~D2;
always#4 D3=~D3;
always#5 D4=~D4;
always#6 D5=~D5;
always#7 D6=~D6;
always#8 D7=~D7;
always#9S0=~S0;
always#10 S1=~S1;
always#11 S2=~S2;
always@(D0or D1orD2or D3orD4orD5orD6or D7orS0or S1orS2)
$monitor("Attime=%t,Output=%d",$time,out); endmodule
Schematic Diagram:-

Simulation
 ExperimentNo:- 6

Aim:-Writeaprogramtoimplementan1:8DemuxandverifyusingTest-bench.

SoftwareUsed:-Xilinx

DesignSourceCode:-moduledemux1to8(inputd,input s0,input s1,input s2, outputy1, output y2,

output y3, output y4, output y5, output y6, output y7, output y8);
not (s0n,s0),(s1n,s1),(s2n,s2);
and(y1,d,s0n,s1n,s2n),(y2,d,s0,s1n,s2n),(y3,d,s0n,s1,s2n),(y4,d,s0,s1,s2n),
(y5,d,s0n,s1n,s2),(y6,d,s0,s1n,s2),(y7,d,s0n,s1,s2),(y8,d,s0,s1,s2);
endmodule

Schematic Diagram:-
 ExperimetNo:-7

AIM: Write a program in verilog to implement flip flops

JKFLIP FLOP

moduleJK_Flip_Flop(Q,Qbar,clk,reset,J,K); output
Q,Qbar;
inputclk,reset,J,K;
reg Q;
always@(posedgeclk)
if (reset)
beginQ
<=0;
end
else if(J==0&&K==0)
begin
Q <=Q;
end
else if(J==0&&K==1)
begin
Q <=0;
end
else if(J==1&&K==0)
begin
Q <=1;
end
else if(J==1&&K==1)
begin
Q<=Qbar;
end
assignQbar=~Q;
endmodule

SRFLIP FLOP

moduleSR_Flip_Flop(Q,Qbar,clk,reset,S,R); output
Q,Qbar;
inputclk,reset,S,R;
reg Q;
always@(posedgeclk)
if (reset)
beginQ
<=0;
end
else if(S==0&&R==0)
begin
Q <=Q;
end
elseif(S==0&&R==1)
begin
Q <=0;
end
elseif(S==1&&R==0)
begin
Q <=1;
end
elseif(S==1&&R==1)
begin
Q <=1'bx;
end
assignQbar=~Q;
endmodule

DFLIP FLOP

moduleD_Flip_Flop(Q,clk,reset,d);
output Q;
inputclk,reset,d;
reg Q;
always@(posedgeclk)
if (reset)
beginQ
<=0;
end
elsebegin
Q <= d;
end
endmodule

TFLIPFLOP

moduleT_Flip_Flop(Q,clk,reset,t);
output Q;
inputclk,reset,t;
reg Q;
always@(posedgeclk)
if (reset)
beginQ
<=0;
end
elseif(t==0)
begin
Q <=Q;
end
elseif(t==1)
begin
Q <=~Q;
end
endmodule
 ExperimetNo:-8

AIM:Writeaprograminverilogto implement codeconverters

BCD TO GRAY

modulebcd2gray(Gray,BCD);
output [3:0]Gray;
input [3:0]BCD;
reg [3:0]Gray;
always @(BCD)
begin
Gray[3]=BCD[3];
Gray[2]=BCD[3]^BCD[2];
Gray[1]=BCD[2]^BCD[1];
Gray[0]=BCD[1]^BCD[0];
end
endmodule

GRAY TOBCD
modulebcd2gray(Gray,BCD);
output [3:0]BCD;
input[3:0]Gray;
reg [3:0]BCD;
always @(Gray)
begin
BCD[3]=Gray[3];
BCD[2]=BCD[3]^Gray[2];
BCD[1]=BCD[2]^Gray[1];
BCD[0]=BCD[1]^Gray[0];
end
endmodule
 ExperimetNo:- 9

AIM:Writeaprograminverilogtoimplementupdowncounter

Verilogcodeforupdown counter

moduleup_down_counter(out,up_down,clk,reset);
output [7:0] out;
inputup_down,clk,reset;
reg [7:0] out;
always@(posedgeclk)
if(reset)begin//activehighreset out
<= 8'b0 ;
endelseif(up_down)begin out
<= out + 1;
endelsebegin
out<=out-1;
endendmodule
 ExperimetNo:-10

AIM: Write a program in verilog to implement 4 bit ALU

Verilog code for 4 bit ALU

modulealu(z,a,b,sel);
input [8:0]a,b;
input[3:0]sel;
output[8:0]z;
reg [8:0]z;
always@(sel,a,b)
begin
case(sel)
4′b0000:z=a+b;
4′b0001: z=a-b;
4'b0010:z=b-1;
4′b0011:z=a*b;
4′b0100:z=a&&b;
4′b0101:z=a||b;
4′b0110:z=!a;
4′b0111:z=~a;
4′b1000:z=a&b;
4′b1001:z=a|b;
4′b1010:z=a^b;
4′b1011:z=a<<1;
4′b1100:z=a>>1;
4′b1101:z=a+1;
4′b1110:z=a-1;
endcase
end
endmodule