IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO.
3, SEPTEMBER 2007 509
Understanding of Delamination Mechanism of
Anisotropic Conductive Film (ACF) Bonding
in Thin Liquid Crystal Display (LCD) Module
Bin Xie, Xun Qing Shi, and Han Ding
Abstract—The chip-on-glass (COG) technique using anisotropic
conductive film (ACF) has been developed for liquid crystal display
(LCD) panels with excellent resolution and high quality for several
years. However, many serious manufacturability and reliability
issues were observed from previous studies. In those, delamination
occurring at the ACF interface is one of the common concerns. Few
works presented analysis of delamination mechanism through the
whole COG bonding process with the combination of LCD module
scale and ACF interconnect scale. In this paper, the delamination
mechanism of COG/ACF interconnection was studied by using
finite element analysis. Equivalent block and global-local mod-
eling methods were implemented with nonlinear elastic-plastic
and sequential coupled thermal-mechanical analysis. The crit-
ical parameters of the COG bonding process and geometry of
integrated circuit (IC) and glass were investigated to understand
the mechanism of ACF delamination. It was found that the
delamination could be reduced by decreasing the temperature
difference between bonding head and glass substrate or using thin
and short IC. The local model analysis revealed that the interface
of glass/ACF epoxy encountered the higher stress than that in
the interface of IC/ACF epoxy and had the higher possibility to
delaminate. Therefore, increasing the bonding-strength between
glass and ACF epoxy is the direction to reduce the probability of
ACF delamination.
Index Terms—Anisotropic conductive film (ACF), chip-on-glass
(COG), delamination mechanism, finite element analysis (FEA),
global-local modeling.
I. INTRODUCTION
HE chip-on-glass (COG) technique using anisotropic
T conductive film (ACF) is widely used in the liquid crystal
display (LCD) industry, because of its compactness, reliability,
process simplicity, and environmental friendliness. In the COG
technique, the driver integrated circuit (IC) is directly mounted
on the LCD module by flip chip technology using ACF. The
electrical connections are established between Au bumps of IC
Manuscript received July 18, 2006; revised December 21, 2006. This work
was supported by the National Natural Science Foundation of China under
Grants 50575133, 50390060, 10572010, and km200610005013. This work
was recommended for publication by Associate Editor K.-N. Chiang upon
evaluation of the reviewers comments.
B. Xie and H. Ding are with the Advanced Electronic Manufacturing Center,
School of Mechanical Engineering, Shanghai Jiao Tong University, Shanghai
200030, China.
X. Q. Shi is with the College of Mechanical Engineering and Applied Elec-
tronics Technology, Beijing University of Technology, Beijing 100022, China
(e-mail: xqshi@ieee.org).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCAPT.2007.898697
1521-3331/$25.00 © 2007 IEEE
and indium tin oxide (ITO) tracks of glass through conductive
particles within the ACF and the mechanical interconnections
are maintained by the adhesive through the COG bonding
process [1]. However, because the interconnect between the
bumps and the ITO tracks is through contact instead of sol-
dering, the delamination was often found to occur at the ACF
interface, which could lead to serious display defects.
The root cause of ACF interface delamination is complicated
and various causes were reported in recent literatures, such as
tensile stress due to moisture absorption [2], reflow treatment
performed after bonding [3], residual compressive stress due to
high bonding pressure [4] and oxidation formation of conduc-
tive particles [5]. However, few works presented the analysis of
the delamination mechanism through the whole COG bonding
process and took both the whole LCD module scale and the
local Au bumps and the particles in the ACF into consideration,
resulting in the poor understanding of the effects of the COG
bonding process parameters and the LCD module geometry on
the stress distribution and ACF interface delamination behavior.
In this study, a half LCD module was modeled by imple-
menting the equivalent block method with the nonlinear elastic-
plastic and sequential coupled thermal-mechanical analysis. A
local model of critical Au bump area was developed with global-
local method. With the models, the ACF delamination mech-
anism was investigated from both global and local scale. The
effects of the COG bonding process parameters, LCD module
geometry, and the ACF epoxy material were analyzed in a sys-
tematic manner and the possible solutions for reducing the ACF
interface delamination probability were recommended.
II. FE MODELING OF COG BONDING PROCESS
In the COG bonding process, after a thin layer of ACF mate-
rial is aligned on a glass substrate, a high bonding head temper-
ature and relatively low glass substrate temperature are applied
on the IC chip and glass substrate, respectively. Mechanical
pressure is subsequently applied to deform the conductive parti-
cles which are randomly distributed in the ACF epoxy. After the
ACF epoxy is cured, the heat and pressure are released and per-
manent electrical and mechanical connections are established
by the deformed conductive particles between Au bumps of the
IC and ITO tracks of the glass substrate.
In order to simulate the COG/ACF bonding process described
above, several assumptions were made in this study.
1) Heat transfer analysis was based on 3-D transient heat
transfer theory.
2) The LCD module was exposed to the air during COG/ACF
bonding process.
510 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 3, SEPTEMBER 2007

Fig. 2 FE models with (a) 21 conductive particles and (b) the equivalent block.

Fig. 1 Thermal-mechanical loading profile used for FEA. about twenty-one in the average trapped by each Au bump in this
case. If all particles under each Au bump were simulated, the
numerical model would be extremely huge and the simulation
could not be run with a normal workstation. To simplify the nu-
3) The number of conductive particles trapped under each
merical model without losing the accuracy of stress distribution
bump was constant.
in the global scale, an equivalent block was constructed to repre-
4) In the steps of ACF uncured and cured, the temperature
sent the 21 particles under each Au bump. To determine elastic
distribution in the ACF was in steady state.
modulus of equivalent block, FE models were established for
5) No chemical reaction was considered during ACF curing.
both the 21 particles and equivalent block, as shown in Fig. 2.
With the assumptions above, the numerical simulation
The material properties of Au, Ni, and polymer inside particle
methodology was established to simulate the COG/ACF
involved in the models are listed in Table I. The glass was treated
bonding process. As shown in Fig. 1, it is comprised of four
as a rigid body. Experimental tests showed that during the par-
major steps.
ticle deformation, the ACF epoxy became liquid, so the pres-
1) Temperature application with transient heat transfer: A
sure undertaken by the ACF epoxy could be ignored. The ACF
high bonding head temperature and relatively low glass
epoxy surrounding the particles was removed in the models.
substrate temperature were applied on the top surface of
The simulation results showed that when the elastic modulus
IC and bottom surface of glass, respectively. Under the
of the equivalent block was set as 1 GPa with the pressure of
thermal loading, the heat was transferred to the ACF layer
100 MPa, the mechanical response of the equivalent block ex-
from both the top surface of the IC and the bottom surface
hibited quite similar behavior as that of the particles, as shown
of the glass.
in Fig. 3. Similarly, the simulations were performed for different
2) Particle deformation: When the temperature reached the
pressures. The displacement of Au bump center contacting par-
setting point, uniform pressure was applied onto the top
ticle and contacting equivalent block was plotted in Fig. 4. As
surface of the IC. Under the thermal-mechanical loading,
can be seen, within the pressure range of 40 100 MPa, which
the ACF epoxy became liquid and filled into all the gaps
is usually adopted for COG bonding, the equivalent block could
between the IC and glass, meanwhile the conductive parti-
represent the mechanical response of all the twenty-one parti-
cles were deformed.
cles well.
3) ACF curing: Under the thermal-mechanical loading, the
It was noted that the heat transferred from the bump to
ACF epoxy started to cure. By remaining the loading for
the glass through the nickel coating during the COG bonding
certain time, the whole ACF could cure to a certain degree
process. Therefore, coefficient of thermal expansion (CTE) and
to enhance the interconnect established between the Au
thermal conductivity of the equivalent block were the same as
bumps and ITO tracks. Meanwhile, the stress redistributed
those of nickel. It was the nickel coating that contacted with the
over the whole ACF layer and the regions close to the ACF
bump and the glass, so the yield stress of equivalent block was
layer within the IC chip and glass substrate, respectively.
also the same as that of nickel.
4) Thermal-mechanical loading release: The mechanical
pressure and thermal loading were removed. The LCD B. LCD Module Modeling
module was cooled down to room temperature. The in-
terconnect between IC and glass was formed. The stress With the equivalent block method, a half LCD module
redistributed further over the ACF layer and both IC chip was modeled with the nonlinear elastic-plastic analysis using
and glass substrate would warp. ABAQUS code of version 6.4-4, as shown in Fig. 5. The model
consisted of six different materials, namely, glass, IC chip, ACF
A. Equivalent Block Method epoxy, Au bump, equvalent block, and liquid crystal, whose
properties were obtained from [6]–[9], as listed in Table I.
With the optical microscope, the number of conductive par- Totally, 116 000 elements and 145 000 nodes were used in the
ticles (nickel-coated polymer particles in this study) trapped by model.
each Au bump was counted for different COG bonding con- Since ACF epoxy is sensitive to temperature, it was treated
ditions. It was found when the ACF material and the size and as temperature-dependent material. The rest materials were
layout of the Au bump were fixed, the number of conductive treated as temperature-independent materials. The Au, ACF
particles was less dependent on the bonding conditions and was epoxy and equivalent block were modeled as elastic-plastic
XIE et al.: UNDERSTANDING OF DELAMINATION MECHANISM 511

TABLE I
SUMMARY OF MATERIAL PROPERTIES USED FOR FE MODELS

The properties of materials were obtained from refs. [6]–[9].

Fig. 3 Y direction displacement obtained by setting the elastic modulus of equivalent block as 1 GPa at the mechanical loading condition of 100 MPa: (a) the
detailed 21 conductive particles and (b) the equivalent block.

Fig. 4 Comparison of mechanical response predicted by the two FE models

with the 21 particles and equivalent block.
materials, while all the other materials were considered as
linear elastic materials.
The symmetric -surface was constrained with XSYMM
1 2 3 0 , the bottom -surface of glass
was constrained by 3 0, and the original point o was fixed
to avoid all the movement and rotation. At the last step, when
the thermal-mechanical loading was removed, the constraint of
bottom surface of glass was released to allow the module warp
freely. The bonding time of all the conditions was fixed as 6 s.
Fig. 5 FE model used in this study: (a) half LCD module and (b) zoom-in FE
model for the outmost input of IC (ACF epoxy and glass were removed for
clarity.).
C. Sequentially Coupled Thermal-Mechanical Method
Sequentially coupled thermal-mechanical analysis was per-
formed by first solving the pure transient heat transfer problem
with the heating up and cooling down process, then reading the
temperature solution of steady state and cooling down process
into the mechanical analysis as a predefined field.
512 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 3, SEPTEMBER 2007
The basic energy balance is [10]
(1)
where is a volume of solid material, with surface area ; is
the density of the material; is the internal energy rate; is the
heat flux per unit area of the body flowing into the body; and
is the heat supplied externally into the body per unit volume.
Heat conduction is assumed to be governed by the Fourier
law [10]
(2)
where is the thermal conductivity, is the heat flux and is
the temperature of the material. is the position , and for
three dimensions.
From (1) and (2), the standard Galerkin approach can be ob-
tained as
(3)
For the cooling down process, radiation boundary condition
can be specified as [10]
(4)
where is the radiation constant (emissivity times the
Stefan–Boltzmann constant), is the absolute zero on the
temperature scale and is the sink temperature. Because the
heat radiates to the ambient mainly through the surfaces of IC
and glass, the emissivities of IC (0.88) and glass (0.94) [11]
were used in this study.
An implementation of Newton’s method involving a Jacobian
matrix is illustrated in the following matrix representation of the
coupled equations [10]
(5)
where and are the respective corrections to the incre-
mental displacement and temperature, respectively; and
are the submatrices of the coupled Jacobian matrix and
is the mechanical residual vector.
III. DELAMINATION MECHANISM AND SOLUTIONS
A. Global Delamination Mechanism Analysis
Two parameters dominate the ACF interconnect delamina-
tion, i.e., ACF bonding-strength and interface separation stress
level. The bonding-strength mainly depends on the material
property of ACF, hence when ACF material is selected, the
delamination behavior is mainly governed by the interface
separation stress.
After bonding, when the temperature was cooled down, both
IC chip and glass substrate shrinked due to temperature de-
crease. The shrinkage rate depends on CTE and temper-
ature difference
(6)
Fig. 6 Schematic diagram shows (a) the LCD module warpage and (b) zoom-in
local stress distribution of region highlighted in (a).
In this study, the CTE values of IC and glass were close, as
given in Table I. However, the IC chip experienced much more
temperature drop than that of the glass substrate, which indi-
cated that the shrinkage of the IC chip was much more than
that of the glass substrate when the LCD module was cooled
down to room temperature. The shrinkage difference between
the IC chip and glass substrate would result in the IC chip and
glass substrate warping together. However, the glass substrate
was constrained by the big glass, where there was no heating
in the bonding process and the temperature was close to room
temperature. It meant that the warpage of the glass substrate was
limited and smaller than that of the IC chip. The difference in
the shinkage and warpage could generate big shear stress and
tensile stress, the major contributions to the von Mises stress,
on the ACF interconnect, as shown in Fig. 6. When the resul-
tant of the shear stress and tensile stress was bigger than the
ACF bonding-strength locally, the interconnect would open and
delamination could in principle occur. The IC warpage is the
global effect of inter-laminar stress. Larger warpage of IC indi-
cated larger resultant stress and more probability of delamina-
tion if the ACF material was selected. Hence, in the following
study, when the effects of the COG bonding parameters and the
LCD module geometry on ACF interconnect delamination were
investigated, the warpage was used as the indicator of delami-
nation probability and it could be queried from the results of
simulation directly.
B. Simulation Results Analysis and Solutions
Three major COG bonding parameters, i.e., the bonding
head temperature (BHT), glass substrate temperature (GST)
and bonding force (BF), and three major LCD module geometry
parameters, i.e., the IC length, IC thickness and glass thickness,
were investigated. The simulation program is summarized in
Table II.
The simulation results showed that although the stress redis-
tributed and both IC chip and glass substrate warped at the steps
of particle deformation and ACF curing, the influence of these
two steps on LCD module warpage was small. While when the
thermal-mechanical loading was removed and the LCD module
cooled down to room temperature, the IC chip and glass sub-
strate warped severely. Fig. 7 shows the warpage behavior of
LCD module at the condition of BF 139 N/BHT 280 C/ GST
120 C. The value of the IC warpage was 9.24 m, which was
queried from the simulation result. The IC warpage was also
measured using the warpage measurement system (WMS) at the
same condition, which applies the digital image speckle corre-
lation technique [12]. Fig. 8 shows typical IC warpage pattern
XIE et al.: UNDERSTANDING OF DELAMINATION MECHANISM
TABLE II
VALUES OF COG BONDING PARAMETERS AND LCD MODULE GEOMETRY PARAMETERS
Fig. 7 Warpage of LCD module at the condition of BF 130 N/BHT
280 C/GST 120 C with scale factor of 50.
Fig. 8 IC warpage pattern measured using warpage measurement system
(WMS) at the condition of BF 130 N/BHT 280 C/GST 120 C.
measured using WMS, in which the value of the IC warpage was
9.93 m. The good correlation between the simulation and the
experiment verified the global model.
When the BHT and GST were set as 280 C and 120 C,
respectively, the BF varied from 130 N to 208 N as listed in
Table II. The simulation results showed that the effect of BF on
the IC warpage was small and could be ignored.
When the BF and GST were set as 169 N and 120 C, re-
spectively, the BHT varied from 280 C to 330 C as listed in
Table II. The relationship of BHT and IC warpage is shown in
Fig. 9. As seen, the IC warpage increased with the increasing
BHT, exhibited an approximately linear relationship with BHT
in the lower temperature range but became less dependent on the
BHT when the temperature reached to certain level, as shown in
Fig. 9.
When the BF and BHT were set as 169 N and 280 C, respec-
tively, the GST varied from 60 C to 120 C as listed in Table II.
The effect of GST on the IC warpage is shown in Fig. 9. As seen,
the IC warpage decreased linearly with the increasing GST.
Further study showed that IC warpage was mainly dominated
by the bonding temperature difference (BTD), i.e., the differ-
ence of BHT and GST. As shown in Fig. 9, the IC warpage had
an approximately linear relationship with the BTD. Less BTD
could reduce IC warpage as well as probability of delamination
513
Fig. 9 Relationship of bonding head temperature (BHT), glass substrate tem-
perature (GST) and bonding temperature difference (BTD) with IC warpage.
Fig. 10 Relationship of IC length with IC warpage.
effectively. It is because that less BTD could cause less expan-
sion and shrinkage mismatch between the IC and the glass and
less residual von Mises stress inside ACF interconnection.
According to the development trend of display technology,
the LCD module will be made thinner with more functions. The
IC and glass geometry will be miniaturized and are believed to
be critical factor that may cause serious ACF interconnection
reliability issues.
To study the effect of IC and glass geometry on IC warpage,
the COG bonding parameters were set as constant, i.e., BHT
280 C, GST 120 C and BF 208 N. When the glass thick-
ness and IC thickness were set as 300 m and 380 m, respec-
tively, the IC length varied from 11.6 mm to 20.6 mm as listed
in Table II. It was found that longer IC would cause larger IC
warpage. The relationship of the IC length and the IC warpage
was almost linear, as shown in Fig. 10.
When the glass thickness and IC length were set as 300 m
and 20.6 mm, respectively, the IC thickness varied from 85 m
514 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 3, SEPTEMBER 2007
Fig. 11 Relationship of IC thickness and glass thickness with IC warpage.
Fig. 12 Effect of bonding head temperature (BHT), glass substrate temperature
(GST), IC thickness, and IC length on IC warpage.
to 380 m as listed in Table II. As shown in Fig. 11, the
IC warpage decreased linearly with decreasing IC thickness.
When the IC was ultrathin, the IC warpage could be reduced
significantly.
To investigate the effect of glass thickness on the IC warpage,
the IC thickness and IC length were set as 380 m and 20.6 mm,
respectively, and the glass thickness was increased from 150 m
to 300 m as listed in Table II. As shown in Fig. 11, the IC
warpage increased linearly when the glass thickness decreased
from 300 m to 200 m because of less glass stiffness with the
decrease of glass thickness. However, the IC warpage increased
dramatically when the glass thickness decreased from 200 m
to 150 m, which meant the ultrathin glass would cause very
big IC warpage.
Based on the analysis above, the IC warpage as well as de-
lamination probability could be reduced by decreasing the tem-
perature difference between bonding head and glass substrate as
well as using thin and short IC chip. The effect of BHT, GST, IC
thickness and IC length on the IC warpage is shown in Fig. 12
by co-locating the middle point of four lines, which was interpo-
lated with the second and third variations. It was noted that the
symmetrical curve of GST was plotted according the axis to
locate all the curves in the same quadrants (one and three quad-
rants in this study), although the IC warpage decreased with the
increment of GST. As seen from Fig. 12, BHT significantly af-
fected the IC warpage, followed by IC thickness, GST and IC
length. It indicates that BHT is the most important parameter
Fig. 13 Warpage distribution of the outermost output bump area.
that can be used to reduce the probability of delamination. The
thin IC application is also the effective way if various thickness
ICs are available. Although the effect of GST and IC length
is almost the same, the former is the priority because it is the
bonding parameter and easier to adjust, while the latter is harder
to change with constant product.
C. Local Delamination Mechanism Analysis
In order to futher investigate the delamination mechanism
around critical bump area, which is around the outermost output
bump, local model was built. The global-local method is par-
ticularly necessary in this analysis because particles under one
bump in the global model were simplified as a block, which
would change the local stress distribution where particles lo-
cated. The local model consisted of IC, one gold bump, ACF
epoxy, twenty-one conductive particles and glass. The geome-
tries of IC and glass were both 160 m ( ) 90 m ( ) 60 m
( ). The geometry of gold bump was 100 ( ) 30 m ( )
15 m ( ). The computed displacement and temperature field
of the global model with the condition in Fig. 7 were interpo-
lated and transferred to the local model as its boundary condition
and field setting, respectively.
Fig. 13 shows the warpage of all components in the local
model. As seen, the glass substrate showed bigger warpage gra-
dient than the IC chip along the axis from left corner to right
corner. Since the right corner of glass was in the same gradient
level as IC, the warpage difference of the left corner between the
IC and glass was the highest because the left corner of glass con-
nected with big LCD glass and could not warp with IC freely.
This warpage difference would cause the highest tensile stress
on the interface, and further resulted in interface delamination.
From Fig. 14, it was noted that the warpage of each par-
ticle surface decreased from the outer side to the inner side of
gold bump along the axis. This phenomenon agreed with the
whole bump warpage that the outer side and right side of gold
bump (highlighted in the circle) had higher warpage, as shown
in Fig. 15.
The above simulation results indicated that during the COG
bonding, the particle was rotated around the and axises. As
a result, the outer side and right side of the critical bump area
XIE et al.: UNDERSTANDING OF DELAMINATION MECHANISM
Fig. 14 Warpage distribution of gold bump and particles.
Fig. 15 Warpage distribution of gold bump.
Fig. 16 Von Mises distribution in the local model of outermost output bump
area.
would have higher stress values. This was demonstrated by the
local von Mises stress distribution, as seen in Fig. 16.
By hiding the IC, glass and ACF epoxy, the von Mises stress
distribution on the gold bump and particles could be visualized
as shown in Fig. 17. The highest von Mises stress located at
all the side of gold bump. While in the center region, the stress
was much smaller but the distribution was uniform. From the
side to the center, the stress decreased tremendously. It is be-
cause that the compressive stress between bump and particles,
which was formed in the pressure loading, would be released
515
Fig. 17 Von Mises distribution in gold bump and particles.
Fig. 18 Top view of SEM micrograph of glass after IC shear test.
Fig. 19 Top view of SEM micrograph of bump after IC shear test.
somewhat after cooling down because of warpage difference
between IC and glass, while the ACF epoxy around bump con-
nected bump with glass tightly to prevent bump warping with IC
freely. This meant if the bump/ACF epoxy interface delamina-
tion occurred it would initiate at the bump side, then propagate
into the bump center to disconnect the bonding of bump and
conductive particles.
Also it was noted from Fig. 16 that the von Mises stress at
the glass/ACF epoxy interface was much higher than that at
the IC/ACF epoxy and interface. It indicated that the glass/ACF
epoxy interface was easier to delaminate and caused the inter-
face failure problem. This was verified by the experimental re-
sults of IC shear test implemented by Dage 4000 shear tester, in
which the whole IC was sheared off from glass completely, the
highest shear force was 91.064 kg, the shear speed was 100 m/s
and the shear height was 20 m. As seen in Figs. 18 and 19, after
the IC shear tests were performed, the micrographs obtained
with scanning electronic microscopy (SEM) for both glass and
bump showed that most of ACF was sheared off from glass,
516 IEEE TRANSACTIONS ON COMPONENTS AND PACKAGING TECHNOLOGIES, VOL. 30, NO. 3, SEPTEMBER 2007
while particles and ACF residual were remained on the bump. It
implied that increasing the bonding-strength between glass and
ACF epoxy is the direction to reduce the probability of ACF de-
lamination. It should be noted that the bubbles inside the ACF
epoxy would deteriorate ACF interconnect further, as shown in
Fig. 18, which implied bubble reduction could enhance the ACF
bonding-strength.
IV. CONCLUSION
From the above numerical simulations and analysis, the fol-
lowing conclusions were reached.
1) The equivalent block method is an effective approach that
can be implemented to reduce the model size and save
computational time and further apply to investigate the de-
lamination mechanism of ACF interconnection of the LCD
module.
2) Probability of ACF delamination can be reduced by de-
creasing the temperature difference between bonding head
and glass substrate as well as using thin and short IC chip.
Among them, decreasing bonding head temperature under
the constant glass substrate temperature is the priority to
reduce probability of ACF delamination, followed by IC
thickness reduction, glass substrate temperature increment
and IC length reduction.
3) The glass/ACF epoxy interface is easier to delaminate,
which implies that increasing the bonding-strength be-
tween glass and ACF epoxy is the direction to reduce
the probability of ACF delamination. Bubbles inside the
ACF epoxy can deteriorate ACF interconnect further. If
the bump/ACF epoxy interface delamination occurred the
delamination would initiate at the bump side and then
propagate into the bump center.
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Bin Xie received the B.S. degrees in mechanical
engineering and automatic control from the Shanghai
Jiao Tong University, Shanghai, China, in 2002, the
M.S.E. degree in mechanical engineering from the
University of Michigan, Ann Arbor, in 2004, and is
currently pursuing the Ph.D. degree in the Advanced
Electronic Manufacturing Center, Shanghai Jiao
Tong University.
His research interests focus on numerical simula-
tion, process development, and reliability assessment
for electronic packaging.
Xun Qing Shi received the Ph.D. degree from the
Tsinghua University, Beijing, China, in 1995.
He is R&D Manager at Intel Corporation and
Guest Professor at Shanghai Jiaotong University,
Shanghai, China, and the Beijing University of
Technology. His recent research interests are in
the areas of micro- and nano-mechanics, electronic
materials damage, fracture and failure mechanisms,
and reliability of advanced electronic packaging and
optoelectronic packaging.
Han Ding received the Ph.D. degree from the
Huazhong University of Science and Technology
(HUST), Wuhan, China, in 1989.
He worked at the University of Stuttgart, Stuttgart,
Germany, from 1993 to 1994. From 1997 to 2001, He
was a Professor at HUST. He joined Shanghai Jiao
Tong University, Shanghai, China, in 2001, where he
is now a “Cheung Kong” Chair Professor and the Di-
rector of the Robotics Institute. His research interests
include robotics, electronic packaging and manufac-
turing automation.
Dr. Ding is an Associate Editor of the IEEE TRANSACTIONS ON AUTOMATION
SCIENCE AND ENGINEERING.