ELECTRONICS & COMMUNICATION ENGINEERING

CATEGORY L T P CREDIT
ECT448 LOW POWER VLSI
PEC 2 1 0 3

Preamble: This course aims to impart the basic knowledge in designing of Low power VLSI
Circuits .
Prerequisite: Solid State Devices, VLSI Design, Digital Circuit Design.
Course Outcomes: After the completion of the course the student will be able to

Identify various short channel effects and various sources of power

CO 1
dissipation in MOSFET
CO 2 Apply various power reduction techniques to circuits.

CO 3 Apply various clocked and non clocked design styles for logic implementation.

CO 4 Apply Adiabatic and reversible logic for circuit implementation.

Mapping of course outcomes with program outcomes

PO 1 PO 2 PO 3 PO 4 PO 5 PO 6 PO 7 PO 8 PO 9 PO 10 PO 11 PO 12
CO 1 3 2
CO 2 3 2
CO 3 3 3 2
CO 4 3 3

Assessment Pattern
Continuous End Semester
Bloom’s Category Assessment Tests Examination
1 2
Remember 10 10 10
Understand 20 20 20
Apply 20 20 70
Analyse
Evaluate
Create

Mark distribution
Total Marks CIE ESE ESE Duration
150 50 100 3 hours

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Continuous Internal Evaluation Pattern:

Attendance : 10 marks
Continuous Assessment Test (2 numbers) : 25 marks
Course project/Assignment : 15 marks

End Semester Examination Pattern: There will be two parts; Part A and Part B. Part A
contain 10 questions with 2 questions from each module, having 3 marks for each question.
Students should answer all questions. Part B contains 2 questions from each module of
which student should answer any one. Each question can have maximum 2 sub-divisions
and carry 14 marks. Mark patterns are as per the syllabus with 60% for theory and 40% for
logical/numerical problems, derivation and proof.

Course Level Assessment Questions

Course Outcome 1 (CO1): Identify various short channel effects and various sources of
power dissipation in MOSFET
1. Derive the expression of switching power in static CMOS circuit.
2. Explain impact ionization and Hot electron effect.
3. Explain the various factors causing leakage power in MOSET.

Course Outcome 2 (CO2): Apply various power reduction techniques to circuits.

1. Describe the use of transistor and Gate sizing for power deduction.
2. Describe supply voltage scaling method for power reduction.
3. Apply various power reduction schemes to memory cells..

Course Outcome 3 (CO3) : Apply various clocked and non clocked design styles for logic
implementation
1. Implement XOR gate in domino logic.
2. Implement the function F= [AB+CD] in DCVS.
3. Implement basic gates in nmos and pseudo nmos logic.

Course Outcome 4 (CO4): Apply Adiabatic and reversible logic for circuit implementation.
1. Implement Y=AB using adiabatic logic
2. Explain one stage adiabatic buffer.
3. Implement logic functions using different Reversible logic structures.

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Syllabus

Module 1: Physics of Power dissipation in MOSFET devices

Need for low power circuit design, MIS Structure, Short channel effects-surface scattering, punch
through, velocity saturation, impact ionization Hot electron effects, Drain Induced Barrier
Lowering, Deep submicron transistor design issues.

Module 2: Sources of power dissipation in CMOS-Dynamic Power Dissipation: Charging and

Discharging capacitance power dissipation , Short Circuit Power: Short Circuit Current of
Inverter , Short circuit current dependency with input and output load , Glitching Power, Static
Power Dissipation, Leakage Power Dissipation,
Gate level power analysis : Capacitive, internal and Static power dissipation of gate level circuit.

Module 3: Power Reduction Techniques :Supply voltage Scaling Approaches: Multi VDD
and Dynamic VDD, leakage power reduction Techniques – Transistor stacking,
VTCMOS,MTCMOS, DTCMOS, Power gating, Clock gating for Dynamic power dissipation,
Transistor and Gate Sizing for Dynamic and Leakage Power Reduction.

Module 4: Circuit design style- clocked design style- Basic concept, Domino logic (domino
NAND gate), Differential Current Switch Logic. Non clocked circuit design style-fully
complementary logic. NMOS and pseudo –NMOS logic, differential cascade voltage switch
logic(DCVS)
Module 5: Adiabatic switching – Adiabatic charging, adiabatic amplification, One stage and
two stage adiabatic buffer, Adiabatic logic gates, pulsed power supplies, Reversible logic basic
concepts.

Text Books:
1. Gray Yeap, Practical low power digital VLSI design, Springer, 1998
2. Kaushik Roy, Sharat C Prasad, Low power CMOS VLSI circuit design, Wiley India,
2000

References:
1. Abdellatif Bellaouar, Mohamed I Elmasry, Low power digital VLSI design, Kluwer
Academic, 1995
2. Anatha P Chandrakasan, Robert W Brodersen, Low power digital CMOS Design,
Kluwer Academic, 1995
3. Christian Piguet, Low power CMOS circuits, Taylor & Francis, 2006
4. Kiat Seng Yeo, Kaushik Roy, Low voltage, low power VLSI sub systems, Tata
McGraw Hill, 2004

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Course Contents and Lecture Schedule

No Topic No. of
Lecture
1 Physics of Power dissipation in MOSFET devices

1.1 Need for low power circuit design, MIS Structure. 2

Short channel effects-surface scattering, punch through, velocity saturation,
1.2 3
impact ionization, Hot electron effects, Drain Induced Barrier Lowering.
1.3 Deep submicron transistor design issues. 1

2 Sources of power dissipation in CMOS

Dynamic Power Dissipation: Charging and Discharging capacitance power
2.1 1
dissipation
Short Circuit Power: Short Circuit Current of Inverter , Short circuit current
2.2 2
dependency with input and output load .

2.3 Glitching Power, Static Power Dissipation, Leakage Power Dissipation, 4

Gate level power analysis : Capacitive, internal and Static power dissipation
2.4 2
of gate level circuit.
3 Power Reduction Techniques

3.1 Supply voltage Scaling Approaches: Multi VDD and Dynamic VDD 1

Leakage power reduction Techniques – Transistor stacking

3.2 2
VTCMOS,MTCMOS, DTCMOS
3.3 Power gating, Clock gating for Dynamic power dissipation, 2
3.4 Transistor and Gate Sizing for Dynamic and Leakage Power Reduction 2

4 Circuit design style

4.1 Clocked design style- Basic concept, Domino logic 2

4.2 Differential Current Switch Logic 1

Non clocked circuit design style-fully complementary logic. NMOS and
4.3 pseudo –NMOS logic 2

4.4 Differential Cascade Voltage Switch logic(DCVS) 1

5 Adiabatic switching

5.1 Adiabatic charging, adiabatic amplification,. 3

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5.2 One stage and two stage adiabatic buffer 2

5.3 Adiabatic logic gates, pulsed power supplies 1

5.4 Reversible logic basic concepts.. 1

Simulation Assignments

Atleast one assignment should be simulation based using any simulation software. It
can be the design of a circuit in any one of the clocked or non clocked style and perform
power analysis. Samples of simulation assignments are given below.

1. Implement NAND gate in conventional CMOS and domino logic and

perform power analysis in each case.
2. Implement any sample logic function in DCVS.
3. Apply threshold voltage scaling method to a logic function implemented
in conventional style and perform power analysis.

Model Question Paper

Model Question Paper

A P J Abdul Kalam Technological University
EIGHTH SEMESTER B.TECH DEGREE EXAMINATION
BRANCH: ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE: ECT448 LOW POWER VLSI

Time: 3 Hrs Max. Marks: 100

PART A
Answer All Questions

1. Define the terms (3)

a) DIBL
b) Velocity Saturation

2. Discuss the need for low power VLSI Design (3)

3. Explain the dependency of short circuit current with output load? (3)
4. Explain dynamic power dissipation? (3)
5 Describe leakage power reduction using MTCMOS (3)
6. Define Slack time of logic gate . (3)
7. List the advantages and Disadvantages of Clocked design. (3)
8. Explain the methods to overcome charge sharing problem. (3)
9. Draw the schematic and logic symbol of an Adiabatic amplifier.. (3)

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10. List the disadvantages of Retractile cascade of Adiabatic logic Gates. (3)

PART B
Answer one question from each module. Each question carries 14 mark

Module I
11(A) Explain the energy band diagram of MIS structure. (8)
11(B) Describe various transistor leakage mechanisms in deep submicron (6)
transistors .
OR

12(A) Explain various short channel effects. (8)

12(B) Explain how the power efficiency of a chip can be measured? (6)

Module II
13(A) Explain how capacitance can be estimated at gate level? (7)
13(B) Explain the formation of glitches in circuits ? Explain various methods (7)
for eliminating the glitches

OR

14(A) Explain the various sources of leakage power in MOSFET (7)

14(B) A 16 bit bus operating in 5V and 66MHz clock rate is driving (7)
capacitance of 2pF/Bit. Each bit is estimated to have a toggling
probability of 0.25 at each clock cycle. Calculate the power
dissipated in operating the bus.
Module III
15(A) Illustrate with examples how low threshold device and high threshold (7)
device can be effectively used for power reduction.
15(B) Explain dynamic supply voltage scaling mechanism for power (7)
reduction.
OR
16(A) Briefly explain dynamic and leakage power reduction using (7)
transistor sizing.
16(B) Illustrate various mechanisms by which power consumption of (7)
6T RAM cells can be reduced.

Module IV
17(A) Implement the function F= [(a+b)(c+d)]’ in NMOS logic and (7)
domino logic.

17(B) Implement the function F= (A+CD) in DCVS logic (7)

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OR

18(A) Explain how charge sharing problem occur in logic design. How it can (7)
be eliminated?
18(B) Differentiate precharge high and precharge low DCSL. (7)

Module V
19(A) Describe the working of one stage adiabatic buffer. (7)
19(B) Explain pulsed power supply? Describe its importance in adiabatic (7)
logic.

OR

20(A) Describe various reversible gate structures. (7)

20(B) Implement OR and AND function using Fredkin gate. (7)

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