2.

Memory write
3. I/O read
4. I/O write

 1.4 Basic architecture of 8085(8-bit) microprocessor:-

The block diagram of 8085 microprocessor consists 6 major block.

1. ALU
2. Register array
3. Timing/control unit
4. Interrupt control unit
5. Serial I/o control unit
6. Instruction register & Instruction decoder

1. ALU:-
 As the name suggests, it performs arithmetic and logical operations like
Addition, Subtraction, AND, OR, etc. on 8-bit data.
 It consists of accumulator, temporary register & flag flip flop.
 during operating the first operand must be stored in accumulator and the
second operand comes from temporary register which is present in either
memory or any one of the general purpose register.
 After the arithmetic and logical operation the result is also
stored in accumulator.
2. Register array:-
It has eight addressable 8-bit registers: A, B, C, D, E, H, L, F, and two 16-bit registers
PC and SP. These registers can be classified as −
 General Purpose Registers
 Temporary Registers: a) Temporary data register b) W and Z registers
 Special Purpose Registers: a)Accumulator b) Flag registers c) Instruction register
  Sixteen-bit Registers: a) ProgramCounter (PC) b) Stack Pointer (SP)

 General Purpose Registers

 Registers B, C, D, E, H, and L are general purpose registers in 8085
Microprocessor. All these GPRS are 8-bits wide. They are less important than the
accumulator. They are used to store data temporarily during the execution of the
program. For example, there is no instruction to add the contents of Band E
registers. At least one of the operands has to be in A. Thus to add Band E registers,
and to store the result in B register, the following have to be done.
 It is possible to use these registers as pairs to store 16-bit information. Only BC,
DE, and HLcan form register pairs. W hen they are used as register pairs in an
instruction, the left register is understood to have the MS byte and the right register
the LS byte. For example, in DE register pair, the content of the D register is treated
as the MS byte, and the content of E register is treated as the LS byte.

 Temporary Registers
(a)Temporary Data Register - The ALU has two inputs. One input is supplied by the
accumulator and other from the temporary data register. The programmer cannot access
this temporary data register. However, it is internally used for execution of most of the
arithmetic and logical instructions.
(b) W and Z registers - W and Z registers are temporary registers. These registers are
used to hold 8-bit data during the execution of some instructions. These registers are not
available for the programmer since 8085Microprocessor Architecture uses them internally.

 Special Purpose Registers

(a) Register A(Accumulator) - Register A is an 8-bit register used in 8085 to perform
arithmetic, logical, I/O & LOAD/STORE operations. Register A is quite often called as an
Accumulator. An accumulator is a register for short-term, intermediate storage of
arithmetic and logic data in a computer's CPU (Central Processing Unit).In an arithmetic
operation involving two operands, one operand has to be in this register. And the result of
the arithmetic operation will be stored or accumulated in this register. Similarly, in a logical
operation involving two operands, one operand has to be in the accumulator. Also, some
other operations, like complementing and decimal adjustment, can be performed only on
the accumulator.
(b)Flag Register - It is a 3-bit register, in which five of the bits carry significant information
in the form of flags: S (Sign flag), Z (Zero flag), AC(Auxiliary carry flag), P (Parity flag), and
CY (carry flag)

x S-Sign flag - After the execution of arithmetic or logical operations, if bit D7 of the result is
1, the sign flag is set. In a given byte if D7 is1, the number will be viewed as a negative
number. If D7 is U, the number will be considered as a positive number.
x Z-Zero flag -The zero flag sets if the result of the operation in ALU is zero and flag resets
if the result is non zero. The zero flags are also set if a certain register content becomes
zero following an increment or decrement operation of that register.
x AC-auxiliary Carry flag - This flag is set if there is an overflow out of bit 3 i.e. carry from
lower nibble to higher nibble (D3 bit to D4 bit). This flag is used for BCD operations and it
is not available for the programmer.
 x P-Parity flag - Parity is defined by the number of ones present in the accumulator. After
arithmetic or logical operation, if the result has an even number of ones, i.e.even parity,
the flag is set. If the parity is odd, the flag is reset.
x CY-Carry flag - This flag is set if there is an overflow out of bit 7. The carry flag also
serves as a borrow flag for subtraction. In both the examples shown below, the carry flag
is set.
c) Instruction Register - In a typical processor operation, the processor first fetches the
opcodeof instruction from memory (i.e. it places an address on the address bus and
memory responds by placing the data stored at the specifiedaddress on the data bus). The
CPU storesthis opcode in a register called the instruction register. Thisopcode is further
sent to the instruction decoder to select one ofthe 256 alternatives.
 SixteenBit Registers
a) Program counter (PC) - Program is a sequence of instructions. As mentioned earlier,
microprocessor fetches these instructions from the memory and executes them The program
counter is a special purpose register which, at a given time,stores the address of the next
instruction to be fetched. Program Counter acts as a pointer to the next instruction. How
processor increments program counter depends on the nature of the instruction;for one-byte
instruction it increments program counter by one, for two-byte instruction it increments
program counter by two and forthree-byte instruction it increments program counter by three
such that program counter always points to the address of the next instruction.
b)Stack Pointer (SP) - The stack is a reserved area of the memory in the RAM where
temporary information may be stored. A 16-bit stack pointer is used to hold the address of
the most recent stack entry.
3. Timing and Control Unit
It provides timing and control signal to the microprocessor to perform operations. Following
are the timing and control signals, which control external and internal circuits

x Control Signals: READY, RD’, W R’, ALE

x Status Signals: S0, S1, IO/M’
x DMA Signals: HOLD, HLDA
x RESET Signals: RESET IN, RESET OUT
4. Interrupt control unit
x As the name suggests it controls the interrupts during a process. When a microprocessor
is executing a main program and whenever an interrupt occurs, the microprocessor shifts
the control from the main program to process the incoming request. After the request is
completed, the control goes back to the main program.
x There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,
TRAP.

5. Serial I/O Control Unit

It controls the serial data communication by using these two instructions: SID (Serial input
data) and SOD (Serial output data).

6.Instruction register & decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored in the
Instruction register. Instruction decoder decodes the information present in the
Instruction register.

x 1.5 Signal description (pin diagram) of 8085 microprocessor):-

 COURSE MATERIAL
Chapter-2(Instruction Set and Assembly Language
Programming)
2.1 Addressing data and Differentiate between one-byte, two-byte
three byte Instructions with examples.
The word size of 8085 instruction can be

1-byte instruction: ADD B

The opcode and operand are in the same byte.

2-byte instruction: MVI A, 05H

.
The first byte specifies opcode and second byte specify the operand.

3-byte instruction: LDA 2000H.

The first byte specifies opcode and the following two bytes specify 16-bit address.

2.2 Addressing modes in instructions with suitable examples

The various techniques to specify data for instruction is called addressing mode.

Direct addressing: The address of the data is specified in the instruction itself. STA 2000H, IN
07H.

Register addressing: The operands are in general purpose register. MOV A, B , ADD B.

Register indirect addressing: The address of the operand is specified by register pair indirectly.
MOV A, M , ADD M.

Immediate addressing: The operand is specified within the instruction itself.MVI A,03H, ADI
12H.

Implicit addressing: The operand is in the accumulator. CMA, RAL, RAR.

2.3 Instruction Set of 8085

The entire group of instructions is called the instruction set, and this determines the
functionalities the microprocessor can perform.
The 8085 Instructions can be classified into five functional categories: Data Transfer (copy)
operations, Arithmetic operations, Logical operations, Branching operations, and Machine-
control operations.

Data transfer instructions

This group of instructions copy data from a location called a source to another location called a
destination without modifying the contents of the source. The various type of data transfer are:
Between registers: MOV B, D
Data byte to register/memory: MVI A, 45H, MVI M, 34H.
Between memory and register: LDA 2100H, STA 2400H.

Between I/O device and accumulator: IN 16H, OUT 12H.

Arithmetic instruction
The arithmetic instructions are addition, subtraction, increment, and decrement.

Addition

Any 8-bit number, or the content of a register, or the content of a memory location can be added
to the content of accumulator. The sum is stored in the accumulator.
The DAD instruction adds 16-bit numbers in register pairs.

Subtraction
Any 8-bit number, or the content of a register, or the content of a memory location can be
subtracted from the content of accumulator. The result is stored in the accumulator. The
subtraction is performed in 2’s complement form.

Mnemonics Tasks Addressing Length of the Example

performed on mode Instruction
execution
ADI 8-bit Add Immediate Two bytes ADI 30H
immediate to
accumulator
ACI 8-bit Add Immediate Two bytes ACI 4FH
immediate to
accumulator
with carry
SUI 8-bit Subtract Immediate Two bytes SUI 2AH
immediate
from
accumulator
SBI 8-bit Subtract Immediate Two bytes SBI 5CH
immediate
from
accumulator
with borrow
ADD R Add register Direct One byte ADD C
content to
accumulator
ADC R Add register Direct One byte ADC E
content to
accumulator
with carry
SUB R Subtract Direct One byte SUB B
register
content from
accumulator
SBB R Subtract Direct One byte SBB C
register
content and
borrow from
accumulator
DAD Rp Add register Direct One byte DAD B
pair to H and L
registers
INR R Increment Direct One byte INR B
register by 1
INX Rp Increment Direct One byte INX B
register pair
by 1
DCR R Decrement Direct One byte DCR E
register by 1
DCX Rp Decrement Direct One byte DCX D
register pair
by 1
ADD M Add memory Indirect One byte ADD C
content
pointed by HL
register pair to
accumulator
ADC M Add memory Indirect One byte ADC E
content
pointed by HL
register pair to
accumulator
SUB M Subtract Indirect One byte SUB B
memory
content
pointed by HL
register pair
from
accumulator
SBB M Subtract Indirect One byte SBB C
memory
content
pointed by HL
pair and
borrow from
accumulator
INR M Increment a Indirect One byte INR M
memory
content
pointed by HL
register pair
once
DCR M Increment a Indirect One byte INR M
memory
content
pointed by HL
register pair
once
DAA Decimal adjust Implicit One byte DAA
accumulator

Logical instruction
These instructions perform logical operation with content of accumulator. These instructions are
AND, OR, Ex-OR, rotate, compare, and complement.

Logical AND
Any 8-bit number, or the content of a register, or the content of a memory location can be
logically ANDed with the content of accumulator. The result is stored in the accumulator.

Mnemonics Tasks Addressing Length of the Example

performed on mode Instruction
execution
ANI 8-bit Logical AND Immediate Two bytes ANI 0FH
immediate
with
accumulator
XRI 8-bit Exclusive OR Immediate Two bytes XRI 01H
immediate
with
accumulator
ORI 8-bit Logical OR Immediate Two bytes ORI 80H
immediate
with
accumulator
ANA R Logical AND Direct One byte ANA C
register or
memory with
accumulator
XRA R Exclusive OR Direct One byte XRA D
register or
memory with
accumulator
ORA R Logical OR Direct One byte ORA E
register or
memory with
accumulator
ANA M Logical AND Indirect One byte ANA M
memory
pointed by HL
register pair
with
accumulator
XRA M Logical XOR Indirect One byte XRA M
memory
pointed by HL
register pair
with
accumulator
ORA M Logical OR Indirect One byte ORA M
memory
pointed by HL
register pair
with
accumulator
RLC Rotate Implicit One byte RLC
accumulator
left
RRC Rotate Implicit One byte RRC
accumulator
right
RAL Rotate Implicit One byte RAL
accumulator
left through
 carry
RAR Rotate Implicit One byte RAR
accumulator
right through
carry
CPI 8-bit Compare Immediate Two bytes CPI FFH
immediate
with
accumulator
CMP R Compare Direct One byte CMP B
register or
memory with
accumulator
CMP M Compare Indirect One byte CMP M
memory
pointed by HL
register pair
with
accumulator
CMA Complement Implicit One byte CMA
accumulator
CMC Complement Implicit One byte CMC
carry
STC Set carry Implicit One byte STC

Branching Instructions
This instruction alters the sequence of program execution either conditionally or unconditionally.
These instructions are jump, call, return, and restart.

Mnemonics Tasks Addressing Length of the Example

performed on mode Instruction
execution
JMP 16-bit Jump Immediate Three bytes JMP 9500
unconditionally
JC 16-bit Jump if carry is Immediate Three bytes JC 9500
set
JNC 16-bit Jump on no Immediate Three bytes JNC 9500
carry
JP 16-bit Jump on Immediate Three bytes JP 9500
positive
JM 16-bit Jump on minus Immediate Three bytes JM 9500
JZ 16-bit Jump on zero Immediate Three bytes JZ 9500
JNZ16-bit Jump on no Immediate Three bytes JNZ 9500
zero
JPE 16-bit Jump on parity Immediate Three bytes JPE 9500
even
JPO 16-bit Jump on parity Immediate Three bytes JPO 9500
odd
CALL 16-bit Call Immediate Three bytes CALL 9500
unconditionally
CC 16-bit Call on carry Immediate Three bytes CC 9500
CNC 16-bit Call on no carry Immediate Three bytes CNC 9500
CP 16-bit Call on positive Immediate Three bytes CP 9500
CM 16-bit Call on minus Immediate Three bytes CM 9500
CZ 16-bit Call on zero Immediate Three bytes CZ 9500
CNZ 16-bit Call on no zero Immediate Three bytes CNZ 9500
CPE 16-bit Call on parity Immediate Three bytes CPE 9500
even
CPO 16-bit Call on parity Immediate Three bytes CPO 9500
odd
RET Return Implicit One byte RET
unconditionally
RC Return on carry Implicit One byte RC
RNC Return on no Implicit One byte RNC
carry
RP Return on Implicit One byte RP
positive

Machine
control
operation
These instruction
are halt, interrupt,
and do nothing etc.
Mnemonics Tasks performed Addressing mode Length of the
on execution Instruction
NOP No operation Implicit One byte
HLT Halt the Implicit One byte
microprocessor
execution
DI Disable interrupts Implicit One byte
EI Enable interrupts Implicit One byte
RIM Read interrupt Implicit One byte
mask
S IM Set interrupt mask Implicit One byte

2.4 Simple Assembly Language Programming of 8085

2.4.1 simple addition and subtraction
Statement: Add the content of memory location 4000H with content of memory
location 4001H and place the result in memory location 4002H.

(4000H) = 14H
(4001H) = 89H
Result = 14H + 89H = 9DH
Source program
LXI H 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
ADD M : Add second operand
INX H : HL points 4002H
MOV M, A : Store result at 4002H
HLT : Terminate program execution

Statement: Subtract the contents of memory location 4001H from the memory location
2000H and place the result in memory location 4002H.

Program - 4: Subtract two 8-bit numbers

Sample problem:
 (4000H) = 51H
(4001H) = 19H
Result = 51H - 19H = 38H
LXI H, 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
SUB M : Subtract second operand
INX H : HL points 4002H
MOV M, A : Store result at 4002H.
HLT : Terminate program execution

2.4.2 8085 program to find 1’s and 2’s complement of 8-bit number
Problem – W rite a program to find 1’s and 2’s complement of 8-bit number where starting
addr es s i s 200 0 an d t he num be r i s s t or ed at 3000 m em or y a ddr es s and s t or e r es ul t
i nt o 30 01 a nd 3 002 m em or y a ddr es s .

Program

Me mo r y Mnemonics O p e ra n d s Comment

2000 LDA [3000] [ A ] < - [ 3 0 00 ]

2003 C MA [A] <- [A^]

2004 S TA [3001] 1’s complement

2007 AD I 01 [ A] < - [ A] + 0 1

2009 S TA [3002] 2’s complement

200C HLT Stop

2.4.3 Counters and Time delay

A counter is designed simply by loading appropriate number into one of the registers and using INR
or DNR instructions.

• Loop is established to update the count.

• Each count is checked to determine whether it has reached final number ;if not, the loop is
repeated.

Time Delay
x Procedure used to design a specific delay.
x A register is loaded with a number , depending on thec time delay required and then the
register is decremented until it reaches zero by setting up a loop with conditional jump
instruction.

Time delay using One register:

 OPCODE OPERAND COMMENTS T STATES

MVI C,FFH ;Load register C 7

DCR C ;Decrement C 4

JNZ LOOP ;Jump back to 10/7

decrement C

Clock frequency of the system = 2 MHz

Clock period= 1/T= 0.5 μs

Time to execute MVI = 7 T states * 0.5= 3.5 μs

Time Delay in Loop TL= T*Loop T states * N10

= 0.5 * 14* 255

= 1785 μs

= 1.8 ms

N10 = Equivalent decimal number of hexadecimal count loaded in the delay register

TLA= Time to execute loop instructions =

TL –(3T states* clock period)=1785-1.5=1783.5 μs

TIME DELAY USING A REGISTER PAIR

Label Opcode Operand Comments T states

LOOP: LXI B,2384H Load BC with 16-bit count 10

DCX B Decrement BC by 1 6

MOV A,C Place contents of C in A 4

OR A B OR B with C to set Zero flag 4

J NZ LOOP if result not equal to 0 , 10/7

jump back to loop

Time Delay in Loop TL= T*Loop T states * N10

= 0.5 * 24* 9092

= 109 ms

Time Delay using a LOOP within a LOOP

MVI B, 38H 7T

MVI C, FFH 7T

DCR C 4T

JNZ LOOP1 10/7 T

 DCR B 4T

JNZ LOOP 2 10/7T

2.4.4 Looping, Counting & Indexing

Looping-In this technique, the program is instructed to execute certain set of instructions
repeatedly to execute a particular task number of times.

Counting-This technique allows programmer to count how many times the instruction/set of
instructions are executed.

Indexing-This technique allows programmer to point or refer the data stored in sequential
memory location one by one.

2 .4 .5 Stack & subroutines programs

The stack is an area of R/W memory identified by the programmer for temporary storage of
information.
• The stack is a Last in First out (LIFO) structure.
• The stack normally grows backwards into memory.

In other words, the programmer defines the bottom of the stack and the stack grows up into
reducing address range.
Given that the stack grows backwards into memory, it is customary to place the bottom of the
stack at the end of memory to keep it as far away from user programs as possible.
In the 8085, the stack is defined by setting the SP (Stack Pointer) register.
LXI SP, FFFFH
This sets the Stack Pointer to location FFFFH (end of memory for the 8085).
The Size of the stack is limited only by the available memory

Saving Information on the Stack

Information is saved on the stack by PUSH ing it on. It is retrieved from the stack by POPing it
off.
The 8085 provides two instructions: PUSH and POP for storing information on the stack and
retrieving it back. Both PUSH and POP work with register pairs only.
The PUSH Instruction
PUSH B (1 Byte Instruction).
Decrement SP, Copy the contents of register B to the memory location pointed to by SP.
Decrement SP, Copy the contents of register C to the memory location pointed to by SP
The POP Instruction
POP D (1 Byte Instruction).
Copy the contents of the memory location pointed to by the SP to register E, Increment SP.

The POP Instruction

POP D (1 Byte Instruction).
Copy the contents of the memory location pointed to by the SP to register E, Increment SP.
Copy the contents of the memory location pointed to by the SP to register D, Increment SP.

Operation of the Stack

During pushing, the stack operates in a “decrement then store” style.
The stack pointer is decremented first, and then the information is placed on the stack.
During popping, the stack operates in a “use then increment” style.
The information is retrieved from the top of the, the stack and then the pointer is incremented.
The SP pointer always points to “the top of the stack”.

LIFO
The order of PUSHs and POPs must be opposite of each other in order to retrieve information
back into its original location.
PUSH B
PUSH D
...
P OP D
P OP B
Reversing the order of the POP instructions will result in the exchange of the contents of BC and
DE.

The PSW Register Pair

The 8085 recognizes one additional register pair called the PSW (Program Status W ord).
This register pair is made up of the Accumulator and the Flags register.
It is possible to push the PSW onto the stack, do whatever operations are needed, then POP it
off of the stack.
The result is that the contents of the Accumulator and the status of the Flags are returned to what
they were before the operations were executed.

PUSH PSW Register Pair

PUSH PSW (1 Byte Instruction).

Decrement SP, Copy the contents of register A to the memory location pointed to by SP.
Decrement SP, Copy the contents of Flag register to the memory location pointed to by SP.
Pop PSW Register Pair
POP PSW (1 Byte Instruction).
Increment SP, Copy the contents of the memory location pointed to by the SP to Flag register
Increment SP, Copy the contents of the memory location pointed to by the SP to register A

Subroutines
A subroutine is a group of instructions that will be used repeatedly in different locations of the
program.
Rather than repeat the same instructions several times, they can be grouped into a subroutine
that is called from the different locations.
In Assembly language, a subroutine can exist anywhere in the code. However, it is customary to
place subroutines separately from the main program.
The 8085 has two instructions for dealing with subroutines.
The CALL instruction is used to redirect program execution to the subroutine.
The RET instruction is used to return the execution to the calling routine.

CALL 4000H (3 byte instruction)

When CALL instruction is fetched, the Processor knows that the next two memory location
contains 16bit subroutine address in the memory.

Subroutine provides flexibility in writing program and uses memory efficiently.

Nesting:
The programming technique of a subroutine calling another subroutine is called nesting of
subroutine. This process is limited only by available stack locations.
Recursive Subroutine:
A subroutine which is called by itself is called recursive subroutine.
Reentrant Subroutine:
In nested subroutine, if a latter subroutine calls an earlier subroutine, it is known as reentrant
subroutine.
Multiple Ending Subroutines:
The subroutine which has more than one return is called multiple ending subroutines.
Multiple Calling of subroutine:
Calling a subroutine more than once by main program are called multiple calling subroutines.
Parameter passing:
It is necessary pass data and address variable of main program to subroutine. This passing of
data and address is called parameter passing. Parameter passing can be done by using register,
pointer, memory and stack.

2 .4 .6 BCD Arithmetic & 16 bit data operation

Decimal addition of two 8-bit numbers whose sum is 16 bits.
ALGORITHM:
Step1. : Initialize H-L pair with memory address XXXX (say: 8500).
Step2. : Clear Carry register C.
Step3. : Move contents of memory location M to accumulator.
Step4. : Increment memory pointer (i.e. 8501).
Step5. : Add the contents of memory indicated by memory pointer to accumulator.
Step6. : Apply the instruction DAA(Decimal adjust after addition)
Step7: Check for Carry
Step8: Store the sum in XX02
Step9: Store the Carry in XX03 location
Step10: Halt

PROGRAM
Address of Hex Label opcode operand Comments

the code

memory

location

8000 21, LXI H, 8500 Initialise

memory
00,85 H pointer to

point the first

data location
9000.

8003 0E MVI 00 Clear 8003 0E MVI 00 Clear 8003 0E 00 Clear

C accumulator C accumul MVI C accumulator
ator

8004 00

8005 7E M OV A, M The first

number is
added to
 accumulator
[A] [A]+M

8006 23 INX H Increment the

memory
pointer to

next location
of the Data.

8007 86 ADD A, M The 2nd

number is
added to

contents of
accumulator

8008 27 DAA

8009 D2 JNC FWD Is Carry

exists? No,
go to the

label FWD

800C 0C INR C Make carry =1

800D 32 FWD ST A 8502 H The contents

of
accumulator
are

stored in
memory
location 8502.

800E 02

800F 85

8010 79 M OV A, C Carry is
moved to
accumulator

8011 32 ST A 8503 H A Carry is

stored in the
location

8503

8012 03

8013 85

8014 76 HLT Stop the

 execution

Subtraction of two 8-bit Decimal numbers.

Explanation: In this program we can’t use the DAA instruction after SUB or SBB instruction
because it is decimal adjust after addition only. So, for decimal subtraction the number which
is to be subtracted is converted to 10’s complement and then DAA is applied.

ALGORITHM:
Step1. : Initialise H-L pair with the address of second number (XX01).
Step2. : Find its ten’s complement
Step3. : Decrement the H-L pair for the first number (XX00)
Step4. : Add the first number to the 10’s complement of second number.
Step5. : Store the result in XX02.
Step6. : Stop the execution

PROGRAM:
ADDRESS HEX LAB OPCODE OPERAND COMMENTS
CODE EL
8000 21 LXI H,8500 Initialise H-L
pair and get
theSecond
number in to
8501
location

8001 00

8002 85
8003 3E M VI A,99 [A]  99

8004 99
8005 96 SUB M 9’s complement
of second
number

8006 3C INR A 10’s

complement of
second
number
8007 2B DCX H Address of the
first number
8008 86 ADD M Add first
number to 10’s
complement of
second number
8009 27 DAA
32 ST A 8502 Store the result
800A in the location
8502
800B 02
800C 85
800D 76 HLT Stop the
execution

Addition of two 16-bit numbers whose sum is 16 bits or more

Explanation: First 16-bit number is stored in two consecutive locations (Ex 8500 &8501)
because in each location we can store only one 8-bit number. Store the second 16-bit number
in the next two consecutive locations (For Ex: 8502 &8503).Add the LSB of the first number to
the LSB of the second number and the MSB of the first number to the MSB of the second
number using the DAD instruction. Store the sum in the next two locations and the carry (if
any) in the third location.

ALGORITHM:
Step1: First 16 bit number is in locations 8500 & 8501 respectively
Step2: Second 16-bit number is in locations 8502 & 8503
Step3: Add the two 16-bit numbers using DAD Instruction.
Step4: Sum is stored in locations 8504 & 8505.
Step5: Carry (if any) is stored in the location 8506.
Step6: Halt

PROGRAM:
ADDRESS HEX – LABEL OPCO OP E R A COMMENTS
CODE DE ND
8000 2A,00,85 LHLD 8500 H First 16-bit
8001 00 number in H-L
8002 85 pair
8003 EB XCHG Exchange first
number to D-E
Pair
8004 2A LHLD 8502 H
8005 02
8006 85
8007 0E M VI 00 MSB of the sum
is initially 00
8008 00
8009 19 DAD D Add tw o 16 –bit
numbers
800A D2 JNC FWD Is Carry? If yes
800B 0E go to the next
800C 80 line .Else go to
the 800E
LOCATION
800D OC INR C Increment carry
800E 22 FWD SHLD 8504 H Store the LSB
800F 04 of the Sum in
8010 85 8504 & MSB in
8505 locations
8011 79 M OV A,C MSBs of the
sum is in
accumulator
8012 ST A 8506 H Store the MSB
8013 (Carry) of the
8014 result in 8506
location
8015 HLT Stop execution

Ex: INPUT: 8500- 12 H LSB of the Ist Number RESULT : 8504 - 25H LSB of the Sum
8501- 13 H MSB of the Ist Number 8505 – 25H MSB of the Sum
8502 -13 H LSB of the IInd Number 8506 -- 00 Carry .
8503 -12H MSB of the IInd number.

Subtraction of two 16 –bit numbers

Explanation: It is very similar to the addition of two 16-bit numers.Here we use SUB &SBB
instructions to get the result .The first 16-bit number is stored in two consecutive locations and
the second 16-bit number is stored in the next two consecutive locations.The lsbs are
subtracted using SUB instruction and the MSBs aare subtracted using SBB instruction.The
result is stored in different locations

ALGORITHM:
Step1. : Store the first number in the locations 8500 & 8501.
Step2. : Store the second number in the locations 8502 &8503.
Step4. : Subtract the second number from the first number with borrow.
Step5. : Store the result in locations 8504 & 8505.
Step6. : Store the borrow in location 8506
Step 7: Stop the execution

PROGRAM:

ADDRESS HEX LABE OPCOD OPERAN COMMENTS

CODE L E D
8000 2A, LHLD 8500 H First 16-bit
00,85 number in H-L
pair
8003 EB XCHG Exchange first
number to D-E
Pair
8004 2A LHLD 8502 H Get the second
8005 02 16-bit number in
H-L
pair
8005 02
8006 85
8006 85
8007 7B M OV A, E Get the lower
byte of the First
number in to
Accumulator
8008 95 SUB L Subtract the
lower byte of the
second number
8009 6F M OV L, A Store the result
in L- register
800A M OV A, D Get higher byte
of the first
number
800A 9C SBB H Subtract higher
byte of second
number with
borrow
800B 67 M OV H, A
800C 22 SHLD 8504 Store the result in
800D 04 memory locations
with LSB in
8504 & MSB in
8505
800E 85
800F 76 HLT Stop execution

8501 - FF H MSB of the Ist Number 8505 – 11 H MSB

8502 -EE H LSB of the IInd Number
8503 –EE H MSB of the IInd number

BLOCK TRANSFER
Write an assembly language program to transfer a block of data from source memory
location to destination memory location.
Given data:-
Source Destination
2500H=46H 2800H= 46H
2501H=35H 2801H=35H
2502H=37H 2802H=37H
2503H=3AH 2803H=3AH
2504H=4BH 2804H=4BH

ALGORITHM:
Step 1: initialized the H-L pair to get the 1st data
Step :2 load the no. of data into B register.
Step-3: initialize the destination address in DE register pair.
Step 4: initialize source address in H-L pair
Step 5: load the data into accumulator from source memory.
Step 6: store the data from accumulator into destination memory.
Step 7: increment H-L & D-E register pair
Step 8 : decrement B-register

PROGRAM:
ADDRESS LABE OPCOD OPERAN COMMENTS
L E D
3000H LXI H, 24FFH Load immediately
24FF in H-L pair.
3003H MOV B ,M Move the data
from memory to
B-register.
3004H LXI D,2800H Load the
destination
address(2800H)
into DE register
pair.
3007H LXI H,2500H Load the source
address (2500H)
into H-L pair.
300AH LOOP MOVE A ,M Move the data
from memory to
accumulator
300BH XCHG Exchange the DE
pair with H-L pair.
3000CH MOV M,A Move the data
from accumulator
to destination
memory location.
300EH INX D Increment the DE
register pair.
300FH DCR B Decrement the B
register.
3010H JNZ LOOP Jump if no zero
into the program
3013H HLT Stop the
program.
2.4.8 Largest & Smallest numbers in an Array

To find the largest number in a data array

ALGORTHM:
Step1: Store the count in the Memory location pointed by H-L register.
Step2: Move the I st number of the data array in to accumulator
Step3: Compare this with the second number in Memory location.
Step4: The larger in the two is placed in Accumulator
Step5: The number in Accumulator is compared with the next number in memory .
Step 6: The larger number is stored in Accumulator.
Step 7; The process is repeated until the count is zero.
Step 8: Final result is stored in memory location.
Step 9: Stop the execution

PROGRAM
ADD HEX – LABEL OPCOD OPERAN COMMENTS
RESS CODE E D
8000 21,00,8 LXI H, 8500 INITIALISE H-L
5 PAIR
8003 7E M OV C,M Count in the C
register
8004 23 INX H First number in
H-L pair
8005 4E M OV A,M Move first
number in to
Accumulator
8006 0D DCR C Decrement the
count
8007 91 LOOP1 INX H Get the next
number
8008 BE CMP M Compare the
next number
with previous
number
8009 D2 JNC LOOP2 Is next number
>previous
maximum?No,go
to the
loop2
800A 0D
800B 80
800C 7E M OV A,M If,yes move the
large
number in to
Accumulator
800D 0D LOOP2 DCR C Decrement the
count
800E C2 JNZ LOOP1 If count not
equal to
zero,repeat
800F 07
8011 80
8012 78
8013 32 ST A 85XX Store the largest
number in
the location
 85XX
8014 XX
8015 85
8016 76 HLT Stop the
execution

Ex : Input : 8500- N(Say N=7 ) Result : 8508 - 7F

8501-05
8502-0A
8503-08
8504-14
8505 -7F
8506-25
8507-2D

To find the smallest number in a data array.

ALGORTHM :

Step1: Store the count in the Memory location pointed by H-L register.
Step2: Move the I st number of the data array in to accumulator
Step3: Compare this with the second number in Memory location.
Step4: The smaller in the two is placed in Accumulator
Step5: The number in Accumulator is compared with the next number in memory .
Step 6: The smaller number is stored in Accumulator.
Step 7; The process is repeated until the count is zero.
Step 8: Final result is stored in memory location.
Step 9: Stop the execution

PROGRAM
ADD HEX – LABEL OPCOD OPERAN COMMENTS
RESS CODE E D
8000 21 LXI H 8500 Initialise the H-L
pair.
8001 00
8002 85
8003 7E M OV C,M Count in the C
register

8004 23 INX H First number in

H-L pair
8005 4E M OV A ,M Move first
number in to
Accumulator
8006 0D DCR C Decrement the
count
8007 91 LOOP1 INX H Get the next
number
8008 BE CMP M Compare the
next number
with previous
number
8009 D2 JC LOOP2 Is next number
<previous
smallest ?If yes
go to the
 loop2
800A 0D
800B 80
800C 7E M OV A,M No,move the
smaller
number in to
Accumulator
800D 0D LOOP2 DCR C Decrement the
count
800E C2 JNZ LOOP1 If count not
equal to
zero,repeat
800F 07
8011 80
8012 78
8013 32 ST A 85XX Store the
smallest
number
in the location
85XX
8014 XX
8015 85
8016 76 HLT Stop the
execution

Ex: Input : 8500 - N((Say N=7) Result : 8508 – 04

8501-09
8502-0A
8503-08
8504-14
8505 -7F
8506-04
8507-2D
2.5 Memory & I/O Addressing

In Memory Mapped Input Output −

x We allocate a memory address to an Input-Output device.
x Any instructions related to memory can be accessed by this Input-Output device.
x The Input-Output device data are also given to the Arithmetic Logical Unit.
Input-Output Mapped Input Output −
x We give an Input-Output address to an Input-Output device
x Only IN and OUT instructions are accessed by such devices.
x The ALU operations are not directly applicable to such Input-Output data.
 COURSE MATERIAL
Chapter-3(Timing Diagram)

1.1 Opcode:
It is the short form of instruction which specify the task to be performed by the
microprocessor.

Operand:
Operand may be a register, data & address on which the opcode work.

T-State:
x The time required by the microprocessor to complete an operation of accessing memory or
input/output devices is called machine cycle.

x One time period of frequency of microprocessor is called t-state.

x A t-state is measured from the falling edge of one clock pulse to the falling edge of the next
clock pulse.

Instruction cycle:
Time required to execute and fetch an entire instruction is called instruction cycle. It consists:

x Fetch cycle – The next instruction is fetched by the address stored in program counter
(PC) and then stored in the instruction register.
x Decode instruction – Decoder interprets the encoded instruction from instruction register.

Reading effective address – The address given in instruction is read from main memory
x
and required data is fetched. The effective address depends on direct addressing mode
or indirect addressing mode.
Execution cycle – In fetch cycle the opcode is fetched from memory and it is moved to
the data register, then to the instruction register.
x After that it moves to the decoder circuit to decode the instruction.
x If the operand is GPRS the execution is immediately performed.
Machine cycle- The time required by the microprocessor to complete an operation of
accessing memory or input/output devices is called machine cycle.
x It is required to perform one of the following operation.
1. Opcode fetch(4 Tstate)
2. Memory read(3 T state)
3. Memory write(3 Tstate)
4. I/O read(3 Tstate)
5. I/O write(3 Tstate)
1.2 Timing diagram for opcode fetch

Timing diagram for memory read operation

Timing diagram for memory write operation

Timing diagram for I/O read operation

Timing diagram for I/O write operation

1.3 Neat sketch for the timing diagram for 8085 instruction MOV :
Example:
MOV B, C
Opcode: MOV
O per a nd: B and C
2000: MOV B, C
Only opcode fetching is required for this instruction and thus we need 4 T states for the timing
d i a g r a m . F o r t h e o p c o d e f e t c h t h e I O/ M ( l o w a c t i v e ) = 0 , S 1 = 1 a n d S 0 = 1 .
The timing diagram of MOV instruction is shown below:

I n O p c o de f e t c h ( t 1 - t 4 T s t a t e s ) :
1. 00 – lower bit of address where opcode is stored, i.e., 00
2. 20 – higher bit of address where opcode is stored, i.e., 20.
3. ALE – provides signal for multiplexed address and data bus. Only in t1 it used as
address bus to fetch lower bit of address otherwise it will be used as data bus.
4. RD (low active) – signal is 1 in t1 & t4 as no data is read by microprocessor.
Signal is 0 in t2 & t3 because here the data is read by microprocessor.
5. WR (low active) – signal is 1 throughout, no data is written by microprocessor.
6. IO/M (low active) – signal is 1 in throughout because the operation is performing
on memory.
7. S0 and S1 – both are 1 in case of opcode fetching.
N e a t s k et c h f o r t h e t i m i n g d i a g r a m f o r 8 0 8 5 i n st r u ct i o n M V I :
Example: MVI B, 45
Opcode: MVI
Operand: B is the destination register and 45 is the source data which needs to be transferred
t o t he r egi s t er .
’45’ data will be stored in the B register.

x The opcode fetch will be same in all the instructions.

x O nl y t he r e ad i ns t r uc t i on of t he opc ode nee d s t o be adde d i n t he s uc c es s i v e T s t at es .
x For the opcode fetch the IO/M (low active) = 0, S1 = 1 and S0 = 1. Also, 4 T states will
be required to fetch the opcode from memory.
x F or t he opc o de r ea d t he I O / M ( l o w ac t i v e) = 0, S 1 = 1 and S 0 = 0. A l s o, onl y 3 T s t at es
will be required to read data from memory.

I n O p co d e f et ch ( t 1- t 4 T st at e s ) –
x 00 – lower bit of address where opcode is stored.
x 20 – higher bit of address where opcode is stored.
x A LE – P r ov i des s i gnal f or m ul t i pl ex ed add r e s s and dat a b us . O nl y i n t 1 i t us ed as
address bus to fetch lower bit of address otherwise it will be used as data bus.
R D ( l ow ac t i v e) – S i gn al i s 1 i n t 1 & t 4, no dat a i s r ead b y m i c r opr o c es s or . S i gnal i s 0
i n t 2 & t 3, dat a i s r ead b y m i c r opr oc es s or .
W R (low active) – Signal is 1 throughout, no data is written by microprocessor.
 IO/M (low active) – Signal is 0 in throughout, operation is performing on memory.
S0 and S1 – Signal is 1 in t1 to t4 states, as to fetch the opcode from the memory.

I n O p co d e r ead ( t 5- t 7 T st at e s ) –

x 01 – lower bit of address where data is stored.

x 20 – higher bit of address where data is stored.
x A LE – P r ov i des s i gnal f or m ul t i pl ex ed add r e s s and dat a b us . O nl y i n t 5 i t us ed as
address bus to fetch lower bit of address otherwise it will be used as data bus.
R D ( l ow ac t i v e) – S i gn al i s 1 i n t 5 as no dat a i s r ead b y m i c r opr oc e s s or . S i gnal i s 0 i n
t 6 & t 7 as dat a i s r ead b y m i c r opr oc es s or .
W R (low active) – Signal is 1 throughout, no data is written by microprocessor.
IO/M (low active) – Signal is 0 in throughout, operation is performing on memory.
S 0 – S i gnal i s 0 i n t hr o ugh out , ope r at i o n i s per f or m i ng on m em or y t o r ea d dat a 4 5.
S1 – Signal is 1 throughout, operation is performing on memory to read data 45.

Neat sketch for the timing diagram for 8085 instruction LDA:
 COURSE MATERIAL
Chapter-4
(Microprocessor Based System Development Aids)
4.1 Concept of interfacing:
x I nt er f ac i ng i s a t ec hni q ue t o c onn ec t i nput d e v i c es , out put dev i c es and m em or y t o ot he r
peripheral with the microprocessor.

x W e knoe that the microprocessor is useless until and unless we do not connect any
peripherals with it.

x So for communication purpose in between microprocessor and peripheral interfacing is

r equ i r e d.

4 . 2 D e f i n e Ma p p i n g :
Mapping is a technic by which we can address various memories ICs and it is of two types.

1. Memory mapped I/O or Memory mapping

2. I / O m apped I / O or I / O m appi ng.

Differentiate betw een memory mapped I/O and I/O mapped I/O.

Features M e mo r y M a p p e d I O I O M a p p e d I O
I O d e v i c es a r e Th e y c a n n o t b e
accessed like any accessed like any
o t h e r m em o r y o t h e r m em o r y
Ad d r e s s i n g location. location.

Th e y a r e Th e y a r e
a s s i g n e d w i t h 16 - a s s i g n e d w i t h 8-
b i t a d dr e s s b i t a d dr e s s
Address Size values. values.

T h e i n s t r uc t i o n T h e i n s t r uc t i o n
I n s t r uc t i o n s u s e d ar e L D A an d u s e d ar e I N a n d
Used S TA , e t c . O U T.

Cycles involved
d u r i n g o p er a t i on
a r e M e m or y
R e a d , M e m or y
Cycles W rite.
Cycles involved
d u r i n g o p er a t i on
a r e IO r e a d a n d
I O w r i t e s i n th e
c a s e of I O
Ma p p e d I O .
 A n y r e g i s t e r ca n O n l y A c c u m u l a t or
c o m m un i c a t e w i t h can communicate
the IO device in with IO devices in
Re gister s c a s e of M e m o r y c a s e of I O
Communicating Ma p p e d I O . Ma p p e d I O .

2 1 6 I O po r t s a r e Onl y 256 I/O

possible to be ports are
u s e d f or available f or
interfacing in case interfacing in
o f Me m o r y c a s e of I O
Space Involved Ma p p e d I O . Ma p p e d I O .

During writing or During writing or

read cycles read cycles
( I O / M` = 0 ) i n ( I O / M` = 1 ) i n
c a s e of M e m o r y c a s e of I O
I O / M` s i g n a l Ma p p e d I O . Ma p p e d I O .

N o s e p ar a t e
c o n t r o l s i g n al
required since we
have unified
m e m or y s p a c e i n S p e c i a l c o n tr o l
t h e c a se o f s i g n a l s ar e us e d
Me m o r y Ma p p e d in the case of IO
C o n t r o l Si g n a l IO. Ma p p e d I O .

Arithmetic and Arithmetic and

l o g i c a l op e r at i o n s l o g i c a l op e r at i o n s
a r e pe r f o r m e d cannot be
dir ectly on the performed directly
Arithmetic and data in the case o n t h e d a t a i n th e
Logical o f Me m o r y c a s e of I O
o p e r at i o n s Ma p p e d I O . Ma p p e d I O .

Me m o r y Ma p p i n g :
In this technique memory location are identified by input &output devices.

Advantage:

x More than 256 number of memory location can be specified by this technique.

x The CPU can be transfer the data within the input or output device directly with the
ac c um ul at or s , s o t hi s t ec hni q ue i s v er y f as t .

D i sad van t ag e:

x Due to the wider address space the interface hardware is complicated.

x T he c om pl ex i t y of t he pr og r am i s v er y l ar g e.
I / O Ma p p i n g :
x I n t hi s t ec hni qu e t he I / O dev i c es ar e c ons i de r ed as a m em or y l oc at i on.

x This technique required two specific instruction that is in and out.

x To access I/O devices we required two control signal that is IOR’ & IOW ’.

x W e c a n n o t a c c e s s m o r e t h a n 2 5 6 n u m b e r o f I/ O p o r t s .

Advantage :

x A ddr es s s pac e i s l es s .

x O nl y t w o i ns t r uc t i ons ar e us e d.

D i sad van t ag e:

x T he m i c r opr oc es s or pi n m us t gener at e c o nt r ol s i gnal t o di s t i n gui s h bet w ee n m em or y &

I / O oper at i on.

MEMORY INTERFACING:

x W hile executing an instruction there is a necessity for the microprocessor to access

memory frequently for reading various instruction codes and data stored in the memory.
The interfacing circuit aids in accessing the memory.

B a s i c c onc e pt of me mor y i nt e r f a c i ng:

1. Microprocessor 8085 can access 64Kbytes memory since address bus is 16-bit. But it is
not always necessary to use full 64Kbytes address space. The total memory size depends
upon the application.
2. Generally EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as a
data memory. W hen both, EPROM and RAM are used, the total address space 64Kbytes
is shared by them.
3. The capacity of program memory and data memory depends on the application.
4. It is not always necessary to select 1 EPROM and 1 RAM. W e can have multiple EPROMs
and multiple RAMs as per the requirement of application.
 5. We can place EPROM/RAM anywhere in full 64 Kbytes address space. But program
memory (EPROM) should be located from address 0000H since reset address of 8085
microprocessor is 0000H.
6. It is not always necessary to locate EPROM and RAM in consecutive memory For
example : If the mapping of EPROM is from 0000H to OFFFH, it is not must to locate RAM
from 1000H. W e can locate it anywhere between 1000H and FFFFH. W here to locate
memory component totally depends on the application.

The memory interfacing requires to :

x Select the chip

x Identify the register
x Enable the appropriate buffer.
Microprocessor system includes memory devices and I/O devices. It is important to note that
microprocessor can communicate (read/write) with only one device at a time, since the data,
address and control buses are common for all the devices. In order to communicate with memory
or I/O devices, it is necessary to decode the address from the microprocessor. Due to this each
device (memory or I/O) can be accessed independently. The following section describes common
address decoding techniques.

Address Decoding Techniques :

x Absolute decoding/Full Decoding

x Linear decoding/Partial Decoding
Absolute decoding:

In absolute decoding technique, all the higher address lines are decoded to select the memory
chip, and the memory chip is selected only for the specified logic levels on these high-order
address lines; no other logic levels can select the chip. Fig. 4.14 shows the Memory Interfacing in
8085 with absolute decoding. This addressing technique is normally used in large memory
systems.
Linear decoding:

In small systems, hardware for the decoding logic can be eliminated by using individual high-
order address lines to select memory chips. This is referred to as linear decoding. Fig. 4.15
shows the addressing of RAM with linear decoding technique. This technique is also
called partial decoding. It reduces the cost of decoding circuit, but it has a drawback of multiple
addresses (shadow addresses).
Fig. 4.15 shows the addressing of RAM with linear decoding technique. A15 address line, is
directly connected to the chip select signal of EPROM and after inversion it is connected to the
chip select signal of the RAM. Therefore, when the status of A15 line is ‘zero’, EPROM gets
selected and when the status of A15 line is ‘one’ RAM gets selected. The status of the other
address lines is not considered, since those address lines are not used for generation of chip
select signals.

Programmable peripheral interface:(8255 PPI)

x The peripherals can not be connected with the microprocessor directly so we use 8255
which is known as programmable peripheral interface(PPI).

x 8255 is a general purpose programmable device used for data transfer between processor
and I/O devices. • It has 3 programmable I/O ports (PA,PB &PC) and port operation
(IN/OUT Port) is defined by control word in the control word register. • Ports are operated
in two modes: • i) I/O modes: Mode 0, Mode 1,& Mode 2 • Ii) BSR (Bit set/Reset) mode

Internal block diagram of 8255 PPI:

8255A is widely used programmable parallel I/O device. It can be programmed to transfer data
under various conditions, from simple I/O to interrupt I/O. It is flexible, versatile and economical
(when multiple I/O ports are required), but somewhat complex. It is an important general purpose
I/O device that can be used with almost any microprocessor.

The 8255A has 24 input output pins that can be grouped primarily in two 8 bits parallel ports: A
and B, with the remaining 8 bits as port C. The 8 bits of port C can be used as individual bits or
be grouped in two four bits ports: Cupper (CU) and Clower (CL) as in figure (a). The functions of
these ports are defined by writing a control word in the control registers.

The internal architecture of 8255 consists of 3 section.

1. Data bus buffer
2. Read/write control logic
3. Group A & Group B control
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus.
Data is transmitted or received by the buffer upon execution of input or output instructions by the
CPU. Control words and status information are also transferred through the data bus buffer.

Read/Write and Control Logic

The function of this block is to manage all of the internal and external transfers of both Data and
Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn,
issues commands to both of the Control Groups.

Group A and Group B Controls

The functional configuration of each port is programmed by the systems software. In essence,
the CPU "outputs" a control word to the 8255. The control word contains information such as
"mode", "bit set", "bit reset", etc., that initializes the functional configuration of the 8255. Each of
the Control blocks (Group A and Group B) accepts "commands" from the Read/W rite Control
logic, receives "control words" from the internal data bus and issues the proper commands to its
associated ports.

Ports A, B, and C
The 8255 contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of
functional characteristics by the system software but each has its own special features or
"personality" to further enhance the power and flexibility of the 8255.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both "pull-up" and "pull-
down" bus-hold devices are present on Port A.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This
port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit
latch and it can be used for the control signal output and status signal inputs in conjunction with
ports A and B.

Operating modes of 8255 PPI:

There are two different modes of 8255. These modes are:

x Bit Set Reset (BSR) Mode
x Input/ Output Mode
x Bit Set Reset (BSR) Mode
x This mode is used to set or reset the bits of the Port-C only. For BSR mode always D7 will
be 0. The control register is looking like this:
x The (D3, D2, D1) will be 000 to 111. In this mode it affects only one bit of Port C at a time.
When user set the bit, it remains set until user unset it. The user needs to load the bit
pattern in control register to change the bit.

x Input/ Output Mode

x This mode is selected when the D7 bit of the control register is 1.
x This mode has also three different modes. These modes are Mode 0 and Mode 1 and
Mode 3.
x Mode 0 – Simple or basic I/O Mode
x In this mode all of the ports A, B and C can be used as input or output mode. The outputs
are latched, but inputs are not latched. This mode has interrupt handling capability.
x Mode 1 – Handshake or Strobed I/O
x In this mode the Port A and Port B can be used as input or output ports, the port C are
used for handshaking. In this mode the inputs and outputs are latched. This mode also
has the interrupt handling capability, and signal control to match the speed of CPU and IO
devices.
x Mode 3 – Bidirectional I/O
x In this mode only Port A can work, and port B can either be in mode 0 or mode 1, and the
port C are used for handshaking. In this mode the inputs and outputs are latched. The
control register is looking like below in this mode:
Bits Function

D7 1 for IO mode and 0 for BSR mode

D6 & D5 These are used to set port A mode. for 00, it is m0 mode, for 01, it is m2 mode and 10 or 11, it is m

D4 1 when port A is taking input, 0 when port A is sending output.

D3 1 when higher nibble of port C is taking input, and 0 when higher nibble is sending output.

D2 It tells the mode of Port B. For 0, it is m0 mode, and for 1, it is m1 mode.

D1 1 when port B is taking input, 0 when port B is sending output.

D0 1 when lower nibble of port C is taking input, and 0 when lower nibble is sending output.

Pin diagram of 8255 PPI :

PA0 to PA1

These pins are the data lines for the port A. These pins are equally distributed on both sides of
the top of the 8255 IC. The keys 1 to 4 and 37 to 40 are the pins devoted for port A.
PB0 to PB1

These pins are the data lines for Port B and the keys 18 to 25 are the pins that carry the data of
port B.

PC0 to PC1

These pins are the data lines for the port C. The keys 10 to 17 carry the data bits of port A.
Among these, the pins 10 to 13 are the Port C upper pins, and 314 to 17 are the pins devoted for
port C lower.

D0 to D7

These pins carry the 8-bit binary code which is used to instruct the working of the entire IC.
These pins together are called as the control word or control register. The keys 27 to 34 carry the
contents of the control word.

A0 and A1

These pins decide which port will be selected for transferring the data. These keys are present at
pins 8 and 9.

A0 A1 Port selected

0 0 Port A

0 1 Port B

1 0 Port C

1 1 Control Register

RD'

It is an active low signal key which puts the IC in reading mode. It is present at key number 5.

WR'

It is an active low signal key which puts the IC in writing mode. It is present at key number 36.

CS'

It is also an active low signal key which is responsible for chip selection. The key number 6 is
devoted to chip select key.
RESET

This key present at 35 number when in set mode, resets the entire data present in all the keys to
their default values.

GND

There is one ground key for 8255 IC present at key number 7.

VCC

The VCC key is from where the IC receives the 5V input. It is present at the key 26.

ADC interfacing with 8255 PPI:

Interface 8255 with 8085 that are explained before.

• The ADC 0808 is 8 -channel 8 -bit ADC chip.

• It has 8 analog inputs i. e. IN 0 -IN 7.

• One of these channels is selected by sending address to a address line of ADC.

 DAC interfacing with 8255 PPI

Follow the initial 3 steps of interfacing of 8255 with 8085 that are explained before.

• The DAC 0808 is 8 -bit digital to analog convertor IC.

• It converts digital data into equivalent analog current.

• Therefore I to V converter is used to convert analog output current of DAC to equivalent analog
voltage. • PA 0 -PA 7 pins of Port A are connected to D 0 -D 7 pins of DAC.

• In above DAC dual power supply of +/- 10 V is applied with reference voltage 10 V as shown in
diagram.

• According to theory of DAC Equivalent analog output is given as: V 0=Vref

Ex: 1. If data =00 H [0000], Vref= 10 V V 0= 0 Volts. 2. If data is 80 H [10000000], Vref= 10 V V 0= 5

Volts.

The control word format of 8255 for above interfacing is given as: • Control word = 80 H
 PROGRAM CODE

Interfacing seven segment displays

An output device which is very common is, especially in the kit of 8085 microprocessor and it is
the Light Emitting Diode consisting of seven segments. Moreover, we have eight segments in a
LED display consisting of 7 segments which includes ‘.’, consisting of character 8 and having a
decimal point just next to it. W e denote the segments as ‘a, b, c, d, e, f, g, and dp’ where dp
signifies ‘.’ which is the decimal point. Moreover, these are LEDs or together a series of Light
Emitting Diodes. W e have shown the internal circuit comprising of a display of seven segment is
as shown in Fig 2
a 7-segment display is as shown in the following Fig
Generate square wave on all line of 8255 PPI
program
Address HEX Codes Labels Mnemonics Comment

8000 16, AA MVI D,AAH Load 10101010 into D

8002 7A ROTATE MOV A,D Load D to A

8003 07 RLC Rotate A to the left

8004 57 MOV D,A Store A into D again

8005 E6, 01 ANI 01H Mask A with 01H

8007 D3, 10 OUT 10H Send output to port 10

8009 C3, 02, 80 JMP ROTATE Jump to ROTATE for next phase

Design Interface a traffic light control system using 8255

The 8085 Microprocessor is a popular Microprocessor used in Industries for various applications.
Such as traffic light control, temperature control, stepper motor control, etc. In this project, the
traffic lights are interfaced to Microprocessor system through buffer and ports of programmable
peripheral Interface 8255. So the traffic lights can be automatically switched ON/OFF in desired
sequence. The Interface board has been designed to work with parallel port of Microprocessor
system.
Source Program:
MVI A, 80H: Initialize 8255, port A and port B

OUT 83H (CR): in output mode

START: MVI A, 09H

OUT 80H (PA): Send data on PA to glow R1 and R2

MVI A, 24H

OUT 81H (PB): Send data on PB to glow G3 and G4

MVI C, 28H: Load multiplier count (40ıο) for delay

CALL DELAY: Call delay subroutine

MVI A, 12H

OUT (81H) PA: Send data on Port A to glow Y1 and Y2

OUT (81H) PB: Send data on port B to glow Y3 and Y4

MVI C, 0AH: Load multiplier count (10ıο) for delay

CALL: DELAY: Call delay subroutine

MVI A, 24H

OUT (80H) PA: Send data on port A to glow G1 and G2

MVI A, 09H

OUT (81H) PB: Send data on port B to glow R3 and R4

MVI C, 28H: Load multiplier count (40ıο) for delay

CALL DELAY: Call delay subroutine

MVI A, 12H

OUT PA: Send data on port A to glow Y1 and Y2

OUT PB: Send data on port B to glow Y3 and Y4

MVI C, 0AH: Load multiplier count (10ıο) for delay

CALL DELAY: Call delay subroutine

JMP START

Delay Subroutine:
DELAY: LXI D, Count: Load count to give 0.5 sec delay

BACK: DCX D: Decrement counter

MOV A, D

ORA E: Check whether count is 0

JNZ BACK: If not zero, repeat

DCR C: Check if multiplier zero, otherwise repeat

JNZ DELAY

RET: Return to main program

 COURSE MATERIAL
Chapter-5 Microprocessor(Architecture and programming-
16 bit-8086)

5.1 Register organization of 8086:

x The 8086 has four groups of the user accessible internal registers.

These are

1. Instruction pointer(IP)

2. Four General purpose registers(AX,BX,CX,DX)

3. Four pointer (SP,BP,SI,DI)

4. Four segment registers (CS,DS,SS,ES)

5. Flag Register(FR)

x The 8086 has a total of fourteen 16-bit registers including a 16 bit register called the status
register (flag register), with 9 of bits implemented for status and control flags.

x Most of the registers contain data/instruction offsets within 64 KB memory segment.

x There are four different 64 KB segments for instructions, stack, data and extra data. To
specify where in 1 MB of processor addressable memory these 4 segments are located
the processor uses four segment registers:

Segment Registers
1.Code segment (CS)

It is a 16-bit register containing address of 64 KB segment with processor instructions. The

processor uses CS segment for all accesses to instructions referenced by instruction pointer
(IP) register.

2. Stack segment (SS)

It is a 16-bit register containing address of 64KB segment with program stack. By default, the
processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP)
registers is located in the stack segment. SS register can be changed directly using POP
instruction.

3. Data and Extra segment (DS and ES)

It is a 16-bit register containing address of 64KB segment with program data. By default, the
processor assumes that all data referenced by general registers (AX, BX, CX, and DX) and
index register (SI, DI) is located in the data and Extra segment.

Data Registers
 1) AX (Accumulator)

It is consists of two 8-bit registers AL and AH, which can be combined together and used
as a 16-bit register AX. AL in this case contains the loworder byte of the word, and AH
contains the high-order byte. Accumulator can be used for I/O operations and string
manipulation.

2) BX (Base register)

x It is consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the loworder byte of the word,
and BH contains the high-order byte.

x BX register usually contains a offset for data segment.

3) CX (Count register)

x It is consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. W hen combined, CL register contains the low-order
byte of the word, and CH contains the high-order byte.

x Count register can be used in Loop, shift/rotate instructions and as a counter in

string manipulation.

x 8086 has the LOOP instruction which is used for conuter purpose when it is
executed CX/CL is automatically decremented by 1.

4) DX (Data register)

x It is consists of two 8-bit registers DL and DH, which can be combined

together and used as a 16-bit register DX. W hen combined, DL register
contains the low-order byte of the word, and DH contains the high-order
byte.

x DX can be used as a port number in I/O operations.

x In integer 32-bit multiply and divide instruction the DX register contains high-
order word of the initial or resulting number.

Pointer register
1. Stack Pointer (SP) is a 16-bit register is used to hold the offset address for stack
segment.

2. Base Pointer (BP) is a 16-bit register is used to hold the offset address for stack segment.

i)BP register is usually used for based, based indexed or register indirect addressing.

ii)The difference between SP and BP is that the SP is used internally to store the address
in case of interrupt and the CALL instrn.

3. Source Index (SI) and Destination Index (DI ) These two 16-bit register is used to
hold the offset address for DS and ES in case of string manipulation instrn.

i. SI is used for indexed, based indexed and register indirect addressing, as well as a
source data addresses in string manipulation instructions.
ii. DI is used for indexed, based indexed and register indirect addressing, as well as a
destination data addresses in string manipulation instructions.

Instruction Pointer (IP)

It is a 16-bit register. It acts as a program counter and is used to hold the offset address
for CS

Flag register
A flag is a 16-bit register containing 9 one bit flags.

i. Overflow Flag (OF)

x This flag is set if an overflow occurs. i.e. if the result of a signed operation is large
enough to be accommodated in a destination register.

ii. Direction Flag (DF) –

x This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address to the highest address. i.e. auto-
incrementing mode.

x Otherwise, the string is processed from the highest address towards the lowest
address, i.e. auto-decrementing mode.

iii. Interrupt-enable Flag (IF) –

x If this flag is set, the maskable interrupts are recognized by the CPU.
Otherwise they are ignored. Setting this bit enables maskable interrupts.

iv. Single-step Flag (TF) –

x If this flag is set, the processor enters the single step execution mode. In
other words, a trap interrupt is generated after execution of each instruction.
The processor executes the current instruction and the control is transferred
to the Trap interrupt service routine.

v. Sign Flag (SF) –

x This flag is set when the result of any computation is negative. For signed
computations, the sign flag equals the MSB of the result.

vi. Zero Flag (ZF) –

x set if the result is zero.

vii. Auxiliary carry Flag (AF) –

x set if there was a carry from or borrow to bits 0-3 in the AL register.

viii. Parity Flag (PF) –

x set if parity (the number of "1" bits) in the low-order byte of the result is even.

ix. Carry Flag (CF) –

 x This flag is set when there is a carry out of MSB in case of addition or a
borrow in case of subtraction. For example. When two numbers are added, a
carry may be generated out of the most significant bit position. The carry
flag, in this case, will be set to 1’. In case, no carry is generated, it will be ‘0.

5.2 Internal Architecture of 8086

The 8086 has two parts, the Bus Interface Unit (BIU) and the Execution Unit (EU). – The BIU
fetches instructions, reads and writes data, and computes the 20-bit address. – The EU decodes
and executes the instructions using the 16-bit ALU. – The two units functions independently.

Minimum and Maximum Modes: – The minimum mode is selected by applying logic 1 to the MN /
MX input pin. This is a single microprocessor configuration. – The maximum mode is selected by
applying logic 0 to the MN / MX input pin. This is a multi micro processors configuration.

Bus Interface Unit (BIU):

x The BIU performs all bus operations such as instruction fetching, reading and writing
operands for memory and calculating the addresses of the memory operands.

x The instruction bytes are transferred to the instruction queue.

x It provides a full 16 bit bidirectional data bus and 20 bit address bus.

x The bus interface unit is responsible for performing all external bus operations.

Specifically it has the following functions:

x Instruction fetch , Instruction queuing, Operand fetch and storage, Address calculation
relocation and Bus control.

x The BIU uses a mechanism known as an instruction queue to implement a pipeline

architecture.
 x This queue permits prefetch of up to six bytes of instruction code. W henever the queue of
the BIU is not full and it has room for at least two more bytes and at the same time EU is
not requesting it to read or write operands from memory, the BIU is free to look ahead in
the program by prefetching the next sequential instruction.

x These prefetching instructions are held in its FIFO queue. W ith its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory cycle.

x After a byte is loaded at the input end of the queue, it automatically shifts up through the
FIFO to the empty location nearest the output.

x The EU accesses the queue from the output end. It reads one instruction byte after the
other from the output of the queue. If the queue is full and the EU is not requesting access
to operand in memory.

x These intervals of no bus activity, which may occur between bus cycles, are known as
Idle state.

x If the BIU is already in the process of fetching an instruction when the EU request it to
read or write operands from memory or I/O, the BIU first completes the instruction fetch
bus cycle before initiating the operand read / write cycle.

x The BIU also contains a dedicated adder which is used to generate the 20bit physical
address that is output on the address bus. This address is formed by adding an appended
16 bit segment address and a 16 bit offset address.

x For example: The physical address of the next instruction to be fetched is formed by
combining the current contents of the code segment CS register and the current contents
of the instruction pointer IP register.

EXECUTION UNIT (EU):

x The Execution unit is responsible for decoding and executing all instructions.

x The EU extracts instructions from the top of the queue in the BIU, decodes them,
generates operands if necessary, passes them to the BIU and requests it to perform the
read or write bys cycles to memory or I/O and perform the operation specified by the
instruction on the operands.

x During the execution of the instruction, the EU tests the status and control flags and
updates them based on the results of executing the instruction.

x If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted
to top of the queue.

x W hen the EU executes a branch or jump instruction, it transfers control to a location

corresponding to another set of sequential instructions.

x W henever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.

The BIU contains the following registers:

IP - the Instruction Pointer

CS - the Code Segment Register

DS - the Data Segment Register

SS - the Stack Segment Register

ES - the Extra Segment Register

The BIU fetches instructions using the CS and IP, written CS: IP, to contract the 20-bit address.
Data is fetched using a segment register (usually the DS) and an effective address (EA)
computed by the EU depending on the addressing mode.

5.3 Signal description of 8086:

The following signal descriptions are common for both modes.

AD15-AD0:
These are the time multiplexed memory I/O address and data lines. Address remains
on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and
T4.
A19/S6, A18/S5, A17/S4, A16/S3:
These are the time multiplexed address and status lines. During T1 these
are the most significant address lines for memory operations. During I/O
 operations, these lines are low. During memory or I/O operations, status
information is available on those lines for T2, T3, Tw and T4.

• A16/S3,A17/S4-
A16,A17 are multiplexed with segment identifier signals S3
and S4 which combinedly indicate which segment register
is presently being used for memory accesses as in below
fig.

S4 S3 Indication

0 0 Extrasegment(ES)

0 Stack segment(SS)
1

1 Code segment(CS)
0

1 Data segment (DS)

1

• A18/s5: A18 is multiplexed with status S5 of the interrupt enable flag bit
which is updated at the beginning of each clock cycle.
• A19/s6: A18 is multiplexed with status S6.

/ S7: (Bus High enable)

• The bus high enable is used to indicate the transfer of data over the higher
order (D15-D8) data bus as shown in table.
• It goes low for the data transfer over D15-D8 and is used to derive chip
selects of odd address memory bank or peripherals. BHE is low during T1 for
read, write and interrupt acknowledge cycles, whenever a byte is to be
transferred on higher byte of data bus.
• The status information is available during T2, T3 and T4. The signal is active
low.
A0 Indication

0 0 Whole W ord

0 1 Upper byte from or to odd address

1 0 Lower byte from or to even address

1 1 None

(Read):
• This signal on low indicates the peripheral that the processor is performing s
memory or I/O read operation. The signal is active low.
READY:
 • This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is
synchronized by the 8284A clock generator to provide ready input to the
8086. This signal is active high.
• enter into wait states and remain idle : READY = 0
• no effect on the operation of µ : READY = 1

INTR (Interrupt Request):

• This is a level triggered input and hardware interrupt pin.
• If any interrupt request is pending, the processor enters the interrupt
acknowledge cycle. This can be internally masked by resulting the interrupt
enable flag.

NMI : non-maskable interrupt

• This is a edge triggered input and hardware interrupt pin which causes Type
2 interrupt.

:
This input is examined by a ‘W AIT’ instruction.
•
If the TEST pin goes low, execution will continue, else the processor remains
•
in an idle state.
CLK (Clock Input):
• The clock input provides the basic timing for processor operation and bus
control activity. VCC (power supply) : +5.0V, ±10% RESET:
• µ : reset if RESET is high

GND(Ground) : Two pins labeled GND(0 voltage

Minimum modes & Timings:

Pin functions for the minimum mode operation of 8086
1. M/IO’
x This is a status line logically equivalent to S2 in maximum mode. W hen it is low, it
indicates the CPU is having an I/O operation, and when it is high, it indicates that the
CPU is having a memory operation.
2. INTA’(Interrupt Acknowledge):
x when this signal it goes low, the processor has accepted the interrupt.
3. ALE (Address Latch Enable):
x This output signal indicates the availability of the valid address on the address/data
lines, and is connected to latch enable input of latches.
4. DT/R’ (Data Transmit/Receive):
x This output is used to decide the direction of data flow through the transreceivers
(bidirectional buffers).
x When the processor sends out data, this signal is high and when the processor is
receiving data, this signal is low.
5. DEN’( Data Enable):
 x This signal indicates the availability of valid data over the address/data lines. It is used
to enable the transreceivers (bidirectional buffers) to separate the data from the
multiplexed address/data signal.
6. HOLD, HLDA- Acknowledge:
x When the HOLD line goes high, it indicates to the processor that another master is
requesting the bus access.
x The processor, after receiving the HOLD request, issues the hold acknowledge signal
on HLDA pin, in the middle of the next clock cycle after completing the current bus
cycle.
7. WR’(Write):
x When it is low the processor perform memory or Io write .
Pin functions for the maximum mode operation of 8086:

1. S2’,S1’,S0’ – Status Lines:

x These signals are connected to 8288.These are the status lines which reflect the
type of operation according to the below table, being carried out by the processor.

S2’ S1’ S0’ Indication

0 0 0 Interrupt acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
0 0 0 Code access
0 0 1 Read memory
0 1 0 Write memory
0 1 1 Passive State

2.LOCK’:
• This output pin indicates that other system bus master will be prevented from gaining the
system bus, while the LOCK signal is low
• The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until the
completion of the next instruction. W hen the CPU is executing a critical instruction which
requires the system bus, the LOCK prefix instruction ensures that other processors connected
in the system will not gain the control of the bus.
3. QS1, QS0 (queue status)
• These lines give information about the status of the code-prefetch queue. These are
active during the CLK cycle after while the queue operation is performed
 QS 1 QS 0 Indication

0 0 No operation

0 1 First byte of opcode from the queue

1 0 Empty Queue

1 1 Subsequent byte from queue

RQ/GT1’ , RQ/GT0’ : (Request/Grant)

x These pins are used by the other local bus master in maximum mode, to force the
processor to release the local bus at the end of the processor current bus cycle.

x Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1.

ADDRESSING MODES OF 8086

Addressing mode indicates a way of locating data or operands. Depending upon the data types
used in the instruction and the memory addressing modes, any instruction may belong to one or
more addressing modes, or some instruction may not belong to any of the addressing modes.
Thus the addressing modes describe the types of operands and the way they are accessed for
executing an instruction. Here, we will present the addressing modes of the instructions
depending upon their types. According to the flow of instruction execution, the instructions may
be categorized as
(i) Sequential control flow instructions and

(ii) Control transfer instructions.

Sequential control flow instructions are the instructions, which after execution, transfer
control to the next instruction appearing immediately after it (in the sequence) in the
program. For example, the arithmetic, logical, data transfer and processor control
instructions are sequential control flow instructions. The control transfer instructions, on
the other hand, transfer control to some predefined address somehow specified in the
instruction after their execution. For example, INT, CALL, RET and JUMP instructions fall
under this category.

The addressing modes for sequential control transfer instructions are explained as
follows:

1. Immediate:

In this type of addressing, immediate data is a part of instruction, and appears in the
form of successive byte or bytes.

Example: MOV AX, 0005H

In the above example, 0005H is the immediate data. The immediate data may be 8-bit
or 16-bit in size.

2. Direct:

In the direct addressing mode, a 16-bit memory address (offset) is directly specified in
the instruction as a part of it.

Example: MOV AX, [5000H]

Here, data resides in a memory location in the data segment, whose effective address
may be computed using 5000H as the offset address and content of DS as segment
address. The effective address, here, is 10H*DS+5000H.

3. Register:

In register addressing mode, the data is stored in a register and it is referred using the
particular register. All the registers, except IP, may be used in this mode.

Example: MOV BX, AX.

4. Register Indirect:

Sometimes, the address of the memory location, which contains data or operand, is
determined in an indirect way, using the offset registers. This mode of addressing is
known as register indirect mode. In this addressing mode, the offset address of data is
in either BX or SI or DI registers. The default segment is either DS or ES. The data is
supposed to be available at the address pointed to by the content of any of the above
registers in the default data segment.

Example: MOV AX, [BX]

Here, data is present in a memory location in DS whose offset address is in BX. The
effective address of the data is given as 10H*DS+ [BX].
5. Indexed:

In this addressing mode, offset of the operand is stored in one of the index registers.
DS and ES are the default segments for index registers SI and DI respectively. This
mode is a special case of the above discussed register indirect addressing mode.

Example: MOV AX, [SI]

Here, data is available at an offset address stored in SI in DS. The effective address,
in this case, is computed as 10H*DS+ [SI].

6. Register Relative:

In this addressing mode, the data is available at an effective address formed by adding
an 8-bit or 16-bit displacement with the content of any one of the registers BX, BP, SI and
DI in the default (either DS or ES) segment. The example given before explains this
mode.

Example: MOV Ax, 50H [BX]

Here, effective address is given as 10H*DS+50H+ [BX].

7. Based Indexed:

The effective address of data is formed, in this addressing mode, by adding content of
a base register (any one of BX or BP) to the content of an index register (any one of SI
or DI). The default segment register may be ES or DS.

Example: MOV AX, [BX] [SI]

Here, BX is the base register and SI is the index register. The effective address is
computed as 10H*DS+ [BX] + [SI].

8. Relative Based Indexed:

The effective address is formed by adding an 8-bit or 16-bit displacement with the sum
of contents of any one of the bases registers (BX or BP) and any one of the index
registers, in a default segment. Example: MOV AX, 50H [BX] [SI]

Here, 50H is an immediate displacement, BX is a base register and SI is an index

register. The effective address of data is computed as 160H*DS+ [BX] + [SI] + 50H.

8086 Instruction Set and Assembler Directives:

The 8086 microprocessor supports 6 types of Instructions. They are

1. Data transfer instructions

2. Arithmetic instructions

3. Bit manipulation instructions

4. String instructions

5. Program Execution Transfer instructions (Branch & loop Instructions)

6. Processor control instructions

1. Data Transfer instructions: These instructions are used to transfer the data from
source operand to destination operand. All the store, move, load, exchange, input and
output instructions belong to this group.

General purpose byte or word transfer instructions:

MOV : Copy byte or word from specified source to specified destination

PUSH : Push the specified word to top of the stack

POP : Pop the word from top of the stack to the specified location

PUSHA : Push all registers to the stack

POPA : Pop the words from stack to all registers

XCHG : Exchange the contents of the specified source and destination operands one
of which may be a register or memory location.

XLAT : Translate a byte in AL using a table in memory

Simple input and output port transfer instructions:

1. IN : Reads a byte or word from specified port to the accumulator

2. OUT : Sends out a byte or word from accumulator to a specified port

Special address transfer instructions:

1. LEA : Load effective address of operand into specified register

2. LDS : Load DS register and other specified register from memory

3. LES : Load ES register and other specified register from memory.

Flag transfer registers:

1. LAHF : Load AH with the low byte of the flag register

2. SAHF : Store AH register to low byte of flag register

3. PUSHF : Copy flag register to top of the stack

4. POPF : Copy word at top of the stack to flag register

2. Arithmetic instructions : These instructions are used to perform various

mathematical operations like addition, subtraction, multiplication and division etc….

Addition instructions:

1.ADD : Add specified byte to byte or word to word

2.ADC : Add with carry

3.INC : Increment specified byte or specified word by 1

4.AAA : ASCII adjust after addition

5.DAA : Decimal (BCD) adjust after addition

Subtraction instructions:

1. SUB : Subtract byte from byte or word from word

2. SBB : Subtract with borrow

3. DEC : Decrement specified byte or word by 1

4. NEG : Negate or invert each bit of a specified byte or word and add 1(2’s
complement)

5. CMP : Compare two specified byte or two specified words

6. AAS : ASCII adjust after subtraction

7. DAS : Decimal adjust after subtraction

Multiplication instructions:

1. MUL : Multiply unsigned byte by byte or unsigned word or word.

2. IMUL : Multiply signed bye by byte or signed word by word

3. AAM : ASCII adjust after multiplication

Division instructions:

1. DIV : Divide unsigned word by byte or unsigned double word by word

2. IDIV : Divide signed word by byte or signed double word by word

3. AAD : ASCII adjust after division

4. CBW : Fill upper byte of word with copies of sign bit of lower byte

5. CW D : Fill upper word of double word with sign bit of lower word.

3. Bit Manipulation instructions : These instructions include logical , shift and rotate
instructions in which a bit of the data is involved.

Logical instructions:

1. NOT :Invert each bit of a byte or word.

2. AND : ANDing each bit in a byte or word with the corresponding bit in another byte
or word.

3. OR : ORing each bit in a byte or word with the corresponding bit in another byte or
word.

4. XOR : Exclusive OR each bit in a byte or word with the corresponding bit in another
byte or word.

5. TEST :AND operands to update flags, but don’t change operands.

Shift instructions:

1. SHL/SAL : Shift bits of a word or byte left, put zero(S) in LSBs.

2. SHR : Shift bits of a word or byte right, put zero(S) in MSBs.

3. SAR : Shift bits of a word or byte right, copy old MSB into new MSB.

Rotate instructions:

1. ROL : Rotate bits of byte or word left, MSB to LSB and to Carry Flag [CF]

2. ROR : Rotate bits of byte or word right, LSB to MSB and to Carry Flag [CF]

3. RCR :Rotate bits of byte or word right, LSB TO CF and CF to MSB

4. RCL :Rotate bits of byte or word left, MSB TO CF and CF to LSB

4. String instructions:

A string is a series of bytes or a series of words in sequential memory locations. A

string often consists of ASCII character codes.

1. REP : An instruction prefix. Repeat following instruction until CX=0

2. REPE/REPZ : Repeat following instruction until CX=0 or zero flag ZF=1

3. REPNE/REPNZ : Repeat following instruction until CX=0 or zero flag ZF=1

4. MOVS/MOVSB/MOVSW : Move byte or word from one string to another

5. COMS/COMPSB/COMPSW : Compare two string bytes or two string words

6. INS/INSB/INSW : Input string byte or word from port

7. OUTS/OUTSB/OUTSW : Output string byte or word to port

8. SCAS/SCASB/SCASW : Scan a string. Compare a string byte with a byte in AL or a

string word with a word in AX

9. LODS/LODSB/LODSW : Load string byte in to AL or string word into AX

5. Program Execution Transfer instructions:

These instructions are similar to branching or looping instructions. These instructions

include conditional & unconditional jump or loop instructions.

Unconditional transfer instructions:

1. CALL : Call a procedure, save return address on stack

2. RET : Return from procedure to the main program.

3. JMP : Goto specified address to get next instruction

Conditional transfer instructions:

1. JA/JNBE : Jump if above / jump if not below or equal

2. JAE/JNB : Jump if above /jump if not below

3. JBE/JNA : Jump if below or equal/ Jump if not above

4. JC : jump if carry flag CF=1

5. JE/JZ : jump if equal/jump if zero flag ZF=1

6. JG/JNLE : Jump if greater/ jump if not less than or equal

7. JGE/JNL : jump if greater than or equal/ jump if not less than

8. JL/JNGE : jump if less than/ jump if not greater than or equal

9. JLE/JNG : jump if less than or equal/ jump if not greater than

10.JNC : jump if no carry (CF=0)

11.JNE/JNZ : jump if not equal/ jump if not zero(ZF=0)

12.JNO : jump if no overflow(OF=0)

13.JNP/JPO : jump if not parity/ jump if parity odd(PF=0)

14.JNS : jump if not sign(SF=0)

15.JO : jump if overflow flag(OF=1)

16.JP/JPE : jump if parity/jump if parity even(PF=1)

17.JS : jump if sign(SF=1)

6. Iteration control instructions:

These instructions are used to execute a series of instructions for certain number of
times.

1. LOOP :Loop through a sequence of instructions until CX=0

2. LOOPE/LOOPZ : Loop through a sequence of instructions while ZF=1 and CX = 0

3. LOOPNE/LOOPNZ : Loop through a sequence of instructions while ZF=0 and CX

=0

4. JCXZ : jump to specified address if CX=0

ASSEMBLER DIRECTIVES :
Assembler directives are the directions to the assembler which indicate how an
operand or section of the program is to be processed. These are also called pseudo
operations which are not executable by the microprocessor. The various directives are
explained below.

1. ASSUME : The ASSUME directive is used to inform the assembler the name of the
logical segment it should use for a specified segment.

Ex: ASSUME DS: DATA tells the assembler that for any program instruction which
refers to the data segment ,it should use the logical segment called DATA.

2.DB -Define byte. It is used to declare a byte variable or set aside one or more
storage locations of type byte in memory. For example, CURRENT_VALUE DB 36H
tells the assembler to reserve 1 byte of memory for a variable named CURRENT_
VALUE and to put the value 36 H in that memory location when the program is loaded
into RAM .
 3. DW -Define word. It tells the assembler to define a variable of type word or to
reserve storage locations of type word in memory.

4. DD(define double word) :This directive is used to declare a variable of type double
word or restore memory locations which can be accessed as type double word.

5.DQ (define quadw ord) :This directive is used to tell the assembler to declare a
variable 4 words in length or to reserve 4 words of storage in memory .

6.DT (define ten bytes):It is used to inform the assembler to define a variable which is
10 bytes in length or to reserve 10 bytes of storage in memory.

7. EQU –Equate It is used to give a name to some value or symbol. Every time the
assembler finds the given name in the program, it will replace the name with the value
or symbol we have equated with that name.

8.ORG -Originate : The ORG statement changes the starting offset address of the
data. It allows to set the location counter to a desired value at any point in the
program.For example the statement ORG 3000H tells the assembler to set the location
counter to 3000H.

9 .PROC- Procedure: It is used to identify the start of a procedure or subroutine.

10.END- End program .This directive indicates the assembler that this is the end of the
program module.The assembler ignores any statements after an END directive.

11. ENDP- End procedure: It indicates the end of the procedure (subroutine) to the
assembler.

12.ENDS-End Segment: This directive is used with the name of the segment to
indicate the end of that logical segment.

Simple assembly language programming using 8086

instructions:
Write a Program For Read a Character From The Keyboard

MOV ah, 1h //keyboard input subprogram

INT 21h // character input
// character is stored in al
MOV c, al //copy character from alto c

Write a Program For Reading and Displaying a Character

MOV ah, 1h // keyboard input subprogram

INT 21h //read character into al
MOV dl, al //copy character to dl
MOV ah, 2h //character output subprogram
INT 21h // display character in dl

Write a Program Using General Purpose Registers

ORG 100h
MOV AL, VAR1 // check value of VAR1 by moving it to the AL.
LEA BX, VAR1 //get address of VAR1 in BX.
MOV BYTE PT R [BX], 44h // modify the contents of VAR1.
MOV AL, VAR1 //check value of VAR1 by moving it to the AL.
RET
VAR1 DB 22h
END

Write a Program For Displaying The String Using Library Functions

include emu8086.inc //Macro declaration

ORG 100h
PRINT ‘Hello World!’
GOTOXY 10, 5
PUTC 65 // 65 – is an ASCII code for ‘A’
PUTC ‘B’
RET //return to the operating system.
END //directive to stop the compiler.
 COURSE MATERIAL
Chapter-6 Microcontroller(Architecture and programming-8
bit)

Distinguish between microprocessor & microcontroller

x Microprocessor consists of only a Central Processing Unit, whereas Micro Controller
contains a CPU, Memory, I/O all integrated into one chip.
x Microprocessor is used in Personal Computers whereas Micro Controller is used in an
embedded system.
x Microprocessor uses an external bus to interface to RAM, ROM, and other peripherals, on
the other hand, Microcontroller uses an internal controlling bus.
x Microprocessors are based on Von Neumann model Micro controllers are based on
Harvard architecture
x Microprocessor is complicated and expensive, with a large number of instructions to
process but Microcontroller is inexpensive and straightforward with fewer instructions to
process.

8 bit and 16 bit microcontroller:

x The main difference between 8 bit and 16 bit microcontrollers is the width of the data pipe.

As you may have already deduced, an 8 bit microcontroller has an 8 bit data pipe while a

16 bit microcontroller has a 16 bit data pipe.

x This fundamental difference between 8 bit and 16 bit microcontrollers is felt during

mathematical operations. A 16 bit number gives you a lot more precision than 8 bit

numbers. Although relatively rare, using an 8 bit microcontroller may not suffice the

required accuracy of the application.

x 16 bit microcontrollers are also more efficient in processing math operations on numbers

that are longer than 8 bits. A 16 bit microcontroller can automatically operate on two 16 bit

numbers, like the common definition of an integer. But when you are using an 8 bit

microcontroller, the process is not as straightforward.

x The functions implemented to operate on such numbers will take additional cycles.

Depending on how processing intensive your application is and on how many calculations

you do, this may affect the performance of the circuit.

 x Another key difference between 8 bit and 16 bit microcontrollers is in their timers. 8 bit

microcontrollers can only use 8 bits, resulting in a final range of 0x00 – 0xFF (0-255) every

cycle. In contrast, 16 bit microcontrollers, with its 16 bit data width, has a range of 0x0000

– 0xFFFF (0-65535) for every cycle. A longer timer maximum value can surely come in

handy in certain applications and circuits.

x Initially, the price of 16 bit microcontrollers was way above that of 8 bit microcontrollers.

But as time progressed and designs improved, the price of 8 bit and 16 bit microcontrollers

has reduced quite a lot. 8 bit microcontrollers can be purchased dirt cheap. W hile 16 bit

microcontroller cost more, prices tend to vary a lot depending on the features that are

included in the microcontroller.

CISC & RISC processor:

RISC Processor:

x RISC stands for Reduced Instruction Set Computer Processor, a microprocessor

architecture with a simple collection and highly customized set of instructions. It is built to
minimize the instruction execution time by optimizing and limiting the number of
instructions.
x It means each instruction cycle requires only one clock cycle, and each cycle contains
three parameters: fetch, decode and execute.
x The RISC processor is also used to perform various complex instructions by combining
them into simpler ones. RISC chips require several transistors, making it cheaper to
design and reduce the execution time for instruction.
x Examples of RISC processors are SUN's SPARC, PowerPC, Microchip PIC processors,
RISC-V.

Advantages of RISC Processor

1. The RISC processor's performance is better due to the simple and limited number of the
instruction set.
2. It requires several transistors that make it cheaper to design.
3. RISC allows the instruction to use free space on a microprocessor because of its
simplicity.
4. RISC processor is simpler than a CISC processor because of its simple and quick design,
and it can complete its work in one clock cycle.

Disadvantages of RISC Processor

1. The RISC processor's performance may vary according to the code executed because
subsequent instructions may depend on the previous instruction for their execution in a
cycle.
2. Programmers and compilers often use complex instructions.
 3. RISC processors require very fast memory to save various instructions that require a
large collection of cache memory to respond to the instruction in a short time.

CISC Processor

x The CISC Stands for Complex Instruction Set Computer, developed by the Intel. It has
a large collection of complex instructions that range from simple to very complex and
specialized in the assembly language level, which takes a long time to execute the
instructions.
x So, CISC approaches reducing the number of instruction on each program and ignoring
the number of cycles per instruction.
x It emphasizes to build complex instructions directly in the hardware because the hardware
is always faster than software. However, CISC chips are relatively slower as compared to
RISC chips but use little instruction than RISC. Examples of CISC processors are VAX,
AMD, Intel x86 and the System/360.

Advantages of CISC Processors

1. The compiler requires little effort to translate high-level programs or statement languages
into assembly or machine language in CISC processors.
2. The code length is quite short, which minimizes the memory requirement.
3. To store the instruction on each CISC, it requires very less RAM.
4. Execution of a single instruction requires several low-level tasks.
5. CISC creates a process to manage power usage that adjusts clock speed and voltage.
6. It uses fewer instructions set to perform the same instruction as the RISC.

Disadvantages of CISC Processors

1. CISC chips are slower than RSIC chips to execute per instruction cycle on each program.
2. The performance of the machine decreases due to the slowness of the clock speed.
3. Executing the pipeline in the CISC processor makes it complicated to use.
4. The CISC chips require more transistors as compared to RISC design.
5. In CISC it uses only 20% of existing instructions in a programming event.

Architecture of 8051 microcontroller

x The 8051 Microcontroller is an 8 – bit Microcontroller i.e. it can read, write and process 8 –
bit Data. There are a bunch of manufacturers like Atmel, NXP, TI, who manufacture their
own versions of 8051 Microcontroller.

x Irrespective of the manufacturer, the internal hardware design i.e. the 8051 Microcontroller
Architecture remains more or less the same. The following image shows the 8051
Microcontroller Architecture in a block diagram style.
 We have seen the internal architecture of the 8051 Microcontroller in the above section.
Now, we will see the features of the 8051 Microcontroller Architecture.

Some of the features like internal ROM and RAM will vary with the specific model of the
8051 Microcontroller.

x 8 – bit CPU with two Registers A (Accumulator) and B.

x Internal ROM of 8K Bytes – It is a flash memory that supports in – system programming.
x Internal RAM of 256 Bytes – The first 128 Bytes of the RAM i.e. 00H to 7FH is again
divided in to 4 banks with 8 registers (R0 – R7) in each bank, 16 bit addressable registers
and 80 general purpose registers. The higher 128 Bytes of the RAM i.e. 80H to FFH
consists of SFRs or Special Function Registers. Using SFRs we can control different
peripherals like Timers, Serial Port, all I/O Ports, etc.
x 32 I/O Pins (Input / Output Pins) – Arranged as 4 Ports: P0, P1, P2 and P3.
x 8- bit Stack Pointer (SP) and Processor Status W ord (PSW ).
x 16 – bit Program Counter (PC) and Data Pointer (DPTR).
x Two 16 – bit Timers / Counters – T0 and T1.
x Control Registers – SCON, PCON, TCON, TMOD, IP and IE.
x Serial Data Transmitter and Receiver for Full – Duplex Operation – SBUF.
x Interrupts: Two External and Three Internal.
x Oscillator and Clock Circuit.

Signal description of 8051 microcontrollers

805 1 m i c r oc ont r ol l er i s a 40 pi n D u al I nl i ne P ac k age ( D I P ) . T hes e 40 pi ns s er v e di f f er ent

functions like read, write, I/O operations, interrupts etc. 8051 has four I/O ports wherein
eac h p or t has 8 pi ns w hi c h c an b e c onf i gur e d as i nput or o ut put de pen di n g up on t he
l ogi c s t at e of t he pi ns . T her ef or e, 32 o ut of t hes e 40 pi ns ar e d edi c at ed t o I / O por t s . T he
r e s t o f t h e p i n s a r e d e d i c a t e d t o V C C , G N D , XT A L 1 , XT A L 2 , R S T , A L E , E A ’ a n d P SE N ’ .

P i n di agr am of 8051 m i c r opr oc es s or i s as g i v en bel o w :

D e s c r i p t i o n o f t h e P in s :

x Pin 1 to Pin 8 (Port 1 ) –

Pin 1 to Pin 8 are assigned to Port 1 for simple I/O operations. They can be configured
as input or output pins depending on the logic control i.e. if logic zero (0) is applied to the
I/O port it will act as an output pin and if logic one (1) is applied the pin will act as an
input pin. These pins are also referred to as P1.0 to P1.7 (where P1 indicates that it is a
pin in port 1 and the number after ‘.’ tells the pin number i.e. 0 indicates first pin of the
p o r t . S o , P 1 . 0 m e a n s f i r s t p i n o f p o r t 1 , P 1 . 1 m e a n s s e c o n d p i n o f th e p o r t 1 a n d s o o n ) .
T hes e pi ns ar e bi di r ec t i onal pi ns .

x P i n 9 ( R ST ) –

Reset pin. It is an active-high, input pin. Therefore if the RST pin is high for a minimum of
2 machine cycles, the microcontroller will reset i.e. it will close and terminate all
a c t i v i t i e s . It i s o f t e n r e f e r r e d a s “ p o w e r - o n - r e s e t ” p i n b e c a u s e i t i s u s e d t o r e s e t t h e
m i c r oc ont r ol l er t o i t ’ s i ni t i al v al u es w hen po w er i s on ( hi g h) .

x Pin 10 to Pin 17 (Port 3) –

x Pin 10 to pin 17 are port 3 pins which are also referred to as P3.0 to P3.7. These
pins are similar to port 1 and can be used as universal input or output pins. These
p in s a r e b id i r e c t io n a l p in s .
x These pins also have some additional functions which are as follows:
P 3. 0 ( R X D )

10th pin is RXD (serial data receive pin) which is for serial input. Through this input
s i gnal m i c r oc ont r ol l er r ec ei v es d at a f or s er i al c om m uni c at i on.

P 3. 1 ( T X D ) :
11th pin is TXD (serial data transmit pin) which is serial output pin. Through this
out put s i gn al m i c r oc on t r ol l er t r ans m i t s dat a f or s er i al c om m uni c at i o n.

P 3. 2 an d P 3. 3 ( I N T 0′ , I N T 1′ ) :
12th and 13th pins are for External Hardware Interrupt 0 and Interrupt 1 respectively.
W hen this interrupt is activated(i.e. when it is low), 8051 gets interrupted in whatever
it is doing and jumps to the vector value of the interrupt (0003H for INT0 and 0013H
for INT1) and starts performing Interrupt Service Routine (ISR) from that vector
l oc at i on.

P 3. 4 an d P 3. 5 ( T 0 an d T 1) :
14t h a nd 15t h pi n ar e f or T i m er 0 and T i m er 1 ex t er na l i np ut . T he y c an be c o nn ec t ed
with 16 bit timer/counter.

P3.6 (WR’) : P3.6 (WR’) :

16th pin is for external memory write i.e. writing data to the external memory.

P 3. 7 ( R D ’ ) :
17th pin is for external memory read i.e. reading data from external memory.

Pin 18 and Pin 19 (XTAL2 And XTAL1) –

These pins are connected to an external oscillator which is generally a quartz crystal
oscillator. They are used to provide an external clock frequency of 4MHz to 30MHz.

P i n 20 ( G N D ) –
This pin is connected to the ground. It has to be provided with 0V power supply.
Hence it is connected to the negative terminal of the power supply.

Pin 21 to Pin 28 (Port 2)

P i n 21 t o pi n 28 a r e p or t 2 pi ns al s o r ef er r e d t o as P 2. 0 t o P 2. 7. W hen a ddi t i onal
external memory is interfaced with the 8051 microcontroller, pins of port 2 act as
higher-order address bytes. These pins are bidirectional.

P i n 2 9 ( PS E N ) –
P S E N s t ands f or P r ogr am S t or e E nabl e. I t i s out put , ac t i v e- l o w pi n. T hi s i s us ed t o
read external memory. In 8031 based system where external ROM holds the program
code, this pin is connected to the OE pin of the ROM.

Pin 30 (ALE/ PROG)

ALE stands for Address Latch Enable. It is input, active-high pin. This pin is used to
distinguish between memory chips when multiple memory chips are used. It is also
us ed t o de - m ul t i pl ex t he m ul t i pl ex e d ad dr es s and dat a s i g nal s av a i l abl e at por t 0.
During flash programming i.e. Programming of EPROM, this pin acts as program
pul s e i n put ( P R O G ) .
Pin 31 (EA/ VPP) –
EA stands for External Access input. It is used to enable/disable external memory
interfacing. In 8051, EA is connected to Vcc as it comes with on-chip ROM to store
programs. For other family members such as 8031 and 8032 in which there is no on-
chip ROM, the EA pin is connected to the GND.
Pin 32 to Pin 39 (Port 0) –
Pin 32 to pin 39 are port 0 pins also referred to as P0.0 to P0.7. They are
bi di r ec t i ona l i np ut / out p ut pi ns . T he y d on’ t h a v e an y i nt er n al pu l l - u p s . H enc e, 10 K ?
pul l - up r e gi s t er s ar e u s ed as ex t er n al pul l - u ps . P or t 0 i s al s o des i gnat e d as A D 0-
A D 7 bec aus e 80 51 m ul t i pl ex es a ddr es s and dat a t hr ou gh p or t 0 t o s av e pi ns .
P i n 40 ( V C C ) –
T hi s pi n pr ov i des p o w er s uppl y v ol t a ge i . e. + 5 V ol t s t o t he c i r c ui t .

Me m o r y o r g a n i z a t i o n :
x In the 8051, the memory is organized logically into program memory and data
memory separately. The program memory is read-only type; the
data memory is organized as read–write memory.
x Again, both program and data memories can be within the chip or
outside.
x The Intel 8051 has 128 bytes of RAM and 4 KB of ROM within the chip.
The address bus of the 8051 is 16 bits wide. So it can access 64 KB of
memory.
INTERNAL RAM STRUCTURE:
x The 8051 has 128 bytes of internal data RAM, which is accessible as
bytes or sometimes as bits.
x The address of the internal RAM starts at 00H and occupies space up to
7FH. The RAM space is divided into three blocks—the register banks, the
 bit-addressable memory, and the scratch pad memory.
The 8051 has four register banks of eight registers each, with addresses from
00H to 1FH. In assembly language, they are addressed by the
names R0–R7.
x The register banks are identified with 2 bits in the processor status word.
The PSW has two bits for identifying the register bank, i.e., 00 represents
bank 0, 01 represents bank 1, 10 represents bank 2, and 11 represents
bank 3.
x In the 8051, bitwise operations are also possible with special instructions
using the bit addresses. The bit-addressable memory is both bit-
addressable (from 00H to 7FH) and byte-addressable (from 20H to 2FH).
Bit operations are helpful in many control algorithms.
x Using general-purpose scratch pad memory, programmers can read and
write data at any time for any purpose. This memory ranges from the
byte address 30H to the address 7FH.
SPECIAL FUNCTION REGISTERS (SFRs):
SFR, which occupies upper 128 bytes of internal memory are the
registers, that control the entire processor
They can e accessed by DIRECT addressing.
The registers available in the 8051 are as follows :
Accumulators - A and B
• Process Status W ord - PSW
• I/O port registers - P0, P1, P2, P3
• Data pointers - DPH and DPL
• Serial data buffer register - SBUF
• Stack pointer - SP
• Timer registers - TH0, TH1 and TL0, TL1
• Timer Control Registers - TCON, TMOD
• Power and Port control - PCON, SCON
• Interrupt Control Registers - IP, IE.
• Programmers should not use the addresses in the range 80H to FFH
(other than SFR) as it is used by INTEL CORPORATION for expansion
functions of 8051.
The 8051 has two accumulators -A register and B register. The register B
forms the accumulator for multiplication and division instructions and for
other instructions it can be accessed as a general purpose register.
The stack in the 8051 is organized within the internal RAM area.
The stack pointer is eight bits wide and has to be initialized with an
address in the RAM area. W hen the 8051 is reset, the stack pointer is by
default set to 07H.
The stack pointer is incremented before storing a data in the stack.
Similarly, while reading data from the stack, the data is read first and
then the stack pointer is decremented.

8051 Timers :
x The 8051 comes -with two 16 bit timers, both of which may be
controlled, set, read, and configured individually.
x he 8051 timers have three general functions: Programming predefined length
of time, and then issuing an interrupt request.
x Counting the transitions on an external pin,
Generating baud rates for the serial port.
x Basically the timers are the digital counters which are incremented at
the pulses given to it. The timers can be controlled to -function through
four SFRs namely, TMOD, TCON, TH0/TL0 and TH1/TL1.
x The timers will have overflow when it counts to full value and resets to 0
upon next count. The overflow in the timers will set the two bits in the TCON
SFR. This overflow can be programmed to interrupt the microcontroller execution
and execute a predefined subroutine .
x If the timer registers are incremented by the internal clock pulses from
the microcontroller, then the operation is termed as ‘Timing’ operation.
Meanwhile if the timer registers get their clock pulses from an external
device through the port 3 pins of 8051, then the operation is termed as ‘Counting’.
Timer 0 external input pin P3.4 (T0) is used give clock input to timer 0 to
act as counter.
x Timer 1 external input pin P3.5 (T1) is used give clock input to timer 1.
The 8051 has two timers and each of them will have similar operations
and functions. The timer in 8051 is basically a 16-bit register which can be
incremented depending upon the clock pulses applied to it. These
timer registers are configured as the Special Function Registers.
x These SFRs at any time has the timer/counter register content. So, the timers
can be stopped at any time and the contents can be read from
these registers .Since there are only two bytes devoted to the value of
each timer it is apparent that the maximum value a timer may have is 65,535.
If a timer contains the value 65,535 and is subsequently incremented, it
will reset to 0 with an indication of overflow.
x One timer is TIMER0 and the other is TIMER1. Each timer also has two 8
bit SFRs namely TH0 and TL0 forming the higher and lower order bytes of
Timer0 and TH1 and TL1 forming the higher and lower bytes of Timer1.
x The TMOD SFR -used to control the mode of operation of both timers.
Each bit of the SFR gives the micro controller specific information -how to run
a timer. The higher order four bits (bits 4 through 7) relate to
Timer 1 whereas the low four bits (bits 0 through 3) perform the same
functions for timer 0.

8051 interrupts:
8051 basically has following five interrupt sources so that any of the
following events will make 8051 to execute an interrupt service routine. Timer 0 Overflow.
Timer 1 Overflow. Reception/Transmission of Serial Character.
External hardware interrupt 0.
External hardware interrupt 1.
Different interrupt sources have to be distinguished and 8051 must execute
different subroutines depending –interrupt triggered.
This is accomplished by jumping or calling to a fixed address when interrupt
occurs. These addresses are called interrupt vector addresses or interrupt
handler addresses.
 Interrupt Flag Interrupt Vector
Address
External 0 IE 0 0003h
Timer 0 TF0 000Bh
External 1 IE 1 0013h
Timer 1 TF1 001Bh
Serial RI/TI 0023h

Whenever Timer 0 overflows (i.e., the TF0 bit is set), the main program
will be temporarily suspended and control will jump to 000BH.

It is assumed that service routine at address 0003H handles the situation

of Timer 0 overflowing.

Enabling and disabling the interrupts:

By default at power up, all interrupts are disabled. This means that even
if, for example, the TF0 bit is set, the 8051 will not execute the interrupt.

Programming must be done specifically to enable interrupts. Interrupt Enable Special

Function Register IE SFR at the address A8h is
used to enable and disable interrupts by modifying its bits

The interrupts enabling can be handled individually by - bit addresses for

the individual bits of IE register.

Interrupt Priorities and Polling Sequence

The 8051 automatically evaluates whether an interrupt occurs after every

instruction. W hen checking for interrupt conditions, it checks
them in the following order:

a)External 0 Interrupt

b)Timer 0 Interrupt

c)External 1 Interrupt

d)Timer 1 Interrupt

e)Serial Interrupt

The above list -gives the interrupt priority.

ADDRESSING MODES OF 8051:

The way by which a data in specified in an instruction is called as
addressing mode.

The data fetched for execution depends upon the addressing mode.

The instruction set of 8051 supports 5 addressing modes

i) Immediate Addressing Mode:

 the data to be manipulated is directly given in the
instruction itself. The data is preceded by a # symbol. E.g. ADD A, #80h.

This instruction adds the data 80h to the contents of the accumulator and the
result is stored in the accumulator
itself. This addressing mode will be used when the data for the arithmetic and
logical operation is needed only once and is a constant.

ii) Register Direct Addressing:

The register, that contains the data to be manipulated, is specified in the

instruction.

E.g. ADD A, R0.

This instruction will add the contents stored in register R0 with the
accumulator contents and store the result in accumulator. The registers A,
DPTR and R0 to R7 are used in Register direct addressing.
This addressing mode uses temporary registers which hold the data for
the operation.

iii) Memory Direct Addressing:

The memory address that contains the data to be operated
is specified here in the instruction.

E.g. ADD A, 74h.

This instruction adds the data in accumulator with that

stored in memory address 74h.
All internal RAM addresses including that of special function registers can be
used in memory direct addressing instructions. This addressing mode is
used when the data stored in
memory is to be used in arithmetic and logical instructions. The data
in memory used in the direct addressing can be
changed at any other point in the program.

iii) Memory Indirect Addressing:

The register, which contains the actual memory address of

the data, is specified in the instruction.
The register specified is preceded by @ symbol in assembly language format.
E.g. ADD A, @R0.

The value stored in the register R0 is now the address of the memory location
of the data to be fetched from this
memory location, the data is fetched and the instruction is
executed. The data pointer register (DPTR) is used to access
the data in the external memory with 16-bit addresses.

The indirect addressing mode is very much useful for accessing data
which are continuously stored in memory and accessed consecutively in
program.

iv) Indexed Addressing:

In this type of addressing, the instruction consists of two
parts - a base address and an offset. This type of addressing is useful in
relative memory accessing and relative jumping. The base address
is stored in data pointer (DPTR) or any other register.
The offset value is stored in Accumulator. E.g. MOVC A, @A+DPTR.

This instruction adds the contents of the accumulator with the contents of the
data pointer and the result forms the actual
address of the data from where it is fetched. This data is moved on to
the accumulator.
The indexed addressing mode is useful in accessing data structures similar to
lookup tables. The base address will hold the address of the starting point of
the table and the offset will point the particular entry in the table.

Arithmetic Instructions:

These instructions are used to do arithmetic operations. The common

arithmetic operations like addition, subtraction,
multiplication and division are possible with 8051 All the data used in
arithmetic instructions must be available
inside the controller i.e. in the internal RAM area only.
ADD instruction is used to add any 8 bit data with Accumulator and the
result is stored in Accumulator (A) register. The carry generated if any is
stored in Carry flag of the processor status word.
The ADDC instruction is also used to add any 8 bit data with Accumulator
along with Carry bit.

The SUBB instruction -subtract contents of a register from the

Accumulator content and during this subtraction, the Carry bit is also
subtracted from the accumulator.
For ADD and SUBB instructions, one of the data must be in Accumulator and
the other data - in any direct addressed or indirect addressed
internal memory location or can be an immediate data.

• In addition to - ADD, ADDC and SUBB instructions in 8085, -have

instructions MUL and DIV. The register B is exclusively used for these two
instructions. The
operands should be stored in the registers A and B for the MUL and DIV
instructions.

• The MUL instruction multiplies the contents of A and B registers and

stores the 16 bit result in the combined A and B registers.
The lower order byte -result is stored in A register and the higher order
byte - stored in B register.
The DIV instruction upon execution will divide the contents of A register
by the contents of B register.

• The quotient of the result - stored in A register and the remainder is

stored in B register.
A division by 0 i.e. 0 in the B register before executing DIV AB will result
in the overflow flag (OV) set to 1. DA A
instruction -to convert binary sum obtained after adding two BCD
numbers into BCD number.

Logical Instructions:

In addition to logical AND, OR and XRL operation, 8051 has additional

instructions - CLR, CPL. All the data for the logical instructions -available
in the internal RAM only.
The instruction CLR A -to clear the contents of A register, CPL is used to
complement or logically invert the contents of the A register and SWAP -
to swap the nibbles of A register.
8051 supports four rotate operations with the options –rotating left or
right and rotating through carry or not.

Branching Instructions:

8051 supports unconditional jumping and subroutine calling in three

different ways.
They are Absolute jump AJMP, ACALL, long jump LJMP, LCALL, and short
jump SJMP.

Conditional Branching Instructions

x The syntax for short jump instruction- SJMP 8-bit address.

This 8 bit address is a relative address- to the program counter. The
branching address -by adding the address given in the instruction
with the program counter content.
The 8-bit address is a 2's complement number i.e., the most significant
bit -sign + or -. The remaining 7 bits - specify the address. using SJMP -
branch to anywhere between 127 bytes after the program counter
content and 128 bytes before it.(From (PC-128 bytes) to (PC+127 bytes))

x . For example, 8800: SJMP 06h

This instruction shift the execution to the location 8808h. The program
counter content after fetching the 2 byte - SJMP instruction is 8802h. So,
06h added to 8802H results in 8808h. The syntax for LJMP -“LJMP
16-bit address”. After the execution of this
instruction the Program counter -loaded with the 16 bit address and the
execution shifts to that location.

x The syntax for AJMP instruction is “AJMP 11 bit jump address”. The
destination branching address -absolute jumping is calculated -
keeping MSB 5 bits of the Program counter as it is and changing the LSB
11 bits to that as given -instruction. For example, 8800: AJMP 7F0h •
This instruction branch the execution address 8FF0h. After fetching-
program counter content will be 8802h. Keeping the MSB 5 bits of the
PC (10001) as it is, and changing the LSB 11 bits to that given
in the
instruction (111 1111 0000) , the branching address becomes 8FF0h.
 The micro controller 8051 -single instruction for counter operation
to

x decrement -result (DJNZ). -very useful in looping using a counter similar

to “for loop” in high level languages.
Similarly, jumping after checking the result of a comparison -done by a
single instruction (CJNE) -very useful for looping of instruction execution
based on a condition. Used in programming constructs similar to “do
while” in high level languages.

Serial communication:
Computers transfer data in two ways:
i) Parallel:Often 8 or more lines (wire conductors) are
used to transfer data to a device that is only a few feet away.

ii)Serial:To transfer to a device located many meters

away, the serial method is used. The data is sent one bit at a time.

At the transmitting end, the byte of data must be converted to serial bits
using parallel-in-serial-out shift register At the receiving end, there is a serialin-
parallel-out shift register to receive the serial data and pack them into byte.

When the distance is short, the digital signal can be transferred as it is on a

simple wire and requires no modulation If data is to be transferred on the
telephone line, it must be converted from 0s and 1s to audio tones.
Serial data communication uses two methods

i)Synchronous method transfers a block of data at a time

ii)Asynchronous method transfers a single byte at a time .

It is possible to write software to use either of these methods, but the

programs can be tedious and long. There are special IC chips made by many
manufacturers for serial communications
UART (universal asynchronous Receivertransmitter)
USART (universal synchronous-asynchronous Receiver-transmitter).

If data can be transmitted and received,it is a duplex transmission. If data

transmitted one way a time, it is referred to as half duplex If data can go both
ways at a time, it is full duplex This is contrast to simplex transmission.

Interfacing 8255 to 8051

When the 8051 is connected to external memory, port 0 (P0) is used for the lower-order
address and data bus and port 2 (P2) is used for the higher-order address bus.

Since the port 3 pins have an alternative function, the net result is that
only P1 is left for input and output operation.

One way to expand the number of I/O ports is to connect the 8255
programmable peripheral interface with the 8051.
The interfacing of the 8255 with the 8051 is done assuming the 8255 as a memory
location, because the 8051 supports only memory-mapped I/O.

For accessing the external memory in the 8051, the MOVX instruction is used.

The lower-order address bus and the data bus are multiplexed and are

available in the port 0 pins. This is de-multiplexed using a latch and the ALE signal.

The first step in the general interfacing method is to decide the

addresses for the port. The 8051 uses 16-bit addresses and the most significant

address lines are used for decoding and selecting the device.

Here, the higher-order address bus from port 2 is given to a decoder logic circuit.

From the decoder, the 8255 chip select signal is generated.

The 8255 needs four addresses for interfacing with any processor—three

for the ports A, B, and C and one for the control register.

The lower-order address lines A0 and A1 are connected to select one of these four

registers.

The read and write control signals are available from the port 3 pins P3.7 and P3.6.

Example:Program PC4 of the 8255 to generate a pulse of 50 ms with

50% duty cycle.

External Memory Interfacing in 8051

External memory interfaced to 8051 can be of two types -external

program memory and external data memory.

The external memory accesses are accomplished with the Ports 0 and 2 of 8051 as

they serve as the multiplexed address/ data buses. The

external memory in 8051 is always accessed with 16 bit addresses. The 8051 outputs

the signal ALE (Address Latch enable) in order to

demultiplex the lower order address and data bus.

In addition, the micro-controller sends the control signals on the Port3 lines.

i)Program memory interfacing

The program memory can be placed outside the chip in addition to the internal program

memory. The complete program memory can be

placed outside the chip neglecting the internal program memory.

Applying proper the voltage level on the input line EA of 8051 can do the

selection of any of the above two methods.

Connecting EA to Ground will disable the internal program memory and

all program memory accesses are done to external memory. The Read

strobe signal given by the micro-controller is PSEN. This active low signal is

connected to the Read selection line of the memory chips.

ii) Accessing External Data Memory

The data memory in the system - be Random Access memory as it should facilitate both

read and write operation of data. The external data memory is interfaced in the

same way as the program memory is interfaced.

The major difference is that the read and writes operations can be

done in Read /W rite Random Access Memory. The control signals for reading and

writing to data memory are available from the port3 pins. P3.6 pin

gives data memory write

enable signal and P3.7 pin gives out the RAM read enable signal.