Bo On KTMT 2 de Thi

lOMoARcPSD|30860100
BỘ ÔN KTMT 2 - đề thi
Kiến trúc máy tính _ hợp ngữ (Trường Đại học Sư phạm Kỹ Thuật Thành phố Hồ Chí
Minh)
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lOMoARcPSD|30860100
THI Kiến trúc máy tính và hợp ngữ (Thi

Chung)
Bắt đầu vào lúc Monday, 28 May 2018, 1:10 PM
State Finished
Kết thúc lúc Monday, 28 May 2018, 2:14 PM
Thời gian thực 1 giờ 4 phút
hiện
Câu hỏi 1 Consider the following assembly instruction sequence

Hoàn thành CMP DL, 0
JB x_label
Đạt điểm 1,00
CMP DL, 9
JA a_label
ADD DL, 30h
JMP x_label
a_label:
CMP DL, 0Fh
JA x_label
ADD DL, 31h
x_label:
MOV AL, DL
watch point:
...
Choose correct value of AL register at watch point for different value of DL?
DL=55h 85h
DL=0FFh 41h
DL=10 38h
DL=8 0FFh
Câu hỏi 2 Select correct match for AX (Decimal) at watch points:

Hoàn thành MOV AX, 1BC
Đạt điểm 1,00 MOV CL, 2
SHL AX, CL
watch point #1:
ADD AX, 166
watch point #2:
SHR AX, CL
watch point #3:
SHR AX, CL
......
watch point #1: 1064 1776
watch point #2: 266 1942

watch point #3: 266
485

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Câu hỏi 3 if the location to which the control is to be transferred lies in a segment other
Hoàn thành than the current one, then the jump instruction is called
Đạt điểm 0,50

Select one:
intrasegment mode
intersegment mode
intrasegment indirect mode
intrasegment direct mode
Câu hỏi 4 Structural components of computer include:

Hoàn thành
Select one or more:
Đạt điểm 1,00
System interconnection
Interrupt
Central processing unit

I/O
Memory
DMA
Câu hỏi 5 Which could be correct ones for the destination operand in a data movement
Hoàn thành instruction?
Đạt điểm 0,50

Select one or more:
immediate data
all choices are correct
register
memory location
Câu hỏi 6 the instruction, JMP C008:2000h is an example of

Hoàn thành
Select one or more:
Đạt điểm 0,50
intrasegment mode
near jump
intersegment jump
far jump
Câu hỏi 7 Given a row of memory image in debug

Hoàn thành 0AE8:0120 13 96 D0 E0 00 40 08 42 - 99 80 3E 20 99 00 75 24
Đạt điểm 1,00 SI = 120
The following instruction is executed:
MOV EAX, [SI+4]
Assume the value in EAX is a 32-bit floating-point binary, what is the value of
EAX in decimal?
Answer: 4000 0899

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Câu hỏi 8 Given a code snippet:

Hoàn thành int n = 10;
Đạt điểm 1,00 do {
n--;
} while (n > 0);
Which ones are the equivalent logic sequence of instructions in Assembly
Select one or more:

mov cx, 10
a_label:
.....
loop a_label
mov cx, 10
a_label:
.....
dec cx
cmp cx,0
jz a_label
mov cx, 10
a_label:
.....
dec cx
loop a_label
mov cx, 10
a_label:
dec cx
cmp cx, 0
jz e_label
jmp a_label
e_label:
Câu hỏi 9 The following sequence of instructions are executed. What is the correct
Hoàn thành value of AX, CX, DX at watch point?
Đạt điểm 1,00 MOV AX,30

MOV CX,FFFF
MUL CX
watch point:
CX
FFFF
=
AX
FFD0
=
DX 002F
Câu hỏi 10 Write mask byte (in hex) to set higher 4 bits in a byte value with OR instruction (LSB
Không trả lời is the 1st bit).
Đạt điểm 0,50

Answer: F0

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Câu hỏi 11 After executing PUSH EAX instruction, the stack pointer
Hoàn thành
Select one:
Đạt điểm 0,50
increment by 1
decrements by 4
decrement by 1
increment by 2
Câu hỏi 12 Given an assembly code copying the memory buffer Buff1 to Buff2:
Không trả lời PUSH DS
Đạt điểm 1,00 POP ES
LEA SI, Buff1
LEA DI, Buff2
MOV CX,20
;--- Start of block
cp_loop:
MOV AL, Byte Ptr [SI]
MOV Byte Ptr ES:[DI], AL
INC SI
INC DI
LOOP cp_loop
; ---End of block
Choose equivalent string operations in place of block
Select one or more:

CLD
cp_loop:
MOVSB
LOOP cp_loop
STD
cp_loop:
MOVSB
LOOP cp_loop
CLD
cp_loop:
REP MOVSB
LOOP cp_loop
CLD
REP MOVSB
Câu hỏi 13 the instruction that is used as prefix to an instruction to execute it repeatedly
Hoàn thành until the CX register becomes zero is
Đạt điểm 0,50

Select one:
CMPS
SCAS
CMPS
REP
Câu hỏi 14 Write mask byte (in hex) to clear all the lower 7 bits of a byte value with AND
Hoàn thành instruction.
Đạt điểm 0,50

Answer: AND AL, 01111111B 80

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Câu hỏi 15 Convert -89.2345 to IEEE 32-bit floating point format (1 sign+ 8 exponent + 23
Không trả lời mantissa) in hex
Đạt điểm 1,00

Answer:

Không trả lời 072C:FFF0 00 00 00 01 00 00 2C 07 - 07 01 2C 07 17 72 00 00
Đạt điểm 1,50 SS=072C, SP=FFF8, DS = 072C
Assume the stack now stores two (2) 16-bit parameters and one (1) 16-bit
return address in following order: stack top (return address) >> parameter #1
>> parameter #2.
The following sequence of instructions are executed. What is the correct values
at watch points?
MOV BP, SP
watch point #1 (BP):
MOV AX, [BP+2]
watch point #2 (AX):
ADD AX, [BP+4]
MOV DI, 120
MOV [DI], AX
watch point
Chọn...
#1:
watch point
Chọn...
#2:
watch point
Chọn...
#3:
Câu hỏi 17 The instruction that subtracts 1 from the contents of the specified
Hoàn thành register/memory location is
Đạt điểm 0,50

Select one:
DEC
SUB
SBB
INC

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Câu hỏi 18 Memory dump at 1D20:0200 shown as below:

Không trả lời 1D20:0200 00 20 10 5D 55 47 00 90 - 00 10 20 30 40 50 60 70
Đạt điểm 1,00 Given value of registers:
DS = 1D20, ES = 1D20, DI = 20A
The following sequence of instructions are executed:
MOV SI,208h
MOV AX,0040h
MOV CX,000Ah
CLD
REPNZ SCASB
watch point:
.....
What is the correct value of AX, SI, DI registers at watch point?
DI
Chọn...
=
AX
Chọn...
=
SI
Chọn...
=
Câu hỏi 19 What is the meaning of Amdahl's law in processor performance evaluation?
Hoàn thành
Select one:
Đạt điểm 1,00
the cost reduce when moving from single-core to multicore processor
the maximum speedup of a multicore processor

the potential speedup of a program using multiple processor compared to
a single processor
the speedup of a multicore processor when increasing system bus speed
Câu hỏi 20 Which are the correct actions for LODSW string operation if DF is reset (=0)
Hoàn thành
Select one or more:
Đạt điểm 0,50
decrease DI by 2
Load 16-bit value at memory location pointed by ES:[DI] into AX
increase SI by 2
Load 16-bit value at memory location pointed by DS:[SI] into AX
Câu hỏi 21 When many devices of different transmission speed connect to the same bus,
Không trả lời the overall system performance suffers. How did the design engineers resolved
this:
Đạt điểm 1,00
Select one:
PCI Express bus
Multiple-Bus hierarchies
PCI bus
Split system bus into local bus and memory bus

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Câu hỏi 22 the instruction, CMP to compare source and destination operands by
Hoàn thành __________
Đạt điểm 0,50

Select one:
adding
comparing
dividing
subtracting
Câu hỏi 23 To balance the super speed of CPU with the slow response of memory, which
Hoàn thành of the following measures have been made by engineers in system design?
Đạt điểm 1,00

Select one or more:
Make use of both on-chip and off-chip cache memory
Make wider data bus path
Using higher-speed bus and us hierarchy

To move data directly by DMA
Hoàn thành value of AX, DX at watch point?
Đạt điểm 1,00 MOV DL,FF

MOV AL,42
IMUL DL
watch point:
AX = FFBE
41BE
DX
0000
=
Câu hỏi 25 In the RCR instruction, the contents of the destination operand undergoes function as
Hoàn thành
Select one:
Đạt điểm 0,50
carry flag is pushed into LSB then MSB is pushed into carry flag
overflow flag is pushed into MSB then LSB is pushed into carry flag
carry flag is pushed into MSB then LSB is pushed into carry flag
auxiliary flag is pushed into LSB then MSB is pushed into carry flag
Câu hỏi 26 Which could be correct ones for the source operand in an instruction?
Hoàn thành
Select one or more:
Đạt điểm 0,50
immediate data
memory location
indirect data
register
Câu hỏi 27 Convert the 32-bit floating point number A3358000 (in hex) to decimal.
Hoàn thành Note:
Đạt điểm 1,00 Result with exponent should be written like (e.g): 1.2345678x10^-13
or 1.2345678x10^13 (no space between digits/characters)
Answer: -9.83913471531×10^-18

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Câu hỏi 28 Select correct match for register values at watch points:
Hoàn thành MOV AX, 152D
Đạt điểm 1,00 ADD AX, 003F
watch point #1:
ADD AH, 10
watch point #2:
......
watch point
AH = 25
#2:
watch point
AL = 6C
#1:
Câu hỏi 29 Which are the correct actions for SCASW string operation if DF is set (=1)
Hoàn thành
Select one or more:
Đạt điểm 0,50
decrease DI by 2
compare the value in AX register with 16-bit value at the memory location
pointed by ES:[DI] and set/clear flag bits accordingly
increase DI by 2
compare the value in AX register with 16-bit value at the memory location
pointed by DS:[SI] and set/clear flag bits accordingly
Câu hỏi 30 What is the correct value of SI, AL (in hex) at watch point:
Hoàn thành 01: MOV SI, 300h
Đạt điểm 1,00 02: MOV AL, 10h
03: MOV CX, 7
04: Loop_label:
05: MOV [SI], AL
06: ADD AL,10h
07: INC SI
08: LOOP Loop_label
watch point:
SI 80h
AL
80h
=
Câu hỏi 31 Select the correct sequence of instructions to compute -1024/128 (all values
Hoàn thành are in hex).
Đạt điểm 1,00

Step 1: CWD mov fc00
Step 2: MOV CX,80 cwd
Step 3: MOV CL,80 mov 80
Step 4: IDIV CL

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Câu hỏi 32 Select correct match for AL and carry flag at watch point #1:
Hoàn thành MOV BL, 8C
Đạt điểm 1,00 MOV AL, 7E
ADD AL, BL
watch point #1:
......
AL 0A
Carry
set
flag

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Câu hỏi 33 Given a flowchart of an algorithm:

Hoàn thành
Đạt điểm 1,00
Select the correct instruction sequence:
Select one or more:

mov dl,10
cmp al,bl
jnz n_label
add dl,10
jmp e_label
n_label:
mov cl,1
shl dl,cl
e_label:
mov dh,dl
mov dl,10
cmp al,bl
jnz n_label
add dl,10
mov dh,dl
jmp e_label
n_label:
mov cl,1
shl dl,cl
e_label:
mov dh,dl
mov dl,10
cmp al,bl
jnz n_label
add dl,10
jmp e_label
n_label:
mov cl,1
shr dl,cl
e_label:
mov dh,dl
mov dl,10
cmp al,bl
jz n_label
mov cl,1
shl dl,cl
jmp e_label
n_label:
add dl,10
e_label:
mov dh,dl

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Câu hỏi 34 After executing the POP EAX instruction, the stack pointer
Hoàn thành
Select one:
Đạt điểm 0,50
decrements by 4
decrements by 2
increments by 4
increment by 1
Câu hỏi 35 Sign-extend number BF (8-bit binary) to 16-bit. Write result in hex
Hoàn thành
Đạt điểm 0,50 Answer: 191
Câu hỏi 36 Which of the following instructions are not valid?

Hoàn thành
Select one or more:
Đạt điểm 0,50
MOV DS, B800h
MOV AX, [BP+2]

MOV SP, SS:[SI+2]
MOV AX, SI
Hoàn thành value of flag bits at watch point?
Đạt điểm 1,00 MOV AL, 0F

ADD AL, F1
watch point:
Zero flag (OF)

=
reset
set 0100
Carry flag
set set
(CF) =
Câu hỏi 38 Major structural components of the CPU include:

Hoàn thành
Select one or more:
Đạt điểm 1,00
Registers
Arithmetic and Logic Unit
Instruction Pointer (PC)
Interconnections
Control Unit
Instruction Register
Câu hỏi 39 Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64
Hoàn thành sectors per track. Sector size is 1 kB. What is the disk capacity
Đạt điểm 1,00

Answer: 512 KB

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Câu hỏi 40 What best describe the Spatial and Temporal Locality?
Hoàn thành
Tempor
Đạt điểm 1,00
al be exploited by keeping recently used instruction and data in cache memory and by exploiting a cache hierarchy
locality
Spatial
be exploited by moving data between cache and memory more efficient
locality
Câu hỏi 41 Given a code snippet:

Hoàn thành int ax, bx;
Đạt điểm 1,00 ...
if (ax >= bx)
ax -=bx;
else
bx -=ax;
What is the equivalent logic sequence of instructions in Assembly
Select one:
cmp ax,bx
jl a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
jbe a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
ja a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
jge a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
Câu hỏi 42 Which of the following is not a data copy/transfer instruction?

Hoàn thành
Select one or more:
Đạt điểm 0,50
ADC
MOV
LEA
DAS
Return to: General

lOMoARcPSD|30860100
18/5/2018 Kiểm tra cuối kỳ đề 1

Question 1 Consider the following assembly instruction sequence
Complete CMP DL, 0
JB x_label
Marked out of 1.20
CMP DL, 9
JA a_label
ADD DL, 30h
JMP x_label
a_label:
CMP DL, 0Fh
JA x_label
ADD DL, 37h
x_label:
MOV AL, DL
watch point:
...
DL=10 38h
DL=8 41h
DL=55h 55h
DL=0FFh 0FFh
Question 2 The following sequence of instructions are executed. What is the correct value of CF and
Complete OF at watch point?
Marked out of 1.00 MOV AX,FFF6h

MOV CX,1000h
IMUL CX
watch point:
OF= set
CF= undefined
http://exam.hcmute.edu.vn/mod/quiz/review.php?attempt=39105 2/18
lOMoARcPSD|30860100

Question 3 Which could be correct ones for the destination operand in a data movement instruction?
Complete
Select one or more:
Marked out of 0.50
register
immediate data
memory location
Question 4 Write mask byte (in hex) to clear bit 2nd, 3rd, 5th of a byte value with AND instruction (LSB is 1st
Complete bit).
Marked out of 1.20

Answer: 10010111
Question 5 if the location to which the control is to be transferred lies in a segment other than the
Complete current one, then the jump instruction is call
Marked out of 0.50

Select one:
intersegment mode
intrasegment mode
Question 6 Convert the 32-bit floating point number 44363800 (in hex) to decimal.
Complete
Marked out of 1.20 Answer: 1144403968
lOMoARcPSD|30860100

Question 7 The following sequence of instructions are executed. What is the correct value of flag bits at
Complete watch point?
Marked out of 1.00 MOV AX,FFFF

MOV CX,5
MUL CX
watch point:
Carry flag (CF) = set
Overflow flag (OF) = not defined
Question 8 In multiplication instruction, when the source operand is 16 bit, how can the result be taken?
Complete
Select one:
Marked out of 0.50
from AX:DX pair
from AX
from EAX
from DX:AX pair
Question 9 Given a row of memory image in debug

Complete 0AE8:0120 13 96 D0 E0 D0 E0 A2 1E - 99 80 3E 20 99 00 75 24
Marked out of 1.00 Initially, AX=BX=CX=DX=0, SI=128
What are value of AX,DX after execution of the following instructions?
MOV EDX, [SI]
MOV EAX, [SI+4]
DX = 203E
AX = 8099
lOMoARcPSD|30860100

Question 10 Which statements are correct for HDDs?
Complete
Select one or more:
Marked out of 1.00
Head, Track, Sector are key parameters for access data on hard disk
Bits are stored on tracks
Head, Track, Cylinder are key parameters for access data on hard disk
Bits are store randomly on disk surfaces
Question 11 Which are correct action for SCASW string operation if DF is set (=1)
Complete
Select one or more:
Marked out of 0.50
compare value in AL register with memory location pointed by DS:[SI]
decrease DI by 2
compare value in AL register with memory location pointed by ES:[DI]
increase DI by 2

Marked out of 1.00 SI = 120, DI = 128
Select correct sequence of instructions to subtract words at [DI] from [SI] then store the
result at memory location 12A
Step 1: MOV AX, [SI]
Step 2: SUB AX, [DI]
Step 3: SUB AX, [SI]
Step 4: MOV BX, 012A
lOMoARcPSD|30860100

Question 13 The instruction that supports addition when carry exists is
Complete
Select one:
Marked out of 0.50
DAS
SBB
ADC
ADD
Question 14 In computer, how does the processor serve multiple interrupt request from devices?
Complete
Select one:
Marked out of 1.00
Each device are assigned an interrupt priority, the device with lower priority will be
served.
Device with higher priority will use interrupt enable flag
The processor can not process multiple interrupt requests
Each device are assigned an interrupt priority, the device with higher priority will be
served.
Marked out of 1.00 MOV AL, 80

MOV BL, 2
MUL BL
watch point:
Overflow flag (OF) = reset
Question 16 To test one bit in a byte value without destructing the byte, use __________ instruction.
Complete
Select one:
Marked out of 0.50
AND
OR
NOT
TEST
lOMoARcPSD|30860100

Question 17 Which are correct about the data registers of IA-32 processors:
Complete
Select one or more:
Marked out of 1.00
Lower halves of the 32-registers an be used as 4 16-bit data registers: AX,BX,CX,DX
complete 32-bit registers: EAX, EBX, ECX, EDX
Lower halves of the 16-registers an be used as 8-bit data registers:

AH,AL,BH,BL,CH,CL,DH,DL
Higher halves of the 32-bit registers can be used as 16-bit registers:

EAH,EAL,EBH,EBL,ECH,ECL,EDH,EDL
Question 18 Convert 0.1015625 to IEEE 32-bit floating point format (1 sign+ 8 exponent + 23 mantissa)
Complete
Marked out of 1.20 Answer: Thay thuong tinh cho em 7d qua mon, em cam on!
Marked out of 1.00 MOV DL,FF

MOV AL,F6
IMUL DL
watch point:
OF = set
CF = set
Question 20 Choose correct features for SRAM and DRAM

Complete
Marked out of 1.00 SRAM Faster access time, cost more per bit, smaller size
DRAM Slower access time, cheaper cost per bit, can manufacture with larger size
lOMoARcPSD|30860100

Question 21 Given a flowchart of an algorithm:
Complete
Marked out of 1.20
Select one or more:

mov dl,10
cmp al,bl
jz n_label
mov cl,1
shl dl,cl
jmp e_label
n_label:
add dl,10
e_label:
mov dh,dl
mov dl,10
cmp al,bl
jnz n_label
add dl,10
jmp e_label
n_label:
mov cl,1
shr dl,cl
e_label:
mov dh,dl
mov dl,10
cmp al,bl
jnz n_label
add dl,10
jmp e_label
n_label:
mov cl,1
shl dl,cl
e_label:
mov dh,dl
lOMoARcPSD|30860100

mov dl,10
cmp al,bl
jnz n_label
add dl,10
mov dh,dl
jmp e_label
n_label:
mov cl,1
shl dl,cl
e_label:
mov dh,dl
Marked out of 1.00 MOV AL, 0F

ADD AL, F1
watch point:
Zero flag (OF) = set
Carry flag (CF) = neither set nor reset
Question 23 Which are correct action for STOSB string operation if DF is reset (=0)
Complete
Select one or more:
Marked out of 0.50
decrease DI by 1
Store 8-bit value from AL into memory location pointed by DS:[SI]
increase DI by 1
Store 8-bit value from AL into memory location pointed by ES:[DI]
lOMoARcPSD|30860100

Question 24 What are components of Von Neumann, namely IAS computer?
Complete
Select one or more:
Marked out of 1.00
I/O Equipments
Monitor
CPU
Memory
Bus
Punched card reader
Question 25 Compute the physical address of the next instruction will be execute if instruction pointer is
Not answered 091D and code segment located at 1FAF
Marked out of 1.00
Answer:
Question 26 Which set of registers are valid for addressing a stack memory location?
Complete
Select one or more:
Marked out of 1.00
SS:BP
SS:BX
DS:SI
SS:SP
Question 27 The instruction that is used for finding out the codes in case of code conversion problems is
Complete
Select one:
Marked out of 0.50
XOR
JCXZ
XLAT
XCHG
lOMoARcPSD|30860100

Question 28 To clear one or more bits in a byte value, use __________ instruction.
Complete
Select one:
Marked out of 0.50
OR
NOT
AND
XOR
Marked out of 1.00 MOV AL,-5

SUB AL,124
watch point:
Zero flag (OF) = not defined
Sign flag (SF) set
Question 30 the memory stack area of a program shown in figure

Complete
Marked out of 1.00
The value of SP register is 1D50. What is the value of SP follows the execution of PUSH SI
Answer: 90
Question 31 Enter debug command to fill 256 bytes in data segment starting from 100 with value 0D
Complete
Marked out of 1.00 Answer: ADD 0D, 256[100]
lOMoARcPSD|30860100

Question 32 Which are correct action for LODSB string operation if DF is reset (=0)
Complete
Select one or more:
Marked out of 0.50
increase SI by 1
Load 8-bit value at memory location pointed by ES:[DI] into AL
Load 8-bit value at memory location pointed by DS:[SI] into AL
decrease DI by 1
Question 33 Given a code snippet:

Complete int n = 10;
Marked out of 1.20 do {
n--;
} while (n > 0);
Select one or more:

mov cx, 10
a_label:
dec cx
cmp cx, 0
jz e_label
jmp a_label
e_label:
mov cx, 10
a_label:
.....
dec cx
loop a_label
mov cx, 10
a_label:
.....
dec cx
cmp cx,0
jz a_label
mov cx, 10
a_label:
.....
loop a_label
lOMoARcPSD|30860100

Question 34 For better speed, in CPU design, engineers make use of the following techniques:
Complete
Select one or more:
Marked out of 1.00
Speculative execution
Branch prediction
Faster CPU internal bus
Pipelining
Question 35 In multiplication instruction, when the source operand is 8 bit, _________ will be multiplied
Complete with source.
Marked out of 0.50

Select one:
Whatever general purpose register
BX
AL
AX
Question 36 Which are valid based index addressing?

Complete
Select one or more:
Marked out of 1.00
[BX+SI]
[BX+DI]
[DX+SI]
[SP+DI]
Question 37 Memory dump at 1D20:0200 as below:

Complete
1D20:0200 00 20 10 5D 55 47 00 90 - 00 10 20 30 40 50 60 70
Marked out of 1.00 Given value of registers: DS = 1D20, SI = 200, BX = 202, AX = 0103
Identify correct value of AX register after XLAT instruction is executed.
AH = 5Dh
AL = 10h
lOMoARcPSD|30860100

Question 38 Given a code snippet (ax, bx are none negative integers):
Complete if (ax >= bx)
Marked out of 1.20 ax -=bx;
else
bx -=ax;
Select one:
cmp ax,bx
jbe a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
jb a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
ja a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
jnbe a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
lOMoARcPSD|30860100

Question 39 The instruction, MOV AX, 0005h belongs to which addressing mode?
Complete
Select one:
Marked out of 0.50
Immediate
direct
register
index
Question 40 Part of computer memory is shown in figure

Complete
Marked out of 1.00
What is the value of AX register after instruction MOV AX, [1D4B] executed
Answer: 2D
Question 41 Which of the following instructions are not valid?

Complete
Select one or more:
Marked out of 0.50
MOV AX, [BP+2]
MOV AX, SI
MOV DS, B800h
MOV SP, SS:[SI+2]
lOMoARcPSD|30860100

Question 42 The following sequence of instructions are executed. What is the correct value of AX, CX,
Complete DX at watch point?
Marked out of 1.00 MOV AX,0020

MOV CX,0010
MUL CL
watch point:
AX = 0200
DX 020F
CX = 0010
Question 43 Basic functions that a computer can perform including:

Complete
Select one or more:
Marked out of 1.00
Data movement
Direct memory access
Control
Data storage
Interrupt
Data processing
lOMoARcPSD|30860100

Question 44 Select correct match for register values at watch points:
Complete MOV AX, 4FCA
Marked out of 1.00 ADD AX, DDA9
watch point #1:
ADD AH, F3
watch point #2:
......
watch point #1: AH = 20
watch point #2: AL = 73
Question 45 Hereafter is instruction sequence to compute the sum of 8 bytes starting at memory address
Complete 200. Two lines of code are possibly missing. Choose correct one to fill in?
Marked out of 1.20 01: _____________; possibly missing code

02: MOV AL, 0
03: MOV CX, 8
04: Loop_label:
05: _____________; possibly missing code
06: ADD AX, [SI];
07: INC SI
08: LOOP Loop_label
01: MOV SI, 200
05: CWD
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lOMoARcPSD|30860100

Vu Ngoc Phat
THE EXAM PERFORMANCE PROGRAM

INFORMATION TECHNOLOGY CENTER
 Call Us: (+84 - 8) 38968641 - (+84 - 8) 38961333  Email: ic@hcmute.edu.vn
Dashboard ► Học kỳ 2 năm 2016 - 2017 ► Lớp Chất lượng cao ► CAAL240180_16_2_8506 ► General ►
Kiểm tra cuối kỳ đề 2
Started on Monday, 5 June 2017, 1:11 PM

State Finished
Completed on Monday, 5 June 2017, 2:20 PM
Time taken 1 hour 9 mins
Question 1 Convert the 32-bit floating point number 44363C00 (in hex) to decimal.
Complete
Question 2 The instruction that subtracts 1 from the contents of the specified register/memory location
Complete is
Marked out of 0.50

Select one:
SUB
DEC
SBB
INC
lOMoARcPSD|30860100

Complete 1D20:0200 00 20 10 5D 55 47 00 90 - 00 10 20 30 40 50 60 70
Marked out of 1.00 Given value of registers:
DS = 1D20, ES = 1D20,
DI = 20A, SI = 208,
BX = 202, AX = 0103, CX = 0003
and flag bit DF = 1
What is the correct value of AX, SI, DI registers after the instruction REP LODSW is
executed?
DI = 0202h
AX = 5040h
SI = 5547h
Question 4 Which are correct action for SCASW string operation if DF is reset (=0)
Complete
Select one or more:
Marked out of 0.50
decrease DI by 2
increase DI by 2
Question 5 Which are correct about the Pointer registers of IA-32 processors:
Complete
Select one or more:
Marked out of 1.50
Base Pointer (BP): The 16 bit pointer refers to stack memory
Stack Pointer (SP): the 16 bit pointer to the top of stack
Instruction Pointer (IP): the 16 bit register points to the next instruction to be execute
Base Pointer (EBP): The 32 bit pointer refers to stack memory
Stack Pointer (ESP): the 32 bit pointer to the top of stack
Instruction Pointer (EIP): the 32 bit register points to the next instruction to be execute
lOMoARcPSD|30860100

Complete
Select one or more:
Marked out of 1.00
Punched card reader
Bus
Monitor
Memory
I/O Equipments
CPU

Complete
Select one or more:
Marked out of 1.00
Question 8 The instruction that loads effective address is

Complete
Select one:
Marked out of 0.50
LAHF
LDS
LEA
LES
Question 9 Enter debug command to fill 250 bytes in the memory segment FED5 in computer memory
Not answered starting from 100 with value AD
Marked out of 1.00
Answer:
lOMoARcPSD|30860100

Question 10 The following sequence of instructions are executed. What is the correct value of EAX,
Complete EBX, EDX at watch point?
Marked out of 1.00 MOV EAX,00002000

MOV EBX,00100000
MUL EBX
watch point:
EAX = 00000002
EDX = 00000000
EBX = 00021000
Question 11 Convert 39887.5625 to IEEE 32-bit floating point format (1 sign+ 8 exponent + 23 mantissa) in hex
Not answered
Marked out of 1.20 Answer:
Question 12 The instruction, MOV AX, 1234h is an example of

Complete
Select one:
Marked out of 0.50
Immediate addressing mode
based index addressing mode
direct addressing mode
register addressing mode
lOMoARcPSD|30860100


MOV BL, 2
MUL BL
watch point:
Carry flag (CF) = reset

ADD AL,132
ADD AL,1
watch point:
Sign flag (SF) reset
Complete
Select one:
Marked out of 1.00
served.
served.
lOMoARcPSD|30860100

Question 16 the instruction, JMP C008:2000h is an example of
Complete
Select one or more:
Marked out of 0.50
intersegment jump
far jump
near jump
intrasegment mode
Question 17 In multiplication instruction, the result is taken from AX means the source operand is
Complete ______ bit
Marked out of 0.50

Select one:
8
16
None of the choices are correct
Question 18 Memory dump at 1D20:0200 shown as below:

Complete 1D20:0200 00 20 10 5D 55 47 00 90 - 00 10 20 30 40 50 60 70
Marked out of 1.00 Given value of registers:
DS = 1D20, ES = 1D20, DI = 20A
The following sequence of instructions is being executed:
MOV SI,208h
MOV AX,0040h
MOV CX,000Ah
CLD
REPNZ SCASB
watch point:
.....
What is the correct value of AX, SI, DI registers at watch point?
SI = 020Ch
DI = 4030h
AX = 020Bh
lOMoARcPSD|30860100

Question 19 What is the correct value of SI, AL (in hex) at watch point:
Complete 01: MOV SI, 300h
Marked out of 1.00 02: MOV AL, 10h
03: MOV CX, 7
04: Loop_label:
05: MOV [SI], AL
06: ADD AL,10h
07: INC SI
08: LOOP Loop_label
watch point:
SI 308h
AL = 70h
Question 20 Physical address of a memory location is 5FE2E. This memory address located by DI
Not answered register which now has value of 993E. Compute the memory address of data segment
register
Marked out of 1.00
Answer:

Complete
Select one or more:
Marked out of 1.00
Data movement
Data processing
Control
Interrupt
Data storage
lOMoARcPSD|30860100

Complete int ax, bx;
Marked out of 1.20 ...
if (ax >= bx)
ax -=bx;
else
bx -=ax;
Select one:
cmp ax,bx
jbe a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
jl a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
jge a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
ja a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
lOMoARcPSD|30860100

Question 23 Given an assembly code copying the memory buffer Buff1 to Buff2:
Complete PUSH DS
Marked out of 1.20 POP ES
LEA SI, Buff1
LEA DI, Buff2
MOV CX,20
;--- Start of block
cp_loop:
MOV AL, Byte Ptr [SI]
MOV Byte Ptr ES:[DI], AL
INC SI
INC DI
LOOP cp_loop
; ---End of block
Choose equivalent string operations in place of block code from ---Start of block to ---End
of block
Select one or more:

CLD
cp_loop:
MOVSB
LOOP cp_loop
CLD
cp_loop:
REP MOVSB
LOOP cp_loop
CLD
REP MOVSB
STD
cp_loop:
MOVSB
LOOP cp_loop
Question 24 After each execution of POP instruction, the stack pointer is

Complete
Select one:
Marked out of 0.50
increment by 1
increment by 2
decrement by 2
decrement by 1
lOMoARcPSD|30860100

MOV EDX, [SI]
MOV EAX, [SI+4]
EDX = 99007524
EAX = 203E8099
Question 26 Part of memory shown in figure

Not answered
Marked out of 1.00
What is the value of AH follow the execution of this code:

MOV BX, 1D4D
MOV AX, [BX]
Answer:
Question 27 Which are valid based indexed addressing?

Complete
Select one or more:
Marked out of 1.00
[SP][SI]
[BX][SI]
[BP][SI]
[DX][DI]
lOMoARcPSD|30860100

Complete XOR BX, BX
Marked out of 1.20 CMP DL, 5
JLE a_label
CMP DL,17h
JGE a_label
MOV BX, 10h
a_label:
INC BX
watch point:
...
Choose correct value of BX register at watch point for different value of DL?
DL=0FFh 11h
DL=10 01h
DL=17h 01h
DL=0Ah 28h
Question 29 Part of computer memory are shown in figure.

Not answered
Marked out of 1.00
What is the value of AX register after instruction MOV AX, 1D49 executed
Answer:
Question 30 To set one or more bits in a byte value, use __________ instruction.
Complete
Select one:
Marked out of 0.50
NOT
XOR
AND
OR
lOMoARcPSD|30860100

Complete
Marked out of 1.00 DRAM Slow access time, cheaper cost per bit, can only manufacture at larger size
SRAM Faster access time, cost more per bit, smaller size
Question 32 Major structural components of the CPU include:

Complete
Select one or more:
Marked out of 1.00
Arithmetic and Logic Unit
Instruction Register
Interconnections
Control Unit
Instruction Pointer (PC)
Registers
Question 33 Select correct match for AL and carry flag at watch point #1:
Complete MOV BL, 8C
Marked out of 1.00 MOV AL, 7E
ADD AL, BL
watch point #1:
......
AL set
Carry flag 0A
lOMoARcPSD|30860100

Complete if (a>=0 && a <=9)
Marked out of 1.20 x = a + 30h;
else if (a >=10 && a <=15)
x = a + 55;
The logic of the above code snippet in assembly is (with missing lines):
01: CMP DL, 0
02: ------------ ; possibly missing code
03: CMP DL, 9
05: ADD DL, 30h
a_label:
08: CMP DL, 0Fh
10: ADD DL, 55
x_label:
12: MOV AL, DL
...
Choose correct missing instructions in the above sequence of instructions
02: JMP a_label
06: JMP x_label
04: empty
09: empty
lOMoARcPSD|30860100

Complete 072C:FFF0 00 00 00 01 00 00 2C 07 - 07 01 2C 07 17 72 00 00
Marked out of 1.50 SS=072C, SP=FFF8, DS = 072C
Assume the stack now stores two (2) 16-bit parameters and one (1) 16-bit return address in
following order: stack top (return address) >> parameter #1 >> parameter #2.
The following sequence of instructions are executed. What is the correct values at watch
points?
MOV BP, SP
watch point #1 (BP):
MOV AX, [BP+2]
ADD AX, [BP+4]
MOV DI, 120
MOV [DI], AX
watch point #1: AX = 2C07
watch point #2: BP = FFF8
watch point #3: SUB AX, [SI]
lOMoARcPSD|30860100

Question 36 Given a code snippet to look for a value (from AL) in memory buffer Buff
Complete Buff DB 11,22,33,44,55
Marked out of 1.20 ................
01: LEA DI, Buff
03: MOV AL,33
04: MOV CX,5
a_label:
06: CMP Byte Ptr [DI],AL
08: LOOPNZ a_label
...
Choose correct missing instructions in the above sequence of instructions
05: INC DI
07: DEC DI
02: Empty
Question 37 In multiplication instruction, when the value of source operand is 12 (decimal), the other
Complete operand is loaded in AX. Which registers can be used to load source operand?
Marked out of 0.50

Select one or more:
DX
BX
CL
AX
DL
lOMoARcPSD|30860100

Question 38 The following sequence of instructions are executed. What is the correct value of AX
Complete and DX (in hex) at watch point?

MOV CX,1000h
IMUL CX
watch point:
AX= FFF6
DX= 6000
Question 39 the instruction, CMP to compare source and destination operands by __________
Complete
Select one:
Marked out of 0.50
comparing
subtracting
dividing
adding
Question 40 To test one bit in a byte value which can be destructive. use __________ instruction.
Complete
Select one:
Marked out of 0.50
TEST
AND
OR
NOT
Question 41 Which are correct input for XLAT instruction

Complete
Select one or more:
Marked out of 0.50
DS:[BX] pointed to look-up table
DS:[SI] pointed to look-up table
look-up index must be loaded into DL
look-up index must be loaded into AL
lOMoARcPSD|30860100

Question 42 Which are correct action for LODSW string operation if DF is reset (=0)
Complete
Select one or more:
Marked out of 0.50
increase SI by 2
decrease DI by 2
Marked out of 1.00 MOV DL,19

MOV AL,F6
IMUL DL
watch point:
OF = reset
CF = reset
Question 44 The following sequence of instructions are executed. What is the correct value of AX, DX at

MOV AL,42
IMUL DL
watch point:
AX = FF00
DX = FFBE
Question 45 Write mask byte (in hex) to clear the lower 4 bit of a byte value with AND instruction.
Not answered
lOMoARcPSD|30860100

Tran Quang Lam
THE EXAM PERFORMANCE PROGRAM

INFORMATION TECHNOLOGY CENTER
 Call Us: (+84 - 8) 38968641 - (+84 - 8) 38961333  Email: ic@hcmute.edu.vn
Dashboard ► Học kỳ 2 năm 2016 - 2017 ► Lớp Chất lượng cao ► CAAL240180_16_2_8506 ► General ►
Kiểm tra cuối kỳ đề 1
Started on Monday, 5 June 2017, 1:11 PM

State Finished
Completed on Monday, 5 June 2017, 2:20 PM

MOV AL,F6
IMUL DL
watch point:
OF = reset
CF = reset
lOMoARcPSD|30860100

Question 2 In multiplication instruction, when the source operand is 16 bit, how can the result be taken?
Complete
Select one:
Marked out of 0.50
from DX:AX pair
from EAX
from AX:DX pair
from AX

Not answered CMP DL, 0
JB x_label
Marked out of 1.20
CMP DL, 9
JA a_label
ADD DL, 30h
JMP x_label
a_label:
CMP DL, 0Fh
JA x_label
ADD DL, 37h
x_label:
MOV AL, DL
watch point:
...
DL=10 Choose...
DL=8 Choose...
DL=55h Choose...
DL=0FFh Choose...
lOMoARcPSD|30860100

Question 4 Hereafter is instruction sequence to compute the sum of 8 bytes starting at memory address
Complete 200. Two lines of code are possibly missing. Choose correct one to fill in?
Marked out of 1.20 01: _____________; possibly missing code

02: MOV AL, 0
03: MOV CX, 8
04: Loop_label:
05: _____________; possibly missing code
06: ADD AX, [SI];
07: INC SI
08: LOOP Loop_label
01: MOV [SI],200
05: CWD
Question 5 In multiplication instruction, when the source operand is 8 bit, _________ will be multiplied
Complete with source.
Marked out of 0.50

Select one:
AX
BX
AL

Complete
Select one or more:
Marked out of 1.00
[BX+DI]
[DX+SI]
[SP+DI]
[BX+SI]
lOMoARcPSD|30860100

Question 7 Given a flowchart of an algorithm:
Not answered
Marked out of 1.20
Select one or more:

mov dl,10
cmp al,bl
jnz n_label
add dl,10
jmp e_label
n_label:
mov cl,1
shl dl,cl
e_label:
mov dh,dl
mov dl,10
cmp al,bl
jz n_label
mov cl,1
shl dl,cl
jmp e_label
n_label:
add dl,10
e_label:
mov dh,dl
mov dl,10
cmp al,bl
jnz n_label
add dl,10
jmp e_label
n_label:
mov cl,1
shr dl,cl
e_label:
mov dh,dl
lOMoARcPSD|30860100

mov dl,10
cmp al,bl
jnz n_label
add dl,10
mov dh,dl
jmp e_label
n_label:
mov cl,1
shl dl,cl
e_label:
mov dh,dl

Complete
Marked out of 1.00
Answer: 2D
Question 9 The following sequence of instructions are executed. What is the correct value of AX, CX,
Complete DX at watch point?
Marked out of 1.00 MOV AX,0020

MOV CX,0010
MUL CL
watch point:
AX = 020F
DX 0000
CX = 00FF
lOMoARcPSD|30860100

Question 10 Which set of registers are valid for addressing a stack memory location?
Complete
Select one or more:
Marked out of 1.00
DS:SI
SS:SP
SS:BP
SS:BX
Complete
Select one:
Marked out of 1.00
served.
served.

MOV EDX, [SI]
MOV EAX, [SI+4]
AX = 203E
DX = 8099
lOMoARcPSD|30860100

Complete
Select one or more:
Marked out of 1.00
Data movement
Control
Interrupt
Data processing
Data storage
Marked out of 1.00 MOV AX,FFFF

MOV CX,5
MUL CX
watch point:
lOMoARcPSD|30860100

Not answered int n = 10;
Marked out of 1.20 do {
n--;
} while (n > 0);
Select one or more:

mov cx, 10
a_label:
dec cx
cmp cx, 0
jz e_label
jmp a_label
e_label:
mov cx, 10
a_label:
.....
loop a_label
mov cx, 10
a_label:
.....
dec cx
cmp cx,0
jz a_label
mov cx, 10
a_label:
.....
dec cx
loop a_label
Question 16 Write mask byte (in hex) to clear bit 2nd, 3rd, 5th of a byte value with AND instruction (LSB is 1st
Not answered bit).
Marked out of 1.20

Answer:
lOMoARcPSD|30860100

Complete
Marked out of 1.00
Answer: 90
Question 18 To clear one or more bits in a byte value, use __________ instruction.
Complete
Select one:
Marked out of 0.50
AND
XOR
OR
NOT
Question 19 The instruction, MOV AX, 0005h belongs to which addressing mode?
Complete
Select one:
Marked out of 0.50
register
direct
index
Immediate
Question 20 Which are correct about the data registers of IA-32 processors:
Complete
Select one or more:
Marked out of 1.00
Lower halves of the 16-registers an be used as 8-bit data registers:
AH,AL,BH,BL,CH,CL,DH,DL
Lower halves of the 32-registers an be used as 4 16-bit data registers: AX,BX,CX,DX
Higher halves of the 32-bit registers can be used as 16-bit registers:

EAH,EAL,EBH,EBL,ECH,ECL,EDH,EDL
complete 32-bit registers: EAX, EBX, ECX, EDX
lOMoARcPSD|30860100

Not answered
Select one or more:
Marked out of 1.00
Monitor
Memory
I/O Equipments
Punched card reader
Bus
CPU

SUB AL,124
watch point:
Overflow flag (OF) = set
Zero flag (OF) = reset
Sign flag (SF) set
Question 23 Enter debug command to fill 256 bytes in data segment starting from 100 with value 0D
Complete
Marked out of 1.00 Answer: F 100 1FF 0D
lOMoARcPSD|30860100

Question 24 Which are correct action for STOSB string operation if DF is reset (=0)
Not answered
Select one or more:
Marked out of 0.50
decrease DI by 1
Store 8-bit value from AL into memory location pointed by ES:[DI]
increase DI by 1
Store 8-bit value from AL into memory location pointed by DS:[SI]
Complete
Select one or more:
Marked out of 1.00
Pipelining
Branch prediction
Question 26 The following sequence of instructions are executed. What is the correct value of CF and
Complete OF at watch point?

MOV CX,1000h
IMUL CX
watch point:
CF= reset
OF= reset
Question 27 Which are correct action for SCASW string operation if DF is set (=1)
Complete
Select one or more:
Marked out of 0.50
decrease DI by 2
increase DI by 2
lOMoARcPSD|30860100

Marked out of 1.00 SI = 120, DI = 128
Select correct sequence of instructions to subtract words at [DI] from [SI] then store the
result at memory location 12A
Step 1: MOV AX, [SI]
Step 2: SUB AX, [DI]
Step 3: MOV BX, 012A
Step 4: MOV [BX], AX
Question 29 Select correct match for register values at watch points:

Complete MOV AX, 4FCA
Marked out of 1.00 ADD AX, DDA9
watch point #1:
ADD AH, F3
watch point #2:
......
watch point #2: AL = 73
Question 30 Compute the physical address of the next instruction will be execute if instruction pointer is
Complete 091D and code segment located at 1FAF
Marked out of 1.00
Answer: 2040D
lOMoARcPSD|30860100

Complete
Marked out of 1.00 DRAM Slower access time, cheaper cost per bit, can manufacture with larger size
Question 32 Convert the 32-bit floating point number 44363800 (in hex) to decimal.
Complete

MOV BL, 2
MUL BL
watch point:
Question 34 Which could be correct ones for the destination operand in a data movement instruction?
Complete
Select one or more:
Marked out of 0.50
memory location
immediate data
register
lOMoARcPSD|30860100

Marked out of 1.00 MOV AL, 0F

ADD AL, F1
watch point:

Complete 1D20:0200 00 20 10 5D 55 47 00 90 - 00 10 20 30 40 50 60 70
Marked out of 1.00 Given value of registers: DS = 1D20, SI = 200, BX = 202, AX = 0103
Identify correct value of AX register after XLAT instruction is executed.
AL = 10h
AH = 01h
lOMoARcPSD|30860100

Question 37 Given a code snippet (ax, bx are none negative integers):
Not answered if (ax >= bx)
Marked out of 1.20 ax -=bx;
else
bx -=ax;
Select one:
cmp ax,bx
jnbe a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
jb a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
jbe a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
cmp ax,bx
ja a_label
sub ax,bx
jmp x_label
a_label:
sub bx,ax
x_label:
lOMoARcPSD|30860100

Complete
Select one or more:
Marked out of 0.50
MOV AX, SI
MOV AX, [BP+2]
MOV SP, SS:[SI+2]
MOV DS, B800h
Question 39 if the location to which the control is to be transferred lies in a segment other than the
Complete current one, then the jump instruction is call
Marked out of 0.50

Select one:
intersegment mode
intrasegment mode
Question 40 The instruction that supports addition when carry exists is

Complete
Select one:
Marked out of 0.50
ADD
ADC
DAS
SBB
Not answered
lOMoARcPSD|30860100

Question 42 The instruction that is used for finding out the codes in case of code conversion problems is
Complete
Select one:
Marked out of 0.50
JCXZ
XCHG
XLAT
XOR

Complete
Select one or more:
Marked out of 1.00
Question 44 Which are correct action for LODSB string operation if DF is reset (=0)
Complete
Select one or more:
Marked out of 0.50
increase SI by 1
Load 8-bit value at memory location pointed by ES:[DI] into AL
decrease DI by 1
Load 8-bit value at memory location pointed by DS:[SI] into AL
Question 45 To test one bit in a byte value without destructing the byte, use __________ instruction.
Complete
Select one:
Marked out of 0.50
AND
TEST
NOT
OR
lOMoARcPSD|30860100
Nhóm 060708CLC Kiến trúc máy tính và hợp ngữ

Started on Tuesday, 14 March 2017, 10:46 AM
State Finished
Completed on Tuesday, 14 March 2017, 11:25 AM
Time taken 38 mins 36 secs
Question 1 What is the correct sequence of instruction cycle?

Complete
Marked out of Step 5 Calculate operand address

1.20
Step 2 Decode
Step 4 Execution
Step 3 Fetch operand
Step 1 Fetch opcode
Step 6 Store result
Your answer is partially correct.

You have correctly selected 3.
Question 2 Which one best describe cache hit and cache miss?
Complete
Cache
Marked out of
miss the number of memory accesses that CPU must retrieve from the main memory per the total number of memory accesses
1.00
ratio
Cache
hit the number of memory accesses that the CPU can retrieve from the cache per the total number of memory accesses
ratio
Your answer is correct.
Question 3 For cache write policies, which are often used for writehit and writemiss
Complete
Marked out of Writehit Writeback

1.00
Writemiss Writeallocate

Complete
Marked out of DRAM Slower access time, cheaper cost per bit, can manufacture with larger size
1.00

lOMoARcPSD|30860100
Question 5 Identify the correct sequence to update a page onto a flash memory?
Complete
Marked out of Step 3 the entire block is being read from flash into RAM then request data in page is update
1.00
Step 1 the entire block of flash memory are erased
Step 2 The entire block from RAM then is written back to the flash memory
Your answer is incorrect.
Question 6 Choose correct set of registers for x86 processor

Complete
Marked out of Data pointer to source memory in extra segment ES: SI

1.00
Pointer to variable in stack SS: BP
Instruction pointer CS: IP
Data pointer in data segment DS: BX
Question 7 Match the definition of flag bits in PSW

Complete
Marked out of contains the carry of 0 or 1 from the leftmost bit after an arithmetic operation CF
1.00
determine the direction for moving or comparing data between memory areas DF
determine whether an external interrupts are to be ignored or processed IF
the processor switches to singlestep mode TF

Complete
Select one or more:
Marked out of
1.00 Monitor
Memory
Punched card reader
CPU
Bus
I/O Equipments
Question 9 Which is not correct about MOORE law?

Complete
Select one or more:
Marked out of
1.00 The number of transistors that could be put on a single chip was doubling every year
The number of transistors that could be put on a single chip was triple every year nowadays.
Likely triple after 2000
The number of transistors that could be put on a single chip was doubling every year except 1970s

lOMoARcPSD|30860100
Complete
Select one or more:
Marked out of
1.00 Branch prediction
Pipelining
Question 11 To balance the super speed of CPU with the slow response of memory, which of the following measures have been made by engineers in system design?
Complete
Select one or more:
Marked out of
1.00 To move data directly by DMA
Make wider data bus path
Make use of both onchip and offchip cache memory
Using higherspeed bus and us hierarchy
Question 12 What is the meaning of Amdahl's law in processor performance evaluation?

Complete
Select one:
Marked out of
1.00 the cost reduce when moving from singlecore to multicore processor
the potential speedup of a program using multiple processor compared to a single processor
the speedup of a multicore processor when increasing system bus speed
the maximum speedup of a multicore processor
Question 13 What are the processor's instruction categories

Complete
Select one or more:
Marked out of
1.00 Data processing
Control
Processor Cache memory
Processor I/O
Processor Memory
Memory Memory (DMA)
Complete
Select one:
Marked out of
1.00 The processor can not process multiple interrupt requests
Each device are assigned an interrupt priority, the device with higher priority will be served.

Each device are assigned an interrupt priority, the device with lower priority will be served.
Your answer is incorrect.

lOMoARcPSD|30860100
Question 15 Bus is a shared transmission medium, multiple devices connect to it but only one at a time can successfully transmit. Which component in computer
Complete facilitates this operation?
Marked out of
Select one:
1.00
Bus Arbiter
Programmed I/O
Direct Memory Access (DMA)
Bus master
Question 16 When many devices of different transmission speed connect to the same bus, the overall system performance suffers. How did the design engineers
Complete resolved this:
Marked out of
Select one:
1.00
PCI Express bus
PCI bus
Split system bus into local bus and memory bus
MultipleBus hierarchies
Question 17 What are the features of directmapping cache organization?

Complete
Select one or more:
Marked out of
1.00 Thrash > low hit ratio
faster
Simple and inexpensive
small cache memory
Question 18 Which ones are not correct for static RAM?

Complete
Select one or more:
Marked out of
1.00 Cost per bit is higher than dynamic RAM
faster than dynamic RAM because they are made from capacitor
Cheaper than dynamic RAM because simpler chip controller
Cost per bit is lower than dynamic RAM

Question 19 Which one is not correct?

Complete
Select one or more:
Marked out of
1.00 EEPROM is erasable by exposing under UV
PROM is nonvolatile memory
EPROM is erasable electrically
Flash memory can only be erased electrically byte by byte

lOMoARcPSD|30860100

Complete
Select one or more:
Marked out of
1.00 a. Bits are stored on tracks
b. Head, Track, Sector are key parameters for access data on hard disk
c. Bits are store randomly on disk surfaces
d. Head, Track, Cylinder are key parameters for access data on hard disk
Question 21 What is correct about the function of TRIM command in SSD?

Complete
Select one:
Marked out of
1.00 Allow SSD to allocate memory pages in blocks properly for faster access
Allow SSD to defragment scattered data stored in separate pages
Allow OS to notify SSD the presence of occupied blocks of data which are no longer in use and can be erased internally
Allow SSD to manage occupied pages and remove them automatically for later use
Question 22 Which set of registers are valid for addressing a memory location?
Complete
Select one or more:
Marked out of
1.00 DS:SI
DS:BX
SS:DI
CS:IP

Complete
Select one or more:
Marked out of
1.00 [BX+SI]
[SP+DI]
[DX+SI]
[BX+DI]
Question 24 Which are valid index addressing?

Complete
Select one or more:
Marked out of
1.00 [SI]
[DX]
[BX]
[BP]


lOMoARcPSD|30860100
Question 25 8088 is 16 bit processor, the maximum addressable memory is:

Complete
Select one:
Marked out of
1.00 64M
1024K
640K
640M
Question 26 Which are correct about the data registers of IA32 processors:
Complete
Select one or more:
Marked out of
1.00 Lower halves of the 16registers an be used as 8bit data registers: AH,AL,BH,BL,CH,CL,DH,DL
complete 32bit registers: EAX, EBX, ECX, EDX
Lower halves of the 32registers an be used as 4 16bit data registers: AX,BX,CX,DX
Higher halves of the 32bit registers can be used as 16bit registers: EAH,EAL,EBH,EBL,ECH,ECL,EDH,EDL
Question 27 Which are correct about 32 bit index registers of IA32 processors:
Complete
Select one or more:
Marked out of
1.50 EDI: 32 bit pointer to destination memory in data movement instructions
ESH,EDH: 16 bit pointers to higher memory above 1M
DI: 16 bit pointer to destination memory in data movement instructions
SI: 16 bit pointer to source memory in data movement instructions
ESI: 32 bit pointer to source memory in data movement instructions
Question 28 Which statement is correct about interrupt vector table?

Complete
Select one or more:
Marked out of
1.00 Store in the ending area of 1024K of the main memory
Take up 1024 bytes in the main memory
Store on disk
Store in the beginning area of the main memory
Question 29 Part of memory as shown in figure

Complete
Marked out of
1.00
The value of DX register follows the execution of MOV DX, [1D4D] is 127B. What is the endian type of this computer system
Select one:
littleendian
levelendian
bigendian
nonendian

lOMoARcPSD|30860100
Question 30
Part of memory as shown in figure
Complete
Marked out of
1.00
The value of BX register follows the execution of MOV BX, [1D49] is F57F. What is the endian type of this computer system
Select one:
levelendian
bigendian
littleendian
nonendian
Question 31 The value in CS is 1FD0h what is the location of next instruction from 00000h if Instruction pointer is 3CD4h
Complete
Marked out of Answer: 3CD5H

0.50
Question 32 Select correct items to describe best about CISC

Complete
Marked out of Number of clocks per instruction multiclock

1.00
code size of program small code size
Assembly code simpler
Instruction set Complex
Bytes per instruction different for variety of instructions
Question 33 What best describe the Spatial and Temporal Locality?

Complete
Temporal
Marked out of be exploited by keeping recently used instruction and data in cache memory and by exploiting a cache hierarchy
locality
1.00
Spatial
be exploited by using larger cache blocks and by incorporating prefetching mechanisms into the cache control logic
locality

lOMoARcPSD|30860100
Question 34 What can be concluded from the following chart of processor trends:
Complete
Marked out of
1.00
Select one:
The multicore processors and level off clock speed help to make heat dissipation of CPU chip less
The number of transistors in chips produce more heat dissipation
Heat dissipation in processor chip is increasing year after year since 1970
The processor speed keeps increasing after 2003
Question 35 To evaluate processor performance, the following indicators and formulas are used:
Complete
Marked out of
1.00
Which of the following system attributes affects Ic (the number of instructions of a program)
Select one or more:

Cache and memory hierarchy
Processor implementation
Instruction set architecture
Compiler technology
Complete
Marked out of
Which of the following system attributes affects cycle time 
1.00
Select one or more:

Compiler technology

lOMoARcPSD|30860100
Question 37 Key parameters to consider when evaluating processor hardware include:

Complete
Select one or more:
Marked out of
1.00 reliability
performance
power consumption
databus size
size
Address bus size
cost
Question 38 A memory chip has 12 address pins, determine the maximum memory words of this chip?
Complete
Select one:
Marked out of
1.00 2048K
2048
4000
4096
Question 39 Which of the following best describe the memory chip with pinout as shown below:
Complete
Marked out of
1.00
DQ: Data pinout
Select one:
DRAM 64Kx4bit
SRAM 256Kx1bit
DRAM 16Kx4bit
SDRAM 64Kx4bit

lOMoARcPSD|30860100
Question 40 Choose the correct structure of memory chip as shown below

Complete
Marked out of
1.00
Note:
DQ: Data pinout
Select one:
DRAM 2Kx8bit
SRAM 1Kx16bit
SRAM 2Kx8bit
DRAM 1Kx16bit
Question 41 The three key characteristics of memory are: capacity, access time and cost. Which of the following relationships hold for a variety of memory
Complete technologies?
Marked out of
Select one or more:
1.00
Faster access time, greater cost per bit
Higher capacity, higher access time
Greater capacity, smaller cost per bit
Greater capacity, slower access time
Question 42 A SRAM memory chip labeled 32x8bit. Which of the following is correct pinout regarding address and data lines?
Complete
Select one:
Marked out of
1.00 32 address pins, 3 data pins
32 address pins, 4 data pins
Question 43 In the interconnection system, the number of address lines are governs by
Complete
Select one:
Marked out of
1.00 I/O Module
CPU
data bus line
Memory size

lOMoARcPSD|30860100
Question 44 For memory hierarchy below, which relationship hold when moving downward
Complete
Marked out of
1.00
Select one or more:

Increasing access time
Decreasing cost per bit
Decreasing frequency of access by the processor
the processor accesses more often

Increasing capacity
Question 45 Identified correct addressing mode of the following instructions?

Complete
Marked out of MOV AX, BX Register

1.50
MOV BP, [BX+SI] Base relative plus index
MOV AX, ARRAY [BX+SI] Base plus index
MOV AX, [BX] Register indirect
MOV AX,[1234h] Direct
MOV AX, 3540h Immediate


Complete
Marked out of
1.00
Answer: 5A2D

lOMoARcPSD|30860100
Question 47 Part of memory shown in figure

Complete
Marked out of
1.00
What is the value of EAX follow the execution of this code

MOV BX, 1D4C
MOV EAX, [BX]
Answer: 125A

Complete
Marked out of
1.00
The value of SP register is 1D48. What is the value of SI follows the execution of POP SI
Answer: 1D48

Complete
Marked out of
1.00
Answer: 1D4F
Question 50 Consider two different machines, with two different instruction sets, both of which have a clock rate of 200 MHz. The following measurements are recorded
Complete on the two machines running a given set of benchmark programs
Marked out of
3.00
Determine the effective, CPI, MIPS rate and execution time for each machine.
CPI_b 1.92
CPU Time_a 0.2
CPU Time_b 0.23
CPI_a 2.22
MIPs_b 104
MIPs_a 90

lOMoARcPSD|30860100
Question 51 Choose correct RAID volume definitions for a request 2T storage.

Complete
Marked out of RAID 1 Mirror volume 2 x 2T HDDs are needed, no data lost when the primary storage fails
2.00
Spanned Volume 2T HDD + more HDDs to extend storage, no fault tolerance, data lost when one HDD fails
RAID 0 Striped volume 2 x 1T HDDs are needed, enhance data transfer, no fault tolerance, data lost when one HDD fails
RAID5 Volume At least 3 x 2T HDDs, faulttolerance, no data lost, no downtime
Question 52 Consider a 32bit microprocessor whose bus cycle is the same duration as that of a 16bit microprocessor. Assume that, on average, 30% of the operands
Complete and instructions are 32 bits long, 40% are 16 bits long, and 30% are only 8 bits long. Calculate the improvement achieved when fetching instructions and
operands with the 32bit microprocessor?
Marked out of
1.00
Select one:
10%
15%
17%
23%
Question 53 Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per track. Sector size is 1 kB, the average seek time is 10.2 ms and
Complete the drive rotates at 3600 rpm. What is average access time. Given: Rotational delay = 1/(2r), where r is the rotational speed in revolutions per second
Marked out of
1.00 Answer: 16.3 ms
Return to: 12 March 18 M... 

lOMoARcPSD|30860100
5/31/2019 Bài Thi Cuối Kỳ Môn Kiến Trúc Máy Tính và Hợp Ngữ
Thi Online KTMT&HN nhóm lẻ

Started on Friday, 31 May 2019, 1:11 PM
State Finished
Completed on Friday, 31 May 2019, 2:21 PM
Question 1 In multiplication instruction, the upper half of the result is nonzero implies which state of Carry flag and
Complete Overflow flag?
Marked out of
Select one or more:
0.50
OF=1
CF=1
OF=0
CF=0
Question 2 Which is correct about dual-layer DVD?

Complete
Select one:
Marked out of
1.00 the same as double-sided DVD
contains layers on both sides of the disk for writing data to
contains two layers on a single side for writing data to
DVD drives has double laser head for reading from or writing to this disk
Complete
Select one or more:
Marked out of
1.00 Pipelining
Branch prediction
https://lms.hcmute.edu.vn/mod/quiz/review.php?attempt=1165657&cmid=406329 1/12
lOMoARcPSD|30860100

Complete XOR BX, BX
Marked out of CMP DL, 5
1.00 JLE a_label
CMP DL,17h
JGE a_label
MOV BX, 10h
a_label:
INC BX
watch point:
...
Choose correct value of BX register at watch point for different value of DL?
DL=0Ah 01h
DL=0FFh 11h
DL=10 01h
DL=17h 11h
Question 5 Consider a 16-bit microprocessor, with a 16-bit external data bus, driven by an 10-MHz input clock.
Complete Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles.
What is the maximum data transfer rate across the bus that this microprocessor can sustain?
Marked out of
1.00
Select one:
4 MB/s
1 MB/s
5 MB/s
10 MB/s
Question 6 Select correct definition of seek time, rotational delay, access time, transfer time for hard drives with
Complete moveable-head system:
Marked out of
1.00 rotational delay time for the sector in the request track to reach the head
seek time time for the head to settle at the request track
access time access time + settle time
Question 7 Which are the correct actions for LODSW string operation if DF is reset (=0)
Complete
Select one or more:
Marked out of
0.50 decrease DI by 2
increase SI by 2
lOMoARcPSD|30860100
Question 8 In computer organization, the CPU transfer rate is much higher than that of memory. It is easy to match
Complete performance of these components by:
Marked out of
Select one:
1.00
increase the bus speed
producing faster memory module
Introducing cache memory
increase I/O speed
Question 9 For memory hierarchy below, which relationship hold when moving downward
Complete
Marked out of
1.00
Select one or more:

Decreasing cost per bit
the processor accesses more often
Increasing access time
Decreasing frequency of access by the processor
Increasing capacity

Complete
Select one or more:
Marked out of
0.50 MOV DS, B800h
MOV AX, SI
MOV AX, [BP+2]
MOV SP, SS:[SI+2]
lOMoARcPSD|30860100
Question 11 Sign-extend number 1011 0101 (8-bit binary) to 16-bit

Complete
Marked out of Answer: 1111 1111 1011 0101

0.50
Question 12 The principle of cache memory relies on key features: locality of reference which involves spatial and
Complete temporal locality. Match the definition to keywords on the left
Marked out of
Temporal
1.00 the tendency for a processor to access memory locations that have been used recently
locality
Spatial the tendency of execution to involve a number of memory locations that are clustered
locality
tendency to use large cache and prefetch mechanism
Question 13 Which ones are not correct for static RAM?

Complete
Select one or more:
Marked out of
1.00 faster than dynamic RAM because they are made from capacitor
Cheaper than dynamic RAM because simpler chip controller

Cost per bit is higher than dynamic RAM
Cost per bit is lower than dynamic RAM
Question 14 Which of the following instructions are not legal addressing?

Complete
Select one or more:
Marked out of
1.00 MOV AX, [DI]
MOV CX, [SI]

MOV AX, [BX+SP]
MOV AX, [SP+1]
Question 15 Structural components of computer include:

Complete
Select one or more:
Marked out of
1.00 I/O
DMA
System interconnection
Interrupt
Central processing unit
Memory
lOMoARcPSD|30860100
Question 16 A memory chip has 12 address pins, determine the maximum memory words of this chip?
Complete
Select one:
Marked out of
1.00 4096
2048
2048K
4000
Question 17 Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per track. Sector
Complete size is 1 kB. What is the disk capacity
Marked out of
1.00 Answer: 262144 KB

Complete
Marked out of SRAM Faster access time, cost more per bit, smaller size
1.00
DRAM Slower access time, cheaper cost per bit, can manufacture with larger size
Question 19 The following sequence of instructions are executed. What is the correct value of AX, CX, DX at watch
Complete point?
Marked out of MOV AX,0020

1.00 MOV CX,0010
MUL CL
watch point:
DX 0000
AX = 0200
CX = 0010

Complete
Select one or more:
Marked out of
1.00 a. Bits are store randomly on disk surfaces
b. Head, Track, Cylinder are key parameters for access data on hard disk
c. Bits are stored on tracks
d. Head, Track, Sector are key parameters for access data on hard disk
lOMoARcPSD|30860100
Question 21 Which are the correct inputs for XLAT instruction

Complete
Select one or more:
Marked out of
0.50 look-up index must be loaded into DL
DS:[BX] pointed to look-up table
look-up index must be loaded into AL
DS:[SI] pointed to look-up table
Question 22 What is the correct value of SI, AL (in hex) at watch point:
Complete 01: MOV SI, 300h
Marked out of 02: MOV AL, 10h
1.00 03: MOV CX, 7
04: Loop_label:
05: MOV [SI], AL
06: ADD AL,10h
07: INC SI
08: LOOP Loop_label
watch point:
SI 307h
AL = 80h
Complete
Marked out of
1.00
Which of the following system attributes affects cycle time t
Select one or more:

Compiler technology
lOMoARcPSD|30860100
Question 24 To encrypt a byte value, use __________ instruction.

Complete
Select one:
Marked out of
0.50 XOR
AND
NOT
OR
Question 25 In multiplication instruction, when the source operand is 8 bit, _________ will be multiplied with source.
Complete
Select one:
Marked out of
0.50 AX
AL
BX
Question 26 A system programmer needs to compute 449/2+358/4 (decimal). Instruct him to code in debug (number
Complete must be in hex) with the least number of instruction counts.
Marked out of
1.50
Step 1: MOV AX,166
Step 2: MOV CL,2
Step 3: SHR AX,CL
Step 4: MOV BX,AX
Step 5:
MOV AX,01BC
Step 6: ADD AX,BX
Complete
Marked out of Answer: 3DD00000

1.00
Question 28 The instruction that loads the AH register with the lower byte of the flag register is
Complete
Select one:
Marked out of
0.50 LAHF
PUSHF
AH
SAHF
lOMoARcPSD|30860100
Question 29 The following sequence of instructions are executed. What is the correct value of flag bits at watch point?
Complete MOV AL, 0F
Marked out of ADD AL, F1
1.00
watch point:
Question 30 Which are correct about 32 bit index registers of IA-32 processors:
Complete
Select one or more:
Marked out of
1.50 ESI: 32 bit pointer to source memory in data movement instructions
ESH,EDH: 16 bit pointers to higher memory above 1M
SI: 16 bit pointer to source memory in data movement instructions
EDI: 32 bit pointer to destination memory in data movement instructions
DI: 16 bit pointer to destination memory in data movement instructions
Question 31 Select the correct sequence of instructions to compute -1024/128 (all values are in hex).
Complete
Marked out of Step 1: MOV AX,FC00

1.00
Step 2: MOV CX,80
Step 3: CWD
Step 4: IDIV CX
Question 32
Complete
Marked out of
1.50
Calculate MIPS rate for this program

Given:
Answer: 25.80645161
lOMoARcPSD|30860100
Question 33 What is the correct sequence of instruction cycle?

Complete
Marked out of Step 6 Store result

1.20
Step 4 Fetch operand
Step 1 Execution
Step 5 Calculate operand address
Step 2 Fetch opcode
Step 3 Decode
Question 34 Convert the 32-bit floating point number C4361000 (in hex) to decimal.
Complete
Marked out of Answer: -728.25

1.00
Question 35 Write mask byte (in hex) to clear bit 2nd, 3rd, 5th of a byte value with AND instruction (LSB is
Complete 1st bit).
Marked out of
0.50 Answer: E9
Question 36 8088 is 16 bit processor, the maximum addressable memory is:

Complete
Select one:
Marked out of
0.50 640M
640K
1024K
64M
Question 37 Write mask byte (in hex) to set bit 6th, 4th of a byte value with OR instruction (LSB is the 1st
Complete bit).
Marked out of
0.50 Answer: 28
Question 38 the instruction, CMP to compare source and destination operands by __________
Complete
Select one:
Marked out of
0.50 subtracting
adding
dividing
comparing
lOMoARcPSD|30860100
Question 39
Complete
Marked out of
1.00
Calculate the execution time for this program.

Given:
Answer: 0.003875

Complete
Marked out of
1.00
Answer: 5A2D
Question 41 Select correct level for contemporary computer multilevel machine

Complete
Marked out of Level 3 Operating system level

1.00
Level 5 High level programming language
Level 6 Applications
Level 1 Microarchitecture level
Layer 4 Assembly Language level
Level 2 Instruction set level
Level 0 Digital logic level
lOMoARcPSD|30860100

Complete
Marked out of
1.00
Answer: 1D48
Question 43 Choose the correct structure of memory chip as shown below

Complete
Marked out of
1.00
Note:
DQ: Data pinout
Select one:
DRAM 2Kx8-bit
SRAM 1Kx16-bit
SRAM 2Kx8-bit
DRAM 1Kx16-bit
Question 44 Given 8-bit floating-point binary format:

Complete 1 (sign) + 3 (exponent) + 4 (mantissa)
Marked out of Convert the 8-bit floating point number 68 (in hex) to decimal.
1.00
Answer: 12.0
Question 45 Choose correct RAID volume definitions for a request 2T storage.

Complete
RAID 0 -
Marked out of
Striped 2 x 1T HDDs are needed, enhance data transfer, no fault tolerance, data lost when one HDD fails
2.00
volume
RAID5
At least 3 x 2T HDDs, fault-tolerance, no data lost, no down-time
Volume
RAID 1 -
Mirror 2 x 2T HDDs are needed, no data lost when the primary storage fails
volume
Spanned
2T HDD + more HDDs to extend storage, no fault tolerance, data lost when one HDD fails
Volume
lOMoARcPSD|30860100
NHÀ CỦA TÔI  CÁC KHOÁ HỌC CỦA TÔI  HỌC KỲ 2 NĂM HỌC 20162017 
CÁC LỚP HỌC CẬP NHẬT SAU  KT_KTMT  26 MARCH 1 APRIL  BÀI TẬP ÔN
Nhóm 060708CLC Kiến trúc máy tính

và hợp ngữ
Bắt đầu vào lúc Saturday, 8 April 2017, 1:12 PM

State Finished
Kết thúc lúc Saturday, 8 April 2017, 1:22 PM
Thời gian thực 10 phút 13 giây
hiện
Điểm 22,25/22,25
Điểm 10,00 out of 10,00 (100%)
Câu hỏi 1 Given 8bit floatingpoint binary format:

Đúng 1 (sign) + 3 (exponent) + 4 (mantissa)
Đạt điểm 1,00 Convert the 8bit floating point number 57 (in hex) to decimal.
trên 1,00
Đặt cờ
Answer: 5,75
Câu hỏi 2 A system programmer needs to divide 6247 by 300 (decimal). Instruct him to code in debug
Đúng (number must be in hex) and the result should be?
Đạt điểm 1,50

trên 1,50
Đặt cờ Step 1: MOV AX,E799
Step 2: CDW
Step 3: MOV BX,012C
Step 4: IDIV BX
Result:
AX = FFEC
DX = FF09
Câu hỏi 3 Write mask byte (in hex) to clear the lower 4 bit of a byte value with AND instruction.
Đúng

lOMoARcPSD|30860100
Đạt điểm 0,50

Answer: F0
trên 0,50
Đặt cờ
Câu hỏi 4 To isolate one or more bits in a byte value, use __________ instruction.
Đúng
Select one:
Đạt điểm 0,50
trên 0,50 OR
Đặt cờ NOT
AND
XOR
Câu hỏi 5 EAX now stored a 32bit IP address of a host. The network ID (netID) is 20 bit and can be
Đúng extracted from IP byte anding with a 32bit mask. Write correct instruction to extract netID from
EAX register.
Đạt điểm 0,25
trên 0,25 Note: Immediate value must be written in hex
Đặt cờ
Answer: and EAX,FFFFF000
Câu hỏi 6 The following sequence of instructions are executed. What is the correct values at watch point?
Đúng MOV AX, 67FE
Đạt điểm 1,00 MOV BX, AX
trên 1,00
MOV CL, BH
Đặt cờ
MOV CH, BL
watch point:
CX = FE67
BX = 67FE
Câu hỏi 7 The following sequence of instructions are executed. What is the correct value of flag bits at watch
Đúng point?
Đạt điểm 1,00 MOV EAX, 12AE

trên 1,00 SUB EAX, 12AF
Đặt cờ watch point:
sign flag set

lOMoARcPSD|30860100
Câu hỏi 8 Physical address of the stack pointer is 2DA82, stack segment located at 1DAE. Computer the
Đúng value of SP register?
Đạt điểm 1,00

trên 1,00
Answer: FFA2
Đặt cờ
Câu hỏi 9 Match the following hexadecimal numbers to octal

Đúng
Đạt điểm 1,00 E7 347

trên 1,00
Đặt cờ
6E 156
A9 251
Câu hỏi 10 Enter debug command to fill 256 bytes in data segment starting from 100 with value 0D
Đúng
Đạt điểm 1,00

Answer: f 100 1FF 0D
trên 1,00
Đặt cờ
Câu hỏi 11 Given 8bit floatingpoint binary format:

Đúng 1 (sign) + 3 (exponent) + 4 (mantissa)
Đạt điểm 1,00 Convert the 8bit floating point number E7 (in hex) to decimal.
trên 1,00
Đặt cờ
Answer: 11,5
Câu hỏi 12 Match the correct answer for binary operations on the left
Đúng
Đạt điểm 1,50 1111111 111 1111000

trên 1,50
Đặt cờ
1100111 111 1100000

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1010101 + 10101 1101010
1010110 101 1010001
1110011 + 11001 10001100
1111111 + 11111 10011110
Câu hỏi 13 Convert the following binary numbers to hexadecimal

Đúng
Đạt điểm 1,00 10101001 A9

trên 1,00
Đặt cờ
01101110 6E
11100101 E5
11100111 E7
Câu hỏi 14 The following sequence of instructions are executed. What is the correct value of CF and OF at
Đúng watch point?
Đạt điểm 1,00 MOV AX,140h

trên 1,00 MOV CX,8h
Đặt cờ MUL CX
watch point:
CF= reset
OF= reset
Câu hỏi 15 To test one bit in a byte value without destructing the byte, use __________ instruction.
Đúng
Select one:
Đạt điểm 0,50
trên 0,50 NOT
Đặt cờ AND
lOMoARcPSD|30860100
TEST
OR

Đúng 0AE8:0120 13 96 D0 E0 D0 E0 A2 1E 99 80 3E 20 99 00 75 24
Đạt điểm 1,00 Initially, AX=BX=CX=DX=0, SI=121
trên 1,00
What are value of CX,DX after execution of the following instructions?
Đặt cờ
MOV DX, [SI]
MOV CX, [SI+2]
DX = D096
CX = D0E0
Câu hỏi 17 Select correct match for register values at watch points:
Đúng MOV AX, 152D
Đạt điểm 1,00 ADD AX, 003F
trên 1,00
watch point #1:
Đặt cờ
ADD AH, 10
watch point #2:
......
watch point #1: AL = 6C
Câu hỏi 18 A memory location located in extra segment which now has value of 564F. This memory managed
Đúng by ES:SI registerpair. SI now points to 905F. Compute the physical address of this memory
location
Đạt điểm 1,00
trên 1,00
Đặt cờ Answer: 5F54F

lOMoARcPSD|30860100
Câu hỏi 19 Select correct match for AL and carry flag at watch point #1:
Đúng MOV BL, 8C
Đạt điểm 1,00 MOV AL, 7E
trên 1,00
ADD AL, BL
Đặt cờ
watch point #1:
......
Carry flag set
AL 0A
Câu hỏi 20 Convert the 32bit floating point number C4361000 (in hex) to decimal.
Đúng
Đạt điểm 1,00 Answer: 728,25

trên 1,00
Đặt cờ
Câu hỏi 21 Which of the following instructions are not legal addressing?
Đúng
Select one or more:
Đạt điểm 1,00
trên 1,00 MOV AX, [DI]
Đặt cờ MOV AX, [BX+SP]
MOV AX, [SP+1]
MOV CX, [SI]
Câu hỏi 22 Compute the physical address of stack top if stack pointer is FFAE and stack segment located at
Đúng 1DAE
Đạt điểm 1,00

trên 1,00
Answer: 2DA8E
Đặt cờ
Câu hỏi 23 Signextend number 1011 0101 (8bit binary) to 16bit

Đúng
Đạt điểm 0,50

Answer: 1111111110110101
trên 0,50
Đặt cờ

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Câu hỏi 24 The following sequence of instructions are executed. What is the correct value of AX, CX, DX at
Đúng watch point?
Đạt điểm 1,00 MOV AX,30

trên 1,00 MOV CX,FFFF
Đặt cờ MUL CX
watch point:
CX = FFFF
AX = FFD0
DX 002F
Finish review

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Ch¬ng 1. Giíi thiÖu chung
1.1 Tr×nh tù xö lý th«ng tin cña m¸y tÝnh ®iÖn tö lµ:

a. CPU -> §Üa cøng -> Mµn h×nh
b. NhËn th«ng tin -> Xö lý th«ng tin -> XuÊt th«ng tin
c. CPU -> Bµn phÝm -> Mµn h×nh
d. Mµn h×nh - > M¸y in -> §Üa mÒm
1.2. Çc chøc n¨ng c¬ b¶n cña m¸y tÝnh:

a. Lu tr÷ d÷ liÖu, Ch¹y ch¬ng tr×nh, Nèi ghÐp víi TBNV, Truy nhËp bé nhí.
b. Trao ®æi d÷ liÖu, §iÒu khiÓn, Thùc hiÖn lÖnh, Xö lý d÷ liÖu.
c. Lu tr÷ d÷ liÖu, Xö lý d÷ liÖu, Trao ®æi d÷ liÖu, §iÒu khiÓn.
d. §iÒu khiÓn, Lu tr÷ d÷ liÖu, Thùc hiÖn phÐp to¸n, KÕt nèi Internet.
1.3. Çc thµnh phÇn c¬ b¶n cña m¸y tÝnh:

a. RAM, CPU, æ ®Üa cøng, Bus liªn kÕt
b. HÖ thèng nhí, Bus liªn kÕt, ROM, Bµn phÝm
c. HÖ thèng nhí, Bé xö lý, Mµn h×nh, Chuét
d. HÖ thèng nhí, Bé xö lý, HÖ thèng vµo ra, Bus liªn kÕt
1.4. Bé xö lý gåm çc thµnh phÇn (kh«ng kÓ bus bªn trong):

a. Khèi ®iÒu khiÓn, Çc thanh ghi, Cæng vµo/ra
b. Khèi ®iÒn khiÓn, ALU, Çc thanh ghi
c. Çc thanh ghi, DAC, Khèi ®iÒu khiÓn
d. ALU, Çc thanh ghi, Cæng vµo/ra.
1.5. HÖ thèng nhí cña m¸y tÝnh bao gåm:

a. Cache, Bé nhí ngoµi
b. Bé nhí ngoµi, ROM
c. §Üa quang, Bé nhí trong
d. Bé nhí trong, Bé nhí ngoµi
1.6. HÖ thèng vµo/ra cña m¸y tÝnh kh«ng bao gåm ®ång thêi çc thiÕt bÞ sau:
a. §Üa tõ, Loa, §Üa CD-ROM
b. Mµn h×nh, RAM, M¸y in
c. CPU, Chuét, M¸y quÐt ¶nh
d. ROM, RAM, Çc thanh ghi
1.7. Trong m¸y tÝnh, cã çc lo¹i bus liªn kÕt hÖ thèng nh sau:
a. ChØ dÉn, Chøc n¨ng, §iÒu khiÓn
b. §iÒu khiÓn, D÷ liÖu, §Þa chØ
c. D÷ liÖu, Phô thuéc, §iÒu khiÓn
d. D÷ liÖu, §iÒu khiÓn, Phô trî
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1.8. Çc ho¹t ®éng cña m¸y tÝnh gåm:

a. Ng¾t, Gi¶i m· lÖnh, Vµo/ra
b. Xö lý sè liÖu, Ng¾t, Thùc hiÖn ch¬ng tr×nh
c. Thùc hiÖn ch¬ng tr×nh, ng¾t, vµo/ra
d. TÝnh to¸n kÕt qu¶, Lu tr÷ d÷ liÖu, vµo/ra
1.9. Bé ®Õm ch¬ng tr×nh cña m¸y tÝnh kh«ng ph¶i lµ:
a. Thanh ghi chøa ®Þa chØ lÖnh
b. Thanh ghi chøa lÖnh s¾p thùc hiÖn
c. Thanh ghi chøa ®Þa chØ lÖnh s¾p thùc hiÖn
d. Thanh ghi
1.10. Cã çc lo¹i ng¾t sau trong m¸y tÝnh:

a. Ng¾t cøng, ng¾t mÒm, ng¾t trung gian
b. Ng¾t ngo¹i lÖ, ng¾t cøng, ng¾t INTR
c. Ng¾t mÒm, ng¾t NMI, ng¾t cøng
d. Ng¾t cøng, ng¾t mÒm, ng¾t ngo¹i lÖ
1.11. Trong m¸y tÝnh, ng¾t NMI lµ:

a. Ng¾t ngo¹i lÖ kh«ng ch¾n ®îc
b. Ng¾t mÒm kh«ng ch¾n ®îc
c. Ng¾t cøng kh«ng ch¾n ®îc
d. Ng¾t mÒm ch¾n ®îc
1.12. Khi Bé xö lý ®ang thùc hiÖn ch¬ng tr×nh, nÕu cã ng¾t (kh«ng bÞ cÊm) göi ®Õn, th×
nã:
a. Thùc hiÖn xong ch¬ng tr×nh råi thùc hiÖn ng¾t
b. Tõ chèi ng¾t, kh«ng phôc vô
c. Phôc vô ng¾t ngay, sau ®ã thùc hiÖn ch¬ng tr×nh
d. Thùc hiÖn xong lÖnh hiÖn t¹i, råi phôc vô ng¾t, cuèi cïng quay l¹i thùc hiÖn tiÕp
ch¬ng tr×nh.
1.13. M¸y tÝnh Von Newmann lµ m¸y tÝnh:
a. ChØ cã 01 bé xö lý, thùc hiÖn çc lÖnh tuÇn tù
b. Cã thÓ thùc hiÖn nhiÒu lÖnh cïng mét lóc (song song)
c. Thùc hiÖn theo ch¬ng tr×nh n»m s½n bªn trong bé nhí
d. C¶ a vµ c
1.14. M¸y tÝnh ENIAC lµ m¸y tÝnh:

a. Do Bé gi¸o dôc Mü ®Æt hµng
b. Lµ m¸y tÝnh ra ®êi vµo nh÷ng n¨m 1970
c. Dïng vi m¹ch cì nhá vµ cì võa
d. Lµ m¸y tÝnh ®Çu tiªn trªn thÕ giíi
1.15. §èi víi çc tÝn hiÖu ®iÒu khiÓn, ph¸t biÓu nµo sau ®©y lµ sai:
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a. MEMR lµ tÝn hiÖu ®äc lÖnh (d÷ liÖu) tõ bé nhí

b. MEMW lµ tÝn hiÖu ®äc lÖnh tõ bé nhí
c. IOR lµ tÝn hiÖu ®äc d÷ liÖu tõ cæng vµo ra
d. IOW lµ tÝn hiÖu ghi d÷ liÖu ra cæng vµo ra
1.16. Ph¸t biÓu nµo sau ®©y lµ ®óng:

a. INTR lµ tÝn hiÖu cøng ch¾n ®îc
b. INTR lµ tÝn hiÖu ng¾t mÒm
c. INTR lµ tÝn hiÖu ng¾t cøng kh«ng ch¾n ®îc
d. INTR lµ mét tÝn hiÖu ng¾t ngo¹i lÖ
1.17. Ph¸t biÓu nµo sau ®©y lµ sai:

a. INTA lµ tÝn hiÖu CPU tr¶ lêi ®ång ý chÊp nhËn ng¾t
b. INTA lµ tÝn hiÖu göi tõ bé xö lý ra ngoµi
c. INTA lµ tÝn hiÖu tõ bªn ngoµi yªu cÇu ng¾t CPU
d. C¶ a vµ b ®Òu ®óng

a. HOLD lµ tÝn hiÖu CPU tr¶ lêi ra bªn ngoµi
b. HOLD kh«ng ph¶i lµ tÝn hiÖu ®iÒu khiÓn
c. HOLD lµ tÝn hiÖu ®iÒu khiÓn xin ng¾t
d. HOLD lµ tÝn hiÖu tõ bªn ngoµi xin CPU nhêng bus

a. HLDA lµ tÝn hiÖu CPU chÊp nhËn nhêng bus
b. HLDA lµ tÝn hiÖu CPU kh«ng chÊp nhËn nhêng bus
c. HLDA lµ tÝn hiÖu yªu cÇu CPU nhêng bus
d. HLDA lµ mét ng¾t mÒm
1.20. Cho ®Õn nay, m¸y tÝnh ®· ph¸t triÓn qua:
a. 5 thÕ hÖ
b. 4 thÕ hÖ
c. 3 thÕ hÖ
d. 2 thÕ hÖ
1.21. Trong çc giai ®o¹n ph¸t triÓn cña m¸y tÝnh, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. ThÕ hÖ thø nhÊt dïng transistor
b. ThÕ hÖ thø ba dïng transistor
c. ThÕ hÖ thø nhÊt dïng ®Ìn ®iÖn tö ch©n kh«ng
d. ThÕ hÖ thø t dïng vi m¹ch SSI vµ MSI
1.22. Trong çc giai ®o¹n ph¸t triÓn cña m¸y tÝnh, ph¸t biÓu nµo sau ®©y lµ sai:
a. ThÕ hÖ thø hai dïng transistor
b. ThÕ hÖ thø ba dïng transistor
c. ThÕ hÖ thø nhÊt dïng ®Ìn ®iÖn tö ch©n kh«ng
d. ThÕ hÖ thø t dïng vi m¹nh
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1.23. Theo luËt Moore, sè lîng transistor sÏ t¨ng gÊp ®«i sau mçi:
a. 22 th¸ng b. 20 th¸ng
c. 18 th¸ng d. 16 th¸ng
1.24. TÝn hiÖu ®iÒu khiÓn MEMR lµ tÝn hiÖu:

a. §äc lÖnh/d÷ liÖu tõ ng¨n nhí
b. Ghi lÖnh/d÷ liÖu ra ng¨n nhí
c. §äc lÖnh tõ TBNV
d. Ghi lÖnh ra TBNV
1.25. TÝn hiÖu ®iÒu khiÓn MEMW lµ tÝn hiÖu:

c. Ghi lÖnh ra ng¨n nhí
d. Ghi d÷ liÖu ra ng¨n nhí
1.26. TÝn hiÖu ®iÒu khiÓn IOR lµ tÝn hiÖu:

c. §äc d÷ liÖu tõ TBNV
d. Ghi d÷ liÖu ra TBNV
1.27. TÝn hiÖu ®iÒu khiÓn IOW lµ tÝn hiÖu:
a. §äc lÖnh/d÷ liÖu tõ TBNV
b. Ghi lÖnh/d÷ liÖu ra TBNV
c. §äc d÷ liÖu tõ TBNV
d. Ghi d÷ liÖu ra TBNV
1.28. TÝn hiÖu ®iÒu khiÓn INTR lµ tÝn hiÖu:

a. Tõ bªn ngoµi göi ®Õn CPU xin ng¾t
b. Tõ CPU göi ra ngoµi xin ng¾t
c. Tõ bé nhí chÝnh göi ®Õn CPU xin ng¾t
d. Tõ CPU göi ®Õn bé nhí chÝnh xin ng¾t
1.29. TÝn hiÖu ®iÒu khiÓn INTA lµ tÝn hiÖu:

a. CPU tr¶ lêi kh«ng chÊp nhËn ng¾t
b. CPU tr¶ lêi chÊp nhËn ng¾t
c. Tõ bªn ngoµi göi ®Õn CPU xin ng¾t
d. Ng¾t ngo¹i lÖ
1.30. TÝn hiÖu ®iÒu khiÓn HOLD lµ tÝn hiÖu:

a. CPU tr¶ lêi chÊp nhËn ng¾t
b. CPU göi ra ngoµi xin dïng bus
c. Tõ bªn ngoµi göi ®Õn CPU xin dïng bus
d. Tõ bªn ngoµi göi ®Õn CPU tr¶ lêi kh«ng dïng bus
1.31. TÝn hiÖu ®iÒu khiÓn HLDA lµ tÝn hiÖu:

a. CPU tr¶ lêi kh«ng chÊp nhËn ng¾t
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b. CPU tr¶ lêi chÊp nhËn ng¾t

c. Tõ bªn ngoµi göi ®Õn CPU xin ng¾t
d. CPU tr¶ lêi ®ång ý nhêng bus
1.32. Víi tÝn hiÖu ®iÒu khiÓn MEMR, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu do CPU ph¸t ra
b. Lµ tÝn hiÖu ®iÒu khiÓn truy nhËp bé nhí
c. Lµ tÝn hiÖu ®iÒu khiÓn ghi
d. Lµ tÝn hiÖu ®iÒu khiÓn ®äc
1.33. Víi tÝn hiÖu ®iÒu khiÓn MEMW, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu ®îc ph¸t ra bëi CPU
b. Lµ tÝn hiÖu do bªn ngoµi göi ®Õn CPU
c. Kh«ng ph¶i lµ tÝn hiÖu truy nhËp cæng vµo/ra
d. Lµ tÝn hiÖu ®iÒu khiÓn ghi
1.34. Víi tÝn hiÖu ®iÒu khiÓn IOR, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu ®iÒu khiÓn truy nhËp cæng vµo/ra
b. Lµ tÝn hiÖu ®iÒu khiÓn do CPU ph¸t ra
c. Lµ tÝn hiÖu ®iÒu khiÓn ®äc
d. Lµ tÝn hiÖu ®iÒu khiÓn truy nhËp CPU
1.35. Víi tÝn hiÖu ®iÒu khiÓn IOW, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu tõ bªn ngoµi xin ng¾t cæng vµo/ra
c. Lµ tÝn hiÖu ®iÒu khiÓn ®îc göi ®Õn cæng vµo/ra
d. Lµ tÝn hiÖu ®iÒu khiÓn ghi d÷ liÖu
1.36. Víi tÝn hiÖu ®iÒu khiÓn INTR, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu ®iÒu khiÓn tõ bªn ngoµi göi ®Õn CPU
c. Lµ tÝn hiÖu yªu cÇu ng¾t
d. Lµ tÝn hiÖu ng¾t ch¾n ®îc
1.37. Víi tÝn hiÖu ®iÒu khiÓn INTA, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu chÊp nhËn ng¾t
c. Lµ tÝn hiÖu ®iÒu khiÓn ghi cæng vµo/ra
d. Lµ tÝn hiÖu ®iÒu khiÓn xö lý ng¾t
1.38. Víi tÝn hiÖu ®iÒu khiÓn NMI, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu tõ bªn ngoµi göi ®Õn CPU
b. Lµ tÝn hiÖu ng¾t ch¾n ®îc
c. Lµ tÝn hiÖu ng¾t kh«ng ch¾n ®îc
d. CPU kh«ng thÓ tõ chèi tÝn hiÖu nµy
1.39. Víi tÝn hiÖu ®iÒu khiÓn HOLD, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu do CPU ph¸t ra
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b. Lµ tÝn hiÖu tõ bªn ngoµi göi ®Õn CPU

c. Lµ tÝn hiÖu xin nhêng bus
d. Kh«ng ph¶i lµ tÝn hiÖu ®äc cæng vµo/ra
1.40. Víi tÝn hiÖu ®iÒu khiÓn HLDA, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ tÝn hiÖu tr¶ lêi cña CPU
b. Lµ tÝn hiÖu ®ång ý nhêng bus
c. Lµ tÝn hiÖu tõ bªn ngoµi göi ®Õn CPU xin ng¾t
d. Kh«ng ph¶i lµ tÝn hiÖu xin ng¾t tõ bªn ngoµi
1.41. Theo çch ph©n lo¹i truyÒn thèng, cã çc lo¹i m¸y tÝnh sau ®©y:
a. Bé vi ®iÒu khiÓn, m¸y tÝnh ç nh©n, m¸y tÝnh lín, siªu m¸y tÝnh, m¸y vi tÝnh
b. M¸y tÝnh x¸ch tay, m¸y tÝnh lín, m¸y tÝnh ®Ó bµn, m¸y vi tÝnh, siªu m¸y tÝnh
c. M¸y tÝnh x¸ch tay, m¸y tÝnh mini, m¸y tÝnh lín, siªu m¸y tÝnh, m¸y chñ
d. Bé vi ®iÒu khiÓn, m¸y vi tÝnh, m¸y tÝnh mini, m¸y tÝnh lín, siªu m¸y tÝnh
1.42. Theo çch ph©n lo¹i hiÖn ®¹i, cã çc lo¹i m¸y tÝnh sau ®©y:
a. M¸y tÝnh ®Ó bµn, m¸y tÝnh lín, m¸y tÝnh nhóng
b. M¸y tÝnh ®Ó bµn, m¸y chñ, m¸y tÝnh nhóng
c. M¸y chñ, m¸y tÝnh mini, m¸y tÝnh lín
d. M¸y tÝnh mini, m¸y tÝnh nhóng, siªu m¸y tÝnh
Ch¬ng 2. BiÔu diÔn d÷ liÖu vµ sè häc m¸y tÝnh
2.1. §èi víi sè nguyªn kh«ng dÊu, 8 bit, gi¸ trÞ biÓu diÔn sè 261 lµ:
a. 1001 0001 b. 1010
1011
c. 1000 0111 d. Kh«ng
biÓu diÔn ®îc
2.2. §èi víi sè nguyªn kh«ng dÊu, 8 bit, gi¸ trÞ biÓu diÔn sè 132 lµ:
a. 1001 0001 b. 1000
0100
c. 1000 0111 d. Kh«ng
biÓu diÔn ®îc
2.3. §èi víi sè nguyªn cã dÊu, 8 bit, gi¸ trÞ biÓu diÔn sè 129 lµ:
a. 1001 0001 b. 1010
1011
c. 1000 0111 d. Kh«ng
biÓu diÔn ®îc
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2.4. §èi víi sè nguyªn cã dÊu, 8 bit, gi¸ trÞ biÓu diÔn sè 124 lµ:
a. 0111 1100 b. 0101
1011
c. 0100 0111 d. Kh«ng
biÓu diÔn ®îc
2.5. D¶i biÔu diÔn sè nguyªn kh«ng dÊu, n bit trong m¸y tÝnh lµ:
a. 0 -> 2.n b. 0 -> 2.n -
1
c. 0 -> 2n - 1 d. 0 -> 2n
2.6. D¶i biÔu diÔn sè nguyªn cã dÊu, n bit trong m¸y tÝnh lµ:
a. - 2(n - 1) -> 2 (n - 1) b. - 2.n - 1 -> 2.n +1
n-1 n-1
c. - 2 - 1-> 2 - 1 d. - 2n - 1 -> 2n -1 - 1
2.7. S¬ ®å díi ®©y lµ thuËt to¸n thùc hiÖn:
Start
C:=0; A:=0; Bé ®Õm:=n

M chøa sè bÞ nh©n
Q chøa sè nh©n
§óng
Q0 = 1?
Sai
C,A:=A+M
DÞch ph¶i C, A, Q
Dec(Bé ®Õm)
Sai §óng
Bé ®Õm = 0? End
a. PhÐp chia sè nguyªn kh«ng dÊu

b. PhÐp nh©n sè nguyªn kh«ng dÊu
c. PhÐp nh©n sè nguyªn cã dÊu
d. PhÐp chia sè nguyªn cã d©u
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Start
A:=0; Q-1:=0; Bé ®Õm:=n

M chøa sè bÞ nh©n
Q chøa sè nh©n
= 10 = 01
Q0, Q-1
= 11
A := A - M = 00 A := A + M
DÞch ph¶i A, Q, Q-1

Dec(Bé ®Õm)
Lu ý: An-1 ®îc t¸i t¹o
Sai §óng
Bé ®Õm = 0? End
a. PhÐp nh©n sè nguyªn kh«ng dÊu

b. PhÐp nh©n sè nguyªn cã dÊu
c. PhÐp chia sè nguyªn kh«ng dÊu
d. PhÐp chia sè nguyªn cã dÊu
2.9. §èi víi sè nguyªn cã dÊu, 8 bit, dïng ph¬ng ph¸p “DÊu vµ ®é lín”, gi¸ trÞ
biÓu diÔn sè - 60 lµ:
a. 0000 1101 b. 0000 1010
c. 1011 1100 d.
1100 1101
2.10. §èi víi sè nguyªn cã dÊu, 8 bit, dïng ph¬ng ph¸p “DÊu vµ ®é lín”, gi¸ trÞ
biÓu diÔn sè - 256 lµ:
a. 1100 1110 b.
1010 1110
c. 1100 1100 d.
Kh«ng thÓ biÓu diÔn
2.11. §èi víi sè nguyªn cã dÊu, 8 bit, dïng ph¬ng ph¸p “M· bï 2”, gi¸ trÞ biÓu
diÔn sè 101 lµ:
a. 0110 0101 b.
0000 1100
c. 0000 1110 d.
0100 1010
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2.12. §èi víi sè nguyªn cã dÊu, 8 bit, dïng ph¬ng ph¸p “M· bï 2”, gi¸ trÞ biÓu
diÔn sè - 29 lµ:
a. 1000 0000 b.
1110 0011
c. 1111 0000 d.
1000 1111
2.13. Cã biÓu diÔn “1110 0010” ®èi víi sè nguyªn cã dÊu, 8 bit, dïng ph¬ng ph¸p
“DÊu vµ ®é lín”, gi¸ trÞ cña nã lµ:
a. 136
b. 30
c. - 30
d. - 136
2.14. Cã biÓu diÔn “1100 1000” ®èi víi sè nguyªn cã dÊu, 8 bit, dïng ph¬ng ph¸p
“M· bï 2”, gi¸ trÞ cña nã lµ:
a. Kh«ng tån t¹i b. - 56
c. 56
d. 200
2.15. B¶ng díi ®©y m« t¶ qu¸ tr×nh thùc hiÖnphÐp tÝnh:
A Q Q-1 M
0000 0011 0 1001 Gi¸ trÞ khëi t¹o
0111 0011 0 1001 A A - M
0011 1001 1 1001 SHR A, Q, Q-1
0001 1100 1 1001 SHR A, Q, Q-1
1010 1100 1 1001 A A + M
1101 0110 0 1001 SHR A, Q, Q-1
1110 1011 1 1001 SHR A, Q, Q-1
a. 3  9 = 27 c. (-7)  3 = -21
b. 15  9 = 135 d. 5  27 = 135
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2.16. Cã biÔu diÔn “0000 0000 0010 0101” (dïng m· bï 2, cã dÊu), gi¸ trÞ cña
chóng lµ:
a. -37 b. 37
c. - 21 d. 21
2.17. B¶ng díi ®©y m« t¶ qu¸ tr×nh thùc hiÖn phÐp tÝnh:
A Q M = 0011
1111 0101 Khëi t¹o gi¸ trÞ (sè chia vµ bÞ chia kh¸c dÊu)
1110 1010 DÞch tr¸i 1 bit A, Q
0001 M kh¸c dÊu A  A := A + M
1110 1010 A kh¸c dÊu sau khi céng  Q0 = 0 vµ phôc håi A
0000 M kh¸c dÊu A  A := A + M
1101 0100 A kh¸c dÊu sau khi céng  Q0 = 0 vµ phôc håi A
1101 M kh¸c dÊu A  A := A + M
1101 1001 A cïng dÊu sau khi céng  Q0 = 1
1110 M kh¸c dÊu A  A := A + M
1110 0011 A cïng dÊu sau khi céng  Q0=1.
a. 245 : 3 = 81, d 2 b. 59 : 15 = 3, d 14
c. 11 : 3 = 3, d 2 d. (-11) : 3 = (-3), d (-2)
Bé ®Õm := n
Start M chøa sè chia (n bit)
A,Q chøa sè bÞ chia (2n bit)
DÞch tr¸i A,Q ®i 1 bit

B := A
§óng Sai
M, A cïng dÊu?
A := A - M A := A + M
§óng A, B cïng dÊu Sai

hoÆc A = Q = 0?
Q0 = 1 Q0 = 0; A := B
Dec(Bé ®Õm)
Sai §óng
Bé ®Õm = 0? End
a. PhÐp nh©n sè nguyªn kh«ng dÊu
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b. PhÐp nh©n sè nguyªn cã dÊu

c. PhÐp chia sè nguyªn kh«ng dÊu
d. PhÐp chia sè nguyªn cã dÊu
2.19. B¶ng díi ®©y m« t¶ qu¸ tr×nh thùc hiÖn phÐp tÝnh:
C A Q M
0 0000 1011 1100 Gi¸ trÞ khëi t¹o
0 1100 1011 1100 C, A A+M
0 0110 0101 1100 SHR C, A, Q
1 0010 0101 1100 C, A A+M
0 1001 0010 1100 SHR C, A, Q
0 0100 1001 1100 SHR C, A, Q
1 0000 1001 1100 C, A A+M
0 1000 0100 1100 SHR C, A, Q
a. 4  19 = 76 c. -4  31 = -124
b. 11  12 = 132 d. 6  22 = 132
2.20. §èi víi çc sè 8 bit, kh«ng dÊu. H·y cho biÕt kÕt qu¶ khi thùc hiÖn phÐp
céng: 0100 0111 + 0101 1111:
a. 146 b.
166
c. 176 d.
156
2.21. §èi víi çc sè kh«ng dÊu, phÐp céng trªn m¸y tÝnh cho kÕt qu¶ sai khi:
a. Céng hai sè d¬ng, cho kÕt qu¶ ©m
b. Céng hai sè ©m, cho kÕt qu¶ d¬ng
c. Cã nhí ra khái bit cao nhÊt
d. C¶ a vµ b
2.22. §èi víi çc sè cã dÊu, phÐp céng trªn m¸y tÝnh cho kÕt qu¶ sai khi:
a. Céng hai sè d¬ng, cho kÕt qu¶ ©m
b. Céng hai sè ©m, cho kÕt qu¶ d¬ng
c. Cã nhí ra khái bit cao nhÊt
d. C¶ a vµ b
2.23. §èi víi sè cã dÊu, ph¸t biÓu nµo sau ®©y lµ sai:
a. Céng hai sè cïng dÊu, tæng lu«n ®óng
b. Céng hai sè kh¸c dÊu, tæng lu«n ®óng
c. Céng hai sè cïng dÊu, nÕu tæng cã cïng dÊu th× tæng ®óng
d. Céng hai sè cïng dÊu, nÕu tæng kh¸c dÊu th× tæng sai
2.24. §èi víi sè kh«ng dÊu, ph¸t biÓu nµo sau ®©y lµ ®óng:
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a. Khi thùc hiÖn phÐp céng, tæng lu«n ®óng

b. Khi céng hai sè cïng dÊu, cho tæng kh¸c dÊu
c. Khi céng cã nhí ra khái bit cao nhÊt, tæng kh«ng sai
d. Khi céng kh«ng nhí ra khái bit cao nhÊt, tæng ®óng
2.25. §èi víi sè kh«ng dÊu, 8 bit, xÐt phÐp céng: 240 + 27. Ph¸t biÓu nµo sau ®©y
lµ ®óng:
a. Tæng lµ 267
b. Tæng lµ 11
c. Kh«ng cho kÕt qu¶, v× trµn sè
d. C¶ a vµ b ®Òu sai
2.26. §èi víi sè cã dÊu, 8 bit, xÐt phÐp céng: (-39) + (-42). Ph¸t biÓu nµo sau ®©y
lµ ®óng:
a. Kh«ng cho kÕt qu¶, v× trµn sè
b. Kh«ng cho kÕt qu¶, v× cã nhí ra khái bit cao nhÊt
c. Tæng lµ -81
d. Tæng lµ 81
2.27. §èi víi sè cã dÊu, 8 bit, xÐt phÐp céng: (-73) + (-86). Ph¸t biÓu nµo sau ®©y
lµ ®óng:
b. Kh«ng cho kÕt qu¶, v× cã nhí ra khái bit cao nhÊt
c. Tæng lµ 97
d. Tæng lµ -159
2.28. §èi víi sè cã dÊu, 8 bit, xÐt phÐp céng: 91 + 63. Ph¸t biÓu nµo sau ®©y lµ
®óng:
b. KÕt qu¶ sai, v× cã nhí ra khái bit cao nhÊt
c. Tæng lµ 154
d. Tæng lµ -102
2.29. Mét sè thùc X bÊt kú, cã thÓ biÓu diÔn díi d¹ng tæng qu¸t nh sau:
a. X = (-1).S . M . RE
b. X = (-1)S . M . R.E
c. X = (-1)S . M . RE
d. X = (-1)S . M . R.E
2.30. Cho hai sè thùc X1 vµ X2 biÓu diÔn díi d¹ng tæng qu¸t. BiÓu diÔn nµo sau
®©y lµ ®óng ®èi víi phÐp nh©n (X1 . X2):
a. X1 . X2 = (-1)S1. S2 . (M1.M2) . RE1 . E2
b. X1 . X2 = (-1)S1 S2 . (M1.M2) . RE1 . E2
c. X1 . X2 = (-1)S1+ S2 . (M1.M2) . RE1 + E2
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d. X1 . X2 = (-1)S1 S2 . (M1.M2) . RE1 + E2
2.31. . Cho hai sè thùc X1 vµ X2 biÓu diÔn díi d¹ng tæng qu¸t. BiÓu diÔn nµo sau
®©y lµ ®óng ®èi víi phÐp chia (X1 / X2):
a. X1 . X2 = (-1)S1/ S2 . (M1/M2) . RE1 - E2
b. X1 . X2 = (-1)S1 S2 . (M1/M2) . RE1 - E2
c. X1 . X2 = (-1)S1 S2 . (M1/M2) . RE1 + E2
d. X1 . X2 = (-1)S1/ S2 . (M1/M2) . RE1 + E2
2.32. §èi víi chuÈn IEEE 754/85 vÒ biÓu diÔn sè thùc, ph¸t biÓu nµo sau ®©y lµ
sai:
a. Cã tÊt c¶ 3 d¹ng biÓu diÔn
b. Çc d¹ng biÓu diÔn ®Òu dïng c¬ sè 2
c. Çc d¹ng biÓu diÔn ®Òu dïng c¬ sè 10
d. Cã mét d¹ng dïng 64 bit ®Ó biÓu diÔn
2.33. §èi víi chuÈn IEEE 754/85 vÒ biÓu diÔn sè thùc, cã çc d¹ng sau:
a. Single, Double, Real
b. Single, Double-Extended, Comp
c. Single, Double-Extended, Double
d. Double-Extended, Comp, Double
2.34. Trong chuÈn IEEE 754/85, d¹ng ®¬n (single) cã ®é dµi:
a. 16 bit b.
128 bit
c. 32 bit d. 64
bit
2.35. Trong chuÈn IEEE 754/85, d¹ng kÐp (double) cã ®é dµi:

a. 64 bit b. 80
bit
c. 32 bit d.
128 bit
2.36. Trong chuÈn IEEE 754/85, d¹ng kÐp më réng (double-extended) cã ®é dµi:
a. 128 bit b. 80
bit
c. 32 bit d. 64
bit
2.37. §èi víi d¹ng ®¬n (trong chuÈn IEEE 754/85), çc bit dµnh cho çc trêng (S
+ E + M) lµ:
a. 1 + 9 + 22 b. 1 + 8 +
23
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c. 1 + 10 + 21 d. 1 + 11 +
20
2.38. §èi víi d¹ng kÐp (trong chuÈn IEEE 754/85), çc bit dµnh cho çc trêng (S
+ E + M) lµ:
a. 1 + 10 + 52 b. 1 + 11 +
64
c. 1 + 11 + 52 d. 1 + 15 +
48
2.39. §èi víi d¹ng kÐp më réng (trong chuÈn IEEE 754/85), çc bit dµnh cho çc
trêng (S + E + M) lµ:
a. 1 + 15 + 64 b. 1 + 17 +
62
c. 1 + 10 + 64 d. 1 + 14 +
65
2.40. D¹ng biÓu diÔn IEEE 754/85 cña sè thùc 73,625 lµ:
a. 42 39 40 00 H b. 42 93 40 00 H
c. 24 93 40 00 H d. 42 39 04 00 H
2.41. D¹ng biÓu diÔn IEEE 754/85 cña sè thùc - 53,125 lµ:
a. 2C E0 A0 00 H b. C2 00 A0 00 H
c. C2 54 80 00H d. C2 00 80 00 H
2.42. D¹ng biÓu diÔn IEEE 754/85 cña sè thùc 101,25 lµ:
a. 42 CA 80 00 H b. 42 CA 00 00 H
c. 24 AC 00 00 H d. 24 00 80 00 H
2.43. D¹ng biÓu diÔn IEEE 754/85 cña sè thùc - 119,5 lµ:
a. 2C 00 00 00 H b. 2C EF 00 00 H
c. C2 E0 00 00 H d. C2 EF 00 00 H
2.44. Cho biÓu diÔn díi d¹ng IEEE 754/85 nh sau: C2 82 80 00 H. Gi¸ trÞ thËp
ph©n cña nã lµ:
a. - 65,25 b. - 56,25
c. - 65,52 d. - 56,52
2.45. Cho biÓu diÔn díi d¹ng IEEE 754/85 nh sau: C2 BF 00 00 H. Gi¸ trÞ thËp
ph©n cña nã lµ:
a.- 95,25 b. - 95,5
c. - 59,5 d. - 59,25
2.46. Cho biÓu diÔn díi d¹ng IEEE 754/85 nh sau: 42 15 00 00 H. Gi¸ trÞ thËp
ph©n cña nã lµ:
a. 37,52 b. 73,25
c. 37,25 d. 73,52
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2.47. Cho biÓu diÔn díi d¹ng IEEE 754/85 nh sau: 42 22 80 00 H. Gi¸ trÞ thËp
ph©n cña nã lµ:
a. - 40,25 b. 40,25
c. - 40,625 d. 40,625
2.48. Víi bé m· Unicode ®Ó m· ho¸ ký tù, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ bé m· 16 bit
b. Lµ bé m· ®a ng«n ng÷
c. ChØ m· ho¸ ®îc 256 ký tù
d. Cã hç trî çc ký tù tiÕng ViÖt
2.49. Víi bé m· ASCII ®Ó m· ho¸ ký tù, ph¸t biÓu nµo sau ®©y lµ sai:
a. Do ANSI thiÕt kÕ
b. Lµ bé m· 8 bit
c. Cã chøa çc ký tù ®iÒu khiÓn truyÒn tin
d. Kh«ng hç trî çc ký tù ®iÒu khiÓn m¸y in
2.50. Víi bé m· ASCII, ph¸t biÓu nµo sau ®©y lµ sai:

a. Chøa çc ký tù ®iÒu khiÓn mµn h×nh
b. M· cña çc ký tù “&”, “%”, “@”, “#” thuéc phÇn m· më réng
c. M· 30 H -> 39 H lµ m· cña çc ch÷ sè
d. Cã chøa çc ký tù kÎ khung
2.51. Theo chuÈn IEEE 754/85, sè thùc X biÓu diÔn d¹ng ®¬n (single) lµ:
a. X = (-1).S . 1,M . RE
b. X = (-1)S . 1,M . R.(E - 127)
c. X = (-1)S . 1,M . RE - 127
d. X = (-1)S . 1,M. ER - 127
2.52. Theo chuÈn IEEE 754/85, sè thùc X biÓu diÔn d¹ng kÐp (double) lµ:
a. X = (-1).S . 1,M . RE
b. X = (-1)S . 1,M . R.(E - 1023)
c. X = (-1)S . 1,M. ER - 1023
d. X = (-1)S . 1,M . RE - 1023
2.53. Theo chuÈn IEEE 754/85, sè thùc X biÓu diÔn d¹ng kÐp më réng (double-
extended) lµ:
a. X = (-1)S . 1,M . RE - 16383
b. X = (-1).S . 1,M . RE
c. X = (-1)S . 1,M . R.(E - 16383)
d. X = (-1)S . 1,M. ER - 16383
2.54. D¹ng biÓu diÔn IEEE 754/85 cña sè thùc 31/64 lµ:
a. E3 F8 00 00 H b. 3E F8 00 00 H
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c. 3E 8F 00 00 H d. E3 8F 00 00 H
2.55. D¹ng biÓu diÔn IEEE 754/85 cña sè thùc - 79/32 lµ:
a. C0 1E 00 00 H b. 0C 1E 00 00 H
c. C0 E1 00 00 H d. 0C E1 00 00 H
2.56. Cho sè thùc 81,25. Gi¸ trÞ cña nã ë hÖ nhÞ ph©n lµ:
a. 100101,10 b.
1010001,01
c. 100011,101 d.
100010,011
2.57. Cho sè thùc 99,3125. Gi¸ trÞ cña nã ë hÖ nhÞ ph©n lµ:
a. 111011,1010 b.
111011,0011
c. 111010,0101 d. 1100011,0101
2.58. Cho sè thùc 51/32. Gi¸ trÞ cña nã ë hÖ nhÞ ph©n lµ:
a. 1,01011 b. 1,
01110
c. 1,10011 d. 1,00111
2.59. Cho sè thùc 33/128. Gi¸ trÞ cña nã ë hÖ nhÞ ph©n lµ:
a. 0,0100001 b.
0,1010101
c. 0,1001100 d.
0,0100011
Ch¬ng 3. Bé xö lý
3.1. Ph¸t biÓu nµo díi ®©y lµ sai:

a. Bé xö lý ®iÒu khiÓn ho¹t ®éng cña m¸y tÝnh
b. Bé xö lý ho¹t ®éng theo ch¬ng tr×nh n»m s½n trong bé nhí
c. Bé xö lý ®îc cÊu t¹o bëi hai thµnh phÇn
d. Bé xö lý ®îc cÊu t¹o bëi ba thµnh phÇn
3.2. §Ó thùc hiÖn 1 lÖnh, bé xö lý ph¶i tr¶i qua:

a. 8 c«ng ®o¹n b. 7 c«ng ®o¹n
c. 6 c«ng ®o¹n d. 5 c«ng ®o¹n
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3.3. XÐt çc c«ng ®o¹n cña bé xö lý, thø tù nµo lµ ®óng:
a. Gi¶i m· lÖnh -> nhËn d÷ liÖu -> xö lý d÷ liÖu -> ghi d÷ liÖu -> nhËn
lÖnh
b. NhËn lÖnh -> gi¶i m· lÖnh -> nhËn d÷ liÖu -> xö lý d÷ liÖu -> ghi d÷
liÖu
c. NhËn lÖnh -> nhËn d÷ liÖu -> gi¶i m· lÖnh -> xö lý d÷ liÖu -> ghi d÷
liÖu
d. NhËn d÷ liÖu -> xö lý d÷ liÖu -> nhËn lÖnh -> gi¶i m· lÖnh -> ghi d÷
liÖu
3.4. Víi c«ng ®o¹n nhËn lÖnh cña CPU, thø tù thùc hiÖn lµ:
a. Bé ®Õm ch¬ng tr×nh -> Bé nhí -> thanh ghi lÖnh
b. Bé nhí -> Bé ®Õm ch¬ng tr×nh -> thanh ghi lÖnh
c. Bé nhí -> thanh ghi lÖnh -> bé ®Õm ch¬ng tr×nh
d. Bé ®Õm ch¬ng tr×nh -> thanh ghi lÖnh -> bé nhí
3.5. Víi c«ng ®o¹n gi¶i m· lÖnh cña CPU, thø tù thùc hiÖn lµ:
a. Thanh ghi lÖnh -> gi¶i m· -> khèi ®iÒu khiÓn -> tÝn hiÖu ®iÒu khiÓn
b. Thanh ghi lÖnh -> khèi ®iÒu khiÓn -> tÝn hiÖu ®iÒu khiÓn -> gi¶i m·
c. Khèi ®iÒu khiÓn -> thanh ghi lÖnh -> gi¶i m· -> tÝn hiÖu ®iÒu khiÓn
d. Thanh ghi lÖnh -> khèi ®iÒu khiÓn -> gi¶i m· -> tÝn hiÖu ®iÒu khiÓn
3.6. Víi c«ng ®o¹n nhËn d÷ liÖu cña CPU, thø tù thùc hiÖn lµ:
a. §Þa chØ -> tËp thanh ghi -> ng¨n nhí
b. §Þa chØ -> ng¨n nhí -> tËp thanh ghi
c. TËp thanh ghi -> ®Þa chØ -> ng¨n nhí
d. Ng¨n nhí -> tËp thanh ghi -> ®Þa chØ
3.7. Víi c«ng ®o¹n xö lý d÷ liÖu cña CPU, thø tù thùc hiÖn lµ:
a. Thùc hiÖn phÐp to¸n -> ALU -> thanh ghi d÷ liÖu
b. Thùc hiÖn phÐp to¸n -> thanh ghi d÷ liÖu -> ALU
c. ALU -> thùc hiÖn phÐp to¸n -> thanh ghi d÷ liÖu
d. ALU -> thanh ghi d÷ liÖu -> thùc hiÖn phÐp to¸n
3.8. Víi c«ng ®o¹n ghi d÷ liÖu cña CPU, thø tù thùc hiÖn lµ:
a. §Þa chØ -> tËp thanh ghi -> ng¨n nhí
b. §Þa chØ -> ng¨n nhí -> tËp thanh ghi
c. TËp thanh ghi -> ®Þa chØ -> ng¨n nhí
d. TËp thanh ghi -> ng¨n nhí -> ®Þa chØ
3.9. Bé xö lý nhËn lÖnh t¹i:

a. Bé nhí hoÆc thiÕt bÞ ngo¹i vi
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b. Bé nhí
c. ThiÕt bÞ ngo¹i vi
d. CPU
3.10. Bé xö lý nhËn d÷ liÖu t¹i:

a. Bé nhí hoÆc thiÕt bÞ ngo¹i vi
b. Bé nhí
c. ThiÕt bÞ ngo¹i vi
d. CPU
3.11. §èi víi nhiÖm vô cña khèi ®iÒu khiÓn (trong CPU), ph¸t biÓu nµo sau
®©y lµ sai:
a. §iÒu khiÓn nhËn lÖnh tiÕp theo tõ bé nhí, ®a vµo thanh ghi lÖnh
b. T¨ng néi dung cña PC ®Ó trá vµo lÖnh tiÕp theo
c. VËn chuyÓn lÖnh tõ thanh ghi ra bé nhí
d. Ph¸t ra çc tÝn hiÖu ®iÒu khiÓn thùc hiÖn lÖnh
3.12. §èi víi khèi ®iÒu khiÓn (trong CPU), ph¸t biÓu nµo sau ®©y lµ sai:
a. §iÒu khiÓn çc tÝn hiÖu bªn trong vµ bªn ngoµi bé xö lý
b. §iÒu khiÓn çc thanh ghi vµ ALU
c. §iÒu khiÓn bé nhí vµ modul vµo ra
d. ChØ ®iÒu khiÓn çc thanh ghi vµ ALU
3.13. §èi víi khèi ALU (trong CPU), ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Thùc hiÖn çc phÐp to¸n sè häc
b. Thùc hiÖn çc phÐp to¸n logic
c. C¶ a vµ b
d. Kh«ng thùc hiÖn phÐp quay bit
3.14. §èi víi çc thanh ghi (trong CPU), ph¸t biÓu nµo sau ®©y lµ sai:
a. Chøa çc th«ng tin t¹m thêi
b. Lµ møc ®Çu tiªn cña hÖ thèng nhí
c. N»m trong bé xö lý
d. Ngêi lËp tr×nh cã thÓ thay ®æi néi dung cña mäi thanh ghi
3.15. §èi víi çc thanh ghi ®Þa chØ (trong CPU), ph¸t biÓu nµo sau ®©y lµ
®óng:
a. Cã tÊt c¶ 2 lo¹i
b. Cã Ýt nhÊt 3 lo¹i
c. Cã nhiÒu h¬n 4 lo¹i
d. ChØ cã 1 lo¹i
3.16. §èi víi çc thanh ghi ®Þa chØ (trong CPU), ph¸t biÓu nµo sau ®©y lµ sai:
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a. Bé ®Õm ch¬ng tr×nh qu¶n lý ®Þa chØ vïng lÖnh

b. Vïng d÷ liÖu ®îc qu¶n lý bëi thanh ghi con trá d÷ liÖu
c. Vïng lÖnh kh«ng cÇn thanh ghi qu¶n lý
d. Con trá ng¨n xÕp chøa ®Þa chØ ng¨n xÕp
3.17. §èi víi ng¨n xÕp (stack), ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ vïng nhí cã cÊu tróc FIFO
b. Lµ vïng nhí cã cÊu tróc LIFO
c. Con trá ng¨n xÕp lu«n trá vµo ®Ønh ng¨n xÕp
d. Khi cÊt thªm th«ng tin vµo ng¨n xÕp, con trá ng¨n xÕp gi¶m
3.18. Ph¸t biÓu nµo sau ®©y lµ sai:

a. Thanh ghi tr¹ng th¸i cßn gäi lµ thanh ghi cê
b. Thanh ghi tr¹ng th¸i chøa çc tr¹ng th¸i xö lý
c. Cã hai lo¹i cê
d. ChØ cã mét lo¹i cê
3.19. §èi víi khèi ®iÒu khiÓn trong CPU, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. TiÕp nhËn tÝn hiÖu tõ CPU ®Õn
b. Kh«ng tiÕp nhËn tÝn hiÖu tõ TBNV
c. Gi¶i m· lÖnh ®îc chuyÓn tõ thanh ghi tr¹ng th¸i ®Õn
d. Gi¶i m· lÖnh ®îc chuyÓn tõ thanh ghi lÖnh ®Õn
3.20. XÐt çc tÝn hiÖu ®iÒu khiÓn bªn trong CPU, ph¸t biÓu nµo sau ®©y lµ
®óng:
a. §iÒu khiÓn chuyÓn d÷ liÖu tõ bé nhí ra TBNV
b. §iÓu khiÓn chuyÓn d÷ liÖu tõ thanh ghi vµo ALU
c. §iÒu khiÓn chuyÓn d÷ liÖu tõ ALU ra bé nhí
d. §iÒu khiÓn chuyÓn d÷ liÖu tõ CPU vµo ALU
3.21. XÐt çc tÝn hiÖu ®iÒu khiÓn bªn trong CPU, ph¸t biÓu nµo sau ®©y lµ sai:
a. §iÒu khiÓn chuyÓn d÷ liÖu tõ CPU ra thanh ghi
b. §iÒu khiÓn chuyÓn d÷ liÖu tõ thanh ghi vµo ALU
c. §iÒu khiÓn chuyÓn d÷ liÖu tõ ALU ra thanh ghi
d. §iÒu khiÓn ALU thùc hiÖn lÖnh
3.22. XÐt çc tÝn hiÖu ®iÒu khiÓn tõ CPU ra bus hÖ thèng, ph¸t biÓu nµo sau
®©y lµ ®óng:
a. §iÒu khiÓn ®äc d÷ liÖu tõ ALU
b. §iÒu khiÓn ®äc/ghi ng¨n nhí
c. §iÒu khiÓn chuyÓn d÷ liÖu tõ ALU vµo thanh ghi
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d. §iÒu khiÓn ghi d÷ liÖu vµo ALU
3.23. XÐt çc tÝn hiÖu ®iÒu khiÓn tõ CPU ra bus hÖ thèng, ph¸t biÓu nµo sau
®©y lµ sai:
a. §iÒu khiÓn ®äc/ghi cæng vµo/ra
b. §iÒu khiÓn ®äc/ghi ng¨n nhí
c. §iÒu khiÓn ghi d÷ liÖu vµo çc thanh ghi
d. Xö lý çc tÝn hiÖu tõ bªn ngoµi göi ®Õn
3.24. XÐt çc tÝn hiÖu ®iÒu khiÓn tõ bus hÖ thèng ®Õn CPU, ph¸t biÓu nµo sau
®©y lµ ®óng:
a. TÝn hiÖu ®iÒu khiÓn ghi ng¨n nhí
b. TÝn hiÖu ®iÒu khiÓn ®äc ng¨n nhí
c. TÝn hiÖu xin ng¾t
d. TÝn hiÖu chÊp nhËn ng¾t
3.25. XÐt çc tÝn hiÖu ®iÒu khiÓn tõ bus hÖ thèng ®Õn CPU, ph¸t biÓu nµo sau
®©y lµ sai:
a. TÝn hiÖu xin nhêng bus
b. Kh«ng ph¶i lµ tÝn hiÖu ®iÒu khiÓn ®äc ng¨n nhí
c. TÝn hiÖu xin ng¾t
d. TÝn hiÖu tr¶ lêi ®ång ý nhêng bus
3.26. §èi víi khèi ALU (trong CPU), ph¸t biÓu nµo sau ®©y lµ sai:
a. Thùc hiÖn phÐp dÞch bit
b. Thùc hiÖn phÐp so s¸nh hai ®¹i lîng
c. Thùc hiÖn phÐp lÊy c¨n bËc hai
d. Thùc hiÖn phÐp céng vµ trõ
3.27. §èi víi çc thanh ghi (trong CPU), ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Cã lo¹i thanh ghi kh«ng lËp tr×nh ®îc
b. Mäi thanh ghi ®Òu cã thÓ lËp tr×nh ®îc
c. Chøa lÖnh võa ®îc xö lý xong
d. Chøa tr¹ng th¸i cña çc TBNV
3.28. §èi víi thanh ghi tr¹ng th¸i (trong CPU), ph¸t biÓu nµo sau ®©y lµ
®óng:
a. Kh«ng chøa çc cê phÐp to¸n
b. ChØ chøa çc cê phÐp to¸n
c. Chøa çc cê ®iÒu khiÓn
d. Kh«ng chøa çc cê ®iÒu khiÓn
3.29. §èi víi cê carry (CF), ph¸t biÓu nµo sau ®©y lµ ®óng:
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a. §îc thiÕt lËp khi phÐp to¸n cã nhí ra khái bit cao nhÊt
b. §îc thiÕt lËp khi phÐp to¸n kh«ng nhí ra khái bit cao nhÊt
c. Kh«ng ®îc thiÕt lËp khi phÐp to¸n cã nhí ra khái bit cao nhÊt
d. §©y lµ cê b¸o trµn ®èi víi sè cã dÊu
3.30. §èi víi cê carry (CF), ph¸t biÓu nµo sau ®©y lµ sai:
a. §îc thiÕt lËp khi phÐp to¸n cã nhí ra khái bit cao nhÊt
b. Kh«ng ®îc thiÕt lËp khi phÐp to¸n kh«ng nhí ra khái bit cao nhÊt
c. §©y lµ cê b¸o trµn ®èi víi sè kh«ng dÊu
3.31. §èi víi cê overflow (OF), ph¸t biÓu nµo sau ®©y lµ ®óng:
a. §îc thiÕt lËp khi céng hai sè kh¸c dÊu cho kÕt qu¶ ©m
b. §îc thiÕt lËp khi céng hai sè cïng dÊu cho kÕt qu¶ kh¸c dÊu
c. §îc thiÕt lËp khi céng hai sè cïng dÊu cho kÕt qu¶ cïng dÊu
d. §©y lµ cê b¸o trµn ®èi víi sè kh«ng dÊu
3.32. §èi víi cê overflow (OF), ph¸t biÓu nµo sau ®©y lµ sai:
a. Kh«ng ®îc thiÕt lËp khi céng hai sè kh¸c dÊu cho kÕt qu¶ ©m
b. §îc thiÕt lËp khi céng hai sè cïng dÊu cho kÕt qu¶ kh¸c dÊu
c. §îc thiÕt lËp khi céng hai sè cïng dÊu cho kÕt qu¶ cïng dÊu
Ch¬ng 4. KiÕn tróc tËp lÖnh
4.1. Cã tÊt c¶:

a. 9 mode ®Þa chØ
b. 8 mode ®Þa chØ
c. 7 mode ®Þa chØ
d. 6 mode ®Þa chØ
4.2. Mode ®Þa chØ tøc th× lµ mode kh«ng cã ®Æc ®iÓm sau:
a. To¸n h¹ng lµ mét phÇn cña lÖnh
b. To¸n h¹ng n»m ngay trong trêng ®Þa chØ
c. To¸n h¹ng cã thÓ lµ to¸n h¹ng nguån hoÆc ®Ých
d. To¸n h¹ng chØ cã thÓ lµ to¸n h¹ng nguån
4.3. Cho lÖnh assembly: ADD BX, 10. To¸n h¹ng nguån thuéc:
a. Mode ®Þa chØ trùc tiÕp
b. Mode ®Þa chØ gi¸n tiÕp
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c. Kh«ng tån t¹i lÖnh

d. Mode ®Þa chØ tøc th×
4.4. Cho lÖnh assembly: SUB 100, CX. To¸n h¹ng nguån thuéc:
b. Kh«ng tån t¹i lÖnh
c. Mode ®Þa chØ h»ng sè
4.5. Mode ®Þa chØ trùc tiÕp lµ mode mµ to¸n h¹ng lµ:
a. Mét ng¨n nhí cã ®Þa chØ ®îc chØ ra trong lÖnh
b. Mét ng¨n nhí cã ®Þa chØ ë ng¨n nhí kh¸c
c. Mét thanh ghi
d. Mét ng¨n nhí cã ®Þa chØ n»m trong mét thanh ghi
4.6. Cho lÖnh assembly: MOV DX, [20]. To¸n h¹ng nguån thuéc:
b. Kh«ng tån t¹i lÖnh
c. Mode ®Þa chØ h»ng sè
4.7. Cho lÖnh assembly: SUB BX, [30]. To¸n h¹ng nguån thuéc:
a. Kh«ng tån t¹i lÖnh
b. Mode ®Þa chØ gi¸n tiÕp
b. Mode ®Þa chØ tøc th×
d. Mode ®Þa chØ trùc tiÕp
4.8. Mode ®Þa chØ gi¸n tiÕp lµ mode mµ to¸n h¹ng lµ:
a. Mét ng¨n nhí cã ®Þa chØ ®îc chØ ra trong lÖnh
b. Mét ng¨n nhí cã ®Þa chØ n»m trong ng¨n nhí kh¸c
c. Mét thanh ghi cã ®Þa chØ n»m trong mét ng¨n nhí
d. Mét ng¨n nhí cã ®Þa chØ n»m trong mét thanh ghi
4.9. Mode ®Þa chØ thanh ghi lµ mode mµ to¸n h¹ng lµ:
a. Néi dung cña ng¨n nhí cã ®Þa chØ ®îc chØ ra trong lÖnh
b. Néi dung cña ng¨n nhí cã ®Þa chØ n»m trong ng¨n nhí kh¸c
c. Néi dung cña thanh ghi
d. Néi dung cña ng¨n nhí cã ®Þa chØ n»m trong mét thanh ghi
4.10. Cho lÖnh assembly: ADD AX, CX. Mode ®Þa chØ cña to¸n nguån lµ:
a. Tøc th×
b. Trùc tiÕp
c. Gi¸n tiÕp qua thanh ghi
d. Thanh ghi
4.11. Cho lÖnh assembly: SUB CX, [90]. Ph¸t biÓu nµo sau ®©y lµ sai:
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a. To¸n h¹ng ®Ých lµ mode ®Þa chØ thanh ghi

b. To¸n h¹ng nguån lµ mode ®Þa chØ trùc tiÕp
c. To¸n h¹ng nguån lµ mét ng¨n nhí
d. To¸n h¹ng nguån lµ mode gi¸n tiÕp qua thanh ghi
4.12. §èi víi mode ®Þa chØ gi¸n tiÕp qua thanh ghi, ph¸t biÓu nµo sau ®©y lµ sai:
a. To¸n h¹ng lµ mét thanh ghi cã ®Þa chØ n»m trong mét ng¨n nhí
b. To¸n h¹ng lµ mét ng¨n nhí cã ®Þa chØ n»m trong mét thanh ghi
c. To¸n h¹ng lµ néi dung mét ng¨n nhí
d. Thanh ghi tham gia gäi lµ thanh ghi con trá
4.13. Cho lÖnh assembly: MOV DX, [BP]. Mode ®Þa chØ cña to¸n h¹ng nguån lµ:
a. Thanh ghi
b. Gi¸n tiÕp
d. Trùc tiÕp
4.14. §èi víi mode ®Þa chØ dÞch chuyÓn, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ sù kÕt hîp: mode gi¸n tiÕp qua thanh ghi vµ mode tøc th×
b. Cã sù tham gia cña mode ®Þa chØ trùc tiÕp
c. §Þa chØ to¸n h¹ng gåm: néi dung thanh ghi + h»ng sè
d. Cã sù tham gia cña mode ®Þa chØ gi¸n tiÕp qua thanh ghi
4.15. Cho lÖnh assembly: SUB AX, [CX] + 50. Mode ®Þa chØ cña to¸n h¹ng nguån
lµ:
a. DÞch chuyÓn
b. Kh«ng tån t¹i
c. Thanh ghi
d. Gi¸n tiÕp qua thanh ghi
4.16. Mode ®Þa chØ ng¨n xÕp lµ mode:

a. To¸n h¹ng ®îc ngÇm hiÓu
b. To¸n h¹ng lµ ng¨n nhí ®Ønh ng¨n xÕp
c. C¶ vµ b ®Òu sai
4.17. Cho lÖnh assembly: POP BX. Ph¸t biÓu nµo sau ®©y lµ ®óng:
a. §©y lµ mode ®Þa chØ thanh ghi
b. §©y lµ mode ®Þa chØ gi¸n tiÕp qua thanh ghi
c. §©y lµ mode ®Þa ng¨n xÕp
4.18. Mode ®Þa chØ tøc th× lµ mode:

a. To¸n h¹ng lµ h»ng sè n»m ngay trong lÖnh
b. To¸n h¹ng lµ h»ng sè n»m trong mét ng¨n nhí
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c. To¸n h¹ng lµ h»ng sè n»m trong mét thanh ghi

d. C¶ b vµ c ®Òu ®óng
4.19. §èi víi mode ®Þa chØ trùc tiÕp, ph¸t biÓu nµo sau ®©y lµ sai:
a. To¸n h¹ng lµ néi dung cña ng¨n nhí cã ®Þa chØ ®îc chØ ra trong lÖnh
b. To¸n h¹ng lµ néi dung cña ng¨n nhí
c. §Ó t×m ®îc to¸n h¹ng, ph¶i biÕt ®Þa chØ ng¨n nhí
d. §Ó t×m ®îc to¸n h¹ng, ph¶i biÕt ®Þa chØ thanh ghi
4.20. §èi víi mode ®Þa chØ gi¸n tiÕp, ph¸t biÓu nµo sau ®©y lµ sai:
a. To¸n h¹ng lµ néi dung cña ng¨n nhí
b. To¸n h¹ng lµ néi dung cña thanh ghi
c. Cã thÓ gi¸n tiÕp nhiÒu lÇn
d. Tèc ®é xö lý chËm
4.21. §èi víi mode ®Þa chØ thanh ghi, ph¸t biÓu nµo sau ®©y lµ sai:
a. To¸n h¹ng lµ néi dung ng¨n nhí cã ®Þa chØ n»m trong thanh ghi
b. To¸n h¹ng lµ néi dung cña thanh ghi
c. Kh«ng tham chiÕu bé nhí
4.22. §èi víi mode ®Þa chØ gi¸n tiÕp qua thanh ghi, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. To¸n h¹ng lµ mét thanh ghi cã ®Þa chØ n»m trong mét ng¨n nhí
b. To¸n h¹ng lµ mét ng¨n nhí cã ®Þa chØ n»m trong mét thanh ghi
c. To¸n h¹ng kh«ng ph¶i lµ néi dung mét ng¨n nhí
d. Thanh ghi tham gia gäi lµ bé ®Õm ch¬ng tr×nh
4.23. §èi víi mode ®Þa chØ dÞch chuyÓn, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Lµ sù kÕt hîp: mode gi¸n tiÕp qua thanh ghi vµ mode trùc tiÕp
b. Cã sù tham gia cña mode ®Þa chØ tøc th×
c. §Þa chØ to¸n h¹ng kh«ng ph¶i lµ: néi dung thanh ghi + h»ng sè
d. Cã sù tham gia cña mode ®Þa chØ thanh ghi
4.24. §èi víi mode ®Þa chØ ng¨n xÕp, ph¸t biÓu nµo sau ®©y lµ sai:
a. To¸n h¹ng ®îc ngÇm hiÓu
b. To¸n h¹ng lµ ng¨n nhí ®Ønh ng¨n xÕp
c. C¶ vµ b ®Òu sai
4.25. §èi víi lÖnh m· m¸y, ph¸t biÓu nµo sau ®©y lµ sai:
a. Cã 2 thµnh phÇn: m· lÖnh vµ çc to¸n h¹ng
b. M· lÖnh cho biÕt thao t¸c cÇn thùc hiÖn
c. To¸n h¹ng cho biÕt thao t¸c cÇn thùc hiÖn
d. To¸n h¹ng cho biÕt n¬i chøa d÷ liÖu cÇn t¸c ®éng
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4.26. Trong mét lÖnh m· m¸y, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Cã thÓ cã nhiÒu m· lÖnh
b. Kh«ng tån t¹i lÖnh kh«ng cã to¸n h¹ng
c. To¸n h¹ng lµ duy nhÊt
d. Cã thÓ cã nhiÒu to¸n h¹ng
4.27. §èi víi lÖnh m· m¸y, sè lîng to¸n h¹ng cã thÓ lµ:
a. 1, 2, 3 to¸n h¹ng
b. 0, 1, 2, to¸n h¹ng
c. 2, 3, 4 to¸n h¹ng
4.28. §èi víi lÖnh m· m¸y, to¸n h¹ng kh«ng thÓ lµ:
a. Mét h»ng sè
b. Néi dung cña thanh ghi
c. Néi dung cña ng¨n nhí
d. Néi dung cña thanh ghi cã ®Þa chØ n»m trong mét ng¨n nhí
4.29. H×nh vÏ sau lµ s¬ ®å ho¹t ®éng cña mode ®Þa chØ:
LÖnh
M· lÖnh §Þa chØ

Bé nhí
To¸n h¹ng
a. Trùc tiÕp
b. Tøc th×
d. Kh«ng tån t¹i
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LÖnh
Bé nhí
§Þa chØ cña t/h¹ng
To¸n h¹ng
a. Kh«ng tån t¹i

b. Gi¸n tiÕp
c. Thanh ghi
d. Trùc tiÕp
LÖnh
M· lÖnh Tªn thanh ghi
TËp thanh ghi
To¸n h¹ng
a. Gi¸n tiÕp
b. Thanh ghi
c. Kh«ng tån t¹i
d. Gi¸n tiÕp qua thanh ghi
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LÖnh
Bé nhí
TËp thanh ghi
§Þa chØ cña t/h¹ng To¸n h¹ng
a. Tøc th×
b. DÞch chuyÓn
d. Kh«ng tån t¹i
LÖnh
M· lÖnh Register R Address A
Bé nhí
TËp thanh ghi +
§Þa chØ ng¨n nhí
To¸n h¹ng
a. Kh«ng tån t¹i

b. Trùc tiÕp
d. DÞch chuyÓn
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LÖnh
TËp thanh ghi
§Þa chØ cña t/h¹ng
To¸n h¹ng
a. Kh«ng tån t¹i

b. Gi¸n tiÕp qua thanh ghi
c. Trùc tiÕp
d. Gi¸n tiÕp
LÖnh
TËp thanh ghi
Bé nhí
§Þa chØ cña t/h¹ng To¸n h¹ng
a. Gi¸n tiÕp qua ng¨n nhí

b. Kh«ng tån t¹i
d. Trùc tiÕp
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LÖnh
M· lÖnh Register R Address A
TËp thanh ghi
Bé nhí +
§Þa chØ ng¨n nhí
To¸n h¹ng
a. DÞch chuyÓn
b. Gi¸n tiÕp qua thanh ghi
c. Trùc tiÕp
d. Kh«ng tån t¹i
4.37. Cho lÖnh assembly: ADD CX, 20. Ph¸t biÓu nµo sau ®©y lµ ®óng:
a. To¸n h¹ng nguån thuéc mode ®Þa chØ tøc th×
b. To¸n h¹ng nguån thuéc mode ®Þa chØ trùc tiÕp
c. To¸n h¹ng ®Ých thuéc mode ®Þa chØ gi¸n tiÕp qua thanh ghi
d. To¸n h¹ng ®Ých kh«ng thuéc mode ®Þa chØ thanh ghi
4.38. Cho lÖnh assembly: SUB CX, 70. Ph¸t biÓu nµo sau ®©y lµ sai:
b. To¸n h¹ng nguån kh«ng thuéc mode ®Þa chØ trùc tiÕp
c. To¸n h¹ng ®Ých kh«ng thuéc mode ®Þa chØ thanh ghi
d. To¸n h¹ng ®Ých kh«ng thuéc mode ®Þa chØ gi¸n tiÕp
4.39. Cho lÖnh assembly: ADD DX, [40]. Ph¸t biÓu nµo sau ®©y lµ ®óng:
b. To¸n h¹ng nguån kh«ng thuéc mode ®Þa chØ trùc tiÕp
d. To¸n h¹ng ®Ých thuéc mode ®Þa chØ thanh ghi
4.40. Cho lÖnh assembly: MOV BX, [80]. Ph¸t biÓu nµo sau ®©y lµ sai:
a. To¸n h¹ng nguån thuéc mode ®Þa chØ thanh ghi
b. To¸n h¹ng nguån thuéc mode ®Þa chØ trùc tiÕp
c. To¸n h¹ng ®Ých kh«ng thuéc mode ®Þa chØ dÞch chuyÓn
d. To¸n h¹ng ®Ých kh«ng thuéc mode ®Þa chØ trùc tiÕp
4.41. Cho lÖnh assembly: SUB AX, [BX]. Ph¸t biÓu nµo sau ®©y lµ sai:
b. To¸n h¹ng nguån thuéc mode ®Þa chØ gi¸n tiÕp qua thanh ghi
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c. To¸n h¹ng ®Ých kh«ng thuéc mode ®Þa chØ dÞch chuyÓn
4.42. Cho lÖnh assembly: ADD AX, [BP]. Ph¸t biÓu nµo sau ®©y lµ ®óng:
b. To¸n h¹ng nguån thuéc mode ®Þa chØ gi¸n tiÕp qua thanh ghi
d. To¸n h¹ng ®Ých thuéc mode ®Þa chØ gi¸n tiÕp qua thanh ghi
4.43. Cho lÖnh assembly: MOV AX, [BX]+50. Ph¸t biÓu nµo sau ®©y lµ sai:
a. To¸n h¹ng nguån thuéc mode ®Þa chØ dÞch chuyÓn
b. To¸n h¹ng ®Ých kh«ng thuéc mode ®Þa chØ dÞch chuyÓn
c. To¸n h¹ng nguån thuéc mode ®Þa chØ tøc th×
4.44. Cho lÖnh assembly: ADD DX, [SI]+30. Ph¸t biÓu nµo sau ®©y lµ ®óng:
a. To¸n h¹ng nguån thuéc mode ®Þa chØ dÞch chuyÓn
b. To¸n h¹ng ®Ých thuéc mode ®Þa chØ trùc tiÕp
c. To¸n h¹ng nguån thuéc mode ®Þa chØ tøc th×
d. To¸n h¹ng ®Ých thuéc mode ®Þa chØ gi¸n tiÕp
4.45. Cho lÖnh assembly: POP DX. Ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Kh«ng cã to¸n h¹ng nguån
b. To¸n h¹ng ®Ých thuéc mode ®Þa chØ trùc tiÕp
c. To¸n h¹ng ®Ých ®îc ngÇm hiÓu
d. To¸n h¹ng nguån ®îc ngÇm hiÓu
4.46. Cho lÖnh assembly: PUSH AX. Ph¸t biÓu nµo sau ®©y lµ sai:
a. Kh«ng cã to¸n h¹ng nguån
b. To¸n h¹ng ®Ých ®îc ngÇm hiÓu
c. To¸n h¹ng nguån thuéc mode ®Þa chØ thanh ghi
d. To¸n h¹ng ®Ých thuéc mode ®Þa chØ stack
4.47. TÊt c¶ cã çc mode ®Þa chØ sau ®©y:

a. Tøc th×, gi¸n tiÕp, thanh ghi, ng¨n xÕp, gi¸n tiÕp qua ng¨n xÕp, ng¨n nhí,
con trá
b. Gi¸n tiÕp, gi¸n tiÕp qua thanh ghi, trùc tiÕp, dÞch chuyÓn, ng¨n xÕp, con
trá, thanh ghi
c. Tøc th×, gi¸n tiÕp, thanh ghi, dÞch chuyÓn, ng¨n xÕp, trùc tiÕp, gi¸n
tiÕp qua thanh ghi
d. Tøc th×, gi¸n tiÕp qua con trá, thanh ghi, ng¨n xÕp, dÞch chuyÓn, con trá,
ng¨n nhí
4.48. XÐt lÖnh LOAD. LÖnh nµy thuéc:
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a. Nhãm lÖnh sè häc

b. Nhãm lÖnh chuyÓn d÷ liÖu
c. Nhãm lÖnh chuyÓn ®iÒu khiÓn
d. Nhãm lÖnh vµo/ra
4.49. XÐt lÖnh INTERRUPT. LÖnh nµy thuéc:

b. Nhãm lÖnh chuyÓn d÷ liÖu
c. Nhãm lÖnh chuyÓn ®iÒu khiÓn
d. Nhãm lÖnh vµo/ra
4.50. XÐt lÖnh ABSOLUTE. LÖnh nµy thuéc:

b. Nhãm lÖnh vµo/ra
c. Nhãm lÖnh ®iÒu khiÓn hÖ thèng
d. Nhãm lÖnh logic
4.51. XÐt lÖnh ROTATE. LÖnh nµy thuéc:

a. Nhãm lÖnh chuyÓn ®iÒu khiÓn
b. Nhãm lÖnh ®iÒu khiÓn hÖ thèng
c. Nhãm lÖnh quan hÖ
d. Nhãm lÖnh logic
4.52. XÐt lÖnh JUMP. LÖnh nµy thuéc:
a. Nhãm lÖnh chuyÓn ®iÒu khiÓn
b. Nhãm lÖnh quan hÖ
c. Nhãm lÖnh vµo/ra
d. Nhãm lÖnh sè häc
Ch¬ng 5. HÖ thèng nhí
5.1. §èi víi bé nhí ROM, ph¸t biÓu nµo sau ®©y lµ sai:
a. Cã tÊt c¶ 5 lo¹i ROM
b. Lµ lo¹i bé nhí kh¶ biÕn
c. Lµ n¬i chøa çc ch¬ng tr×nh hÖ thèng (BIOS)
d. Lµ n¬i chøa çc vi ch¬ng tr×nh
5.2. §èi víi bé nhí ROM, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Cã thÓ dïng ®iÖn ®Ó xo¸ PROM
b. PROM lµ lo¹i ROM cã thÓ xo¸ vµ ghi l¹i nhiÒu lÇn
c. EPROM lµ lo¹i ROM cã thÓ xo¸ vµ ghi l¹i nhiÒu lÇn
d. Cã thÓ dïng ®iÖn ®Ó xo¸ EPROM
5.3. §èi víi bé nhí RAM, ph¸t biÓu nµo sau ®©y lµ sai:
a. Lµ lo¹i bé nhí kh«ng kh¶ biÕn
b. Lµ n¬i lu gi÷ th«ng tin t¹m thêi
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c. Cã hai lo¹i RAM

d. Lµ bé nhí ®äc/ghi tuú ý
5.4. §èi víi bé nhí RAM, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Lµ lo¹i bé nhí kh«ng kh¶ biÕn
b. RAM lµ viÕt t¾t cña: Read Access Memory
c. SRAM ®îc chÕ t¹o tõ çc tô ®iÖn
d. Lµ n¬i lu gi÷ th«ng tin mµ m¸y tÝnh ®ang xö lý
5.5. §èi víi bé nhí ROM, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. §îc chÕ t¹o tõ m¹ch lËt
b. §îc chÕ t¹o tõ transistor
c. §îc chÕ t¹o tõ diode
d. C¶ b vµ c
5.6. §èi víi bé nhí RAM, ph¸t biÓu nµo sau ®©y lµ sai:
a. DRAM ®îc chÕ t¹o tõ m¹ch lËt
b. DRAM ®îc chÕ t¹o tõ tô ®iÖn
c. SRAM ®îc chÕ t¹o tõ m¹ch lËt
d. SRAM kh«ng cÇn ph¶i lµm t¬i
5.7. Cho chip nhí SRAM cã dung lîng 64K x 4 bit, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Çc ®êng ®Þa chØ lµ: A0 -> A15
b. Çc ®êng ®Þa chØ lµ: D0 -> D15
c. Çc ®êng d÷ liÖu lµ: A0 -> A3
d. Çc ®êng d÷ liÖu lµ: D1 -> D8
5.8. Cho chip nhí SRAM cã dung lîng 16K x 8 bit, ph¸t biÓu nµo sau ®©y lµ sai:
a. Cã 14 ®êng ®Þa chØ
b. Cã 8 ®êng d÷ liÖu
c. Çc ®êng ®Þa chØ lµ: A0 -> A13
d. Çc ®êng ®Þa chØ lµ: A0 -> A14
5.9. Cho chip nhí SRAM cã çc tÝn hiÖu: A0 -> A13, D0 -> D15 , RD, WE. Ph¸t biÓu nµo sau ®©y
lµ sai:
a. Dung lîng cña chip lµ: 16K x 16 bit
b. WE lµ tÝn hiÖu ®iÒu khiÓn ghi d÷ liÖu
c. RD lµ tÝn hiÖu ®iÒu khiÓn ghi d÷ liÖu
d. RD lµ tÝn hiÖu ®iÒu khiÓn ®äc d÷ liÖu
5.10. Cho chip nhí DRAM cã çc tÝn hiÖu: A0 -> A7, D0 -> D7 , RD, WE. Ph¸t biÓu nµo sau ®©y
lµ ®óng:
a. Dung lîng cña chip lµ: 64K x 8 bit
b. Dung lîng cña chip lµ: 8K x 8 bit
c. RD lµ tÝn hiÖu ®iÒu khiÓn ghi d÷ liÖu
d. WE lµ tÝn hiÖu ®iÒu khiÓn ®äc d÷ liÖu
5.11. XÐt vÒ chøc n¨ng, hÖ thèng nhí m¸y tÝnh cã thÓ cã ë:

a. Bªn trong bé xö lý, RAM, ®Üa tõ
b. Çc thanh ghi, bé nhí trong, CD-ROM
c. Çc thanh ghi, ROM, b¨ng tõ
d. Çc thanh ghi, bé nhí trong, bé nhí ngoµi
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5.12. §èi víi hÖ thèng nhí m¸y tÝnh, cã thÓ cã çc ®¬n vÞ truyÒn nh sau:
a. Theo tõ nhí
b. Theo khèi nhí
c. C¶ a vµ b ®Òu ®óng
5.13. XÐt vÒ çc ph¬ng ph¸p truy nhËp trong hÖ thèng nhí, ph¸t biÓu nµo sau ®©y lµ sai:
a. Truy nhËp tuÇn tù ®èi víi bé nhí cache
b. Truy nhËp liªn kÕt ®èi víi bé nhí cache
c. Truy nhËp ngÉu nhiªn ®èi víi bé nhí trong
d. Truy nhËp trùc tiÕp ®èi víi ®Üa tõ
5.14. §èi víi hÖ thèng nhí, cã çc kiÓu vËt lý nh sau:
a. Bé nhí tõ, RAM, bé nhí cache
b. Bé nhí b¸n dÉn, bé nhí tõ, bé nhí cache
c. Bé nhí b¸n dÉn, bé nhí tõ, bé nhí quang
d. Bé nhí quang, bé nhí cache, bé nhí tõ
5.15. §èi víi hÖ thèng nhí m¸y tÝnh, ph¸t biÓu nµo sau ®©y kh«ng ph¶i lµ ®Æc trng vËt lý:
a. Bé nhí kh¶ biÕn
b. Bé nhí kh«ng kh¶ biÕn
c. Bé nhí xo¸ ®îc
d. Bé nhí chØ ®äc
5.16. XÐt s¬ ®å ph©n cÊp hÖ thèng nhí, ph¸t biÓu nµo sau ®©y lµ sai:
a. Møc thanh ghi lµ møc trao ®æi nhanh nhÊt
b. Møc thanh ghi lµ møc trao ®æi chËm nhÊt
c. Møc cache ®îc chia thµnh hai møc
d. Møc cache lµ møc gÇn thanh ghi nhÊt
5.17. XÐt s¬ ®å ph©n cÊp hÖ thèng nhí, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Tõ bé nhí cache ®Õn bé nhí ngoµi, tèc ®é nhanh dÇn
b. Tõ thanh ghi ®Õn bé xö lý, tèc ®é t¨ng dÇn
c. Tõ bé nhí ngoµi ®Õn thanh ghi, dung lîng gi¶m dÇn
d. Tõ bé nhí trong ®Õn bé nhí cache, tÇn suÊt truy nhËp gi¶m dÇn
5.18. Cho chip nhí nh h×nh vÏ, ®©y lµ ký hiÖu cña:
A0 -> A11
Chip
D0 -> D7
nhí
CS
RD WR
a. SRAM 4K x 8 bit
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b. DRAM 4 K x 8 bit
c. SRAM 2K x 8 bit
d. DRAM 2 K x 8 bit
5.19. Cho chip nhí nh h×nh vÏ, ®©y lµ ký hiÖu cña:
A0 -> A12
RAS Chip
D0 -> D15
CAS nhí
CS
a. SRAM 8K x 16 bit
RD WR
b. DRAM 8K x 16 bit
c. SRAM 64M x 16 bit
d. DRAM 64M x 16 bit
5.20. §èi víi bé nhí chÝnh (BNC) m¸y tÝnh, ph¸t biÓu nµo sau ®©y lµ sai:
a. Chøa çc ch¬ng tr×nh vµ d÷ liÖu díi d¹ng th viÖn
b. VÒ nguyªn t¾c, ngêi lËp tr×nh cã thÓ can thiÖp vµo toµn bé BNC
c. ViÖc qu¶n lý logic BNC tuú thuéc vµo tõng hÖ ®iÒu hµnh
d. §îc ®¸nh ®Þa chØ trùc tiÕp bëi bé xö lý
5.21. §èi víi bé nhí chÝnh (BNC) m¸y tÝnh, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. ViÖc ®¸nh ®Þa chØ cho BNC tuú thuéc vµo tõng hÖ ®iÒu hµnh
b. BNC do bé xö lý ®¸nh ®Þa chØ trùc tiÕp
c. Cã nh÷ng lo¹i m¸y tÝnh kh«ng cã BNC
d. Çc ng¨n nhí kh«ng tæ chøc theo byte
5.22. §èi víi bé nhí cache, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Cache cã thÓ ®îc ®Æt trªn cïng chip víi CPU
b. Bé nhí chÝnh cã tèc ®é nhanh h¬n cache
c. Bé nhí cache ®îc ®Æt gi÷a bé nhí chÝnh vµ bé nhí ngoµi
d. Cache kh«ng ®îc ®Æt trªn cïng chip víi CPU
5.23. §èi víi bé nhí cache, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Bé nhí ngoµi nhËn c¶ khèi d÷ liÖu tõ cache
b. TruyÒn d÷ liÖu gi÷a CPU vµ cache theo ®¬n vÞ khèi nhí
c. TruyÒn d÷ liÖu gi÷a CPU vµ cache theo ®¬n vÞ tõ nhí
d. Khi cÇn, CPU nhËn d÷ liÖu trùc tiÕp tõ bé nhí chÝnh
5.24. Khi CPU truy nhËp cache, cã hai kh¶ n¨ng sau:
a. Trît cache, tróng cache
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b. Sai cache, ®óng cache

c. Trªn cache, díi cache
d. Trong cache, ngoµi cache
5.25. Cache ho¹t ®éng nhê vµo nguyªn lý:

a. Nguyªn lý ho¹t ®éng cña m¸y tÝnh
b. Nguyªn lý ®iÒu khiÓn ghi d÷ liÖu
c. Nguyªn lý ®iÒu khiÓn ®äc d÷ liÖu
d. Nguyªn lý ®Þnh vÞ tham sè bé nhí
5.26. Trong sù trao ®æi gi÷a cache vµ bé nhí chÝnh, ph¸t biÓu nµo sau ®©y lµ sai:
a. Bé nhí chÝnh chia thµnh çc block nhí
b. Cache chia thµnh çc line nhí
c. Bé nhí chÝnh chia thµnh çc line nhí
d. KÝch thíc line b»ng kÝch thíc block
5.27. XÐt bé nhí cache, mçi line ®îc g¾n thªm Tag lµ ®Ó:
a. X¸c ®Þnh block nµo cña bé nhí chÝnh ®ang ë trong line
b. X¸c ®Þnh cache cã dung lîng bao nhiªu
c. X¸c ®Þnh line cã dung lîng bao nhiªu
d. X¸c ®Þnh cache cã bao nhiªu line
5.28. XÐt bé nhí cache, cã çc kü thuËt ¸nh x¹ ®Þa chØ sau ®©y:
a. Trùc tiÕp, liªn kÕt hoµn toµn, liªn kÕt tËp hîp
b. Liªn kÕt hoµn toµn, liªn kÕt phô thuéc, gi¸n tiÕp
c. Liªn kÕt tËp hîp, liªn kÕt phÇn tö, gi¸n tiÕp
d. Trùc tiÕp, liªn kÕt phÇn tö, liªn kÕt gi¸n ®o¹n
5.29. Trong kü thuËt ¸nh x¹ liªn kÕt hoµn toµn, çc trêng ®Þa chØ lµ:
a. Tag + Word + Line
b. Tag + Word
c. Tag + Line + Word
d. Tag + Line
5.30. Trong kü thuËt ¸nh x¹ trùc tiÕp, çc trêng ®Þa chØ lµ:
a. Tag + Word + Line
b. Tag + Word
c. Tag + Line + Word
d. Tag + Line
5.31. Trong kü thuËt ¸nh x¹ liªn kÕt tËp hîp, çc trêng ®Þa chØ lµ:
a. Tag + Word + Set
b. Tag + Word
c. Tag + Set + Word
d. Tag + Set
5.32. Cho m¸y tÝnh cã dung lîng bé nhí chÝnh: 128MB, cache: 64KB, line: 8 byte, ®é dµi ng¨n
nhí: 1 byte. Trong trêng hîp kü thuËt ¸nh x¹ trùc tiÕp, d¹ng ®Þa chØ do bé xö lý ph¸t ra ®Ó truy
nhËp cache lµ:
a. 12 + 10 + 5 b. 13 + 10 + 4
c. 14 + 11 + 2 d. 14 + 10 + 3
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5.33. Cho m¸y tÝnh cã dung lîng bé nhí chÝnh: 256MB, cache: 128KB, line: 16 byte, ®é dµi
ng¨n nhí: 2 byte. Trong trêng hîp kü thuËt ¸nh x¹ trùc tiÕp, d¹ng ®Þa chØ do bé xö lý ph¸t ra ®Ó
truy nhËp cache lµ:
a. 11 + 13 + 3 b. 11 + 14 + 2
c. 12 + 13 + 4 d. 12 + 12 + 3
ng¨n nhí: 4 byte. Trong trêng hîp kü thuËt ¸nh x¹ trùc tiÕp, d¹ng ®Þa chØ do bé xö lý ph¸t ra ®Ó
truy nhËp cache lµ:
a. 11 + 11 + 5 b. 12 + 11 + 4
c. 12 + 12 + 3 d. 11 + 12 + 4
ng¨n nhí: 4 byte. Trong trêng hîp kü thuËt ¸nh x¹ liªn kÕt hoµn toµn, d¹ng ®Þa chØ do bé xö lý
ph¸t ra ®Ó truy nhËp cache lµ:
a. 13 + 11 + 2 b. 12 + 12 + 2
c. 24 + 4 d. 24 + 2
ng¨n nhí: 4 byte. Trong trêng hîp kü thuËt ¸nh x¹ liªn kÕt hoµn toµn, d¹ng ®Þa chØ do bé xö lý
ph¸t ra ®Ó truy nhËp cache lµ:
a. 13 + 11 + 2 b. 14 + 10 + 2
c. 23 + 3 d. 24 + 2
ng¨n nhí: 1 byte, set: 4 line. Trong trêng hîp kü thuËt ¸nh x¹ liªn kÕt tËp hîp, d¹ng ®Þa chØ do
bé xö lý ph¸t ra ®Ó truy nhËp cache lµ:
a. 13 + 10 + 4 b. 13 + 9 + 5
c. 14 + 9 + 4 d. 14 + 10 + 4
a. 12 + 12 + 4 b. 13 + 11 + 4
c. 14 + 10 + 4 d. 13 + 9 + 6
a. 13 + 8 + 5 b. 13 + 7 + 6
c. 14 + 7 + 5 d. 14 + 8 + 6
5.40. XÐt kü thuËt ¸nh x¹ trùc tiÕp khi truy nhËp cache, thø tù t×m block trong cache ®îc thùc
hiÖn dùa theo çc trêng trong ®Þa chØ do CPU ph¸t ra nh sau:
a. Line -> Tag -> Word
b. Line -> Word -> Tag
c. Tag -> Line -> Word
d. Tag -> Word -> Line
5.41. §èi víi bé nhí cache, xÐt kü thuËt ¸nh x¹ liªn kÕt tËp hîp, thø tù t×m block trong cache
®îc thùc hiÖn dùa theo çc gi¸ trÞ trong ®Þa chØ do CPU ph¸t ra nh sau:
a. Word -> Set -> Tag
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b. Set -> Word -> Tag

c. Set -> Tag -> Word
d. Word -> Tag -> Set
5.42. XÐt çc thuËt to¸n thay thÕ d÷ liÖu trong cache, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Kh«ng cã thuËt to¸n
b. ¸nh x¹ trùc tiÕp kh«ng cã thuËt to¸n thay thÕ
c. Hai ¸nh x¹ liªn kÕt (hoµn toµn vµ tËp hîp) cã 4 thuËt to¸n
5.43. §èi víi bé nhí cache, çc thuËt to¸n thay thÕ d÷ liÖu lµ:
a. NgÉu nhiªn, FIFO, LRU, LFU
b. NgÉu nhiªn, LIFO, LRU, LFU
c. NgÉu nhiªn, FIFO, LFU, LTU
d. NgÉu nhiªn, LIFO, LTU, LVU
5.44. §èi víi çc ph¬ng ph¸p ghi d÷ liÖu vµo cache, ph¸t biÓu nµo sau ®©y lµ sai:
a. Write through: ghi ®ång thêi vµo c¶ cache vµ bé nhí chÝnh
b. Write back: chØ ghi vµo cache, khi block t¬ng øng bÞ thay thÕ th× míi ghi vµo bé nhí
chÝnh
c. C¶ a vµ b ®Òu sai
5.45. §èi víi çc ph¬ng ph¸p ghi d÷ liÖu vµo cache, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Write back: ghi ®ång thêi vµo c¶ cache vµ bé nhí chÝnh
b. Write through: chØ ghi vµo cache, khi block t¬ng øng bÞ thay thÕ th× míi ghi vµo bé
nhí chÝnh
c. C¶ a vµ b ®Òu kh«ng ®óng
5.46. §èi víi çc thuËt to¸n (TT) thay thÕ d÷ liÖu trong cache, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. FIFO lµ TT thay ®i block míi nhÊt trong çc block hiÖn nay
b. LRU lµ TT thay ®i block cã tÇn suÊt truy nhËp Ýt nhÊt
c. LFU lµ TT thay ®i block truy nhËp gÇn ®©y Ýt nhÊt
d. TÊt c¶ ®Òu sai
5.47. §èi víi çc thuËt to¸n (TT) thay thÕ d÷ liÖu trong cache, ph¸t biÓu nµo sau ®©y lµ sai:
a. FIFO lµ TT thay ®i block cò nhÊt trong çc block hiÖn nay
b. FIFO lµ TT thay ®i block cã tÇn suÊt truy nhËp Ýt nhÊt
c. LRU lµ TT thay ®i block truy nhËp gÇn ®©y Ýt nhÊt
d. Random lµ TT thay ®i block ngÉu nhiªn
5.48. §èi víi çc thuËt to¸n (TT) thay thÕ d÷ liÖu trong cache, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. LIFO lµ TT thay ®i block cò nhÊt trong çc block hiÖn nay
b. LTU lµ TT thay ®i block cã tÇn suÊt truy nhËp Ýt nhÊt
c. LVU lµ TT thay ®i block truy nhËp gÇn ®©y Ýt nhÊt
5.49. §èi víi çc thuËt to¸n (TT) thay thÕ d÷ liÖu trong cache, ph¸t biÓu nµo sau ®©y lµ sai:
a. TT Random cho tØ lÖ cache hit thÊp nhÊt
b. TT LRU cho tØ lÖ cache hit cao nhÊt
c. TT FIFO cho tØ lÖ cache hit cao nhÊt
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d. TT LFU cho tØ lÖ cache hit t¬ng ®èi cao
5.50. H×nh vÏ díi ®©y lµ s¬ ®å kÕt nèi cña 2 IC SRAM:
A0 -> A12
Chip Chip
D4 -> D7
nhí nhí D0 -> D3
RD
WR
CS
a. 4K x 4 bit ®Ó cã modul nhí 8K x 4 bit

b. 8K x 4 bit ®Ó cã modul nhí 16K x 4 bit
c. 8K x 4 bit ®Ó cã modul nhí 8K x 8 bit
d. 4K x 4 bit ®Ó cã modul nhí 4K x 8 bit

A0 -> A14
Chip Chip
D8 -> D15
nhí nhí D0 -> D7
RD
WR
CS
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A0 -> A13
D12 -> D15

Chip Chip Chip Chip D8 -> D11
nhí nhí nhí nhí D4 -> D7
D0 -> D3
RD
WR
a.
CS

A0 -> A11
D6 -> D7
Chip Chip Chip Chip D4 -> D5
nhí nhí nhí nhí D2 -> D3
D0 -> D1
RD
WR
CS

5.54. H×nh vÏ díi lµ s¬ ®å kÕt nèi cña 2 IC SRAM:
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A0 -> A10
Chip nhí
A11 A Y0
D0 -> D3
G Y1
CS Chip nhí
RD WR

A0 -> A14
Chip nhí
A15 A Y0
D0 -> D7
G Y1
CS Chip nhí
RD WR
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A0 -> A9
Chip nhí
A10
A Y0
A11 B Y1
Y2
Chip nhí
G Y3
CS
D0 -> D3
Chip nhí
Chip nhí
RD WR

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A0 -> A12
Chip nhí
A13
A Y0
A14 B Y1
Y2
Chip nhí
G Y3
CS
D0 -> D7
Chip nhí
Chip nhí
RD WR

5.58. H×nh vÏ díi ®©y lµ s¬ ®å kÕt nèi 4 IC SRAM:
A0 -> A12
Chip nhí Chip nhí

A13
A Y0 D4 -> D7
D0 -> D3
G Y1
CS Chip nhí Chip nhí
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WR

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5.59. H×nh vÏ díi ®©y lµ s¬ ®å kÕt nèi 4 IC SRAM:
A0 -> A11
Chip nhí Chip nhí

A12
A Y0 D4 -> D7
D0 -> D3
G Y1
CS Chip nhí Chip nhí
RD
WR
5.60. Víi chip nhí SRAM cã n ®êng ®Þa chØ, m ®êng d÷ liÖu th× dung lîng cña chip lµ:
a. 2m x n bit
b. 2n x m bit
c. 2m x n byte
d. 2n x m byte
5.61. Víi chip nhí SRAM cã n ®êng ®Þa chØ, m ®êng d÷ liÖu th× dung lîng cña chip lµ:
a. 2m x n bit
b. 22n x m bit
c. 22m x n bit
d. 2n x m bit
5.62. Víi chip nhí DRAM cã n ®êng ®Þa chØ, m ®êng d÷ liÖu th× dung lîng cña chip lµ:
a. 22m x n bit
b. 22n x m bit
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c. 22m x n byte
d. 22n x m byte
5.63. Víi chip nhí DRAM cã n ®êng ®Þa chØ, m ®êng d÷ liÖu th× dung lîng cña chip lµ:
a. 2m x n bit
b. 22n x m bit
c. 22m x n bit
d. 2n x m bit
5.64. §èi víi bé nhí cache, xÐt nguyªn lý ®Þnh vÞ vÒ thêi gian, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Th«ng tin võa truy nhËp th× x¸c suÊt bÐ lµ sau ®ã nã sÏ ®îc truy nhËp l¹i
b. Th«ng tin võa truy nhËp th× x¸c suÊt lín lµ sau ®ã nã sÏ ®îc truy nhËp l¹i
c. Th«ng tin võa truy nhËp th× sau ®ã ch¾c ch¾n nã sÏ kh«ng ®îc truy nhËp l¹i
d. Th«ng tin võa truy nhËp th× ch¾c ch¾n lµ sau ®ã nã ®îc truy nhËp l¹i
5.65. §èi víi bé nhí cache, xÐt nguyªn lý ®Þnh vÞ vÒ kh«ng gian, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Môc th«ng tin võa truy nhËp th× x¸c suÊt lín lµ sau ®ã çc môc l©n cËn ®îc truy nhËp
b. Môc th«ng tin võa truy nhËp th× x¸c suÊt bÐ lµ sau ®ã çc môc l©n cËn ®îc truy nhËp
c. Môc th«ng tin võa truy nhËp th× ch¾c ch¾n lµ sau ®ã çc môc l©n cËn ®îc truy nhËp
d. Th«ng tin võa truy nhËp th× ch¾c ch¾n lµ sau ®ã çc môc l©n cËn kh«ng ®îc truy nhËp
5.66. Khi truy nhËp cache, xÐt ¸nh x¹ trùc tiÕp, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Mçi block cã thÓ ¸nh x¹ vµo mét line bÊt kú
b. Mçi block cã thÓ ¸nh x¹ vµo mét line bÊt kú trong mét tËp line x¸c ®Þnh
c. Mçi block chØ ®îc ¸nh x¹ vµo mét line duy nhÊt
d. Mçi block chØ ®îc ¸nh x¹ vµo mét trong bèn line x¸c ®Þnh
5.67. Khi truy nhËp cache, xÐt ¸nh x¹ trùc tiÕp, ph¸t biÓu nµo sau ®©y lµ sai:
a. Mçi block kh«ng thÓ ¸nh x¹ vµo mét line bÊt kú
b. Mçi block kh«ng thÓ ¸nh x¹ vµo mét line bÊt kú trong t¸m line x¸c ®Þnh
d. Mçi block chØ ®îc ¸nh x¹ vµo mét trong hai line x¸c ®Þnh
5.68. Khi truy nhËp cache, xÐt ¸nh x¹ liªn kÕt hoµn toµn, ph¸t biÓu nµo sau ®©y lµ ®óng:
b. Mçi block cã thÓ ¸nh x¹ vµo mét line bÊt kú trong bèn line x¸c ®Þnh
d. Mçi block chØ ®îc ¸nh x¹ vµo mét trong mêi s¸u line x¸c ®Þnh
5.69. Khi truy nhËp cache, xÐt ¸nh x¹ liªn kÕt hoµn toµn, ph¸t biÓu nµo sau ®©y lµ sai:
b. Mçi block cã thÓ ¸nh x¹ vµo mét line bÊt kú trong t¸m line x¸c ®Þnh
c. Mçi block kh«ng chØ ®îc ¸nh x¹ vµo mét line duy nhÊt
d. Mçi block kh«ng chØ ®îc ¸nh x¹ vµo mét trong bèn line x¸c ®Þnh
5.70. Khi truy nhËp cache, xÐt ¸nh x¹ liªn kÕt tËp hîp, ph¸t biÓu nµo sau ®©y lµ ®óng:
b. Mçi block cã thÓ ¸nh x¹ vµo mét line bÊt kú trong mét tËp line x¸c ®Þnh
c. Mçi block cã thÓ ¸nh x¹ vµo mét line duy nhÊt trong mét tËp line x¸c ®Þnh
d. Mçi block chØ ®îc ¸nh x¹ vµo mét line duy nhÊt
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5.71. Khi truy nhËp cache, xÐt ¸nh x¹ liªn kÕt tËp hîp, ph¸t biÓu nµo sau ®©y lµ sai:
a. Mçi block cã thÓ ¸nh x¹ vµo mét line bÊt kú trong mét tËp line x¸c ®Þnh
b. Mçi block kh«ng chØ ®îc ¸nh x¹ vµo mét line duy nhÊt
c. Mçi block chØ ¸nh x¹ vµo mét line duy nhÊt trong mét tËp line x¸c ®Þnh
d. Mçi block chØ ®îc ¸nh x¹ duy nhÊt vµo mét tËp line x¸c ®Þnh
Ch¬ng 6. HÖ thèng vµo ra
6.1. Kh«ng thÓ nèi trùc tiÕp thiÕt bÞ ngo¹i vi (TBNV) víi bus hÖ thèng, v×:
a. BXL kh«ng thÓ ®iÒu khiÓn ®îc tÊt c¶ çc TBNV
b. Tèc ®é trao ®æi, khu«n d¹ng d÷ liÖu kh¸c nhau
c. TÊt c¶ cã tèc ®é chËm h¬n BXL vµ RAM
d. TÊt c¶ çc ý ®Òu ®óng
6.2. Chøc n¨ng cña Modul vµo/ra:

a. Nèi ghÐp víi BXL vµ hÖ thèng nhí
b. Nèi ghÐp víi mét hoÆc nhiÒu TBNV
c. C¶ a vµ b ®Òu ®óng
6.3. Çc thµnh phÇn c¬ b¶n cña TBNV:

a. Bé chuyÓn ®æi tÝn hiÖu, Logic ®iÒu khiÓn, Bé ®Öm
b. Bé chuyÓn ®æi tr¹ng th¸i, Logic ®äc, Bé ®Õm tiÕn
c. Bé chuyÓn ®æi hiÖn thêi, Logic ghi, Bé kiÓm tra
d. Bé chuyÓn ®æi ®Þa chØ, Logic nhËn, Bé ®Õm lïi
6.4. §èi víi chøc n¨ng cña Modul vµo/ra, ph¸t biÓu nµo sau ®©y lµ sai:
a. §iÒu khiÓn vµ ®Þnh thêi gian
b. Mét Modul chØ nèi ghÐp ®îc víi mét TBNV
c. Trao ®æi th«ng tin víi BXL, víi TBNV
d. Bé ®Öm d÷ liÖu, ph¸t hiÖn lçi
6.5. Cã çc ph¬ng ph¸p ®Þa chØ ho¸ cæng vµo/ra:

a. Vµo/ra çch biÖt
b. Vµo/ra theo b¶n ®å bé nhí
c. Vµo ra theo b¶n ®å thanh ghi
d. C¶ a vµ b ®óng
6.6. §èi víi ph¬ng ph¸p vµo/ra çch biÖt, ph¸t biÓu nµo sau ®©y lµ sai:
a. Kh«ng gian ®Þa chØ cæng kh«ng n»m trong kh«ng gian ®Þa chØ bé nhí
b. Dïng çc lÖnh truy nhËp bé nhí ®Ó truy nhËp cæng
c. TÝn hiÖu truy nhËp cæng vµ truy nhËp bé nhí lµ kh¸c nhau
d. Sö dông çc lÖnh vµo/ra trùc tiÕp
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6.7. §èi víi ph¬ng ph¸p vµo/ra çch biÖt, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Kh«ng gian ®Þa chØ cæng n»m trong kh«ng gian ®Þa chØ bé nhí
c. Sö dông çc lÖnh vµo/ra trùc tiÕp
d. Dïng chung tÝn hiÖu truy nhËp cho c¶ bé nhí vµ cæng vµo/ra
6.8. §èi víi ph¬ng ph¸p vµo/ra theo b¶n ®å bé nhí, ph¸t biÓu nµo sau ®©y lµ sai:
a. Kh«ng gian ®Þa chØ cæng n»m trong kh«ng gian ®Þa chØ bé nhí
c. CÇn cã tÝn hiÖu ph©n biÖt truy nhËp cæng hay bé nhí
d. Dïng chung tÝn hiÖu truy nhËp cho c¶ cæng vµ bé nhí
6.9. §èi víi ph¬ng ph¸p vµo/ra theo b¶n ®å bé nhí, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Kh«ng gian ®Þa chØ cæng n»m ngoµi kh«ng gian ®Þa chØ bé nhí
b. Ph¶i ph©n biÖt tÝn hiÖu khi truy nhËp bé nhí hay cæng vµo/ra
c. Sö dông çc lÖnh vµo/ra trùc tiÕp
d. Dïng çc lÖnh truy nhËp bé nhí ®Ó truy nhËp cæng
6.10. Cã 3 ph¬ng ph¸p ®iÒu khiÓn vµo/ra nh sau:

a. Vµo/ra b»ng ch¬ng tr×nh, b»ng ng¾t, b»ng DMA
b. Vµo/ra b»ng ch¬ng tr×nh, b»ng hÖ thèng, b»ng DMA
c. Vµo/ra b»ng ng¾t, b»ng truy nhËp CPU, b»ng DMA
d. Vµo/ra b»ng ng¾t, b»ng truy nhËp CPU, b»ng hÖ ®iÒu hµnh
6.11. Víi ph¬ng ph¸p vµo/ra b»ng ch¬ng tr×nh (CT), ph¸t biÓu nµo sau ®©y lµ sai:
a. Dïng lÖnh vµo/ra trong CT ®Ó trao ®æi d÷ liÖu víi cæng
b. TBNV lµ ®èi tîng chñ ®éng trong trao ®æi d÷ liÖu
c. Khi thùc hiÖn CT, gÆp lÖnh vµo/ra th× CPU ®iÒu khiÓn trao ®æi d÷ liÖu víi TBNV
d. TBNV lµ ®èi tîng bÞ ®éng trong trao ®æi d÷ liÖu
6.12. Víi ph¬ng ph¸p vµo/ra b»ng ch¬ng tr×nh (CT), ph¸t biÓu nµo sau ®©y lµ ®óng:
a. §©y lµ ph¬ng ph¸p trao ®æi d÷ liÖu ®¬n gi¶n nhÊt
b. §©y lµ ph¬ng ph¸p trao ®æi d÷ liÖu nhanh nhÊt
c. ThiÕt kÕ m¹ch phøc t¹p
6.13. Víi ph¬ng ph¸p vµo/ra b»ng ng¾t, ph¸t biÓu nµo sau ®©y lµ sai:
a. TBNV lµ ®èi tîng chñ ®éng trao ®æi d÷ liÖu
b. CPU kh«ng ph¶i chê tr¹ng th¸i s½n sµng cña TBNV
c. Modul vµo/ra ®îc CPU chê tr¹ng th¸i s½n sµng
d. Modul vµo/ra ng¾t CPU khi nã ë tr¹ng th¸i s½n sµng
6.14. Víi ph¬ng ph¸p vµo/ra b»ng ng¾t, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. TBNV lµ ®èi tîng chñ ®éng trong trao ®æi d÷ liÖu
b. Lµ ph¬ng ph¸p hoµn toµn xö lý b»ng phÇn cøng
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c. CPU lµ ®èi tîng chñ ®éng trong trao ®æi d÷ liÖu

d. Lµ ph¬ng ph¸p hoµn toµn xö lý b»ng phÇn mÒm
6.15. Sè lîng ph¬ng ph¸p x¸c ®Þnh modul ng¾t lµ:

a. 4 ph¬ng ph¸p
b. 3 ph¬ng ph¸p
c. 2 ph¬ng ph¸p
d. 1 ph¬ng ph¸p
6.16. Çc ph¬ng ph¸p x¸c ®Þnh modul ng¾t gåm cã:
a. KiÓm tra vßng b»ng phÇn mÒm vµ phÇn cøng, chiÕm bus, chiÕm CPU
b. NhiÒu ®êng yªu cÇu ng¾t, kiÓm tra vßng b»ng phÇn mÒm, chiÕm bus, chiÕm bé
nhí
c. ChiÕm bus, kiÓm tra vßng b»ng phÇn cøng, nhiÒu ®êng yªu cÇu ng¾t, ng¾t mÒm
d. NhiÒu ®êng yªu cÇu ng¾t, kiÓm tra vßng b»ng phÇn mÒm vµ phÇn cøng, chiÕm
bus
6.17. Víi ph¬ng ph¸p nhiÒu ®êng yªu cÇu ng¾t (trong viÖc x¸c ®Þnh modul ng¾t), ph¸t
biÓu nµo sau ®©y lµ ®óng:
a. CPU cã mét ®êng yªu cÇu ng¾t cho çc modul vµo/ra
b. CPU ph¶i cã çc ®êng yªu cÇu ng¾t kh¸c nhau cho mçi modul vµo/ra
c. Sè lîng thiÕt bÞ cã thÓ ®¸p øng lµ kh¸ lín
d. CPU cã nhiÒu ®êng yªu cÇu ng¾t cho mçi modul vµo/ra
6.18. Víi ph¬ng ph¸p kiÓm tra vßng b»ng phÇn mÒm (trong viÖc x¸c ®Þnh modul ng¾t),
ph¸t biÓu nµo sau ®©y lµ ®óng:
a. BXL kiÓm tra mét lóc nhiÒu modul vµo/ra
b. Tèc ®é kh¸ nhanh
c. BXL thùc hiÖn kiÓm tra tõng modul vµo/ra
d. BXL thùc hiÖn phÇn mÒm kiÓm tra tõng modul vµo/ra
6.19. Víi ph¬ng ph¸p kiÓm tra vßng b»ng phÇn cøng (trong viÖc x¸c ®Þnh modul ng¾t),
ph¸t biÓu nµo sau ®©y lµ sai:
a. BXL ph¸t tÝn hiÖu chÊp nhËn ng¾t ®Õn chuçi çc modul vµo/ra
b. Modul vµo/ra ®Æt vect¬ ng¾t lªn bus d÷ liÖu
c. BXL dïng vect¬ ng¾t ®Ó x¸c ®Þnh CTC ®iÒu khiÓn ng¾t
6.20. H×nh vÏ díi lµ s¬ ®å cña ph¬ng ph¸p x¸c ®Þnh modul ng¾t nµo:
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Thanh ghi ng¾t

INTR 3
INTR 2
INTR 1
INTR 0
Modul Modul Modul Modul

vµo ra vµo ra vµo ra vµo ra
BXL
a. KiÓm tra vßng b»ng phÇn mÒm

b. KiÓm tra vßng b»ng phÇn cøng
c. NhiÒu ®êng yªu cÇu ng¾t
d. ChiÕm bus
Cê
yªu INTR
cÇu
ng¾t

BXL

d. ChiÕm bus
Bus d÷ liÖu
Cê
yªu INTR
cÇu
INTA
ng¾t

BXL
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d. ChiÕm bus
6.23. Víi h×nh vÏ díi ®©y, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Ng¾t X vµ ng¾t Y cïng ®îc ®¸p øng mét lóc

b. §©y lµ s¬ ®å ng¾t lång nhau
c. Ng¾t X vµ ng¾t Y göi tÝn hiÖu yªu cÇu cïng mét lóc
d. Xö lý xong ng¾t X råi xö lý ng¾t Y
6.24. Víi h×nh vÏ díi ®©y, ph¸t biÓu nµo sau ®©y lµ sai:
a. §©y lµ s¬ ®å ng¾t tuÇn tù
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b. Ng¾t X ®îc phôc vô tríc ng¾t Y

c. Ng¾t Y göi yªu cÇu ng¾t tríc ng¾t X
d. Ng¾t Y ®îc phôc vô sau ng¾t X
6.25. Víi h×nh vÏ díi ®©y, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. §©y lµ s¬ ®å ng¾t tuÇn tù

c. Ng¾t X cã møc u tiªn cao h¬n ng¾t Y
d. Ng¾t X vµ ng¾t Y cã cïng møc u tiªn
6.26. Víi h×nh vÏ díi ®©y, ph¸t biÓu nµo sau ®©y lµ sai:
a. Ng¾t Y cã møc u tiªn cao h¬n ng¾t X

c. Ng¾t Y ®îc xö lý xong tríc ng¾t X
d. Ng¾t X ®îc xö lý xong tríc ng¾t Y
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6.27. Víi ph¬ng ph¸p vµo/ra b»ng DMA, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Lµ ph¬ng ph¸p do CPU ®iÒu khiÓn trao ®æi d÷ liÖu
b. Lµ ph¬ng ph¸p kh«ng do CPU ®iÒu khiÓn trao ®æi d÷ liÖu
c. Lµ ph¬ng ph¸p ®îc thùc hiÖn b»ng phÇn mÒm
d. Lµ ph¬ng ph¸p trao ®æi d÷ liÖu gi÷a TBNV vµ CPU nhanh nhÊt
6.28. Víi ph¬ng ph¸p vµo/ra b»ng DMA, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. TBNV dïng tÝn hiÖu DACK ®Ó yªu cÇu trao ®æi d÷ liÖu
b. CPU dïng tÝn hiÖu DREQ ®Ó tr¶ lêi ®ång ý DMA
c. DMAC göi tÝn hiÖu HRQ ®Ó xin dïng çc ®êng bus
d. DMAC göi tÝn hiÖu HLDA ®Ó xin dïng çc ®êng bus
6.29. Víi ph¬ng ph¸p vµo/ra b»ng DMA, ph¸t biÓu nµo sau ®©y lµ sai:
a. Hoµn toµn do DMAC ®iÒu khiÓn trao ®æi d÷ liÖu
b. §©y lµ qu¸ tr×nh trao ®æi d÷ liÖu gi÷a TBNV vµ bé nhí
c. CPU kh«ng can thiÖp vµo qu¸ tr×nh trao ®æi d÷ liÖu
d. CPU vµ DMAC kÕt hîp ®iÒu khiÓn trao ®æi d÷ liÖu
6.30. Víi ph¬ng ph¸p vµo/ra b»ng DMA, ph¸t biÓu nµo sau ®©y lµ sai:
a. §©y lµ ph¬ng ph¸p cã tèc ®é trao ®æi d÷ liÖu chËm
b. §©y lµ ph¬ng ph¸p cã tèc ®é trao ®æi d÷ liÖu nhanh
c. Tríc khi ®iÒu khiÓn, DMAC ph¶i xin phÐp CPU
d. Nhu cÇu trao ®æi d÷ liÖu xuÊt ph¸t tõ TBNV
6.31. Cã çc kiÓu trao ®æi d÷ liÖu DMA nh sau:
a. DMA c¶ m¶ng, DMA theo khèi, DMA mét lÇn
b. DMA ¨n trém chu kú, DMA mét nöa, DMA trong suèt
c. DMA mét nöa, DMA ¨n trém chu kú, DMA c¶ m¶ng
d. DMA theo khèi, DMA ¨n tr«m chu kú, DMA trong suèt
6.32. §èi víi ng¾t cøng, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Cã hai lo¹i ng¾t cøng
b. Mäi ng¾t cøng ®Òu ch¾n ®îc
c. Mäi ng¾t cøng ®Òu kh«ng ch¾n ®îc
d. Ng¾t cøng MI lµ ng¾t kh«ng ch¾n ®îc
6.33. §èi víi ng¾t cøng, ph¸t biÓu nµo sau ®©y lµ sai:
a. Cã hai lo¹i ng¾t cøng
b. Mäi ng¾t cøng ®Òu ch¾n ®îc
c. Ng¾t cøng MI cßn gäi lµ ng¾t INTR
d. Ng¾t cøng MI lµ ng¾t ch¾n ®îc
6.34. §èi víi ng¾t mÒm, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Do BXL sinh ra
b. Do TBNV göi ®Õn
c. Do lÖnh ng¾t n»m trong ch¬ng tr×nh sinh ra
d. Kh«ng ph¶i lµ lÖnh trong ch¬ng tr×nh
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6.35. §èi víi ng¾t mÒm, ph¸t biÓu nµo sau ®©y lµ sai:
a. Kh«ng do bé nhí sinh ra
b. Kh«ng do TBNV göi ®Õn
c. Kh«ng ph¶i lµ mét lÖnh trong ch¬ng tr×nh
d. Lµ mét lÖnh trong ch¬ng tr×nh
6.36. §èi víi ng¾t ngo¹i lÖ, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Lµ ng¾t do lçi ch¬ng tr×nh sinh ra
b. Lµ ng¾t tõ bªn ngoµi göi ®Õn
c. Lµ ng¾t tõ ROM göi ®Õn
d. Lµ ng¾t kh«ng b×nh thêng
6.37. §èi víi ng¾t ngo¹i lÖ, ph¸t biÓu nµo sau ®©y lµ sai:
a. LÖnh chia cho 0 sinh ra ng¾t ngo¹i lÖ
b. LÖnh sai có ph¸p sinh ra ng¾t ngo¹i lÖ
c. Trµn sè sinh ra ng¾t ngo¹i lÖ
d. Lçi bé nhí sinh ra ng¾t ngo¹i lÖ
6.38. Çc bíc cña qu¸ tr×nh DMA diÔn ra theo thø tù sau ®©y:
a. DREQ -> HLDA -> DACK -> HRQ -> trao ®æi d÷ liÖu-> kÕt thóc
b. DREQ -> HRQ -> HLDA -> DACK -> trao ®æi d÷ liÖu-> kÕt thóc
c. HRQ -> HLDA -> DACK -> DREQ -> trao ®æi d÷ liÖu-> kÕt thóc
d. HRQ -> DACK -> DREQ -> HLDA -> trao ®æi d÷ liÖu-> kÕt thóc
6.39. §èi víi kiÓu DMA theo khèi, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Lóc nµo bus rçi th× truyÒn d÷ liÖu
b. BXL bÞ Ðp buéc treo t¹m thêi tõng chu kú bus
c. TruyÒn kh«ng liªn tôc tõng byte d÷ liÖu
d. TruyÒn xong hÕt d÷ liÖu míi tr¶ l¹i bus cho BXL
6.40. §èi víi kiÓu DMA theo khèi, ph¸t biÓu nµo sau ®©y lµ sai:
a. BXL nhêng hoµn toµn bus cho DMAC
b. BXL kh«ng bÞ Ðp buéc treo t¹m thêi tõng chu kú bus
c. TruyÒn kh«ng liªn tôc tõng nhãm 2 byte d÷ liÖu
d. TruyÒn xong hÕt d÷ liÖu míi tr¶ l¹i bus cho BXL
6.41. §èi víi kiÓu DMA ¨n trém chu kú, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. BXL vµ DMAC xen kÏ nhau sö dông bus
b. BXL sö dông bus hoµn toµn
c. DMAC sö dông bus hoµn toµn
d. Khi bé nhí rçi th× DMAC dïng bus
6.42. §èi víi kiÓu DMA ¨n trém chu kú, ph¸t biÓu nµo sau ®©y lµ sai:
a. DMAC chØ sö dông mét sè chu kú nµo ®ã cña bus
b. BXL kh«ng sö dông bus hoµn toµn
c. DMAC sö dông bus hoµn toµn
d. D÷ liÖu kh«ng ®îc truyÒn mét çch liªn tôc
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6.43. §èi víi kiÓu DMA trong suèt, ph¸t biÓu nµo sau ®©y lµ ®óng:
a. Khi DMAC kh«ng dïng bus th× BXL tranh thñ dïng bus
b. Khi BXL kh«ng dïng bus th× tranh thñ tiÕn hµnh DMA
c. BXL vµ DMAC xen kÏ dïng bus
d. BXL bÞ DMAC Ðp buéc nhêng bus
6.44. §èi víi kiÓu DMA trong suèt, ph¸t biÓu nµo sau ®©y lµ sai:
a. Khi DMAC kh«ng dïng bus th× BXL tranh thñ dïng bus
b. DMA ®îc tiÕn hµnh khi BXL kh«ng dïng bus
c. BXL vµ DMAC dïng bus xen kÏ nhau
d. BXL vµ DMAC kh«ng cïng mét lóc dïng bus
Trang 53/53

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THI Kiến trúc máy tính và hợp ngữ (Thi

Câu hỏi 1 Consider the following assembly instruction sequence

Câu hỏi 2 Select correct match for AX (Decimal) at watch points:

watch point #1: 1064 1776

watch point #2: 266 1942

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intrasegment indirect mode

intrasegment direct mode

Câu hỏi 4 Structural components of computer include:

Central processing unit

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all choices are correct

Câu hỏi 6 the instruction, JMP C008:2000h is an example of

Câu hỏi 7 Given a row of memory image in debug

Answer: 4000 0899

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Câu hỏi 8 Given a code snippet:

Select one or more:

Đạt điểm 1,00 MOV AX,30

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Select one or more:

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Câu hỏi 16 Given a row of memory image in debug

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Câu hỏi 18 Memory dump at 1D20:0200 shown as below:

the maximum speedup of a multicore processor

the speedup of a multicore processor when increasing system bus speed

Load 16-bit value at memory location pointed by ES:[DI] into AX

Load 16-bit value at memory location pointed by DS:[SI] into AX

Split system bus into local bus and memory bus

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Make wider data bus path

Using higher-speed bus and us hierarchy

Đạt điểm 1,00 MOV DL,FF

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Câu hỏi 33 Given a flowchart of an algorithm:

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Select the correct instruction sequence:

Select one or more:

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Câu hỏi 36 Which of the following instructions are not valid?

MOV AX, [BP+2]

Đạt điểm 1,00 MOV AL, 0F

Zero flag (OF)

Câu hỏi 38 Major structural components of the CPU include:

Arithmetic and Logic Unit

Instruction Pointer (PC)

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