CHINESE JOURNAL OF MECHANICAL ENGINEERING

·940· Vol. 26, No. 5, 2013

DOI: 10.3901/CJME.2013.05.940, available online at www.springerlink.com; www.cjmenet.com; www.cjmenet.com.cn

Development of FPGA Based NURBS Interpolator and Motion Controller

with Multiprocessor Technique

ZHAO Huan, ZHU Limin*, XIONG Zhenhua, and DING Han

State Key Laboratory of Mechanical System and Vibration, Shanghai Jiao Tong University, Shanghai 200240, China

Received December 22, 2012; revised June 12, 2013; accepted June 24, 2013

Abstract: The high-speed computational performance is gained at the cost of huge hardware resource, which restricts the application of
high-accuracy algorithms because of the limited hardware cost in practical use. To solve the problem, a novel method for designing the
field programmable gate array(FPGA)-based non-uniform rational B-spline(NURBS) interpolator and motion controller, which adopts
the embedded multiprocessor technique, is proposed in this study. The hardware and software design for the multiprocessor, one of
which is for NURBS interpolation and the other for position servo control, is presented. Performance analysis and experiments on an
X-Y table are carried out, hardware cost as well as consuming time for interpolation and motion control is compared with the existing
methods. The experimental and comparing results indicate that, compared with the existing methods, the proposed method can reduce
the hardware cost by 97.5% using higher-accuracy interpolation algorithm within the period of 0.5 ms. A method which ensures the
real-time performance and interpolation accuracy, and reduces the hardware cost significantly is proposed, and it’s practical in the use of
industrial application.

Key words: NURBS interpolator, FPGA-based interpolation, multiprocessor, system on a programmable chip (SOPC),
motion controller

and may lead to fluctuation of interpolation period when

1 Introduction ∗ the sampling interval is too short. Furthermore, the clock
drift between the PC and motion controller may lead to
In modern commercial CAD/CAM systems, non-uniform
commands-gap or -overlap within one sampling interval.
rational B-spline(NURBS) has gained wide popularity and
To overcome these drawbacks, two tasks including
gradually become the standard format for representing the
interpolation and motion control can be performed
analytical or free-form profiles. Meanwhile, NURBS
simultaneously by the same microprocessor, such as digital
interpolators are also studied[1–7] and applied in the
signal processor(DSP) or FPGA. Then, the following
practical CNC systems. Some advanced CNC systems,
merits can be obtained: (1) the interpolator and motion
such as Siemens 840D and FANUC 32i, are already
controller share the same clock; (2) tinier interpolation
capable of performing NURBS interpolation. Due to the
period can be gained accurately; and (3) real-time
non-analytical relationship between the spline parameter
performance will be unnecessary for the PC, so that RTX
and arc-length, it is time-consuming to perform the
won’t be needed. Recently, DSP was introduced to
NURBS interpolation algorithm. In order to meet the
implement the aforementioned two tasks. However, the
high-speed and high-accuracy requirements of the
calculation speed of DSP cannot be enhanced too much due
machining process, it is essential to design an accurate and
to the serial calculation mode and limited computation
fast NURBS interpolator.
power. So, the interpolation period in most of the published
Nowadays, PC is usually adopted to perform NURBS
researches[2, 10–11] is not less than 1 ms. In contrast to PC
interpolation and motion control card to implement
and DSP with pipelined architecture, FPGA has advantages
closed-loop control in the open-architecture CNC
in terms of parallel computation and hardware
system[8–9]. In such case, the software real-time
reconfiguration capability. Thus, FPGA was employed by
extension(RTX) has to be installed to build a real-time
some researchers to overcome the drawbacks of the above
environment for the interpolation, which increases the cost
two methods. YAU, et al[12], realized the real-time NURBS
interpolator and motion controller using a Xilinx XCV600E
* Corresponding author. E-mail: zhulm@sjtu.edu.cn FPGA chip, which has 985 882 system gate counts. In their
This project is supported by National Key Basic Research Program of
China(973 Program, Grant No. 2011CB706804), Shanghai Municipal
work, all the modules are built using logic gates specified
Science and Technology Commission of China(Grant No. 11QH1401400), by hardware description language(HDL). When increasing
and Research Project of State Key Laboratory of Mechanical System & the degree of the NURBS curve or the data bits for more
Vibration of China(Grant No. MSVMS201102)
© Chinese Mechanical Engineering Society and Springer-Verlag Berlin Heidelberg 2013
accurate description or computation, the FPGA cannot
 CHINESE JOURNAL OF MECHANICAL ENGINEERING ·941·

afford the hardware cost. As a result, only 2-degree feedrate setting and adjustment subject to the kinematic
NURBS curve and 16-bits data can be processed. To cope constraints, as well as jerk-limited feedrate scheduling. In
with this issue, YAU, et al[13], later employed a Xilinx the last step, 5-phase S-shape feedrate profile is employed
XC2V4000 FPGA with 4M system gate counts, which can so as to realize smooth motion for less tracking error.
process 3-degree NURBS curve described by 32-bits data.
The total computational time for NURBS interpolation and
motion control with the above two methods is only about
1.84 μs. However, limited by the hardware cost, only the
interpolator based on the first-order Taylor’s expansion is
employed in above studies, which will inevitably cause
considerable feedrate fluctuation. Therefore, though the
interpolation speed is enhanced greatly, the computation
accuracy has to be sacrificed. In addition, with
consideration of the economic factor in practical
applications, it is not an optimal solution to choose a FPGA
with large resource.
This study presents a novel approach to design
FPGA-based NURBS interpolator and motion controller
using the embedded multiprocessor technique. With this
method, two free NIOS II soft cores are embedded into the
FPGA, one for NURBS interpolation while the other for
position servo control. Compared with the existing methods,
it needs less hardware resource but can implement more
complicated interpolation algorithms within the period of
0.5 ms.
The structure of this paper is organized as follows.
Section 2 gives an overview of the NURBS interpolation
and motion control scheme. Section 3 illustrates the
hardware configuration and software realization scheme of
the FPGA system. Performance analysis and experiments
are conducted in section 4. Finally, conclusions are
presented in section 5. Fig. 1. Flowchart of NURBS interpolation and motion control

2 NURBS Interpolation and Motion Control 2.2 NURBS interpolation algorithm

Scheme
In the interpolation process, two main steps are usually
involved: feedrate scheduling and interpolation. Generally,
feedrate scheduling can be implemented in on-line[9] or
off-line[14] mode. Because the arc-length of the NURBS
curve and the acceleration/deceleration (ACC/DEC) time
are determined using iterative approaches, the off-line
feedrate scheduling method is applied in this work. After
that, the information about the feedrate profile is
transferred to the interpolator via data file. The complete
NURBS interpolation and motion control scheme is
illustrated in Fig. 1. The feedrate scheduling is
The interpolator based on second-order Taylor’s
expansion is adopted in this work, which is given as[2]
vk Ts  (Ts2  2) Ak (v T ) 2 C (uk )C (uk )
uk 1  uk   k s , (1)
| C (uk ) | 2 | C (uk ) |4
where uk, vk, Ts, Ak, C(uk) and C(uk) denote the spline
parameter, scheduled speed, interpolation period, scheduled
acceleration, first and second derivatives of the curve,
respectively.
Generally, the NURBS curve is represented by[15]
n i

implemented in the PC while the interpolation and motion  N j , p (u)w j Pj  N j , p (u ) w j Pj

A(u )
j 0 j i  p
control are implemented in a FPGA chip located on a C (u )  n
 i
 , (2)
B(u )
custom motion control card.  N j , p (u)w j  N j , p (u ) w j
j 0 j i  p

2.1 Feedrate scheduling

The feedrate scheduling algorithm adopted in this work where Nj,p(u), p, wj, Pj and i represent the basis function,
is a combination of those methods proposed in Refs. [9, 14]. degree of the curve, weight, control point and the index that
It comprises the following major steps: curve scanning for u lies in the knot vector, respectively. The first and second
sharp corners and positions with discontinuous curvature, order derivatives of the parametric curve have the
 ZHAO Huan, et al: Development of FPGA Based NURBS Interpolator and Motion Controller
·942· with Multiprocessor Technique

following forms: Similarly, the derivatives of Q(u) can be calculated by

using the following equation:
A(u )  B (u )C (u )
C (u )  , i
B(u )
(3)
Q(u )( r )   N (j r, p) Pj 
j i  p
i i
A(u )  2 B (u )C (u )  B (u )C (u )
C (u ) 
B (u )
.  N (j r, 1)
p1 S j   N (j r,  2)
p  2T j ,
(6)
j i p 1 j i  p  2

To handle Eq. (1), de Boor-Cox algorithm[16–17] is where

employed to evaluate C(ui) and C(ui). Let Q(u) be a
B-spline, its value can be obtained by p ( Pj  Pj1 ) ( p 1)( S j  S j1 )
Sj  , Tj  . (7)
u j p  u j u j  p 1  u j
i i
Q(u )   N j , p (u ) Pj   N j , p1 (u ) Pj1 
Consequently, one can get
j i  p j i p 1
i
  N j ,0 (u ) Pjp  Pi p , (4) 
 Q(u )(1) 

i
N j , p1 S j  Sip1 ,
j i 
 j i p 1
(8)

 i
where Q(u )(2) 
  N j , p2T j  Ti p 2
,
 Pj ,
 h  0,  j i  p  2
Pjh    h h1 h h1

(1 α j ) Pj1  α j Pj , h  1, 2, , p.
 where Si p–1 and Ti p–2 can be derived by using Eq. (5).
u u j According to Eqs. (2)–(8), C(u), C(u) and C(u) can be
α hj  , u  [ui , ui 1 ], j  i  p  h, , i. (5)
u j  p 1h  u j computed in sequence.
As for the feedrate and acceleration required by Eq. (1),
their values can be obtained directly from the feedrate
Clearly, Eq. (4) can be calculated recursively with reference
profile, which has already been determined in the
to Eq. (5).
procedure of feedrate scheduling. Here, to reduce the
In this work, a computational structure is proposed to
computational load of the hardware interpolator, an
enhance the calculation speed. Without loss of
incremental method is adopted. For instance, in the first
generalization, the degree of the B-spline is set as three. As
phase of the feedrate profile, the speeds at the current and
illustrated in Fig. 2, two matrixes {Pjh} and {αjh} are
the next periods can be expressed as
involved, and the calculation process can be divided into
four steps. 
 1
Step (1): Bridge coefficients αjh are figured out with 
 v(t )  vstr  J max t 2 ,

 2
reference to the parameter uj, and stored into the buffer,  (9)

v(t  T )  v  1 J (t  T ) 2 ,
where j  i  p  h, , i , and h  1, 2, , p .  s str max s

 2
Step (2): The iterative computation of Pjh begins from the
fourth column shown in Fig. 2. At this column, the value of where vstr, Jmax and t are the starting speed, maximum jerk
each element is set to be the corresponding control point Pj. and relative time that starts from the beginning of the
current period. Assuming Jmax2 to be constant, two
multiplications and two additions are needed with this
equation. Alternatively, the ending speed can be calculated
using the following expression:


 1 2

∆v(t )  v(t  Ts )  v(t )  J max Ts t  J max Ts ,
 2 (10)


v(t  Ts )  v(t )  ∆v(t ),


Fig. 2. Computational structure for the de Boor-Cox algorithm

Step (3): The value of each element located at the upper
triangular region of {Pjh} is calculated using Eq. (5). Then
the values are saved into the buffer for the next iteration.
Step (4): Finally, the first element of matrix {Pjh} is
picked out as the desired result Q(u).
which needs only one multiplication and two additions. So
Eq. (10) is employed instead of Eq. (9). To use this method,
the expressions of Δ(v )t and acceleration A(t) in the five
different phases of the S-shape feedrate profile are listed in
Table 1. Where Tstr, Tcv and Tend are the acceleration time,
constant-feedrate time and deceleration time of the
 CHINESE JOURNAL OF MECHANICAL ENGINEERING ·943·

ACC/DEC process, respectively. complicated algorithms are modularized with this method,
the hardware cost may be larger than the benefit it brings.
Table 1. ∆v(t) and A(t) in different stages In order to solve this issue, a method integrating CPU IP
of the feedrate profile core, HDL and logic blocks is proposed. The CPU
ACC/DEC processors are utilized to perform interpolation and position
Expressions of ∆v(t) and A(t)
stage servo control, while the HDL or block diagram to
∆v(t )  J maxTst  J maxTs 2  2, modularize the logical circuits.
Phase 1
A(t )  J max t In this work, NIOS II for the FPGA from Altera is
∆v(t )  J maxTst  J maxTs 2  2  2 J maxTstrTs , employed as the soft-core. NIOS II processor provides
Phase 2
A(t )  J maxTstr  J max t various attractive features such as 32-bits data path,
Phase 3 ∆v(t )  0, A(t )  0 embedded DSP element, floating-point instructions(FPIs)
∆v(t )  J maxTst  J maxTs 2  2  2 J maxTstrTs  J maxTcvTs , for single-precision operations[20]. In addition, the
Phase 4
A(t )  J max (2Tstr  Tcv  t ) computational performance of NIOS II can be up to
∆v(t )  J maxTst  2 J maxTstrTs  2 J maxTendTs  J maxTcvTs , 250DMIPS, and multiprocessor is also supported. Since all
Phase 5
A(t )  J max (t  2Tstr  Tcv  2Tend ) the procedures are written in standard C language and
debugged the same as that in the PC, it is more convenient
than the HDL based method.
2.3 Motion control algorithm
In this work, the traditional PID controller expressed in 3.1.2 Hardware structure
Eq. (11) is chosen for closed-loop position control: The motion control system is implemented using a
k
Cyclone II series FPGA EP2C20F484C8N from Altera,
u (kTs )  K p E (kTs )  K i  E ( jTs )  which contains 18 752 logic elements (LEs), 239 616 bits
j 0
random access memory (RAM), 26 embedded multipliers,
K d  E (kTs )  E ((k 1)Ts ) , (11)
4 phase-locked loops (PLLs) and 315 user I/O pins. The
hardware structure is depicted in Fig. 3.
where u(kTs), E(kTs), Kp, Ki and Kd represent the velocity
control signal, the position error and three gains,
respectively.

3 Design of FPGA based Interpolator

and Motion Controller
In this section, multiprocessor technique is applied to
design the FPGA-based NURBS interpolator and motion
controller. The FPGA development flow consists of two
stages: hardware design with a set of functional modules,
and software development in three steps.

3.1 Hardware design
3.1.1 Realization scheme
In the traditional motion control system, the combination
of DSP and FPGA is the most popular hardware
architecture[18–19]. Sharing the same clock cycle, DSP is
adopted to perform various algorithms for motion control
while FPGA to generate logical modules with parallel
structures which cannot be realized by DSP. However, with
the developments of the large scale integration technology
and embedded DSP elements, it is more cost-effective to
design motion control system just employing FPGA due to
its reconfiguration capability, simple development process,
high density and economic characteristic.
The methodologies for development of FPGA include
HDL, dedicated logic blocks, intellectual property (IP)
cores, etc. Nowadays, the interpolator and motion
controller are usually designed using HDL. In such case,
the FPGA system can execute concurrent operations
because of its parallel architecture. However, when
Fig. 3. Structure of the FPGA that configured for NURBS
interpolator and motion controller
As shown in Fig. 3, the FPGA consists of five main
modules: 1) NURBS interpolator; 2) dual-port RAM
(DPRAM); 3) mutual exclusion (MUTEX) and shared
memory[21]; 4) position servo controller; 5) encoder sampler.
The other relative peripherals comprise digital-to-analog
converter (DAC) and amplifier, SDRAM and FLASH chip.
1) NURBS interpolator: The interpolator is designed
using NIOS IIs processor, which is the standard version
with balanced performance and size among three kinds of
NIOS II processors[20]. The dominant frequency provided
for the processor is 133 MHz, which is generated by the
PLL. An interval timer core is also embedded to generate
the timer interrupt for both the interpolator and motion
controller.
2) DPRAM: A DPRAM with 2 00016-bits is designed
using the on-chip RAM[22], which is utilized to store the
feedrate scheduling results transferred from the PC and
 ZHAO Huan, et al: Development of FPGA Based NURBS Interpolator and Motion Controller
·944· with Multiprocessor Technique
provide them to the interpolator.
3) MUTEX and shared memory: The shared memory is a
1632-bits DPRAM, which is used to transfer the
interpolated results from the interpolator to the motion
controller at every sampling interval. In order to protect the
resources in the shared memory from data corruption when
multiple processors modify the resource simultaneously, a
MUTEX is added as a component.
4) Motion controller: The configuration of the motion
control processor is the same as the interpolator. It receives
reference commands from the shared memory, and sends
the velocity control signal to the DAC chip utilizing serial
peripheral interface (SPI) protocol.
5) Encoder sampler: This circuit is designed using HDL.
So it is capable of capturing and accumulating the
quadrature encoder pulses(QEP) with high speed. The
actual positions are latched and updated at every clock
cycle.
The DAC module contains two components: converter
and amplifier. Two AD1866 devices, which have 16-bits
serial input and four voltage outputs, are adopted to convert
the digital velocity commands to analog signals. A TL084
chip is utilized to amplify the analog signals from 1~1 V
to 10~10 V. A SDRAM chip K4S641632H-UC60 and a
FLASH chip JS28F640 are used to save the program and
data of the NIOS II cores.
3.2 Software design
The software is designed in three steps: realization of the
off-line feedrate scheduling, configuration for the
interpolator and motion controller, and programming for
two NIOS II processors.
3.2.1 Realization of the off-line feedrate scheduling
The feedrate scheduling algorithm presented in section
2.1 is coded in Visual Studio C++, and executed in a
non-deterministic Win32 environment.
After implementation of the algorithm, a data file
containing the following information is generated: the
geometrical description of the NURBS curve, which
contains the number of the control points, degree of the
spline, control points multiplying the weights, weight
vector, knot vector; number of the sub-segments; total
interpolation time; Jmax, vstr, ACC/DEC time/modes.
Then, a normal Win32 thread reads the data file
sequentially, and sends the information of a new NURBS
curve to the motion controller at the time that the FPGA
finishes half of the current block’s interpolation task.
3.2.2 Configuration for soft-cores
The follow chart of software design for the FPGA system
is depicted in Fig. 4.
Firstly, the SOPC Builder tool, which is integrated in the
Altera Quartus II software, is applied to customize the
configuration of the two processors, so as to build the
hardware environment for the program running in the NIOS
II cores. The following modules are then added into the
configuration: two NIOS II/s cores used as interpolator and
motion controller, Avalon-MM tri-state bridge, interval
timer which interrupts at every 0.5 ms, MUTEX, interface
for the FLASH memory, SDRAM memory, DPRAM and
shared memory. In order to hardware-accelerate the
arithmetic operations, the FPIs for single-precision
operations are adopted in the interpolator[23].
Fig. 4. Software design flow for the FPGA based
interpolator and motion controller
Secondly, the block of the NIOS II processor is
integrated into the Quartus II. The other functional circuits
or logical modules are added as well, including encoder
sampler, DPRAM and shared memory. With pins connected
and assigned, the project is analyzed and synthesized. Then
a SRAM object file (*.sof) is generated and downloaded to
the FPGA. Up to now, the hardware environment is ready
and then the software in the NIOS II IDE can be developed.
3.2.3 Programming for multiprocessor
NIOS II IDE is an integrated development tool for
editing and debugging procedures running in the NIOS II
processors.
Two projects are created for NURBS interpolator and
motion controller, respectively. The project of the NURBS
interpolator consists of two threads: timer interrupt thread
and loop thread. During the implementation of the loop
thread, the interpolator accesses the DPRAM repeatedly to
check whether updated feedrate scheduling results are
transferred from the PC via the PCI bus. If so the
interpolator will read the data into the buffer to prepare for
the interpolation of the next curve. When the timer interrupt
occurs, the interpolation interrupt service routine (IISR)
executes the interpolation task introduced in section 2.2 and
sends the coordinate points to the shared memory.
The project of the motion controller has the similar
software structure to that of the interpolator. At every
sampling interval, the motion controller reads the position
 CHINESE JOURNAL OF MECHANICAL ENGINEERING
commands from the shared memory and actual positions
from the encoder sampler, and then executes the PID
algorithm. After that, the digital velocity commands are
transferred to the DAC chip for conversion.
The aforementioned two NIOS II processors have
pipelined architectures, so the processing time is inevitably
longer than the scheme based on HDL or logic block.
However, all of the modules in the FPGA execute in
parallel, so interpolation and motion control tasks can be
implemented at the same time, which means that higher
real-time performance can be obtained than DSP-based
scheme with the same dominant frequency.
4 Analysis and Experiments Validation
In the following, performance analysis and experimental
verification are implemented to demonstrate the advantages
and applicability of the proposed design. Concisely, the
design schemes introduced in Refs. [12–13] are marked as
methods (1) and (2), respectively, while that presented in
our work as method (3).
4.1 Performance analysis
Suppose that the axes number and curve degree are three,
the comparison results about hardware cost and consuming
time among the three different approaches are summarized
in Table 2. Generally, the hardware cost of Cyclone series
FPGAs from Altera is evaluated by the number of LEs.
However, for the purpose of comparison, the amount of
LEs should be converted to that of logic gate counts by
multiplying 8–21 depending on different applications[24].
Typically, one LE is equivalent to 12 logic gates. In our
work, 2 264 LEs are modularized for the NURBS
interpolator and 2 129 LEs for the motion controller, which
means 27 168 and 25 548 logic gates are consumed,
respectively. Furthermore, the computational time for
interpolation and motion control are 297 μs and 30 μs,
respectively. Because of parallel implementation, the total
time spent is indeed the interpolation time.
Table 2. Comparison results of three different methods
Schemes of NURBS interpolator Method Method
and motion controller (1) (2)
Number of motion axes Na 3 3
Order of Taylor’s expansion Nt 1 1
Number of data bits Nb 32 32
Degree of NURBS curve p 3 3
Gate counts for interpolator Ngi103 1 098 1 098
Gate counts for motion controller Ngc10 3
504 504
Total time spent for interpolation
NA 1.84
and servo control ttotalμs
Note: NA stands for “Not Available”, which means the FPGA doesn’t
have enough hardware resource to realize the interpolation.
From Table 2, it can be found that higher-accuracy
algorithm can be adopted by our method. Meanwhile, the
proposed method can reduce the hardware cost by 97.5% as
·945·
compared to that of method (1)(2). However, the results
indicate that the computing efficiency of our method is
worse than that of method (1)(2). But given the specified
interpolation period of 0.5 ms, there is still enough
computational power for more complex algorithms with the
proposed method. Thus, the analysis demonstrates that our
method can not only meet the requirement of high-speed
interpolation, but also realize significant reduction of
hardware cost, at the same time provide enough resource
for further promotion of computational accuracy.
4.2 Experimental results
In this subsection, experiments are performed on a
platform containing three components: a PC with Pentium
IV 2.4 GHz CPU and 2 GB SDRAM, a custom motion
control card which has a FPGA chip as designed in section
3, an X-Y table driven by YASKAWA SGDV series servo
drivers and SGMJV motors with free load. The
interpolation and motion control tasks are performed in
sequence in the following, and the parameters of the
interpolator and motion controller are listed in Table 3.
Table 3. Parameters of the experiments
Parameter Value
Chord error tolerance εcmm 0.001
Arc-length error tolerance εaµm 1
Interpolation/motion control period Tsms 0.5
Maximum feedrate Fmax(mm • s–1) 100
Curvature constant κcbcmm–1 1
Maximum acceleration Amax(m • s–2) 3
Maximum jerk Jmax(m • s–3) 60
6 553.6
Encoder resolution Er(pulse • mm–1)
Proportional gains for two axes Kps–1 2.93
Integral gains for two axes Kis–2 0.015 3
The butterfly curve similar to Ref.[13] is chosen as the
experimental case, which has 51 control points and 3
degree. The trajectory of the curve is shown in Fig. 5.
Method
(3)
3
2
32
3
27.168
25.548
297
Fig. 5. Trajectory of the butterfly curve
Firstly, the feedrate scheduling algorithm mentioned in
section 2 is performed, and the scheduled feedrate profile
can be obtained as shown in Fig. 6.
 ZHAO Huan, et al: Development of FPGA Based NURBS Interpolator and Motion Controller
·946· with Multiprocessor Technique

where xk , yk and zk are the actual feedrates of three axes.

Fig. 6. Feedrate profile after off-line feedrate scheduling

Subsequently, the interpolation task is performed, and

Fig. 8. Contour error for the butterfly curve
the reference commands are sent to the motion controller with method (3)
for PID calculation. As shown in Fig. 7, by applying the
first- and second-order Taylor’s expansions in our hardware
system, the maximum feed fluctuation ratios are 2.08% and
0.135 7%, respectively. Therefore, with our method higher-
accuracy performance can be obtained.

Fig. 9. Actual feedrate of the platform

with method (3)
As can be seen, the maximum contour error can be
confined under 25.52 μm, and the root mean square value is
9.692 4 μm. Moreover, the platform can realize the motion
with the scheduled feedrate profile as shown in Fig. 9.
Hence, the experimental results demonstrate the practical
applicability of the proposed method with higher-accuracy.
Fig. 7. Feedrate fluctuation comparison
between methods (1)(2) and (3)
5 Conclusions

Finally, the X-Y table is driven by the motion control (1) A novel approach to design the hardware interpolator
card to track the desired trajectory. The experimental results and motion controller based on FPGA is proposed. A
about contour error and actual feedrate profile using FPGA chip from Altera is selected as the microprocessor
method (3) are illustrated in Fig. 8 and Fig. 9. The contour on the board. Two NIOS II soft-cores are embedded into
error is evaluated using the algorithm presented in Ref. [25], the FPGA, one of which works as NURBS interpolator and
while the actual feedrate vk* is evaluated using the the other as motion controller.
numerical derivatives estimated from actual x-, y- and z- (2) The feedrate scheduling algorithm is implemented
positions: off-line and a data file is generated. Then, a normal Win32
thread sends the feedrate scheduling results to the custom
motion control card to perform real-time interpolation and
xk 1  xk y  yk position servo control.
xk  , yk  k 1 , (3) Performance analysis and experiments are conducted
Ts Ts
(12) to verify the superiority and applicability of the proposed
zk 1  zk *
zk  , vk  xk 2  yk 2  zk 2 , method. The results have shown that, despite some
Ts reduction of computational efficiency compared with the
 CHINESE JOURNAL OF MECHANICAL ENGINEERING
existing FPGA-based interpolators, higher-accuracy
interpolation algorithm can be adopted using less hardware
resource with specified sampling interval of 0.5 ms.
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Biographical notes
ZHAO Huan, born in 1983, is currently a PhD candidate at State
Key Laboratory of Mechanical System and Vibration, Shanghai
Jiao Tong University, China. He received his bachelor degree
from Jilin University, China, in 2006. His research interests
include parametric interpolation and contour following control for
CNC machine tools.
Tel: +86-21-34206412; E-mail: huanzhao@sjtu.edu.cn
ZHU Limin, born in 1973, is currently a professor at Shanghai
Jiao Tong University, China. He received his PhD degree from
Southeast University, China, in 1999. His research interests
include surface modeling, CNC machining and inspection.
E-mail: zhulm@sjtu.edu.cn
XIONG Zhenhua, born in 1974, is currently a professor at
Shanghai Jiao Tong University, China. He received his PhD
degree from The Hong Kong University of Science & Technology,
China, in 2002. His research interests include servo motion
control and electronic manufacturing.
E-mail: mexiong@sjtu.edu.cn
DING Han, born in 1963, is currently a professor at Shanghai
Jiao Tong University, China. He received his PhD degree from
Huazhong University of Science and Technology, China, in 1989.
His research interests include digital and electronic
manufacturing.
E-mail: hding@sjtu.edu.cn