O Difference between microprocessor and miro ceteler

Microprocesor Micro cortroler

Micro proceboris her t c tte D Mi°o cortroller is heart t the
computer systern. erbedded ystem.
i) It is just a pocesD,memoryD hey are proceos alerg witn
amd Ilo are conected externally iterral memory exter ral comporents
) ost entire systern increaus. Cost ertire ston is dow.
iD Cant be wsd in compadD mbe used in (empaut yterns
Syotens & hence in effüent. omd hence they are efiuert.
Due to exterral components power Since exteral cemporents re pw,
Consmptien is high. power cenunpien is low.

Leas number efo regsters, horce op More umberes reguteo,hone

are memory basd. Prgomms are easier to write
v) Baad en Von Neumann macdel. i) Baysd en Harvad architeture.

Speed is relathvely stower. ) Sfoed &fest

Mainy usod in Posoral computers bd mainly in MB Payeas
machines.
The dircut becomes large,since he craut bSmall, ine memory
devices are cenneted exterly. od I/o e preset intenally.
Hgher cdoce speed Low dok Speed.
x) Extera! Buw is wod to Irterface Uoes Irternal bus or cenmunicatien
with devices. ond for iterfairg
2 Expain RISC degn philesophy.
ARM core usRs RISC archi tecture. It ua desgn phiosephy
tht exealte
aimed at deliverig snple but powerful instuch oy
in a sirge doch yce
" RISC philesophy concentrate on redurg the compexity &irstructibu
peformed by the harcure
Four Major Design Ales:
DInstuctiens:
lawes.
> Reduced numbor ot instruct en
>
Simple oeaiens that can be exeuted in aingle yce.
>Compler synthesze cmplated instructions y combining simle
instructens
> Each instructien btfred Jerngth
DPpelines:
> Proceina t instructerns is broken down into saller ni t
5that can be exected in prallel.
> Intruchens ccn be deco ded in one ppeine stoge
i) Registes: b
> larger nunber greral puTpse reg terset.
>Aruy regter cam certaun eiter data or an addre.
i Lodstore Architecture:
>Procesor oprte) ondato held in regsters.
Soperate lcad and store instructiens tramsfers df data botwean
reguter bank ond erteral memory.
Since memory occes is syto repatgt multpe times
wald reduce ettaenoy ond increases tine.
Eaplain ARM desgn pilaophy.
The feotures tat haup crion tte ARM procesor deaig
Desigred to be sall to reduce power cerumpthen ordexterd
batery ife.
High code density to congirsate for hawirg mtd
mernorg
ARM hos incor porated hacwre debug technology within be
rocesso.
They are price Sensitve amd use slow low cost memoy deuices.
Instructen set for Embedded te use
) Var able cyce exeaton tor Certain instructieny
> Nol eery ARM instucin exeautes n a age yde.
> The tramster con occur on seqential memory
addreses, uhh
irreas perfomemce.no
ode densty is abo improed since multple regutar tronstexs are
cermme at starty end e fnctieeder
o,snabci
DInine barrel shiter eocng to more cemple instructien:
harcvaro Cernporent t t pre processes ore
>It isS a tinput
registers betre it D usod by on intucteny.
> Lmproved core performce amd cocde densi ty.
iD Thuob (6-bit instructen set:
> ARM Uenhanced hy adcing
O t6-bite nset which permit the
ARM ore to exete l6 or82 bit instructten.
>16-bit insachens improve code dersi ty y about 3o / over
32-bit fxed length instructheny.
 D ordiberal executho
inthucion that s eXeeuted uhena soecikc cond ten
>T1 D an
has becn satsfed.
It improves prfomonc ond code der yby redcigbrcmch
inyructer

Enhonced Trstruchons:
> The enhamced Digtal Sgrd Processor (DSp) in struchers were
added to the stordard ARM Inshruchen set tosupport fat
l6x\6bit mulhlier oRratonu and atwatien.

@apbin ARM Embedded software Jayprs with aat dicgrm.

Appliccten
|Operbry sterme
Enbalizatie Device Driver
Hardware device
Fg Softuae absrachon layer eceautrg on horduare.
" The initaizaten code is the first code executed on he b0ard
and it Jets up he minimun part t the boad before

hording contrel over to the oprabng ytem.

the operabng syte provides an infrastructure to centro
appiabens ond monog narrare tem resees. Many
errbected systern do not feque afull arang yotern but
merely a imple tsk shecler thot ls ei ther event or d
driven.
 " The device drivers are the hird compo nent.They provide a
conssternt software nterface to the prpherals on the havcware
device
Applicahon perform ore o the (asks requur ed foradovice
The software cemporent on run frern ROM oy RAM. ROM code
that ued on the device code y caed hrmMre.
Inibalzatien ode takes the proe) or from the rest state toa
run state, where tte operatiag system con un.
It conkgues:
> Memory contrallers tou
> ProceOr cache
> Iitiaizes some dev ices. ro
* Booting inveves looding an imag and harding entrol over to that
image.
6
Ecplain the excepheng ond interruptt in ARM procer with mremiry
locaien.N
When an eccepen or interrupt Ocrs, the
proceshorset the r
to a speutic memory addrebs.y oabay oot C
The oddre, is within a specific
speifc adcre ronge, called the vector table.
he entries in tte vector table are instrucons that brnch to
speihc reutnes desigred to horrcle a partulor ercepti en or
interuppt bozu91

The memory moap adare Ox0000 0000 i reberved for the vecr
table, a Jet 32 bl Worc.
" when an exceptern or interrupt occurs,the prcessor susporel
nomal eyeute Ondd starb dooding instrachens frem te eceoh o
Vector table
" Some cemnen vetoy insruehons
Reset Vector ox00000 000): Aaation o frst isuchon exeatad
by proessor uhen power is appied. It brcmehes to inibalzahe
cocde
Unde hned instucten
Connet decocle n
vecorfoxomoo041:ued when processor
inshructien.
Software Interrupt Vechor LoKOO0 00008): It) caled wen
yeu
exeaute a swI instructien It is und to
invoke m as reubino
> Pretet dh abort
ectoroxo000000
to teteh am insrucho from n
C: uhen proeAsor atempt
addread without the correct
aCLeb perrmssier
> Data abort vectoroO000OCO] :It s rased when
an
instructin atterpt to aces dta memory itheut the
Correct acces permisiers.

Interrupt rauest ector [oxocoooo13: Usecl by exterral

hoelaae
to interruot nommal ereutien ftow ot procesor. It an be
rauje it Ra are no maskd in the CPSR.
Fat nterrupt reouest vechor: It
revesed tor hordrre
requiig festor repone bmey. It an eny be rab ed rt
FEa, are not masked in SR.