Exclusive-OR and Ex-NOR

(or)Equivalence gate
„ Exclusive-OR and Equivalence gates perform the following
Boolean functions

A ⊕ B = A B + AB
A•B = AB + AB

„ The two operations are the complements of each other. Each

commutative and associative.
associative

( A ⊕ B ) ⊕ C = A ⊕ (B ⊕ C ) = A ⊕ B ⊕ C
EC214 Digital Logic Design
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„ Implementation of a two-input exclusive-OR function with
AND, OR, and NOT gates.

A⊕ B

„ Implementation of a two-input exclusive-OR function with

NAND gates.

A⊕ B

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„ Implementation of a two-input exclusive-NOR function
with AND, NOR, and NOT gates.

„ Implementation of a two-input exclusive-NOR function

with NOR gates.

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„ When the number of variables in a function is odd, the
minterms with an even number of 0’s are the same as the
minterms
i t with
ith an odd
dd number
b of
f 1’s.
1’ Th
Therefore,
f an exclusive-
l i
OR expression is equal to an equivalence expression.

BC 00 01 11 10 BC 00 01 11 10
A A
0 1 1 0 1 1
1 1 1 1 1 1

„ When the minterms of a function with an odd number of

v ri bl s have
variables h v even
v n numb
numberr off 1’s
1 s orr an
n odd
dd numb
numberr of
f 0’s
0 s, the
th
function can be expressed as the complement of either Ex-OR
or an equivalence expression.

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„ An n-variable exclusive-OR expression is equal to the Boolean
functions with 2n/2 minterms whose equivalent binary numbers
have an o
ha odd num
numberr of 1’s.
s. The
h funct
function
on can expressed
pr ss in
n tterms
rms
of the exclusive-OR operation on the four variables.

CD 00 01 11 10 CD 00 01 11 10
AB AB
00 1 1 00 1 1
01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 10 1 1

„ An n-variable whose equivalent binary numbers have an even

number of 0 0’ss. The function can expressed in terms of the
equivalance operation on the four variables.
EC214 Digital Logic Design
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 Combinational Circuits
„ Define Combinational Circuit
„ Combinational circuit defines as the out put of the
combinational circuit at any instant time depends only on the
present state values at that time.
„ The block diagram of the combinational circuit show in figure

„ A combinational circuit consists of n input variables,

variables logic gates
and m output variables
EC214 Digital Logic Design
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 Design Procedure of Combinational Circuits
„ Identify the inputs and outputs of the combinational logic
circuit and draw a block diagram.

„ Draw a truth table such that it completely describes the

operation of the circuit.

„ Write down the Boolean function for the outputs

„ Simplify the Boolean function for the output using Boolean

algebra (or) k-map.

„ Draw the logic diagram.

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 Half Adder
„ Half adder is a combinational circuit which performs the
arithmetic addition of two binary digits.

„ Half Adder consist of a two input and two output,

output two input
denote A and B two outputs denotes sum and carry

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 Truth Table of the Half Adder

input out put

A B Sum carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

The Boolean expression of Half Adder

sum(A,B) = ∑ (1,2)

carry(A,B) = ∑(3)

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 B B
A 0 1 A 0 1
0 1 0

1 1 1 1

sum = A B + A B
carry = AB
A⊕ B
Logic diagram of the Half Adder is show in Fig.

It can be implemented with an exclusive-OR and an AND gate.

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 Full Adder
„ Full adder is a combinational circuit which performs the
arithmetic addition of three binary digits.

„ Full Adder consist of a three input and two output, three input
denote A B and C two outputs denotes sum and carry

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 Truth Table of the Full Adder

In puts Out puts

A B C Sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

The Boolean expression of Full Adder

sum(A B C) = ∑ (1,2,4,7)
sum(A,B,C) (1 2 4 7) carry(A B C) = ∑(3,5,6,7)
carry(A,B,C) ∑(3 5 6 7)
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 BC 00 01 11 10 BC 00 01 11 10
A A
0 1 1 0 1

1 1 1 1 1 1 1

sum = A ⊕ B ⊕ C carry = AB + BC + AC
the circuit
th i it di
diagram of
f th
the full
f ll adder
dd implementing
i l ti with
ith two
t
half adders and OR gate is show in Fig

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 Half Subtractor
„ A Half Subtractor is a combinational circuit that subtract two
bits and produces their difference.

„ Half Subtractor consist of a two input and two output,

output two
input denote A and B two outputs denotes Difference and
Borrow

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 Truth Table of the Half Subtractor

input out put

A B Diff Borrow
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

The Boolean expression of Half Subtractor

Difference (A,B) = ∑ (1,2)

Borrow (A,B) = ∑(1)

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 B B
A 0 1 A 0 1
0 1 0 1
1 1 1
__ __ __
Difference = A B + A B Borrow = A B
L i di
Logic diagram of
f the
th Half
H lf Subtractor
S bt t isi show
h in
i Fig.
Fi

It can be implemented with an exclusive-OR , NOT and an AND

gate. EC214 Digital Logic Design
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 Full Subtractor
„ A Full Subtractor is a combinational circuit that subtract
three bits and produces their difference.

„ Full Subtractor consist of a three input and two output, three

input denote A B and C two outputs denotes Difference and
Borrow

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 Truth Table of the Full Subtractor

In puts Out puts

A B C Diff Borrow
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

The Boolean expression of Full Subtractor

Diff(A B C) = ∑ (1,2,4,7)
Diff(A,B,C) (1 2 4 7) Borrow (A,B,C)
(A B C) = ∑(1,2,3,7)
∑(1 2 3 7)
EC214 Digital Logic Design
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 BC 00 01 11 10 BC 00 01 11 10
A A
0 1 1 0 1 1 1

1 1 1 1 1
__ __
Difference = A ⊕ B ⊕ C Borrow = AB+ AC + BC
the circuit
th i it di
diagram of
f th
the full
f ll Subtractor
S bt t implementing
i l ti with
ith
two half subtractor and OR gate is show in Fig

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 Magnitude Comparator
„ A Magnitude comparator is a combinational circuit that compares
two numbers, A and B, an determines their relative magnitudes.
„ The outcome of the comparison is A > BB, A = BB, A < B.
B
„ The circuit for comparing two n-bit number has 22n inputs in
the truth table and it becomes too cumbersome even with n=3

„ Block diagram of magnitude comparator show in fig

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Design 1 – bit Magnitude Comparator

Block diagram of 1 bit comparator

Truth table of 1 bit comparator

input output
A B A<B A=B A>B
0 0 0 1 0
0 1 1 0 0
1 0 0 0 1
1 1 0 1 0
EC214 Digital Logic Design
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The Boolean expression of 1 Bit Magnitude Comparator

A<B = ∑ (1) A=B = ∑(0,3

∑(0 3 ) A> B= ∑(2)

A< B = AB
A> B = AB
A= B = AB + AB
Logic diagram of the 1 Bit Comparator is show in Fig.

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 Design the 2 bit magnitude Comparator

Block diagram of 2 bit comparator

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 Truth table of 2 bit comparator

input output input output

A1 A0 B1 B0 A<B A A>B A1 A0 B1 B0 A<B A A>B
= =
B B
0 0 0 0 0 1 0 1 0 0 0 0 0 1
0 0 0 1 1 0 0 1 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0 1 0 0 1 0
0 0 1 1 1 0 0 1 0 1 1 1 0 0
0 1 0 0 0 0 1 1 1 0 0 0 0 1
0 1 0 1 0 1 0 1 1 0 1 0 0 1
0 1 1 0 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 1 1 1 1 0 1 0

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The Boolean expression of 2 Bit Magnitude Comparator

A<B = ∑ (1,2,3,6,7,11)
(1 2 3 6 7 11)
A=B = ∑(0,5,10,15 )
A> B= ∑(4,8,9,12,13,14)

A=B = ∑(0,5,10,15 )
xi = Ai Bi + Ai Bi
B1 B0 00 01 11 10
A1 A0
00 1
A1 A0 B1 B0 + A1 A0 B1 B0 + A1 A0 B1 B0 + A1 A0 B1 B0
01 1
( A1B1 + A1 B1 ) ( A0 B0 + A0 B0 )
11 1

10 1
x1 x 0

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A<B = ∑ (1,2,3,6,7,11) A> B= ∑(4,8,9,12,13,14

B1 B0 00 01 11 10
B1 B0 00 01 11 10
A1 A0
A1 A0
00 1 1 1
00
01 1 1
01 1
11
11 1 1 1
10 1
10 1 1

A1 B1 + A1 A0 B1 B0 + A1 A 0 B1 B0
A1 B1 + A1 A0 B1 B0 + A1 A0 B1 B0
A1 B1 + x1 A0 B0 A1 B1 + x1 A0 B0

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Logic
g diagram
g of the 2Bit Comparator
p is show in Fig.
g

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 Design the 4 bit magnitude Comparator
Consider two numbers, A and B, with four digits each.
A = A 3 A 2 A1 A 0
B = B 3 B 2 B1 B 0
If A3 = B3 A2 = B2 A1 = B1, A0 = B0 it can be expressed logically
Exclusive NOR expression
Exclusive-NOR

xi = A i Bi + A i Bi i = 0,1,2,3

( A = B ) = x 3 x 2 x1 x0
( A. > B ) = A3 B3 + x 3 A2 B 2 + x 3 x 2 A1 B1 + x 3 x 2 x1 A0 B 0
( A. < B ) = A3 B3 + x3 A 2 B2 + x 3 x 2 A1 B1 + x3 x 2 x1 A 0 B0
EC214 Digital Logic Design
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Logic diagram of the 4 Bit Comparator is show in Fig.

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 Applications of Comparator
„ Comparators are often used as a part of addressing
decoding circuit in computers.

„ To select a specified input and output device for a

storage of data.

„ It is used in the actual circuit to derive the physical

variable towards the reference values.

„ It also used in control applications

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 Decode
„ A Decoder
D d i a combinational
is bi ti l circuit
i it that
th t converts
t information
i f ti
from n input lines to a maximum of 2n unique output lines.
„ If the n-bit decoder information has unused or don’t care
combinations,
bi ti th decoder
the d d output
t t will
ill have
h l
less th
than 2n outputs.
t t
„ The decoders are called n-to m line decoders where m ≤ 2n
„ The general structure of the decoder is show in

Applications
„ Decoder are used in counter systems
„ It is also used in analog to digital converter
„ Decoder output can be used to display the system.
31
 Design 2-to-4 line decoder
The block diagram of the 2-to -4 line decoder is show in Fig.

The truth table of a 2-to-4

2 to 4 line decoder

INPUT OUTPUTS
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
32
The Boolean expression of 2-to-4 line decoder

D0 = A
A’ B
B’ , D1 = A
A’ B,
B D2 = A B
B’, D3 = A B
Logic diagram of the 2-to-4 line decoder is show in Fig.

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 Design 3-to-8 line decoder
The block diagram of the 3-to -8 line decoder is show in Fig.

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The truth table of a 3-to-8 line decoder
In puts Out puts
A B C D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

Th B
The Boolean
l expression
i off 3-to-8
3 t 8 li
line d
decoder
d

D0 = A’B’C’, D1 = A’B’C, D2 =A’BC’, D3 = A’BC

D4 = AB’C’, D5 =AB’C, D6 = ABC’, D7 = ABC

35
Logic diagram of the 3-to-8 line decoder is show in Fig.

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 Design BCD to Decimal decoder
The block diagram of BCD to Decimal decoder is show in Fig.

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The truth table of BCD to Decimal decoder
In puts Out puts
A B C D D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
0 0 0 0 1 0 0 0 0 0 0 0 0 0
0 0 0 1 0 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 0 0 0 0 0
0 0 1 1 0 0 0 1 0 0 0 0 0 0
0 1 0 0 0 0 0 0 1 0 0 0 0 0
0 1 0 1 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 0 1 0 0 0
0 1 1 1 0 0 0 0 0 0 0 1 0 0
1 0 0 0 0 0 0 0 0 0 0 0 1 0
1 0 0 1 0 0 0 0 0 0 0 0 0 1

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 CD 00 01 11 10
AB
00 1 1 1 1

01 1 1 1 1

11 X X X X

10 1 1 X X

The Boolean expression of BCD to Decimal Decoder

D0 = A’B’C’D’, D1 = A’B’C’D, D2 =B’CD’, D3 = B’CD

D4 = BC’D’, D5 =BC’D, D6 = BCD’, D7 = BCD,

D8 = AD’, D9 = AD

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Logic diagram of the BCD to Decimal decoder is show in Fig.

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Implement the full adder with decoder and two OR gates

In puts Out puts

x y z sum carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 EC2141Digital Logic
1
Design
1
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The Boolean expression of Full Subtractor

sum(x,y,z)
( ) = ∑ (1,2,4,7)
(1 2 4 7) carry(x,y,z)
( ) = ∑(3,5,6,7)
∑(3 5 6 7)

Logic diagram implementation of a full adder with a decoder is

show in Fig.
Fig

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Construct a 4 x 16 decoder with two 3 x 8 decoder

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 Encoder
„ An encoder is a digital function that produces a reverse
operation from that of a decoder.

„ An encoder has 2n or less input lines and n output lines.

The block diagram of Encoder is show in Fig.

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Design a octal to binary encoder

D0 D1 D2 D3 D4 D5 D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
45
The Boolean expression of octal to binary encoder
x= D4 + D5 + D6 + D7
Y D2 + D3 + D6 + D7
Y=
z= D1 + D3 + D5 + D7
Logic diagram of octal to binary encoder is show in Fig.

46
 Design decimal to BCD Encoder
The block diagram of decimal to BCD Encoder is show in Fig.

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The truth table of Decimal to BCD decoder

In puts Out puts

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 w x y z
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1
EC214 Digital Logic Design
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The Boolean expression of decimal to BCD encoder
w= D8 + D9
x= D4 + D5 + D6 + D7
x
Y= D2 + D3 + D6 + D7
z= D1 + D3 + D5 + D7 + D9

49
 Multiplexer (or) MUX (or)
Data selector
„ The term “multiplex” means “many into one”.

„ A digital
di i l multiplexer
l i l i a combinational
is bi i l circuit
i i that
h selects
l
binary information from one of many input lines and directs it to
g output
a single p line.

(or)
„ Multiplexer
p is define as transmitting g a large
g number of
information units over a smaller number of channels.

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Block diagram of multiplexer show in Fig

„ It is consisting
g of a 2n input
p lines and n selection lines and
one output.

„ A multiplexer is also called a data selector, since it selects

one of many inputs and steers the binary information along
pre-selected line and that is why it is also called as data
selector.

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 Application of Multiplexer
„ Multiplexing can be used to route data from one of several
sources to one destination.

„ Implement logic function in sum-of-products from directly

from a truth table without the need for simplification.

„ A multiplexer can also be used as a part of control

sequencer.
q

„ It can used Parallel to serial converter.

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 Design 4 : 1 Multiplexer
The block diagram of 4 : 1 MUX is show in Fig.

A 4-line to 1-line multiplexer has four input lines having signals as

I0, I1, I2 and I3. The variables S0 and S1 are the control inputs
which guide the input to output.
output
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 The truth table of 4 : 1 MUX

S0 S1 output
0 0 I0
0 1 I1
1 0 I2
1 1 I3

Logical expression for the output in terms of the information input

and the selected inputs
__ ___ __ ___
Output = I 0 S 0 S 1+ I 1 S 0 S 1 + I 2 S 0 S 1+ I 3 S 0 S 1

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Logic diagram implementation 4: 1 MUX is show in Fig.

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 I0

I1

I2 Input
Data
I3

S1

S0 Select
Line
Output
I0 I1 I2 I3 I0 I1 I2 I3 Output
Data
EC214 Digital Logic Design
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Implement given function f( x,y,z)= Σ (1,3,5,6) with
(a) 8:1 MUX (b) Dual 4:1 MUX (c) 4 : 1 MUX

(a)

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(b) Implementing 8: 1 MUX with Dual 4:1 MUX

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(c)

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Implementing the logic function using a multiplexer 2 N-1 input
lines where ‘N’ is the number of variables in the function:

f( A,B,C,D) = Σ (4,5,6,7,8,13,14,15)

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Implementing the following Boolean function using 8:1 MUX
f( P,Q,R,S) = Σ (0,1,3,4,8,9,15)

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Implement full adder with 4 X 1 Multiplexer

The Boolean expression of Full Adder

sum(A,B,C) = ∑ (1,2,4,7) carry(A,B,C) = ∑(3,5,6,7)

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Logic diagram of implementation of full adder with 4 X 1 MUX

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Implement the following Boolean function using 8: 1 Multiplexer

F ( A , B , C , D ) = AB D + AC D + BC D + AC D
F ( A, B , C , D ) = ∑ (1, 3, 4, 5, 6,11,15)

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 De-multiplexer
„ The word “ demultiplex” means one into many.
„ A circuit that performs the reverse operation of Multiplexer.
„ A demultiplexer is a combinational circuit that receives
information on a single input and transmits the same information
over one of several output lines

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 Design a 1-line to 4-line Demultiplexer
The block diagram of 1 : 4 DEMUX is show in Fig.

Data Select outputs

input Inputs
D S0 S1 D0 D1 D2 D3
D 0 0 D 0 0 0
D 0 1 0 D 0 0
D 1 0 0 0 D 0
D 1 1 0 0 0 D
66
The Boolean expression for the 1-to-4 line Demultiplexer

D0 = S 0 S1 D D1 = S 0 S1 D
D2 = S 0 S1 D D 3 = S 0 S1 D
L i di
Logic diagram of
f implementation
i l t ti off 1 X 4 DEMUX

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 Design of BCD to 7 Segment Decoder

„ A seven – segment display consists of seven

elements that are made of either LCDs (Liquid
C
Crystals
l Diodes
D d ) or LEDs
LED (Light
(L h – Emitting
E diodes
d d )
that element are labeled a-g

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„ Depending on which elements are turned on they
di l
display d
decimal
i l numbers
b 0 th
through
h 9

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The block diagram of BCD to seven segment decoder is show in Fig.

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 Seven segment display
di l output truth
h table
bl

BCD Inputs Segment Output

Display
A B C D a b c d e f g

0 0 0 0 1 1 1 1 1 1 0

0 0 0 1 0 1 1 0 0 0 0

0 0 1 0 1 1 0 1 1 0 1

0 0 1 1 1 1 1 1 0 0 1

0 1 0 0 0 1 1 0 0 1 1

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 Seven segment display output truth table

BCD Inputs Segment Output

Display
A B C D a b c d e f g

0 1 0 1 1 0 1 1 0 1 1

0 1 1 0 0 0 1 1 1 1 1

0 1 1 1 1 1 1 0 0 0 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 0 0 1 1

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 CD 00 01 11 10 CD 00 01 11 10
AB AB
00 1 1 1 00 1 1 1 1
01 1 1 01 1 1
11 X X X X 11 X X X X
10 1 1 X X 10 1 1 X X

a = B'D' + B D + A + B'C b = B' + C'D' + C D

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 CD 00 01 11 10
CD 00 01 11 10
AB
AB
00 1 1 1
00 1 1 1
01 1 1 1 1
01 1 1
11 X X X X
11 X X X X
10 1 1 X X
10 1 X X

c= B + C' + D d= B'D' + B'C + B C'D + C D'

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 CD 00 01 11 10 CD 00 01
0 11 10
0
AB AB
00 1 1 00 1
01 1 01 1 1 1
11 X X X X 11 X X X X
10 1 X X 10 1 1 X X

e =B'D'
B'D' + C D' f C'D'
f= 'D' + B C'' + B D' + A

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 CD 00 01 11 10
AB
00 1 1

01 1 1 1

11 X X X X

10 1 1 X X

g = B'C + B C' + A + B D'

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Logic diagram of BCD to seven segment display

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 Parity generators and Checker
„ The circuit that generates the parity bit in transmitter
is called a parity generator. The circuit that checks the
parity in the receiver is called a parity checker.
checker
„ A parity bit is an extra bit included with a binary message to
make the number
m um of
f 1’s either odd or even..
„ A parity bit added to n-bit code produces (n+1)-bit code with
an odd (or even) count of 1s.
„ Odd Parity bit
„ Count of 1s in (n+1)-bit code is odd, so use an even function to
generate the odd parity bit.
„ The 1s of an even function correspond to minterms having an

index with an even number of 1s.

EC214 Digital Logic Design
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 Design a 3 bit odd parity generator
The truth table of 3 bit odd
The block diagram of 3 bit odd Parity generator
parity generator is show in Fig.
In puts Odd
parity
A B C p
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

EC214 Digital Logic Design

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 The Boolean expression of 3 bit odd parity generator

P(A,B,C) = ∑ (0,3,5,6)

BC 00 01 11 10
A
0 1 1

1 1 1

The logic diagram of 3 bit odd parity generator

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„ Even Parity bit
„ Countt of
C f 1s i (n+1)-bit
1 in 1) bit code
d iis even, so use an odd
dd function
f ti
to generate the even parity bit
„ The 1s of an odd function correspond to minterms having an
i d
index with
ith an odd
dd number
b of f 1
1s.

Design a 3 bit even parity generator

EC214 Digital Logic Design

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 In puts Even
parity
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

EC214 Digital Logic Design

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 The Boolean expression of 3 bit even parity generator

P(A,B,C) = ∑ (1,2,4,7)

BC 00 01 11 10
A
0 1 1

1 1 1

The logic diagram of 3 bit even parity generator

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 Parity Checker
Design a 4 bit even parity Checker

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 Truth table of 4 bit even parity checker

In puts Even In puts Even

parity parity
x y z p C x y z p C
0 0 0 0 0 1 0 0 0 1
0 0 0 1 1 1 0 0 1 0
0 0 1 0 1 1 0 1 0 0
0 0 1 1 0 1 0 1 1 1
0 1 0 0 1 1 1 0 0 0
0 1 0 1 0 1 1 0 1 1
0 1 1 0 0 1 1 1 0 1
0 1 1 1 1 1 1 1 1 0

EC214 Digital Logic Design

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 The Boolean expression of 4 bit even parity checker

C (x,y,z,p) = ∑ (1,2,4,7,8,11,13,14)

ZP 00 01 11 10
XY
00 1 1

01 1 1
C = X ⊕Y ⊕ Z ⊕ P
11 1 1

10 1 1

The logic diagram of 4 bit even parity Checker

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Design a 4 bit Odd parity Checker

I puts
In t Odd I puts
In t Odd
parit parit
y y
x y z p C x y z p C
0 0 0 0 1 1 0 0 0 0
0 0 0 1 0 1 0 0 1 1
0 0 1 0 0 1 0 1 0 1
0 0 1 1 1 1 0 1 1 0
0 1 0 0 0 1 1 0 0 1
0 1 0 1 1 1 1 0 1 0
0 1 1 0 1 1 1 1 0 0
0 1 1 1 0 1 1 1 1 1
EC214 Digital Logic Design
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 ZP 00 01 11 10
XY
00 1 1

01 1 1

11 1 1

10 1 1

The logic diagram of 4 bit Odd parity Checker

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 Error detection
detect on and Correct
Correction
on
using Hamming Code
Number of Parity Bits determined by the following relationship

2 ≥ m + p +1
p

Where m designated by the number of information bits

p designated by the number of parity bits

Using trial and error method find out the number of

parity bit.
b
Parity bits are placed in the positions that are numbered
corresponding to ascending powers of two (1,2,4,8,..)
(1 2 4 8 )
EC214 Digital Logic Design
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Determine the single-error-correcting code for the BCD number
1001 using even parity

2 p ≥ m + p +1 Let p=3 8 = 4 + 3 +1
Bit Designation P1 P2 M1 P4 M2 M3 M4
Bit Position 1 2 3 4 5 6 7
Binary Position 001 010 011 100 101 110 111
Number
Information bits 1 0 0 1
y Bits
Parity 0 0 1

Bit P1 checks bit positions 1,3,5,7 ------- 0

Bit P2 checks bit positions 2,3,6,7
2 3 6 7 ------- 0
Bit P3 checks bit positions 4,5,6,7 ------- 1

The seven bit hamming code 0 0 1 1 0 0 1

EC214 Digital Logic Design
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Determine the single-error-correcting code for the number
1011 using odd parity

2 p ≥ m + p +1 Let p=3 8 = 4 + 3 +1
Bit Designation P1 P2 M1 P4 M2 M3 M4
Bit Position 1 2 3 4 5 6 7
Binary Position 001 010 011 100 101 110 111
Number
Information bits 1 0 1 1
y Bits
Parity 1 0 1

Bit P1 checks bit positions 1,3,5,7 ------- 1

Bit P2 checks bit positions 2,3,6,7
2 3 6 7 ------- 0
Bit P3 checks bit positions 4,5,6,7 ------- 1
The seven bit hamming code 1 0 1 1 0 1 1
EC214 Digital Logic Design
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Determine the single-error-correcting code for the number
10110 using odd parity

2 p ≥ m + p +1 Let p=4 16 ≥ 5 + 4 + 1
Bit Designation P1 P2 M1 P4 M2 M3 M4 P4 M5

Bit Position 1 2 3 4 5 6 7 8 9

Binary Position 0001 0010 0011 0100 0101 0110 0111 1000 1001
Number
Information bits 1 0 1 1 0

Parity
y Bits 1 0 1 1

Bit P1 checks bit positions 1,3,5,7,9 ------- 1

Bit P2 checks bit positions 2,3,6,7

2 3 6 7 ------- 0

Bit P3 checks bit positions 4,5,6,7 ------- 1

Bit P4 checks bit positions 8,9

8 9 ------- 1
The nine bit hamming code 1 0 1 1 0 1 1 1 0
EC214 Digital Logic Design
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Seven bit hamming code is received as 0010001.Find the error
in the code and correct it. Using even parity

Bit Designation P1 P2 M1 P4 M2 M3 M4
Bit Position 1 2 3 4 5 6 7
Received code 0 0 1 0 0 0 1

Bit P1 checks
h k bit positions
iti 1 3 5 7
1,3,5,7 parity check is good 0 LSB

Bit P2 checks bit positions 2,3,6,7 parity check is good 0

Bit P3 checks bit positions 4,5,6,7 parity check is bad 1 MSB

The error pposition code is 100. the bit in p

position 4 is in error.
It is a 0 and should be a 1.

The correct code is 0011001.

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 A 8 bit data is encoded using hamming code and is then
transmitted, the received bit stream is 000011101010. Assume
even parity

Bit P1 P2 M1 P3 M2 M3 M4 P4 M5 M6 M7 M8
Designation
Bit Position 1 2 3 4 5 6 7 8 9 10 11 12
Received 0 0 0 0 1 1 1 0 1 0 1 0
code
d

Bit P1 checks bit positions 1,3,5,7,9,11 Parity check is good 0 LSB

Bit P2 checks bit positions 2,3,6,7,10,11 parity check is bad 1

Bit P3 checks bit positions 4,5,6,7,12 parity check is bad 1
B P4 checks
Bit h k bit
b positions 8,9,10,11,12
10 11 1 parity check
h k is good
d 0 MSB
B

The error position code is 0110. the bit in position 6 is in error.

It is a 1 and should be a 0.
0
The correct code is 000010101010.
EC214 Digital Logic Design
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 Binary parallel Adder
A binary parallel adder is a digital function that
will produce arithmetic sum of two binary number
in parallel.

Input carry 011 0 Ci

Augend 1 0 1 1 Ai
Addend 0 0 1 1 Bi

Sum 1 110 Si
0 0 11 Ci + 1
Output Carry
EC214 Digital Logic Design
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 4-bit Parallel adder show in figure

Parallel adder consists of full adder connected in cascade

with output carry from one full adder is connected to
input carry of next full adder.
Disadvantage:
g Carry
y Propagation
p g Delay
y and speed
p is
reduced
EC214 Digital Logic Design
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 Carry Lookahead Adder
Reducing Carry Propagation Delay

carry propagate Pi = AiْBi sum Si = PiْCi

carry Ci+1 = Gi + PiCi
carry generate Gi =EC214
Ai BDigital
i Logic Design
J Ravindranadh 97
 C 0 = input carry
C 1 = G 0 + P0 C 0

C 2 = G1 + P1C1 = G1 + P1 (G0 + P0 C 0 )
= G1 + P1G0 + P1 P0 C 0
C 3 = G 2 + P2 C 2
= G 2 + P2 ( G 1 + P1G 0 + P1 P0 C 0 )
= G 2 + P2 G 1 + P2 P 1 G 0 + P2 P1 P0 C 0

Boolean function for each output carry is expressed

in sum of product, each function can be implemented
with one level of AND gates followed by an OR gate.

Note that c3 does not have to wait for c2 and c1 to

Propagate;
p g in fact c3 is p
propagated
p g at the same time
As c2 and c1.
EC214 Digital Logic Design
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EC214 Digital Logic Design
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EC214 Digital Logic Design
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 BCD Adder or Decimal adder
„ The BCD must be able to do the following rules for
addition of two BCD numbers.
„ Th adding
The ddi two BCD numbers,b if the
h sum of f BCD
numbers equal to or less than 9, it is a valid BCD
number.
„ If the sum of BCD number is greater than 9, it
is an invalid result add 0110 to the sum of BCD
number.
mb
„ While adding two BCD numbers , carry comes
then add the 0110

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BCD addition
1 1 1 1
5 0 1 0 1 9 1 0 0 1 9 1 0 0 1
3 0 0 1 1 5 0 1 0 1 9 1 0 0 1
8 1 0 0 0 14 1 1 1 0 18 1 0 0 1 0
add 0 1 1 0 add 0 1 1 0
1 0 1 0 0 1 1 0 0 0
Design BCD adder

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Truth table of BCD adder

Binary Sum BCD Sum

k z8 z4 z2 z1 c w x y z
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1

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 Binary Sum BCD Sum
k z8 z4 z2 z1 c w x y z
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1

By inspection (or) using k

k-map
map
c = k + z8 z4 + z8 z2
EC214 Digital Logic Design
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The logic diagram of BCD adder

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 BCD Subtraction
„ BCD subtraction
bt ti i th
is the addition
dditi of f th
the 9’s
9’ complement
l t of
f the
th
subtrahend to the minuend.
„ 9’s complement of a number can be obtained by adding 1010
t th
to the 1’s
1’ complement
l t of
f the
th number,
b di
discard
d th
the carry

BCD subtraction
9’ss complement
9
9 1001
-4 1011 -4 0101
+1010 1110
10101 0110
10100
1
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Digital Logic 01
Design
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EC214 Digital Logic Design
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 Code Converter
Convert 4 bit binary to gray code

Bl k di
Block diagram of
f 4 bit
bi bi
binary to gray code
d is
i shown
h in
i fig
fi

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Truth table of 4 bit binary to gray code is shown in fig
B1 B2 B3 B4 G1 G2 G3 G4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
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1 0 0 0 109
The Boolean expression of The Boolean expression of

G1 ∑ (8,9,10,11,12,13,14,15) G2 = ∑ (4,5,6,7,8,9,10,11)

B3 B4 00 01 11 10
B3 B4 00 01 11 10
B1 B2
B1 B2
00
00
01
01 1 1 1 1
11 1 1 1 1
11
10 1 1 1 1
10 1 1 1 1

G1 = B1 G 2 = B1 B 2 + B1 B 2
= B1 ⊕ B 2

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The Boolean expression of The Boolean expression of

G3 ∑ (2,3,4,5,10,11,12,13) G4 ∑ (1,2,5,6,9,10,13,14)

B3 B4 00 01 11 10
B3 B4 00 01 11 10
B1 B2
B1 B2
00 1 1
00 1 1
01 1 1
01 1 1
11 1 1
11 1 1
10 1 1
10 1 1

G 3 = B 2 B3 + B 2 B3 G 4 = B3 B4 + B3 B4
= B 2 ⊕ B3 = B 3 ⊕ B4

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The logic
g diagram
g of 4 bit binary
y to gray
g y code
convert

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Convert 4 bit gray to binary code

Block diagram of 4 bit gray code to binary is

shown
h in
i fig
fi

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Truth table of 4 bit gray to binary code is shown in fig
G1 G2 G3 G4 B1 B2 B3 B4
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
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The Boolean expression of The Boolean expression of

B1 ∑ (8,9,10,11,12,13,14,15) B2 = ∑ (4,5,6,7,8,9,10,11)

G3 G4 00 01 11 10
G3 G4 00 01 11 10
G1 G2
G1 G2
00
00
01
01 1 1 1 1
11 1 1 1 1
11
10 1 1 1 1
10 1 1 1 1

B1 = G1 B 2 = G1 G 2 + G1G 2
= G1 ⊕ G2

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 The Boolean expression of The Boolean expression of

B3 ∑ (2,3,4,5,8,9,14,15) B4 ∑ (1,2,4,7,8,11,13,14)

G3 G4 00 01 11 10 G3 G4 00 01 11 10
G1 G2 G1 G2
00 1 1 00 1 1
01 1 1 01 1 1
11 1 1 11 1 1
10 1 1 10 1 1

B3 = G1 G2 G3 + G1G2 G3 + G1G2 G3 + G1 G2 G3 B 4 = G1 ⊕ G 2 ⊕ G 3 ⊕ G 4
= G1 ⊕ G2 ⊕ G3

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The logic diagram of 4 bit Gray to Binary code
convertor

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Convert BCD to Excess-3 code

Block diagram of BCD to Excess-3 is shown in fig

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Truth table of BCD to Excess-3 is shown in fig

A B C D W X Y Z
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

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The Boolean expression of The Boolean expression of

W= ∑ (5,6,7,8,9)+d(10 to 15) X ∑ (1,2,3,4,9)+d(10

X= (1 2 3 4 9) d(10 to
t 15)

CD 00 01 11 10
CD 00 01 11 10
AB
AB
00
00 1 1 1
01 1 1 1
01 1
11 X X X X
11 X X X X
10 1 1 X X
10 1 X X

W = A + BD + BC X = BC + B D + B C D

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The Boolean expression of The Boolean expression of

Y= ∑ (0,3,4,7,8)+d(10 to 15) Z ∑ (0,2,4,6,8)+d(10

Z= (0 2 4 6 8) d(10 to
t 15)

CD 00 01 11 10
CD 00 01 11 10
AB
AB
00 1 1
00 1 1
01 1 1
01 1 1
11 X X X X
11 X X X X
10 1 X X
10 1 X X

Y = C D + CD Z = D

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The logic diagram of BCD to Excess-3 convertor

EC214 Digital Logic Design

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Convert Excess-3 to BCD code

Block diagram of Excess-3 to BCD is shown in fig

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Truth table of Excess-3 to BCD is shown in fig

W X Y Z A B C D
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

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The Boolean expression of The Boolean expression of

A= ∑ (11,12)+d(0,1,2,13,14,15) B=
B ∑(7,8,9,10)+d(0,1,2,13,14,15)
∑(7 8 9 10) d(0 1 2 13 14 15)

YZ 00 01 11 10
YZ 00 01 11 10
WX
WX
00 X X X
00 X X X
01
01 1
11 1 X X X
11 X X X
10 1
10 1 1 1

A = WX + WYZ B = W Y + W YZ + WY Z

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The Boolean expression of The Boolean expression of
D= ∑(4,6,8,10,12)+d(0,1,2,13,14,15)
C= ∑(5,6,9,10)+d(0,1,2,13,14,15)
∑(5 6 9 10)+d(0 1 2 13 14 15)

YZ 00 01 11 10
YZ 00 01 11 10
WX
WX
00 X X X
00 X X X
01 1 1
01 1 1
11 X X X
11 1 X X X
10 1 1
10 1 1

C = YZ +Y Z D = Z

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The logic diagram of Excess-3 to BCD convertor

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EC214 Digital Logic Design
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