Description of Functions EDC 15C B271.V10 - 2

Description of functions Page 2-1
Y281 S01 271-V10 EDC 15C B271.V10 AN271 1.0
2 Signal I/O
2.1 Analog signal inputs
The analog value conditioning is subdivided into two parts:
• analog signal sampling and
• standardization and checking of raw values
AN
analog evaluation
signal inputs
speed -
AN0 synchronous
AN1
AN2
AN3
AN4
AN5
time
AN6 synchronous
CPU AN7 quick
AN8 (20ms)
AN9 anm...
AN12 (see tabel below)
AN13 acquisition
AN14
AN15
AN10
MUX AN11
time
synchronous
slow
(100ms)
ANEINSTR.DSF
Figure AN1: Structure of analog value conditioning
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2.1.1 Analog value sampling

The following analog control unit inputs are sampled centrally:
Designation Parameter Period- Raw value meas. meas. Period
block sampling value value evalu.
Function diagnosis [ms]
Fuel pressure anwKDF_.. n-syn anoU_KDF anmKDF admKDF n-syn
sensor
Booster-capacitor anwUC1_.. n-syn anoU_UC1 anmUC1 admUC1 n-syn
voltage (2 bank)
t-syn
(1 bank)
Booster-capacitor anwUC2_.. n-syn anoU_UC2 anmUC2 admUC2 n-syn
voltage (2 bank)
t-syn
(1 bank)
Current pressure anwIDV_.. t-sync. anoU_IDV anmIDV admIDV 10
control valve
Boost pressure anwLDF_.. n-syn. anoU_LDF anmLDF admLDF 20
sensor
Air mass meter anwLMM_.. t-sync. anoU_LMM anmLMM admLMM 20
[n]
Accelerator pedal anwPGS_.. t-sync. anoU_PGS anmPGS admPGS 20
sensor Pot2
Accelerator pedal anwPWG_.. t-sync. anoU_PWG anmPWG admPWG 20
sensor Pot1
Atmospheric anwADF_.. t-sync. anoU_ADF anmADF admADF 100
pressure sensor
Exhaust gas anwAT1_.. t-sync. anoU_AT1 anmAT1 admAT1 100
temp. sensor 1
Fuel temperature anwKTF_.. t-sync. anoU_KTF anmKTF admKTF 100
Air temperature anwLTF_.. t-sync. anoU_LTF anmLTF admLTF 100
Battery voltage anwUBT_.. t-sync. anoU_UBT anmUBT admUBT 10
Water anwWTF_.. t-sync. anoU_WTF anmWTF admWTF 100
temperature
Sensor voltage 1 anwUG1_.. t-sync. anoU_UG1 anmUG1 admUG1 100
Sensor voltage 2 anwUG2_.. t-sync. anoU_UG2 anmUG2 admUG2 100
Sampling saves the results of the periodic analog-digital-conversion as raw values. The
saved values are evaluated later. Additionally to the periodic signal sampling a speed-
synchronous sampling is active (AGD, LDF, LMM, KDF, UC1, UC2).
At the beginning of the speed-synchronous sampling apossibly running conversion is
stopped. In the next signal sampling period the stopped conversion is restarted.
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The sampled values are generally saved as raw values by PEC transfer, where speed-
and time-synchronous raw values are stored in different ARRAYs. The conversion is
started at a fixed interval of 1 ms, so that the raw values are not older than maximum 2 ms
at the time of processing.
The sensors, which are connected to the controller by an analog-multiplexer, are
subdivided into four multiplex groups (groups 0-3). If the currently sampled values are
processed time-synchronously, the MUX is switched on and the sampling for the next
processing starts. Therefore only signals which are to be evaluated in 100 ms intervals can
be connected to the MUX.
Assignment of the analog signal inputs:
Analog inputs anw... KAN Signal
CPU Bit 3...0
AN0 0000 UC1
AN1 0001 UC2
AN2 0010 LDF
AN3 0011 UBT
AN4 0100 LMM CPU
AN5 0101 not used
AN6 0110 KDF
AN7 0111 not used
AN8 1000 not used
AN9 1001 not used
AN10 1010 MUX 1 AMUX
AN11 1011 MUX 2
AN12 1100 IDV
AN13 1101 PWG CPU
AN14 1110 PGS
AN15 1111 AT1
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The number of logical MUX groups is determined by the software.

Logical MUX group anw..._KAN Bit 6...4 MUX 1 MUX 2
0 000 UG1 UG2
1 001 KTF LTF1
2 010 not used WTF1
3 011 not used not used
4 100 ADF not used
By channel number anw..._KAN the corresponding group and the channel number are
set.
anw..._KAN: :
Bit Value Meaning
0-3 Channel assignment
4-6 ADC-channel of the MUX-group
7 0 time-synchronous analog value sampling
1 engine speed-synchronous analog value sampling
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2.1.2 Analog value evaluation (error reaction)

The processing of the raw values is carried out in three different intervals: speed-
synchronous (speed-interrupt-synchronous), time-synchronous fast (20 ms) and time-
synchronous slow (100 ms).
anm...
ANAUSW.DSF
anw...GEB=001B
anw...GEB=000B
>1
&
>1
anw...GEB=001
finally defective
intact recognition time
valid value
0
fbwE..._.B
defect recognition time
[n-1]
last
fbwE..._.A
healing ramp
anw..._DPL
&
1
temporary
defective
>1
finaly defective
fboS....0
fboS... .2
fboS... .1
>1
anwGEB.8 => 2
anwGEB.9 => 3
anw..._KL
a>b
a<b
anw..._DPL
anw...GEB.1
anw...GEB.2
b
a
1
b
a
jump
ramp
anw..._VOR
anw..GEB.0
anw..._MAX
anw.._MIN
fboSUG1
fboSUG2
0
anoU_...
Figure AN2: Analog value evaluation
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With evaluation of the analog signals the converted raw values are checked and
transformed into physical values. The check consists of a SRC (Signal Range Check ). For
exceeding the valid range a default value is used for the raw value. By using the data set
parameter anw..._GEB it can be chosen, if the default value is to be taken by ramp or
directly.
By the Sensor ID the following functions can be chosen:
• linearization by characteristic curve
• switching over to default value by jump or ramp.
If the raw value is within the valid range again after a SRC error, the new value is
shifted to the present value by ramp with the gradient anw..._DPL.
Remark: This is independent of applicating the switch over to the default value by jump
or ramp in the sensor ID word. Therefore anw..._DPL has always to be set.
Assignment of the sensor ID in the data set:

anw..._GEB:
Bit Value Meaning
0 0 no linearization
1 linearization by curve
1 0 no jump
1 switch over to default value by jump
2 0 no ramp
1 switch over to default value by ramp
3-7 0 not used
8 0 not connected to any sensor voltage
1 connected to sensor voltage 1
9 0 not connected to any sensor voltage
1 connected to sensor voltage 2
10-15 0 not used
Remark:
• For sensor ID = 0 the ADC raw value is output unchanged
• If the sensor ID = 1 the last valid value is frozen and output for “temporarily" or
“finally" defective sensor
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anw.._GEB error
temporarily finally temporarily finally
defective defective recovered recovered
...10x last valid meas. meas. value meas. value meas. value
value anm... is anw... by ramp remains at anw... by ramp
frozen with gradient default value with gradient
anw..._DPL from anw..._VOR anw..._DPL
frozen value from default
anw..._VOR to value
default value anw..._VOR to
the presently
calculated value
...01x last valid meas. meas. value meas. value meas. value
value anm... is jumps from remains at anw... by ramp
frozen frozen value to default value with gradient
default value anw..._VOR anw..._DPL
anw..._VOR from default
value
anw..._VOR to
the presently
calculated value
...001 last valid meas. last valid meas.
meas. value
value anm.. is value anm... is
anw... jumps
frozen frozen
from the frozen
value anw... to
the presently
calculated value
...000 The ADC raw value is output unchanged with the meas. value anm...
Remark: The bits 0-2 of the air flow sensor (LMM) are not evaluated in anmLMM_GEB.
The analog value sampling and processing accesses data (parameters) by standardized
data structures (parameter blocks). Not every sensor-sampling and –processing software
routine uses or can use all data (parameters). Therefore every applicable, fixed and
recommended bits of the sensor IDs anw...GEB are listed in the following table.
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meas. value applicable recommended

anmKDF x x x 1 0 1
anmKTF x x x 1 0 1
anmLMM - - x 0 0 1
anmLTF x x x 1 0 1
anmPWG x x x 0 0 1
anmUBT x x x 1 0 0
anmUG1 x x x 1 0 0
anmUG2 x x x 1 0 0
anmWTF x x x 1 0 1
anmUC1 x x x 1 0 1
anmUC2 x x x 1 0 1
anmIDV x x x 1 0 1
anmAT1 x x x 1 0 1
Meaning of the data fields:

x applicable
- not applicable
x fixed
2.1.2.1 Diagnosis message

If the sensor ID is not equal Zero, the actual living physical value cannot be found in the
analog message anm... for a SRC error. But this is required by OBDII1. Therefore a
diagnosis message adm... exists for each signal in addition to the analog message anm.... If
an error is detected by the Signal Range Check the raw value is limited to anw..._MIN or
anw..._MAX. If linearization by curve is set in the sensor ID (anw..._GEB.0 = 1), the
limited raw value is linearized by the curve anw..._KL and stored in the diagnosis message
adm... The latter can be stored as environmental condition in the error memory by its
message number.
1
See chapter Error treatment, Definition of terms
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anw..._MAX
MAX
anw..._KL
adm...
anoU_...
anw...GEB.0
anw..._MIN MIN
ANDIAGMS.DSF
Figure AN3: Forming of the diagnosis message
2.1.2.2 Evaluation of the accelerator pedal sensor
anoU_PWG admPWG
[ mV ]
error
A/D reaction anmPWG
[%]
anwPWG_KL fbwEPWG_L
anwPWG_MIN fbwEPWG_H
fbwEPWG_L Init
anwPWG_MAX
fbwEPWG_H anwPWG_VOR ANPWG.DSF
Figure AN4: Evaluation of the PWG
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2.1.2.3 Evaluation of the redundant accelerator pedal sensor
anoU_PGS admPGS
[ mV ] error
A/D anmPGS
reaction
[%]
anwPGS_KL fbwEPGS_L
anwPGS_MIN
fbwEPGS_H Init
fbwEPGS_L
anwPGS_MAX anwPGS_VOR ANPGS.DSF
fbwEPGS_H
Figure AN5: Evaluation of the PGS
2.1.2.4 Evaluation of the atmospheric pressure sensor
anoU_ADF admADF
[ mV ]
A/D error
reaction anmADF
[ hPA ]
anwADF_MIN anwADF_KL fbwEADF_L

fbwEADF_L fbwEADF_H Init
anwADF_MAX anwADF_VOR
ANADF.DSF
fbwEADF_H
Figure AN6: Evaluation of the ADF
Evaluation of the signals AT1, AT2, KTF, LTF, WTF, UG1, UG2 and UBT is carried
out analogous to the ADF signal.
2.1.2.5 Evaluation and plausibility check of the water temperature sensor

In case of a water temperature sensor defect two substitute values are needed for the
system. One low substitute value anwWTF_VGS for the glow and start function
(mrmSTART_B=1) and one high substitute value anwWTF_VGN for the driving function
(mrmSTART_B=0).
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The plausibility check of the WTF sensor is carried out once per driving cycle. In doing
so, dependent on the water temperature after initialization, a time is determined from the
curve anwWSZ_zKL within which the water temperature must have attained the value
anwWSZ_mT or the minimum temperature increase dT_W/dt of anwWSZ_mTA If one of
these conditions is met, the test is finished and the error fbbEWTF_S is reported as o.k.. If
these conditions are not fulfilled, the error fbbEWTF_S is reported after passing the
allowed warm-up time. The test is only carried out when the engine speed dzmNmit is
above the threshold anwWSZ_DZ and the fuel quantity mrmM_EAKT is above the
threshold anwWSZ_mM.
Init
anoWTFstrt
old
a
anmWTF
a<b
b
anwWSZ_zKL
& fbbEWTF_S
anmWTFd
anwWSZ_mTA b a<b
a
a<b
anwWSZ_mT b
dzmNmit a
a>b
anwWSZ_DZ b
& start anoW_Zt
mrmM_EAKT a
a>b
anwWSZ_mM b
ANWTFPLA.DSF
Figure AN7: Water temperature plausibility check after engine start
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2.1.2.6 Evaluation of the boost-pressure sensor
anoU_LDF admLDF
[ mV ]
A/D
anoU_LDFA SRC failed

last anwLDF_MIN anwLDF_KL
fbwELDF_L
anwLDF_MAX
fbwELDF_H
error
reaction anmLDF
[ hPa ]
anoU_LDFA fbwELDF_L
0.5 fbwELDF_H
Init
anwLDF_VOR
[ mV ]
A/D
prior
anwLDF_MIN anwLDF_KL
ANLDF.DSF
fbwELDF_L
anwLDF_MAX
fbwELDF_H
Figure AN8: Evaluation of the LDF
In order to determine the anmLDF message the last two values (oldold and old) are
averaged. Before each new speed-synchronous conversion the last speed-synchronous
value is restored.
2.1.2.7 Evaluation of the fuel pressure sensor
anoU_KDF admKDF
[ mV ] error
A/D
reaction anmKDF
[ hPa ]
anwKDF_MIN anwKDF_KL fbwEKDF_L
fbwEKDF_L fbwEKDF_H
Init
anwKDF_MAX
fbwEKDF_H anwKDF_VOR ANKDF.DSF
Figure AN9: Evaluation of the KDF
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Fuel pressure sensor plausibility-check:

To recognize a damaged rail pressure-sensor, the current through the pressure regulator
valve is checked for plausibility with the averaged rail pressure. The check is executed, if
every of the following conditions are fulfilled:
1. Control deviation | ( zumPQsoll - zumP_RAILm ) | is for the time anwKDF_T
smaller then the limit anwKDFSmax.
2. Engine fuel quantity (mrmM_EMOT) is smaller than the limit (anwKDF_Mo)
Note: This limit together with the speed limit below is used for the detection of
overrun.
3. The engine speed (dzmNmit) is between the thresholds anwKDF_Nu (lower limit)
and anwKDF_No (upper limit).
4. Electrical shut-off valve (EAB) inactive that means:
1: active EAB: ehmFEAB = 50%
0: aktives EAB: 100% - ehmFEAB = 50%
5. Pump element shut-off inactive (ehmFKHP > 50 %)
6. Afterrun is not active (mrmSTATUS.2 == 0).
7. No error in fuel pressure sensor errorpath (fboSKDR == 0).
8. No error in fuel pressure plausibility-error path (fboSKDP == 0).
9. No signal range check-error at DRV current (fbbEIDV_L ==0 and fbbEIDV_H ==
0).
10. No signal range check-error at fuel pressure sensor signal and fuel pressure sensor
supply (fbbEKDF_L == 0 and fbbEKDF_H == 0 and fbbEKDF_V == 0.
If all of these conditions are fulfilled, the averaged rail pressure (zumP_RAILm) is
checked for the limits anwPmax_KF and anwPmin_KF = f (dzmNmit, anmIDV). If the rail
pressure is not in these limits the error fboSKDF.7 is reported as defective, otherwise
fboSKDF.7 is reported ok.
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a
zumPQsoll
anoKDFTst.0
a<b anoKDFTst.1
b & anoKDFTst.2
zumP_RAILm &
anwKDFSmax treshold timer
expired ( anwKDF_T)
a
mrmM_EMOT
a<b
b
anwKDF_Mo
a
dzmNmit
a>b
b
anwKDF_Nu
a<b
b
anwKDF_No
100 % a
a<b
ehmFEAB b
50 %
cowVAR_EAB
a
ehmFKHP
a>b
b
50 %
mrmSTATUS.2
(after-run active)
1
fboSKDR
1
fboSKDP 1
& anoKDFTst.3
fbbEIDV_L
1
fbbEIDV_H 1
fbbEKDF_L
1
fbbEKDF_H 1
fbbEKDF_V 1
zumP_RAILm
a
anoKDFTst.4
dzmNmit a>b
b ANKDPLAU.DSF
anmIDV
anwPmax_KF
a
anoKDFTst.5 >1 fbbEKDF_P
a<b error
b debouncing
0
anwPmin_KF
Figure AN10: Fuel pressure sensor test-plausibility of the KDF
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Olda anoKDFTst shows the current test status :

anoKDFTst:
Bit Meaning
0 |governor deviation P_Rail| < anwKDFSmax
1 anoKDFTst.0 = 1 and waiting time anwKDF_T elapsed
2 anoKDFTst.1 = 1 and driving quantity < anwKDF_Mo
3 anoKDFTst.2 = 1 and no shut off condition 3.10) active
4 anoKDFTst.3 = 1 and upper plausibility limit exceeded
5 anoKDFTst.3 = 1 and lower plausibility limit exceeded
6 report: no error
7 report: error
Message anmKDF: the raw value transformed engine-speed synchronously during the
current interrupt is used.
2.1.2.8 Evaluation of the fuel pressure sensor current
anoU_IDV admIDV
error
[ mV ]
A/D reaction
anmIDV
anwIDV_MIN anwIDV_KL fbwEIDV_L

fbwEIDV_L fbwEIDV_H
Init
anwIDV_MAX
fbwEIDV_H anwIDV_VOR ANIDV.DSF
Figure AN11: Evaluation of the IDV
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2.1.2.9 Evaluation of the air mass meter
anoU_LMM anoLMM_KL anoU_LMM1S anoU_LMM2S
segment
U_LMM [kg/h] anmLMM
A/D scan 1ms average over
M (i) 2nd segment
L [kg/h]
anwLMM_KL
dzmNmit
anwGFH51KL
SRC
Low fbbELM5_L
no error detection or healing
anwLMM_MIN
fbwELM5_L...
dzmNmit<=anwLMD_N1
dzmNmit>=anwLMD_N2 >1
0
fboSUG1 fbbELM5_V
fboSUG2
fboSUG1
anwLMM_GEB.8 and .9
SRC
High fbbELM5_H
no error detection or healing
anwLMM_MAX
fbwELM5_H...
>1
a
mrmM_EAKT
a>b 1
b
dzmNmit
anwLMD_H_T
anwLMMSRKL
ANHFM1MS.DSF
anoLMM_MSR
Figure AN12: Sampling ratiometric, time synchronous / 1ms and evaluation of the LMM
The signal of an air mass meter (hotfilm air mass sensor HFM, signal proportional to air
mass flow) can be detected and is passed on regardless wether a SRC or a plausibility error
is present.
For the air mass sensor (LMM) a SRC-Low is carried out only within the engine speed
range (lower threshold anwLMD_N1, upper threshold anwLMD_N2) and in case of intact
sensor supply voltage. By using the sensor ID anwLMM_GEB bit8 and bit9 that faulty
sensor supply voltage can be selected which is debounced via fbwELM5_V. and output in
fbbELM5_V.
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A SRC High is carried out only if the actual air mass falls below the engine speed
dependent air mass threshold anwLMMSRKL for at least the time anwLMD_H_T and if no
sensor supply voltage error is present.
Dimensioning of the recursive filter requires a compromise between the demands for a
small standing wave ratio (big time constants) and small transient times of the control loop
(small time constants). That means the dimensioning strongly depends on the air pulsation
in the intake manifold of the engine.
The low-pass has to have a time constant TTP < 100 ms in any case. The memory factor
GF in the transmission function has to be applicated engine speed dependently .
The memory factor is calculated from:
GF(n) = exp( -Tseg(n) / TTP ) GF memory factor
n crankshaft speed
TTP low-pass time constant
Tseg(n) = 1 / (Z x n) Tseg segment duration
Z number of cylinders
The type of the air mass sensor is choosen by the software switch cowV_LMM_S.
Remark: The diagnosis message admLMM corresponds to the message anmLMM and is
limited by the MIN and MAX values of the SRC. This value will not be limited
if no SRC is carried out.
cowV_LMM_S:
Value Meaning
0 no air mass meter implemented
1 butterfly valve sensor not supported
2 hot film air mass sensor not supported
3 hot film air mass sensor HFM5 not supported
4 hot film air mass sensor HFM5 1ms
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2.1.2.10 Evaluation of the exhaust stroke indicator

Init
fbbEAHO_H
anwAHO_MAX
anwAHO_VOR anoU_AHO
anwAHO_T
a
b a<b
anwAHO_GF anwAHO_N
anwAHO_MAX
fbwEAHO_H
anoU_AHP
anoU_AHR anoU_AHK admAHR
[mV] [mm] error

A/D anmAHR
reaction
anwAHR_MIN anwAHR_KL fbwEAHR_L

fbwEAHR_L. fbwEAHR_H Init
anwAHR_MAX
fbwEAHR_H. anwAHR_VOR ANAHR.DSF
Figure AN13: Evaluation of the AHR
Calculation is carried out only if cowVAR_ARF is set to “control by AHR”. During

initialization the learned offset anoU_AHO is pre-set with anwAHO_MAX. The SRC of the
offset is carried out only below the engine speed threshold anwAHO_N.
2.1.2.11 Sampling of the booster voltages UC1 & UC2 (two-bank operation)
The booster voltages are sampled during the fuel metering interrupt BOB every 180
Grad alternately (according to the bank) and stored into the messages anmUC1 and
anmUC2 during the following engine speed interrupt DZI. The analog values used in the
BOB come from the time synchronous memory array, i.e. they are maximum 1ms old in
the BOB.
2.1.2.12 Sampling of the booster voltage UC1 (one-bank operation)

During the engine speed interrupt DZI the message anmUC1 is generated as follows:
The maximum of the time different detected UC1 voltages are transmitted as messages
anmUC1. For this the last time synchronous (max. 1ms old) UC1-voltage anoUC_t, the
voltage anoUC_n1 from the last engine speed synchronously detected memory array and
the voltage anoUC_n2 from the second to last engine speed synchronously detected
memory array are used. From these three voltages the maximum anoUC1_max is
transmitted as message anmUC1.
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One-bank operation: see chapters "Injector-powerstages error recognition" and "Check of

booster voltage"
Note:
One-bank operation: anwUC1_KAN = 128 anwUC2_KAN = 129 ehwUC_TOGG = 0
Two-bank operation: anwUC1_KAN = 0 anwUC2_KAN = 1 ehwUC_TOGG = 1
2.1.2.13 Error processing of the sensor supply voltage

After implementing the new C167 platform sensor supply is done by shared supply
lines, where up to four supplied sensors can be assigned to one line.
supply-rail 1
U_GEB1
sensor 1.1 sensor 1.2 sensor 1.3 sensor 1.4
supply-rail 2
U_GEB2
sensor 2.1 sensor 2.2 sensor 2.3 sensor 2.4
ANSENSP.DSF
Figure AN14: Sensor supply
For error processing failure of a supply line has to be reported (SRC monitoring) to the
sensor error path, because the substitute reactions for sensor failure are linked to the error
path of the corresponding sensor in the driving software.
The bit fbbE..._V is set in the error path of an active sensor (PWG, PGS, KDF, LDF,
LMM) in case of sensor supply voltage failure.
After occurrence of a sensor supply voltage error one of the following values are given
out in the sensor message anm..., depending on the applicated value of the sensor ID
anw..._GEB (not with LMM): the default value anw..._VOR through jump or ramp, the last
valid measured value or the raw value. A SRC of the analog value is no longer carried out.
A possibly started SRC error debouncing is cancelled. This prevents from consecutive
errors at occurrence of a sensor supply voltage error.
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Furthermore the error debouncing time of the analog value SRC has to be applicated
longer than the error debouncing time of the sensor supply voltage SRC in order to prevent
from consecutive errors. Note that the sensor supply voltage is evaluated every 20 ms
(every 100ms via MUX).
2.1.2.14 Sensor assignment to supply rails

supply rail Sensor
U_GEB1 PGS LMM KDF
U_GEB2 PGW LDF
2.1.2.15 Application hints for error handling

With the error handling occuring errors should be recognized in the following sequence:
• Sensor voltage error
• SRC error
• Plausibility error
This can be achieved by an appropriate application of the error debouncing times.

ANFEHLERBEH.DSF
type of error
PLAU
SRC
GEB
0
error debounce time
Figure AN15: Error debouncing time
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2.2 Digital signal inputs

The digital inputs are read centrally, processed and distributed system-wide. For input
Terminal 15 also the non-debounced (dimK15roh) is made available. The OLDAs
dioROH0 and dioROH1 show the electrical conditions. The messages dimDIGpre0 or
dimDIGpre1 show the logical, debounced conditions of the inputs.
dimK15roh
dioROH0 dimDIGpre0
dim...
...
...
...
...
digital logical
inputs preparation
0-15
dioROH1 dimDIGpre1
digital
inputs
16-21
DIALLG.DSF
Figure DI1: Processing of the digital inputs (general)
dioROH0.13 dimDIGpre0.13 plausibility dimBRE

debouncing
check
0
1
diwBRE_inv
diwBRE_Z1
diwBRE_ben DIBREMS.DSF
diwBRE_Z2
Figure DI2: Processing of the digital inputs (e.g. brake input)
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In the logical conditioning four parameters are available for each hardware-input.
Unused inputs diw..._ben are outmasked. Each input is converted into its corresponding
logical level depending on the data set parameter diw..._inv and debounced with its own
filtering time constants separately for increasing diw..._Z1 and decreasing edges diw..._Z2.
For each input whose logical level at initialization is TRUE, its debouncing counter is
initialized with the maximum value.
debouncing counter
MAX_CNT
DIENTPR.DSF
switching
threshold off
diw..._Z2
switching
threshold on
diw..._Z1
MIN_CNT
t
dioROH.x
t
dimDIGpre.x
Figure DI3 : Debouncing of the digital inputs
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dioROH0 and dimDIGpre0 contain the raw and debounced conditions respectively of
the inputs 0-15.
dioROH0, dimDIGpre0:
Bit Meaning Message SG-Pin Input signal
4 brake redundant dimBRK 48 I_S_BRKRED
9 clutch dimKUP 102 I_S_CONV
7 brake dimBRE 47 I_S_BRKMN
15 terminal 15 ignition lock dimK15 22 I_S_T15
dioROH1, dimDIGpre1:
Bit Meaning Message SG-Pin Input signal
3 glow relay feedback dimGZR 62 I_S_GLW
2.2.1 Brake information conditioning

The source of brake information is determined through the variant switch cowV_BRE.
cowV_BRE:
Value Meaning
1 Brake via hardware
2 Brake via CAN
The digital input for the brake dimBRE is checked for plausibility with the (optional)
redundant brake contact2 dimBRK under the following conditions:
• The brake signal is sampled through the digital input (cowV_BRE = 1)
• FGR present (cowFUN_FGR.0 = 1)
• Terminal 15 active (dimK15roh = 1)
• The digital input of the (optional) redundant brake contakt is active
(diwBRK_ben = 1)
2
A redundant brake contact only makes sense in combination with a FGR (cowFUN_FGR.0 = 1). The basic
software contains no FGR function.
Correspondingly, the basic-SG is not supplied with a signal of a redundant brake signal.
Generating of the message dimBRK and its check for plausibility with dimBRE is a preset for projects that
wish to use a redundant brake contakt.
In the basic software the message dimBRK behaves neutral.
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The error "implausibility after initialization" fbbEBRE_I is reported if there is an

implausibility after initialization (with removed brake signal plug).
By fbwEBRE_PT.0 may be applied if the plausibility error fbbEBRE_P is debounced
time- or event-controlled. For time-controlled processing there is a plausibility error if the
redundant brake contact is active alone for a certain time; for event-controlled processing if
only one of the inputs is active for a certain number of actuations.
cowV_BRE=1 fbbEBRE_P
cowFUN_FGR.0
dimK15roh
diwBRS_ben=1
& error
debouncing
after init.: fbbEBRE_I
plausible
DIBRPLAU.DSF
dimDIGpre0.13 dimBRE
dimDIGpre0.5* dimBRK*
*) optional
Figure DI4: Plausibility check for brake
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2.2.2 Clutch information conditioning

Clutch information conditioning depends on the transmission type (selectable by
cowVAR_GTR).
2.2.2.1 Transmission type = manual shifting (cowVAR_GTR = 1)

The digital input for the clutch dimKUP is checked for plausibility by using the present
vehicle speed. For the plausibility check the fact is used that it is not possible to accelerate
a vehicle from a standstill to a high speed without actuating the clutch.
A state diagram of the strategy for the plausibility check is shown in the following
figure.
K5/ESM 1.12.1999 DI
F=0* && status = Init 1

t < diwUKU_tim - start timer t if not running yet
- dimKUP = diwUKU_vgw
F=0* &&
t ≥ diwUKU_tim
status = Init 2
F=1*
diwUKU_US1
F=0* && fgmFGAKT > diwUKU_US1
F=1*
fbbEKUP_P = 1*
status = 1st clutch signal transition

- Intact report after every transition of KUP
F=0* && fgmFGAKT
fbbEKUP_P = 0
F=1*
F=0* &&
(healed)
status = check plausibility
F=0*
- do plausibility check (refer separate picture)
F=0* &&
F=0* status = no plausibility check fbbEKUP_P = 1
F=1*
- dimKUP = diwUKU_vgw (finally defective)
F=1*
status = clutch defective
F=0*
status = clutch ok
- dimKUP = dimDIGpre...
{
1, 1st transition of clutch
DIZUSTAUT.DSF signal detected
*)F=
0, else
Figure DI5: State machine
A timer is started after initialization and the default value diwUKU_vgw is used for
dimKUP (state "Init 1"). In the beginning the clutch signal must be considered as not yet
available. The first signal change of the clutch signal is waited for.
K5/ESM 1.12.1999 DI
After the time diwUKU_tim has elapsed without a change of the clutch signal a switch
is made to state "Init 2". In this state the vehicle speed is checked fgmFGAKT for
exceeding the threshold diwUKU_VS1. If this is the case it is supposed that "ignition
off/on" has occured during driving and a switch to the state "no plausibility check".
Remark: For application of diwUKU_tim the v-filtering constant fgwFGF_GF and the
distance factor have to be taken into account.
If, however, the threshold diwUKU_VS1 was not exceeded the plausibility check is
carried out (state "check plausibility"). The pausibility check works as described below:
If a vehicle speed above the threshold for driving diwUKU_VS2is reached without
previous signal change of the clutch switch, the single error fbbEKUP_P is reported as
defective. The error pre-debouncing is reset if the path fboSFGG is defective or the
previous speed threshold has not been exceeded.
fboSFGG
error fbbEKUP_P
fgmFGAKT a
& predebouncing
diwUKU_VS2 b a>b
Reset
Figure DI6: Plausibility check of the clutch information for manual shifting
If the defect recognition (fbwEKUP_PA) is running, fbbEKUP_P is set and switched to

the state "clutch defective".
When the first signal change of the clutch is detected the state "1st clutch signal
transition" is taken. If no error fbbEKUP_P is present a switch is made to the stable state
"clutch ok". If, however, fbbEKUP_P is set a report as intact can contribute to recovery at
each signal change of the clutch. If intact recognition is running it is again switched to the
state "clutch ok".
2.2.2.2 Transmission type = automatic (cowVAR_GTR= 2)

The message mrmGANG is checked.
If it’s value corresponds to the positions "N" (neutral position) or "P" (park position)
dimKUP is set to 1 (clutch actuated).
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2.3 Power stage processing

The power stage processing takes on the control of the physical power stages. Access to
the power stages is managed according to their priority.
For power stages with hardware-based error recognition (CJ920, CJ420) the power
stage processings takes on the error handling.
EH
processing
ehm . xxx ehmSxxx
CJ920 power stages
error detection
CJ920/CJ420
injector power stage CY220
processing
ehm . xxx ehmSxxx
CJ911 power stages
EHSTRK. DSF
Figure EH1 : Structure of the power stage handler
Assignment of the messages ehm . xxx to the physical power stages is done by means of
the the pin-number.
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CJ920 power stages:

Message Meaning Pin-Nr CJ920-
ehwEST_... assignment
(Low-Byte) ehwCJ9_Pxy
ehm . ARS Exhaust gas recirculation positioner 80h ehwCJ9_P03
ehwCJ9_P05
ehm . LF1 Fan 1 relay C6h ehwCJ9_P14
ehm . EAB Electric fuel pump 14h ehwCJ9_P02
ehm . GZS Glow relay CEh ehwCJ9_P01
ehm . KDR Fuel pressure regulator valve D0h ehwCJ9_P08
ehwCJ9_P10
ehm . LDK Throttle plate actuator 08h ehwCJ9_P07
ehm . DIA Diagnosis lamp C8h ehwCJ9_P06
ehm.LF2 Fan 2 relay 84h ehwCJ9_P11
ehm.LDS Boost pressure actuator 9Ch ehwCJ9_P09
CJ420-power stage:
Message Meaning Pin-Nr ehwEST_...
(Low-Byte)
ehm . GAZ Glow indicator D2h ehwCJ4_P04
ehm.EKA Variable swirl actuator 86h ehwCJ4_P03
Explanation of messages:
.=F Default value of the driving function: in these messages the default values
of the driving function for the corresponding power stages are handed over
to the power stage handler.
.=D Default value for diagnosis: in these messages the default values for
diagnosis of the corresponding power stages are handed over to the power
stage handler.
.=S State: in these messages the power stage handler makes the state of the
corresponding power stage available.
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Structure of the state message:

Bit Value Meaning
0-13 correspond to the sensor ID of the power stage
14 0 power stage intact
1 power stage defective
15 0 diagnosis active
1 driving software active
The Pin number follows from the Port pin (µC167) or the output port of the GAD 40, by
which the corresponding power stage is controlled.
Definition of power stage number:
µC Port power stage number

P2.0 ... P2.15 00h ... 1Eh
P3.0 ... P3.15 20h ... 3Eh
P4.4 ... P4.7 48h ... 4Eh
P7.0 ... P7.7 80h ... 8Eh
P8.0 ... P8.7 90h ... 9Eh
XP1.0 ... XP1.14 A0h ... BCh
XP1.15 K15 - not useable as powerstage output
XP2.0 ... XP2.7 C0h ... CEh
GAD_PWM1 D0h
GAD_PWM2 D2h
GAD_PWM3 D4h
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158
8.7
P8
Attention:
144
8.0
Changes to the pin numbers
are not permitted!!
142
7.7
P7
128
7.0
126
6.7
P6
112
212
6.0
GAD PWM
110
206 208
P5
X2P
80 82 84
5.05.15.2
192
190
78
64 66 68
P4
X1P
4.0
62
160 162
P3
30 32 34 36
3.03.13.2
P2
EHPIN.DSF
02468
2.02.12.2
Figure EH2: Pin numbers of the power stage
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2.3.1 Diagnostic messages

ehmBW1, ehmBW2: Diagnostic bits of powerstage CJ920
ehmBW3: Diagnostic bits of one or two CJ420 powerstage circuits
There are two bits for each powerstage which contain the following diagnostic
information:
Value Meaning
00 Short circuit to ground
01 Short circuit to +Ubatt
10 open circuit
11 no error detected
CJ920-Power stage:
ehmBW1 Bitmask Meaning Pin-No. CJ920-
Hex- occupation by
value powerstage
processing
0000 0000 0000 0011 Diagnostic bits of powerstage #1 CJ920 CE ehwCJ9_P01
0000 0000 0000 1100 Diagnostic bits of powerstage #2 CJ920 14 ehwCJ9_P02
0000 0000 1100 0000 Diagnostic bits of powerstage #4 CJ920 CA ehwCJ9_P04
0000 1100 0000 0000 Diagnostic bits of powerstage #6 CJ920 C8 ehwCJ9_P06
1100 0000 0000 0000 Diagnostic bits of powerstage #8 CJ920 D0 ehwCJ9_P08

Hex- occupation by
value powerstage
processing
0000 0000 0000 0011 Diagnostic bits of powerstage #9 CJ920 9C ehwCJ9_P09
0000 0000 0000 1100 Diagnostic bits of powerstage #10 CJ920 D0 ehwCJ9_P10
0000 0000 1100 0000 Diagnostic bits of powerstage #12CJ920 02 ehwCJ9_P12
0000 0011 0000 0000 Diagnostic bits of powerstage #13 CJ920 CC ehwCJ9_P13
0000 1100 0000 0000 Diagnostic bits of powerstage #14 CJ920 C6 ehwCJ9_P14
1111 0000 0000 0000 not used – dummy bits always 1 -
The value ehwCJ9_920 has to be set to 1, because only one powerstage CJ920 is
supported.
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CJ420-Power stage:
Hex- occupation by
value powerstage
processing
0000 0000 0000 0011 Diagnostic bits of powerstage #1 of 1st CJ420 9E ehwCJ4_P01
0000 0000 0000 1100 Diagnostic bits of powerstage #2 of 1st CJ420 9E ehwCJ4_P02
0000 0000 0011 0000 Diagnostic bits of powerstage #3 of 1st CJ420 86 ehwCJ4_P03
0000 0000 1100 0000 Diagnostic bits of powerstage #4 of 1st CJ420 D2 ehwCJ4_P04
0000 0011 0000 0000 Diagnostic bits of powerstage #1 of 2nd CJ420 9A ehwCJ4_P05
0000 1100 0000 0000 Diagnostic bits of powerstage #2 of 2nd CJ420 04 ehwCJ4_P06
0011 0000 0000 0000 Diagnostic bits of powerstage #3 of 2nd CJ420 06 ehwCJ4_P07
1100 0000 0000 0000 Diagnostic bits of powerstage #4 of 2nd CJ420 2E ehwCJ4_P08
If only one CJ420 powerstage is supported by the hardware ehwCJ4_400 has to be set
to 1. For two CJ420 powerstages ehwCJ4_400 has to be set to 2. If only one CJ420 is
calibrated, all bits of the 2nd powerstage are set to one (no error).
2.3.2 Power stage processing

The power stages can be controlled by different sources. Usually this is done by
functions of the driving software. If the diagnosis is activated the powerstages can be
controlled by diagnosis functions. In case of simultaneous access diagnosis functions take
priority over driving software functions.
The power stage processing converts the logical power stages into physical power
stages. Assignment from logical to physical powerstage is defined by the Low byte of the
sensor IDs (ehwEST_...).
The following signal types can be produced:

• digital switching signals
• pulse width modulated signals
• pulse width modulated signals with battery voltage-dependent correction
• pulse width modulated KDR signal with current controller
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One sensor ID (ehwEST_...) for each power stage is stored in the data set, by which the
behaviour of the power stage is defined.
ehwEST_....12
Iinitialize
ehwEST_....13 1 powerstage
ehwEST_....8
dig
ehwEST_....9
1
input
ehmF...
ehwEST_....10 ehoUKORR
PWM
1
13500mV
EHANST.DSF
anmUBTKomp
Figure EH3 : Controlling the KDR-powerstage
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A sensor ID ehwEST_... is structured as follows:

Bit Value Meaning
0-7 hardware assignment
8 1 power stage used
0 not used
9 1 signal type PWM
0 digital
10 1 UBT-correction Yes
0 No
11 is only used for KDR power stage
12 1 level at initialization/recovery High
0 Low
13 1 invert TV
0 do not invert
14-15 not used
Attention: CJ920 power stages which are not used are always switched on (prevents load
drop entry in the error memory of the power stage modules, therefore clocking-
out of the error memory is only necessary in case of a real error).
• Always apply assignment to a HW-Pin (Low byte)!

• ehwEST_....12 (level at initialization/recovery) is interpreted as static rest level for
deactivated power stage by the diagnosis function. For this reason it must be sure
that the applicated level disables power consumption of the actuator or that the
actuator is suitable for constant current).
It is supposed that no load is connected to unused power stages. In this context the
labels cowFUN_LDR and cowFUN_ARF have priority over ehwEST_LDS and
ehwEST_ARS if applied as ≠255.
Example: cowFUN_ARF means “no exhaust gas recirculation" → ARS power stage is
activated.
The label ehwCJ_920 determines the number of CJ920 modules. The data of the phys.
power stage number of the module ehwCJ9_Pxy is applied together with the corresponding
Pin numbers (see table).
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For correction of battery voltage fluctuations a voltage correction may be carried out
(ehwEST_....10). The duty cycle is calculated by the following formula:
13,5 V
TV(korr) = TV(ukorr) ⋅
anmUBT
The corrected duty cycle is output by the OLDA ehoUKORR. This only happens when
UBT-correction is activated.
Pulse width modulated signals are used for control of electropneumatic converters
(EPW).
2.3.2.1 Pulse width modulated signals via Capture Compare Units of the
µC167
The common control frequency for power stages which are controlled via Port 2 of the
µC is stored as data-set parameter ehwEST_T1. The common control frequency for power
stages which are controlled via Port 7.4 - 7.7 and via Port 8 is determined by the data-set
parameter ehwEST_T7. The duty cycle for these power stages is limited to 5%-95%.
2.3.2.2 Pulse width modulated signals via PWM-Unit of the µC167

For power stages which are controlled via Port 7.0 - 7.3 the control frequency for each
power stage is applicable by the data-set parameters ehwPWM_PPx and ehwPWM_VTx (x
= 0,1,2,3 ≡ pin number on Port 7). For these power stages the on/off ratio is also limited to
5%-95%.
ehwPWM_VTx
f
CPU (CPU clock)
1 f
PWM
1 ehwPWM_PPx control frequency

64
EHPWMDPA.DSF
prescaler
Figure EH4 : Calculation of the data-set parameters
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Calculation of the data-set parameters without prescaler:

f CPU
ehwPWM_PPx = −1
f PWM
with prescaler:
f CPU
ehwPWM_PPx = −1
f PWM ∗64
Prescaler ehwPWM_VTx for frequencies < 250Hz!

Small frequency scaler ehwPWM_PPx mean rough quantization, therefore the
frequency scaler ehwPWM_PPx has to be chosen as big as possible!
2.3.2.3 Pulse width modulated signals via Gate Array GAD 4x

The control frequency of the power stages which are handled by the GAD 4x are
completely determined by the labels ehwG_VT1_. and ehwG_VT2_. ( . = 1, 2, 3; used
PWM-Port at GAD 4x)
ehwG_VT1_.
1 KHz f
1 PWM
5 KHz
ehwG_VT2_.
EHPWMFRT.DSF
Figure EH5 : Formation of the control frequency
Connection fPWM, ehwG_VT2_. at ehwG_VT1_. = 0:

1KHz
ehwG_VT2_. = for ehwG_VT2_. = 0 : fPWM = 1KHz
f PWM
Connection fPWM, ehwG_VT2_. at ehwG_VT1_. = 1:
5KHz
ehwG_VT 2 _. = −1
f PWM
The prescaler of the GAD 4x can be switched on and off by using the label
ehwG_VT1_. . If the label is applied with 1, an output frequency of 5 KHz results, for 0 an
output frequency of 1 KHz results.
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With ehwG_VT2_. it is possible to scale down the applied frequency once again (factor
0-32).
Hint for application: Because of the minimum switching times (10µs) required by the
CJx20 power stage modules, limiting of the possible duty cycle
range has to be done at increasing PWM-frequency.
2.3.3 Power stage error recognition of the CJ920/CJ420 power stages

The power outputs are checked for the following error conditions:
11. short circuit to +Ubatt (fbbE..._K)
12. short circuit to ground, line-break or over-heat (fbbE..._O)
The possibilities for diagnosis depend on the control of the power stage. Short circuit to
+Ubatt and overheat can only be recognized if the power stage is gated (conducting). Line-
break (and short circuit to ground) on the other hand can only be recognized for non-gated
(disabled) power stage.
The error codes 'line-break' and 'overheat' are reported by the power stage module in a
common bit combination. With occurrence of this bit combination the power stage is
disabled. After a delay time (ca. 200ms) it is constantly tested if the error 'line-
break/overheat' occurs again. If this is the case, 'line-break' is supposed and after eventual
recovery the power stage is enabled again. Else overheat is supposed and the power stage
stays disabled.
For short circuit the module switches off independently. PWM-power stages operate
with 5%-on/off ratio for errors recognized as finally defective.
For other error codes the power stage is furthermore controlled by the message ehmF...
Save error recognition (short circuit to Ubatt, short circuit to ground or line-break) for
the power stages used as PWM-outputs is only guaranteed if a filtering time of 60µs -
200µs (determined by the power stage module) is kept. This leads to limiting of the TV-
range for high control frequencies.
Example: Effect on power stage with 1 kHz control frequency (e.g.rail pressure governor)
KS-UBatt is recognized for gated power stage. The filtering time of 200µs means that
the power stage has to be gated for at least 200µs in order to recognize KS-UBatt. The
200µs correspond to a duty cycle of 20% for a frequency of 1 kHz. The same is valid for
error recognition of KS-ground and line-break. These errors are recognized for disabled
power stage.
The filtering time of 200µs means that the power stage has to be disabled for at least
200µs. The 200µs time-out correspond to an on/off ratio of 80% for 1 kHz.
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In summary this means that for a control frequency of 1 kHz the power stage errors of
the CJx20 can only be detected within the TV-range of 20 % - 80 %, while within this
range, for the rail pressure governor, the system errors are recognized indirectly by the rail
pressure sensor and the current-measuring of the rail pressure governor.
For application of the power stage frequencies these limitations have to be taken into
account.
2.3.4 Special case KDR power stage

The KDR-power stage differs from "other" CJx20-power stages by the additionally
implemented current control. Through this the meaning of the bits of the sensor ID
ehwEST_KDR and the state message ehmSKDR has been changed.
Dependent on the type of the high pressure pump in the system different current
controllers with several inputs are used for calculating the actuating values of the KDR-
powerstage. With a CP1-pump the controller setpoint is calculated from the message
ehmFKDR. With a CP3-pump the message zumQP_KDR is used for this. The the pump
type is selected by the software switch cowVAR_CP, CP1 is selected by 0 and CP3 by 1.
The power stage processing (e.g. battery voltage correction) is carried out as described
for the CJ420-power stage.
ehwEST_KDR:
Bit Value Meaning CP1 Meaning CP3
0-7 hardware assignment hardware assignment
8 1 power stage used power stage used
0 not used not used
9 1 current-controlled power stage not used
0 always only for controlled
operation
10 1 UBT-correction yes UBT-correction yes
0 no no
11 1 current-controlled power stage not used
0 not contolled
12 level at initialization/recovery level at initialization/recovery
1 High High
0 Low Low
13 1 invert TV invert TV
0 do not invert do not invert
14-15 not used not used
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The state message is structured as follows:

ehmSKDR:
Bit Value Meaning
0-13 equal the sensor ID
14 1 power stage defective
0 power stage intact
15 1 driving software active
0 diagnosis active
2.3.4.1 KDR current regulator for CP1

The current regulator is implemented as a time-synchronous PI controller. The setpoint
value of the controller is taken from the curve ehwTV_I_KL and depends on the control
value. The actual value anmIDV is made available by the analog value conditioning. If the
current through the actuator is not within the valid range [anwIDV_MIN, anwIDV_MAX]
or a short circuit and low-idle respectively is classified as finally defective, the current
regulator is switched off and the I-part of the current regulator is frozen.
The current control is always enabled if ehwEST_KDR.11 is set. If only
ehwEST_KDR.11 is set, the current control is active only during controlled rail-pressure
operation. If ehwEST_KDR.9 is set additionally, there is constant current control.
In any cases the battery voltage correction (ehwEST_KDR.10) can be switched as a
complement.
ehwEST_KDR.11 ehwEST_KDR.9 Status
0 0 no current control
0 1 no current control
1 0 current control only for contr. operation
1 1 constant current control
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anmIDV
ehwEST_KDR.9
zumPS_R_S >1
ehwEST_KDR.8
ehwEST_KDR.11
ehwEST_KDR.13 0
ehwEST_KDR.10 powerstage
ehmFKDR
TVMAX-TV ehoUKORR
13500mV
EHASTKDR.DSF
anmUBTKomp
Figure EH6 : Control of the KDR power stage CP1
anwIDV_KL
anmIDV KDR KDR

D/A current power
converter power
measurement stage stage
fboSIDV
fboSKDR.2 or fboSKDR.3 ehwEST_KDR.8
>1 mrmSTATUS.2
zumPS_R_S
0
& ehwEST_KDR.9 ehwEST_KDR.11 open loop
control activ
0
>1 100%
b ehwBEG_MAX
ehoI_IST
I=MAX-P-VST a>b a
ehmFKDR
ehoUKORR
100 %
b
I=MIN-P-VST a<b a ehwBEG_MIN

anmUBTKomp
13500mV
ehwEST_KDR.13 ehwEST_KDR.10
0
ehwTV_I_KL
ehwBEG_MAX
100 %
ehwBEG_MIN
ehwSTI_...
ehol_IANT
EHKDRIRE.DSF
ehwEST_KDR.13
ehol_SOLL ehol_RAW
ehwSTP_...
ehol_PANT ehmI_STEL
Figure EH7 : Current control KDR power stage CP1
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 EH271 1.0
2.3.4.2 KDR- current regulator for CP3

The CP3-current regulator is implemented as a two-step time-synchronous closed loop
controller. The setpoint ehoI_SOLL2 for the current is taken from the curve ehwQP_I_KL
depending on the control value of the rail pressure regulator zumQP_KDR.
The actuating value ehmI_STEL2 is calculated by a fast P-DT1 precontrol. The base
value is calculated by the P-component ehwKV_KDR, the DT1-component (ehwKD_GF
and ehwKDKOF) compensates the coil inductance of the actuator.
A slow PI-governor compensates specimen leakages as well as temperature fluctuations
affecting the ohmic resistance. The governor deviation ehoI_RAW2 is calculated after a
filtering from the setpoint of the current ehoI_SOLL2 and the actual value anmID2.
In case of an error in the current aquisition fboSIDV or in the KDR-power stage
fboSKDR.7 the governor is reset to Zero. The actuating value ehmI_STEL2 then
corresponds to the P-DT1 precontrol.
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 EH271 1.0
anmIDV D/A KDR

current
power
converter measurement
stage
anwIDV_KL
fboSIDV
≥1 fboSKDR.7
ehwSTPTIGF
b ehwKR_MAX
ehoI_IST2 I=MAX-P_ANT a>b a
a
I=MIN-P_ANT a<b b ehwKR_MIN
ehoI_KR
+
ehwKR_MAX
zumQP_KDR - ehwKI_... ehwKR_MIN
ehol_KI
ehwQP_I_KL ehwSTPTSGF
ehoPTout ehol_RAW2
ehwKP_...
ehol_KP
+ ehoI_STEL2
+
ehwKV_KDR ehwST_max
ehoI_STV ehwST_min
ehol_SOLL2
ehwKD_GF KDR_ICP3.DSF
ehwKDKOF
Figure EH8 : Current control KDR-power stage CP3
ehwEST_KDR.10 ehwEST_KDR.8
KDR
ehmI_STEL2 Powerstage
13500mV
EHASTCP3.DSF
anmUBTKomp
Figure EH9 : Controlling the KDR-powerstage (CP3)
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 EH271 1.0
2.3.5 Injector power stage error recognition

The injector power stages are diagnosed for the following error conditions:
1. overcurrent High-Side-branch (fbbEHS...)
2. overcurrent Low-Side-branch (fbbELS...)
3. load drop (fbbELA...)
4. fast deletion error (fbbESL...)
5. booster capacitor voltage outside window (fbbEUC...)
Overcurrent in Low- or High-Side-branch is if the injector current exceeds a maximum
value. Load drop is recognized if during gating the minimum current Imin is not exceeded.
If the power stage current after end of gating does not fall below Imin within a fixed, given
time, fast deletion error is diagnosed.
Remark: Threshold values are fixed by the hardware.
In addition a weighting of OK- and not-OK messages is performed for these error types,
this means that if an error is classified as temporarily defective, first ehwINJ_GTZ OK-
messages have to occur in sequence before the error debouncing for defect recognition is
reset. Thereby error messages are weighted higher than OK-messages.
This is done because of the following reason:
While the error bits are timed out from the power stage chain any defect that occurred at
this time cannot be saved in the power stage module (active shift register). Due to this fact,
an OK-message may occur which could incorrectly lead to a reset of the error debouncing
for the defect recognition (increase of the time for "finally defective" recognition). This is
prevented by the weighting.
2.3.6 UC monitoring
2.3.6.1 General
A possible hardware defect is to be detected by monitoring of the booster voltage. At a
defective powerstage transistor, alloyed-through free-wheeling diodes or short circuit of
cables the capacitor voltage does not rise to its nominal value.
However, the booster voltage final value will deviate from its setpoint, even if the
remaining recharge duration is no longer sufficient.
Therefore the monitoring function must recognize this case and take into account in the
error-treatment.
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 EH271 1.0
2.3.6.2 Hardware (cowV_UC = 0)

A dicrete sample&hold element has to be implemented to monitor the booster voltage.
This H&S stores the booster voltage before the injection. The switch is closed by the rising
BOB-edge. Afterwards the capacitor CS loads itself up to the divided booster voltage. The
switch is opened again with the rising ON-edge and CS stores the voltage value. In doing so
one receives the most current booster voltage measured after the recharging and before the
next injection.
2.3.6.3 Software (cowV_UC = 1)

To monitor the booster voltage, the voltage is measured shortly before an injection
(before a pilot-injection or, if no pilot-injection is programmed, before a main injection)
and written to a raw-value table (injection raw-value table).
2.3.6.4 UC aquisition
zhmSYN_ST = 4
&
(GAD synchronized)
inj. raw values cowV_UC = 1

(inj. ADC)
P2
U
anmUC?
W
t-sy raw values

UC1
1ms
ADC
UC2
DZ
n-sy raw values

I
last written n-sy value

anwUC?_KAN
ucacquis.dsf
Figure EH10: UC1/UC2 aquisition
2.3.6.5 Monitoring release

Monitoring of UC voltage is performed only if
• an odd segment (dzmSEGM.0 =1) and no time-out (dzmPECC_V.1 =0) is available.
• the engine speed exceeds a determined threshold (dzmNmit > ehwUC_N)
• no test-messages active applicable by ehwUC_TST during after-run
• the power stage are not locked
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 EH271 1.0
The message ehmBK_AUSW determines which bank is to be monitored.
.0
.1
mrmTST_AUS
.2
ehwUC_TST
.3
.4 ≥1
.5
.6
.7 EH_UEFG.DSF
dzmNmit a
ehwUC_N b a>b &
dzmSEGM.0
dzmPECC_V.1 &
ehmBK_AUSW = 1 release of UC1 - monitoring

&
powerstage1 not locked
ehmBK_AUSW = 2 release of UC2 - monitoring

&
powerstage2 not locked
Figure EH11: Monitoring release
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 EH271 1.0
2.3.6.6 Monitoring of recharge voltage

The calculated value determines the attainable booster voltage after recharging,
considering the recharge duration of the battery voltage and the recharge current.
This calculated value can now be compared to the really measured booster voltage.
From this it can be inferred whether the hardware functions correctly.
ehwUC_OFFS
_
ehoUC_MIN a
MIN +
anmUBT ehwUC_RMIN anmUCx b a>b
[0..100V]
ehoTRCHG
ehoUC_SOLL
MIN
zhwVERCHG ehwUT_KF
zhwHERCHG a
fbbEUCx_R
b a<b Entprellung
zhmIRCHG [0..2]
zhmIRCHGK 1
ehoNoInj
zuoAD_VE1 = 0 zhwIRK_KL ehmUCxFE

(Low-Byte) ehmUCxFE
(Low-Byte) fbbUCxRL
a>b
ehwUC_FGRZ
x = 1,2
ehwUCFINx
anmUCx a
ehoNoInj = 1 if time between two injections is longer than 32ms
Þ no calculation of values before switch
ehwUC_RMAX
b a>b
ehoTRCHG = max. permissible RCHG-period limited by zhw.ERCHG 1

and the intervall between two injections
ehmUCxFE
ehmUCxFE
(High-Byte)
(High-Byte) fbbUCxRH
a>b
ehwUC_FGRZ
EH_UERS. DSF
ehwUCFINx
Figure EH12 : Monitoring the recharge voltage
In case of an error a special error counter is increased by ehwUC_FINx (each for Uc too
low/too high) In case of an OK message it is decremented by 1 (engine speed
synchronous!). As soon as an error counter exceeds the threshold ehwUC_FGRZ, an entry
is made in fbbEUCxRH (voltage to high) resp. fbbEUCxRL (voltage to low) (100ms time
loop!).
Furthermore, there is still the error fbbEUCx_R. This error is reported, if the attainable
booster-voltage is below the fixed monitoring-threshold ehwUC_RMIN. This occurs when
the recharge duration was not sufficent which has to be attributed to an unfavourable
application. This error should be active during the application phase and suppressed for the
series phase.
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 EH271 1.0
2.3.7 Drive on at injector load decrease

If injector load decreases are recognized as finally defective the number of the failed
injectors is reported in the message ehmILA and the fuel quantity limiting at system error is
activated (at cowV_FMB_3.2 = 1).
ehmILA = fboSI11.3 + fboSI21.3 + fboSI31.3 + fboSI41.3 + fboSI12.3 + fboSI22.3 +
fboSI32.3 + fboSI42.3
The capacitor voltage monitoring fbwEUCxRL of the respective bank has to be switched
off because the injector is no longer available for recharging.
When the number of the failed injectors exceeds the maximum permitted number
ehwInjLAmx, the engine is turned off.
In case that the maximum permitted number of dropped-off injectors ehwInjLAmx is
applicated to Zero, the capacitor voltage monitoring stays active even if injector errors are
reported.
2.3.8 Error chain of power stage modules
EHERR.DSF
µC
CY220 CJ920 CJ420
P6.7 T T T
P6.5 SY SY SY
P6.6 DA DE DA DE DA DE
Figure EH13 : Error chain of power stage modules.
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 EH271 1.0
2.3.9 Activating CJ920-error diagnosis

Error diagnosis of the CJ920 power stages may be disabled under certain operating
conditions. Therefore following masks are available:
ehwDIAnor: mask for activating error diagnosis in normal operation
ehwDIAubt: mask for activting error diagnosis in case of too low battery voltage
(Ubat < ehwUBT_MIN)
ehwDIAsta: mask for activating error diagnosis at engine start (mrmSTART_B = 1 and
dzmNmit > 0)
error report
short circuit or load decrease recognized fbbE..._K

fbbE..._0
ehwDIAnor.x
1
ehwDIAubt.x
Ubat < ehwUBT_MIN & x = 0...15
ehwDIAsta.x
&
mrmSTART_B
dzmNmit > 0
FEHLERDI.DSF
Figure EH14: Activating the error diagnosis
Assignment of the masks:

Bit 0 1 2 3 4 5 6 7
power stage RS1 DIA LDS LF1 EAB LF2 KHP MIL
Bit 8 9 10 11 12 13 14 15
power stage GAZ GZS ARS KDR LDK EKA --- ---
K5/ESM 1.12.1999 EH
Y281 S01 271-V10 EDC 15C B271.V10 PHNSYK01 2.3
2.4 Engine speed signal

2.4.1 TDS-A-signal generated by HW
The engine speed signal is derived from the incremental engine speed signal (DZG). It
is given out even during the gap of the incremental engine speed signal. The dividing
factor is generated by a 10 bit prescaler, which runs with half-increment pulses. A
hardware divider from the Gate Array is used to guarantee a minimum jitter. The dividing
factor is set by zhwTD_TEIL.
To get an engine speed signal which toggles cylinder synchronous:
cylinder angle
zhwTD_TEIL =
1 ∗ increment angle
2
for example (4 cylinder, 60 increments):
90° 90°
zhwTD_TEIL = = = 30
1 ∗ 360°/60 3°
2
2.4.2 TD-signal generated by SW

The TD engine speed-synchronous signal is a pulse-width modulated signal and is
issued at the control unit. The signal is used to indicate the engine speed , or it is used as
input for the automatic transmission.
dzmSEGM
pht_NSYN TD_HPD
pheK_TDvt
phmTD_HPD speed signal
cowV_TD
SISTRK.DSF
Figure SI1: Structure of engine speed signal
K5/ESM 1.12.1999 SL
Inputs:
phek_TDvt prescaler
phmTD_HPD high level duration TDS
dzmSEGM segment number
cowV_TD variant switch (off/ high/ low/ toggle)
The task pht_NSYN is carried out speed-synchronous with the engine speed interrupt
CC6 and creates a pulse-width modulated signal for engine speed information.
2.4.2.1 Task pht_NSYN

The task for creation of the engine speed signal is carried out speed-synchronous. Per
dzmSEGM interrupts the output is switched according to the selected signal type. The
received message phmTD_HPD includes the high level duration. By the data parameter set
phdK_ the following can be selected.
Data parameter set phdK_:

pheK_TDvt: DZG-pulse prescaler3 (range of values 0..7)
dzmSEGM
pheK_TDvt=1
pheK_TDvt=2
pheK_TDvt=4
0ms 15ms 30ms 45ms 60ms
n=1000 min -1 4 cylinder

SIDZGIVT.DSF
Figure SI2: DZG-pulse prescaler
3
Periodic signal 1 or 2 or 4 for 4 cylinder engine
K5/ESM 1.12.1999 SL
The data parameter set phdK_ is actuated in a recovery routine, so that changing the
prescaler takes effect only after a reset.
cowV_TD: engine speed signal type (0..3)
cowV_TD=0
off
cowV_TD=1 high
cowV_TD=2 low
toggle
cowV_TD=3
SIDZSTYP.DSF
Figure SI3: engine speed signal type
The variant switch cowV_TD is actuated in a recovery routine, so that changing the
signal type takes effect only after a re-set. Influence on the high level duration is always
possible by the received message pheTD_HPD.
K5/ESM 1.12.1999 SL
Y281 S01 271-V10 EDC 15C B271.V10 FGK01 2.19
2.5 Vehicle speed measurement (HW-SIGNAL)

For calculation of the vehicle speed the HW-signal of a vehicle speed sensor (FGG) or a
CAN message is used depending on the variant switch cowVAR_FGG.
cowVAR_FGG:
Value Meaning
1 vehicle speed via FGG
8 vehicle speed via CAN-Message
The vehicle speed sensor (FGG) provides a vehicle speed-proportional number of

pulses. The pulses since last calculation are counted and evaluated. For calculation of the
vehicle speed the summarized total period of the vehicle speed pulses is divided by the
number of FGG pulses. To get the scaled vehicle speed, the total period is multiplied with
the distance factor fgw..._SF and divided by the number of pulses.
This results in the arithmetical average of the vehicle speed since the last calculation.
t(k-1) t(k)
whole period
t-high
FGG-Signal
i+1 i+q
FGIMPSIG.DSF
Figure FG1: FGG-pulse evaluation
3,6 × frequency [Imp / sec ] fgmDAT_NE − 2

v[Km/h] = fgmDAT_SF [Imp / m ]
×2
The distance factor fgmDAT_SF is determined by the customer. It is equivalent to the

number of pulses per meter wheels circumference.
Hint: The vehicle speed to be sampled can be applicated by means of the scaling
exponent fgmDAT_NE.
The scaling exponent permits only integer values from 2 to 8.
(default 2)
K5/ESM 1.12.1999 FG
Y281 S01 271-V10 EDC 15C B271.V10 FGK01 2.19
Example:With the distance factor 5,5 pulses/sec the scaling exponent can be chosen as 3
to get an integer denominator:
3,6 × frequency [Imp / sec ] 3,6 × frequency [Imp / sec ] 3− 2

v[Km/h] = 5,5[Imp / m ] × 2
×2 = ×2
11[Imp / m ]
The vehicle speed is PT1-filtered (fgwFGF_GF) and made available to the system as
fgmFGAKT.
Exceeding the maximum vehicle speed fgw..._VMA is reported by the error
fbbEFGG_H. At occurence of a FGG error the default value fgw..._VGW is output.
In after run (dim15 = 0) this check is not performed, provided that no terminal15 error
(fbbEK15_P) is present.
fgmVsource is initialized by cowVAR_FGG.
fgmVsource = 8
camFGAKT
fgw..._VGW
fgmFGAKT
calculated speed
fboSFGG<>0
fgwFGF_GF
fgmFGUEB
0
fgmVsource = 1
a
fgw..._VMA b
a>b & error
debouncing
fbbEFGG_H
fbwEFGG_HA
..._HB
dimK15 ..._HT
fbbEK15_P >1
FGFGBER.DSF
Figure FG2: Vehicle speed calculation
fgmFGUEB is the calculated vehicle speed. The status fgmFGUEBST becomes Zero if
no pulses have been received (measurement invalid) during the time fgw..._TMX.
K5/ESM 1.12.1999 FG
Y281 S01 271-V10 EDC 15C B271.V10 FGK01 2.19
Remark: The parameters fgw..._TMX and fgw..._SF have to be be applicated identically

within one parameter set!
The status of the vehicle speed measurement can be seen from the status fgoSTAT:
fgoSTAT:
Bit Meaning
0 evaluation of ABS
15 vehicle speed default value active
2.5.1 Calculation of the vehicle speed with CAN message

The vehicle speed camFGAKT from the CAN application layer received by the CAN is
transmitted as fgmFGAKT in the vehicle speed measure module.
CAN vehicle
camFGAKT fgmFGAKT
Application Speed
Layer measuring
FGMSG.DSF
Figure FG3: Vehicle speed as CAN message
2.5.2 Calculation of acceleration (HW-SIGNAL)
fgwABS_BMX
calculated speed fgmBESCH
calculated speed ´old´

fgwBEF_ fgwABS_BMI
whole period duration FGBESCH.DSF
Figure FG4: Calculation of acceleration
K5/ESM 1.12.1999 FG
Y281 S01 271-V10 EDC 15C B271.V10 FGK01 2.19
For calculating the acceleration the difference between current vehicle speed and "old"
vehicle speed is divided by the total period.
The result is PT1-filtered. Afterwards the result is limited to a maximum value
fgwABS_BMX and a minimum value fgwABS_BMI.
The calculated acceleration is made available by the message fgmBESCH.
2.5.3 Ratio vehicle speed to engine speed (HW-SIGNAL)

For calculation of v/n the filtered vehicle speed is divided by the averaged engine speed.
The thus calculated value is limited to fgwDAT_VNX and afterwards it is PT1-filtered
(fgwVNF_GF). It is made available to the system as fgm_VzuN .
At engine speed Zero the value Zero is used.
If a vehicle speed sensor defect occurs, the value Zero is output.
dzmNmit = 0
fboSFGG<>0
fgmFGAKT
dzmNmit MIN
fgwABS_VNX fgm_VzuN
0
fgwVNF_ 0
FGVZUN.DSF
Figure FG5: Calculation of v/n
K5/ESM 1.12.1999 FG
Y281 S01 271-V10 EDC 15C B271.V10 FGK01 2.19
2.5.4 Ratio vehicle speed to engine speed from CAN (EGS)

For activated EGS command (cowFUN_CAN) the message fgm_VzuN is formed from
the received current gear mrmGANG.0 ... 3 using the data set parameters fgwEGS_...
Here a corresponding v/n is applicable for each gear.
fgwEGS_G00 N
fgwEGS_G01 1
fgwEGS_G02 2
fgwEGS_G03 3
fgwEGS_G04 4 cowVAR_GTR = 1
fgwEGS_G05 5
fgwEGS_G06 6
fgwEGS_G07
fgm_VzuN
fgwEGS_G08
fgwEGS_G09
fgwEGS_G10
fgwEGS_G11 R
fgwEGS_G12 R2
fgwEGS_G13 P
fgwEGS_G14
FGVNCAN.DSF
mrmGANG Bit 0-3
Figure FG6: Calculating v/n from mrmGANG
2.5.5 Vehicle speed sensor monitoring

The vehicle speed sensor is monitored during operation. Monitoring is finished if the
message fgmFGUEBST = 1. E.g. the last vehicle speed measure is valid. Test condition is:
• current injection quantity mrmM_EAKT is above the quantity threshold
mrwUEB_CNM.
• engine speed dzmNmit is above the engine speed threshold mrwUEB_CNN.
• fboSFGG.1,.3 intact
If these conditions are fulfilled, the current vehicle speed fgmFGAKT is compared with
the vehicle speed threshold mrwUEB_CNV. If fgmFGAKT < mrwUEB_CNV, the error
fbbEFGG_P is reported and debounced.
K5/ESM 1.12.1999 FG
Y281 S01 271-V10 EDC 15C B271.V10 FGK01 2.19
fbbEFGG_H
fbbEFGG_F &
dzmNmit a
a>b
&
mrwUEB_CNN b
mrmM_EAKT a
mrwUEB_CNM b a>b
fgmFGUEB
a
& error
error
debouncing
fbSEFGG_P
mrwUEB_CNV b a<b
& intact
MRNACFGF.DSF
Figure FG7: Vehicle speed sensor monitoring
Application hint: The error debouncing times fbwEFGG_PA and fbwEFGG_PB have to
be set to a value of ≥ 30ms.
K5/ESM 1.12.1999 FG
Y281 S01 271-V10 EDC 15C B271.V10 MRGBVK01 2.2
2.5.6 Gear selection using the v/n ratio

The transmission type is determined by the variant switch cowVAR_GTR. For manual
shift transmission (cowVAR_GTR = 1) the ratio vehicle speed to engine speed fgm_VzuN
determines the selected gear using the following thresholds.
gear band
fgwGang_1U fgwGang_2U fgwGang_3U fgwGang_4U fgwGang_5U
fgwGang_1O fgwGang_2O fgwGang_3O fgwGang_4O fgwGang_5O
fgm_VzuN
Gang_1 Gang_2 Gang_3 Gang_4 Gang_5
fgwGang_12 fgwGang_23 fgwGang_34 fgwGang_45
mrmGANG.6
1 0 1 1 0 1 1 0 1 1 0 1 1 0 1
(rolling)
GEAR fgwGang1 fgwGang2 fgwGang3 fgwGang4 fgwGang5
MRVNBAND.DSF
gear window
Figure FG8: Subdivision v/n band in gear ranges
K5/ESM 1.12.1999 FG
After shifting into gear and disengaging the clutch the engine speed and the vehicle
speed are linked resulting in discreet values of the v_zu_N -ratio (v/n). By establishing of
fixed thresholds between these discreet values an inference to the gear can be made. ( see
table):
range mrmGANG (Bit0...Bit3)
fgm_VzuN < fgwGang_12 fgwGang1
fgwGang_12 < fgm_VzuN < fgwGang_23 fgwGang2
fgwGang_89 < fgm_VzuN fgwGang9
The assignment of mrmGANG dependent on the window is not fixed but varies by the
application of the values fgwGang1 - fgwGang9.
If a transmission is not in gear, there is no fixed value for fgm_VzuN. As per table it
would be assigned to a random gear. This has negative effects on the parameter selection
for certain EDC-governors (e.g. low-idle governor). For this, additionally to the windows
thresholds, so-called bands-thresholds are implemented which can be applicated close to
the discreet v_zu_N-ratios. Now it can be recognized whether it has in fact shifted into
gear or that the engine and the driving line have no connection. When the v/n ratio is
within these narrow bands, the condition "in gear" is recognized. Otherwise it is assigned
to freely rolling vehicle and this is set in bit 6 of mrmGANG:
K5/ESM 1.12.1999 FG
gear range mrmGANG mrmGANG.6

bands (Bit0...Bit3) (rolling)
fgm_VzuN < fgwGang_1U fgwGang1 1
gear_1 fgwGang_1U < fgm_VzuN < fgwGang_1O fgwGang1 0
fgwGang_1O < fgm_VzuN < fgwGang_2U fgwGang1/ 1
fgwGang2
fgwGang3
fgwGang4
fgwGang5
fgwGang6
fgwGang7
fgwGang8
fgwGang9
fgwGang_9O < fgm_VzuN fgwGang9 1
K5/ESM 1.12.1999 FG
Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
2.6 Engine speed measurement

The engine speed interrupt is derived from the crankshaft signal using a prescaler. The
prescaler is calculated form the number of crankshaft pulses / number of cylinders. See
also chapter "Parameters for adjusting the injections" for further information regarding
adjusting the interrupt. From the period between two interrupts the current engine speed
and an averaged engine speed is calculated and the differential speed is checked for
plausibility. Additionally for each engine speed interrupt a synchronization signal for
speed-synchronous tasks is issued if the period < dzwDZG_ABT .
DZ
dzmSEGM
DZG Interrupt
Speed interrupt
dzmNakt
dzmNmit
Speed calculation dzmPECC_V
DZG Timeout dzmABTAS
dzmUEBER
DZSTRK.DSF
Figure DZ1: Structure of engine speed measurement
Outputs:
dzmSEGM segment number
dzmNakt current engine speed
dzmNmit engine speed
dzmPECC_V dynamical timeout
dzmABTAS sampling time
dzmUEBER overspeed
K5/ESM 1.12.1999 DZ
Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
2.6.1 Engine speed interrupt

The TD-signal supplies a number of edges proportional to the number of cylinders. For
each edge of the pulse the interrupt is activated. The period of such TD-pulses is registered
in the interrupt. Speed-synchronous tasks are activated by this interrupt above an engine
speed limit (maximum activating period = dzwDZG_ABT). The operating system prevents
activation periods from being to short (e.g. for high engine speeds) by outmasking the
corresponding number of activations.
In order to limit the calculator load the activation of several engine speed synchronous
tasks above defined engine speed thresholds can be restricted.
Label Meaning
dzwDIAOff Above this engine speed threshold there are no cylinder-selective
engine speeds and no misfire recognition is carried out.
dzwAbsch Above this engine speed threshold all engine speed governors are
calculated every other engine speed interrupt. (The engine speed
threshold must be higher than or equal to mrwLRNSMAX).
dzwREGOff Above this engine speed threshold the fuel quantity compensation
governing, the low-idle governor and the cylinder balancing are no
longer calculated. (This engine speed threshold must be higher than
dzwAbsch.)
arwAR_Off Above this engine speed threshold the exhaust-gas recirculation is
shut off.
mrwARDOff For the ADR in addition the minimum time between two task calls
can be defined in us. If the engine speed interrupts are triggered off in
shorter intervals, the ARD is not calculated during this interrupt.
mrwLRNSMAX Above this engine speed threshold the cylinder balancing is no longer
calculated.
The segment number is transmitted to the system by the message dzmSEGM. The
current engine speed period is written to the OLDA dzoDZGPERH or dzoDZGPERL. This
output occurs only if speed-synchronous tasks are activated.
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Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
2.6.2 Engine speed sensor time-monitoring

The time-monitoring checks the maximum activation period of speed-synchronous tasks
(dzwDZG_ABT) and the dynamic time-out for recognition of engine speed 0.
In case of exceeding the maximum activation period dzwDZG_ABT the bit
dzmPECC_V.1 is set and the speed-synchronous tasks are activated time-synchronous with
the interval dzwDZG_ABT .
A dynamic time-out dzmPECC_V.2 is recognized if no further engine speed interrupt is
detected after a maximum time. The time until time-out results from the last period: t = last
period * dzwDZGt_FA + dzwDZGt_OF. This time is limited to a minimum (dzwDZGt_MI)
and a maximum (dzwDZGt_MX). Time-out processing is carried out every 2ms. Dynamic
time-out is used to detect interrupt failures (complete failure), it is a reaction time adapted
to the engine speed. In case of a time-out the actual value of the engine speed (dzmNakt) is
set to 0.
dzwDZGt_MX
last period * dzwDZGt_FA + dzwDZGt_OF a

dzmPECC_V.2
b
a<b
dzwDZGt_MI
current period
DZDYNIMP.DSF
Figure DZ2: Dynamic time-out
The message dzmPECC_V shows the status of the time-out task.

dzmPECC_V:
Bit Meaning
0 engine speed cannot be measured
1 dzoDZGPERL, dzoDZGPERH > dzwDZG_ABT
2 dynamic time-out (sensor failure)
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Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
Time since the last interrupt.

[ms]
dzwDZGt_MX dynamic timeout
204
202
36
34
t-sync. Schedule
32
30
n=n*dzwDZG_MVE
28 or tooth missing
Expected interrupt
at constant speed
26
24 dyn.Plaus.=1
22
20
18
16
14 n=n*dzwDZG_MBE
12
dzwDZGt_MI
dyn.Plaus.= 0
6
Interrupt is too early
4
2
dyn.Plaus.=1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 [ms]
3000 1000 500 400
[RPM] 5 cylinders
2000 (Last period duration)
dzwDZG_UNS
DZDYNPLS.DSF
(Speed limit for dyn.plaus.)
Figure DZ3: Timeout and dyn. plausibility
K5/ESM 1.12.1999 DZ
Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
2.6.3 Engine speed calculation from DZG-signal

2.6.3.1 Engine speed calculation and averaging
This is only processed if speed-synchronous tasks are activated.
The sampling-time is determined from the activation period of the speed-synchronous
task and is made available to the system as dzmABTAS.
The current engine speed is determined from the scaling constant dzwDNR_HI,
dzwDNR_LO and the period (scaling constant / period) and made available to the system as
dzmNakt. For high engine speed the summarized periods of those DZG-pulses detected
since last activation are used. Above the engine speed threshold dzwAbsch this averaging is
no longer carried out.
The averaged engine speed is calculated from the two last valid current engine speeds
according to the formula:
current engine speed(k) + current engine speed(k - 1)
averaged engine speed =
2
This engine speed is made available to the system as dzmNmit.

The current engine speed dzmNakt is set to 0 if the period exceeds the threshold
dzwDNR_NU.
Under certain conditions (before synchronization / during the monitoring module test in
after-run) the sampling of engine speed is not possible because no the engine speed
interrupt is generated. In this case an auxiliary engine speed is calculated from an internal
register (INKPEDA) of the gate array, in which the time between 2 teeth is stored.
Afterwards this rough engine speed is filtered by a PT1-component (memory factor
zhwINKPGF). This calculated auxiliary engine speed dzmNink is copied to dzmNakt if the
conventional determined engine speed equals zero and the start bit is set ,or if the condition
“monitoring module test in after run" is attained. Furthermore the disturbance fade out
must not be active. Independently by it, dzmNmit is calculated from dzmNakt . The
monitoring for dynamic plausibility is switched off during the monitoring module test in
after-run.
K5/ESM 1.12.1999 DZ
Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
engine speed
calculation dzmNakt
from interrupt edges dzmNink
engine speed calculation
from tooth distance
(INKPEDA)
zhwINKPGF
disturbance fade out
inactive
&
engine speed calculation
from interrupt edges = 0
mrmSTART_B = 1
&
DZNACTST.DSF
monitoring module test

in after-run
³1
Figure DZ4: Sampling of engine speed

before synchronization / during monitoring module test
2.6.3.2 Dynamic plausibility

Test conditions:
• last valid engine speed > dzwDZG_UNS
• number of segments since start > dzwDZG_AUS
• current period duration > > dzwDZG_MXP
Error dynamic plausibility is recognized if:
last period duration last period duration

> dzwDZG_MBE or < dzwDZG_MVE
currrent period duration current period duration
If dynamic implausibility is recognized, the engine speed dzmNakt is frozen.

The error can be recovered during the time until finally defective if the ratio of the last
valid period (period before occurrence of the error) and the current period is more than
dzwDZG_KMX times within the valid range.
K5/ESM 1.12.1999 DZ
Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
If the condition for dynamic implausibility is fulfilled for longer than

t = last valid period (period before occurrence of the error) ⋅ (dzwDZG_DPL , lower
limit given by the main program period)
finally defective is recognized. The entry fbwEDZG_DA must be 0 for dynamically
calculated ’times until finally defective’, else the value fbwEDZG_DA is added to the
calculated time.
Dynamic plausibility is used to detect sporadic pulse failures. In case of finally
defective the actual value of the engine speed is set to 0.
Recovery after finally defective can occur if the engine speed remains with the last valid
engine speed (dzmNmit before finally defective) within the window of intact recognition
(dzwDZG_FNS) for longer than the time fbwEDZG_DB.
Calculation of the engine speed window:
[dzmNmit * (1 + dzwDZG_FNS)] and [dzmNmit * (1 - dzwDZG_FNS)]
For checking this calculation the engine speed has to be calculated from the period
(same as dzmNakt), because it is set to 0 during this time.
2.6.3.3 Overspeed
Overspeed is recognized when the engine speed exceeds dzwDZG_NUS (engine speed
threshold for overspeed) (error type fbbEDZG_U). Overspeed recognition can be masked
out for the time dzwDZG_UBD after detecting the first DZG-pulse.
The value in the engine speed messages dzmNmit, and dzmNakt is frozen in case of
temporary defect of the engine speed sensor. In case of finally defective engine speed
sensor the value 0 is issued.
K5/ESM 1.12.1999 DZ
Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
2.6.3.4 Engine speed gradient

d_Phi
DZI -2 -1 0 1 2 -2 -1 0 1
dT1, dP1 dT2, dP2

dTZ
dTB
Z1 Z2
Z1-1 Z2-1
Z1-2 Z2-2
2
1 1
0 0
t -20 0
[ms]
DZGRADIENT.DSF
Figure DZ5: Calculation of the engine speed gradient
Angle of the second sampling: dP2 = (Z2 – 1) ⋅ d_Phi

Angle of the first sampling: dP1 = (Z1 – 1) ⋅ d_Phi
(dT1 + dT2)
Sampling rate: dTB = dTZ +
2
dP2 dP1
Engine speed: n2 = ; n1 =
dT2 dT1
n2 - n1 dP2 ⋅ dT1 - dP1 ⋅ dT2
Engine speed gradient: dn_dt(k) = =
dTB dT1 ⋅ dT2 ⋅ dTB
The gradient of the engine speed dzmDNakt is calculated by the sampled time dT1, dT2,
dTZ and the angles dP1 and dP2. Following values can be detected:
dzmDN_T1 → dT1
dzmDN_T2 → dT2
dzmDN_TZ → dTZ
dzmDN_P1 → dP1
dzmDN_Z2 → Z2
dzmDN_Def indicates unusual conditions during sampling.
A high byte of dzmDN_Def being unequal to zero means that sampled times are greater
than 65 ms. At this low engine speeds the gradient is not calculated but set to zero (even
with an error of the DZG: fbbEDZG_D or fbbEDZG_U).
K5/ESM 1.12.1999 DZ
Y281 S01 271-V10 EDC 15C B271.V10 DZK01 2.15
K5/ESM 1.12.1999 DZ

Description of Functions EDC 15C B271.V10 - 2

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Description of Functions EDC 15C B271.V10 - 2

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Description of functions Page 2-1

Y281 S01 271-V10 EDC 15C B271.V10 AN271 1.0

Figure AN1: Structure of analog value conditioning

2.1.1 Analog value sampling

The number of logical MUX groups is determined by the software.

2.1.2 Analog value evaluation (error reaction)

defect recognition time

Figure AN2: Analog value evaluation

Assignment of the sensor ID in the data set:

meas. value applicable recommended

Meaning of the data fields:

2.1.2.1 Diagnosis message

Figure AN3: Forming of the diagnosis message

2.1.2.2 Evaluation of the accelerator pedal sensor

Figure AN4: Evaluation of the PWG

2.1.2.3 Evaluation of the redundant accelerator pedal sensor

Figure AN5: Evaluation of the PGS

2.1.2.4 Evaluation of the atmospheric pressure sensor

anwADF_MIN anwADF_KL fbwEADF_L

Figure AN6: Evaluation of the ADF

2.1.2.5 Evaluation and plausibility check of the water temperature sensor

& start anoW_Zt

Figure AN7: Water temperature plausibility check after engine start

2.1.2.6 Evaluation of the boost-pressure sensor

anoU_LDFA SRC failed

Figure AN8: Evaluation of the LDF

2.1.2.7 Evaluation of the fuel pressure sensor

Figure AN9: Evaluation of the KDF

Fuel pressure sensor plausibility-check:

Figure AN10: Fuel pressure sensor test-plausibility of the KDF

Olda anoKDFTst shows the current test status :

2.1.2.8 Evaluation of the fuel pressure sensor current

anwIDV_MIN anwIDV_KL fbwEIDV_L

Figure AN11: Evaluation of the IDV

2.1.2.9 Evaluation of the air mass meter

anoU_LMM anoLMM_KL anoU_LMM1S anoU_LMM2S

2.1.2.10 Evaluation of the exhaust stroke indicator

[mV] [mm] error

anwAHR_MIN anwAHR_KL fbwEAHR_L

Figure AN13: Evaluation of the AHR

Calculation is carried out only if cowVAR_ARF is set to “control by AHR”. During

2.1.2.12 Sampling of the booster voltage UC1 (one-bank operation)

One-bank operation: see chapters "Injector-powerstages error recognition" and "Check of

2.1.2.13 Error processing of the sensor supply voltage

Figure AN14: Sensor supply

2.1.2.14 Sensor assignment to supply rails

2.1.2.15 Application hints for error handling

This can be achieved by an appropriate application of the error debouncing times.

2.2 Digital signal inputs

Figure DI1: Processing of the digital inputs (general)

dioROH0.13 dimDIGpre0.13 plausibility dimBRE

Figure DI2: Processing of the digital inputs (e.g. brake input)

Figure DI3 : Debouncing of the digital inputs

2.2.1 Brake information conditioning

The error "implausibility after initialization" fbbEBRE_I is reported if there is an

after init.: fbbEBRE_I

2.2.2 Clutch information conditioning

2.2.2.1 Transmission type = manual shifting (cowVAR_GTR = 1)

F=0* && status = Init 1

status = 1st clutch signal transition

Figure DI5: State machine

If the defect recognition (fbwEKUP_PA) is running, fbbEKUP_P is set and switched to

2.2.2.2 Transmission type = automatic (cowVAR_GTR= 2)