ES2C4: Computer Architecture and Systems

2022-2023

Lecture 9
Computer Systems Organisation
(CSO) - Part 4
Dr. D. D. Iliescu
School of Engineering, University of Warwick

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 1 of 24

Contents 1. Serial I/O
1.1. Serial vs. Parallel
Interfaces
1.2. SPI
1. Serial I/O 1.3. UART)
1.4. I2C
1.5. High Speed Serial
1.1. Serial vs. Parallel Interfaces Interfaces
2. Timers, PMW and Interrupts
1.2. Serial Peripheral Interface (SPI) 2.1. Timers
2.2. PWM
2.3 Interrupts
1.3. Universal Asynchronous Receiver/Transmitter (UART)
1.4. Inter-Integrated Circuit (I2C)
1.5. High Speed Serial Interfaces
2. Timers, PMW and Interrupts
2.1. Timers
2.2. Pulse-Width Modulation (PWM)
2.3 Interrupts

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 2 of 24

1. Serial I/O
1.1. Serial vs. Parallel Interfaces

▪ GPIO: One or several bit sent in each transmission

• GPIO communication limited to number of free GPIO pins.
• Better to break message into multiple smaller transmissions. Therefore more data
can be sent with less pins.

▪ Parallel I/O: Connect 1 wire / bit of information, several wires

• (e.g. 8-bit parallel interface - a byte at a time)
• Also send clock or REQ/ACK (request/acknowledge) to indicate when data is ready
• Parallel busses are expensive and cumbersome because of large number of wires
• Mostly used for high-performance applications such as DRAM interfaces

▪ Serial interface sends one bit at a time, over a single wire

• Use many clock cycles to send a large block of information
• Also send timing information about when the bits are valid
• Popular I/O for microcontrollers as fast enough for many applications

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 3 of 24

1. Serial I/O
1.1. Serial vs. Parallel Interfaces (cont.)

▪ Parallel I/O: Several bits sent per transmission

▪ Serial I/O: One bit sent per transmission:

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 4 of 24

1. Serial I/O
1.1. Serial vs. Parallel Interfaces (cont.)

▪ Many standards for serial I/O

• Serial Peripheral Interface (SPI)
• Universal Asynchronous
Receiver/Transmitter (UART)
• Inter-Integrated Circuit (I2C)
• Universal Serial Bus (USB)
• Ethernet

▪ MCUs have dedicated hardware

to send data via these standards
e.g. STM32 MCU on Nucleo Board

Nucleo L432KC Pinout (detail)

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 5 of 24

1. Serial I/O
1.2. Serial Peripheral Interface (SPI)

▪ Interface requires three lines (minimum):

• Serial clock (SCK).
• Master Out Slave In (MOSI)
also known as SDO.
• Master In Slave Out (MISO)
also known as SDI.
• An additional Chip Enable (CE)
also known as CS, SS or NSS pin
could be used to select a peripheral device.
▪ Could be used to connect more than one device
• More than one selector pin required
• Active on 0 (turns ON device), inactive on 1 (turns OFF device)

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 6 of 24

1. Serial I/O
1.2. Serial Peripheral Interface (SPI) (cont.)

▪ Bit change on the falling edge of SCK.

▪ SPI transmission:
• Master (MCU) produces the clock signal.
• Master initiates communication by sending a series of clock pulses.
• Sending-Master puts data on MOSI starting with most significant bit.
• Receiving-Slave puts data on MISO.
• e.g. 8 bit data transmission

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 7 of 24

1. Serial I/O
1.3. Universal Asynchronous Receiver/Transmitter (UART)

▪ Communication without clock. Therefore Data Terminal and Data

Communication devices are not synchronised – asynchronous.
▪ System agrees on data rate – each device generates it own clock.
▪ Protocols include RS-232 and RS-485.
▪ Slower than SPI.

▪ Baudrate
• Signalling rate measured in symbols per second.
• Multi-level signalling –multiple bits per symbol.
• 2-level signalling –each symbol represents a bit.
• For 2-level signalling at 9600 baudrate with a start and stop bit for every 8
bits data, Data Rate = bits transferred per second (b/s):
= 9600 * (8 bits / 10 symbols) =7680 bits/second
Character sent per second = 7680 / 8 = 960 characters/second
© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 8 of 24
1. Serial I/O
1.3. Universal Asynchronous Receiver/Transmitter (UART)(cont.)

▪ UART transmission:
• Lines are at logic ‘1’ when not in use.
• Each character is sent as:
- Start bit (logic ‘0’)
- 7 or 8 data bits
- parity bit (optional)
- One or more stop bits (logic ‘1’).

• Parity bit
- Used to detect if transmission was corrupt.
- Configured as even or odd.
- Even parity –chosen so that total collection of data and parity has an even number of
‘1’s. Receiver checks if even number of 1’s was received and signals an error if not.
- Odd parity is the reverse.

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 9 of 24

 1. Serial I/O
1.4. Inter-Integrated Circuit (I2C)

▪ Interface requires two lines:

• SDA –bidirectional data signal.
• SCK –clock signal.
▪ Bus drivers are open drain. Can pull signal line low, but cannot drive it high.
Thus each signal line has pull-up resistor to restore signal to high.

▪ Updates the obsolete terminology regarding names for device roles

https://learn.sparkfun.com/tutorials/i2c/all
© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 10 of 24
 1. Serial I/O
1.4. Inter-Integrated Circuit (I2C) (cont.)
▪ Interface I2C transmission:
• Start Condition
- Master leaves SCL high
- Pulls SDA line
- Generates clock pulses
• Stop condition
- SCL pulled high and remains
- SDA is pulled high.
https://learn.sparkfun.com/tutorials/i2c/all
© 2022-2023 ES2C4
• Address Frame
- Always sent first for new communication
- 7-bit address MSB first
- R/W bit indication a read (1) or write (0) operation
• Data Frame
- Sent based on R/W
- Length is arbitrary
Lecture 9 - Computer Systems Organisation (CSO) - Part 4 11 of 24
1. Serial I/O
1.5. High Speed Serial Interfaces

▪ Interface Encoded data containing both data and clocking information is sent
in a single differential signal.
• Speeds up to 60 GB/s
▪ Examples include:
• PCIe
• HDMI
• SATA
• USB 3.1
• DisplayPort

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 12 of 24

1. Serial I/O
Summary
▪ 1.1. Serial vs. Parallel Interfaces
• GPIO is limited
• Interfaces included in MCU
▪ 1.2. Serial Peripheral Interface (SPI)
• Simple, easily implementable
• Supports more than one peripheral
▪ 1.3. Universal Asynchronous Receiver/Transmitter (UART)
• Asynchronous
• Various speeds
▪ 1.4. Inter-Integrated Circuit (I2C)
• Peripherals are addressable
▪ 1.5. High Speed Serial Interfaces
• Speeds up to 60 GB/s

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 13 of 24

 2. Timers, PMW and Interrupts
2.1. Timers

▪ 32-bit micro-
controller unit

STM32L342KC MCU
chip

Organisation of
STM32L342KC MCU

https://deepbluembedded.com/getting-started-with-stm32-arm-cortex-mcus/
© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 14 of 24
2. Timers, PMW and Interrupts
2.1. Timers

▪ CPU/MCU executes instructions in rhythm with the clock.

• Clock is used to generate signal for timers, PWM and other peripherals.
• CPU clock is used to synchronise data transfer
▪ Clock sources (interna or external to the MCU) includes:
• Mechanical resonant devices such as crystals or ceramic resonators
• Resistor-capacitor (RC) oscillators
▪ Timers are peripherals for time measurement for MCU
• Timers are also driven by the clock
• Timers accessed through memory-mapped I/O
• Advanced timer (TIM1)
• General purpose timers (TIM2, TIM3, TIM15, TIM16)
• Basic timer (TIM6, TIM7)
• Low power timer (LPTIM)

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 15 of 24

2. Timers, PMW and Interrupts
2.1. Timers (cont.)

▪ A counter is used to generate and keep count of timing signals.

• Counter register holds the current count for a particular timer.
• The counter only goes up to 16 bit (65635) for the STM32L432KC.
▪ Main system clock frequency could be up to 80 MHz. Way too much for the counter
• Need to slow down by dividing the original frequency

▪ e.g. SysTick in Cortex-M4

• 24-bit count-down timer.
• can be used as a Real Time Operating System (RTOS) tick timer or as a simple
counter.
▪ e.g. TIM1 general purpose
• 16-bit count-down timer.
• extra features, allows to generate PWM

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 16 of 24

2. Timers, PMW and Interrupts
2.1. Timers (cont.)

▪ Prescaling
• The prescaler is used to divide the clock feeding the timer.
• Therefore the timer frequency is:
- System clock speed / Prescaler
• The prescaler value is stored in the prescaler register.
▪ Auto Reload Register (ARR)
• Further divides the system clock to give the timer frequency.
• Therefore the timer frequency is:
- System clock speed / (Prescaler x ARR)
• Counter counts up to value in ARR (then resets) before being reloaded.

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 17 of 24

2. Timers, PMW and Interrupts
2.2. Pulse-Width Modulation (PWM)
▪ Interface Square wave signal switched on and off at a particular frequency
▪ The PWM period is the inverse of the frequency
▪ The “on time” is called the pulse width
▪ The pulse width divided by the period is the duty cycle
▪ Used to generate or simulate analog signals (for example to dim an LED).

PWM signal for the servo motor on

the ES2D4 Development Board

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 18 of 24

2. Timers, PMW and Interrupts
2.2. Pulse-Width Modulation (PWM) (cont.)
▪ Capture compare register (CRR)
▪ Used to change the pulse width
▪ One CRR for each channel
▪ Compared to the counter and raises a signal when equal

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 19 of 24

2. Timers, PMW and Interrupts
2.3. Interrupts

▪ Polling is time-consuming and keeps the MCU busy needlessly.

▪ Interface raises interrupt request signal when data is available for the MCU.
• e.g. when a button is pushed
▪ Therefore MCU does not need to monitor peripheral for data.

▪ Classes of Interrupts
• Program: Generated by some condition that occurs as a result of an instruction execution,
such as arithmetic overflow, division by zero, attempt to execute an illegal machine
instruction, or reference outside a user’s allowed memory space.
• Timer: Generated by a timer within the processor. This allows the operating system to
perform certain functions on a regular basis.
• I/O: Generated by an I/O controller, to signal normal completion of an operation, request
service from the processor, or to signal a variety of error conditions.
• Hardware Failure: Generated by a failure such as power failure or memory parity error.

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 20 of 24

 2. Timers, PMW and Interrupts
2.3. Interrupts (cont.)

▪ When an external interrupt

(EXTI) is raised

• the MCU stops its current

task
• branches to an interrupt
service routine (ISR) for
the EXTI raised.
• The MCU returns to its
previous task after
executing the ISR.

Instruction Cycle with Interrupts

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 21 of 24
2. Timers, PMW and Interrupts
2.3. Interrupts (cont.)

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 22 of 24

2. Timers, PMW and Interrupts
2.3. Interrupts (cont.)

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 23 of 24

2. Timers, PMW and Interrupts
Summary
▪ 2.1. Timers
• Several clock sources, internal or external
• Various types of counters, some with special or advanced features
▪ 2.2. Pulse-Width Modulation (PWM)
• Used to generate or simulate analog signals
• Handled via Capture compare register (CRR)
▪ 2.3. Interrupts
• Handled via an interrupt service routine (ISR)

© 2022-2023 ES2C4 Lecture 9 - Computer Systems Organisation (CSO) - Part 4 24 of 24