UNIT

15 Multiprocessor Systems

Names of Sub-Units

Introduction to Multiprocessors, Classification of Multiprocessor, Multiprocessors Interconnections,

Types of Multiprocessor Operating Systems (MOS), MOS Functions and Requirements, Multiprocessors
Operating System Design and Implementation Issues.

Overview

The unit begins by discussing the concept of multiprocessors. Also, the unit explains the classification of
multiprocessor and multiprocessors interconnections. The unit also describes types of multiprocessors
operating systems. The unit discusses the MOS functions and their requirements. Towards the end, the
unit discusses the design and implementation issues of MOS.

Learning Objectives

In this unit, you will learn to:

 Explain the concept of multiprocessors
 Describe the classification of multiprocessors and multiprocessors interconnections
 Define the different types of Multiprocessors Operating Systems (MOS)
 Explain the MOS functions and their requirements
 Describe the design and implementation issues of MOS
 Operating System and Unix Shell Programming

Learning Outcomes

At the end of this unit, you would:

 Analyse the concept of multiprocessors
 Examine the classification of multiprocessors
 Assess the knowledge about the different types of Multiprocessors Operating Systems (MOS)
 Evaluate the significance of MOS function
 Assess the design and implementation issues of MOS

Pre-Unit Preparatory Material

 https://www.cs.vu.nl/~ast/books/mos2/sample-8.pdf

15.1 INTRODUCTION
A multiprocessor system is made up of many processors and a way for them to communicate with
one another. Homogeneous multiprocessing, often known as symmetric multiprocessing (SMP), is a
prevalent type of multiprocessing in computer systems, in which two or more identical processors share
a single main memory.
The primary goal of employing a multiprocessor is to increase the system’s execution speed, with
fault tolerance and application matching as secondary goals. A single central tower connected to two
computer systems is an excellent example of a multiprocessor.
The majority of computer systems are single processor systems, meaning they have only one processor.
Multiprocessor or parallel systems, on the other hand, are becoming increasingly important in today’s
world. Multiple processors function in parallel in these systems, sharing the computer clock, memory,
bus, peripheral devices, and so on. An illustration of the multiprocessor architecture may be seen here.
Figure 1 shows the multiprocessing architecture:

CPU 1 CPU 1 CPU 1 CPU n

Memory

Figure 1: Multiprocessing Architecture

15.2 INTRODUCTION TO MULTIPROCESSORS

A multiprocessor is a computer system that has two or more central processing units (CPUs) that all have
full access to the same RAM. Multiprocessors are divided into two types: shared memory multiprocessors
and distributed memory multiprocessors. Each CPU in a shared memory multiprocessor shares the

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common memory, but each CPU in a distributed memory multiprocessor has its own private memory.
Figure 2 represents the concept of shared memory:

CPU CPU CPU

Shared
CPU CPU
memory

CPU CPU CPU

Figure 2: Shared Memory

15.3 CLASSIFICATION OF MULTIPROCESSOR

There are two basic types of multiprocessors:
 Symmetric multiprocessors
 Asymmetric multiprocessors

15.3.1 Shared Memory Multiprocessors

Multiprocessor refers to a system in which numerous CPUs “share” the same main memory. In a
multiprocessor system, all processes on the different CPUs share a common logical address space,
which is mapped to physical memory that may be shared among the processors. Using load and store
procedures, each process may read and write a data item and processes communicate via shared
memory. The hardware is what allows all CPUs to access and utilise the same main memory. Figure 3
shows the shared memory multiprocessors:

Processor 0 Processor N-1

Data Data
Cache Cache Interconnection
network

Memory

Figure 3: Shared Memory Multiprocessors

15.3.2 Distributed Memory Multiprocessors

Systems with distributed shared memory, often known as virtual shared memory, are the third type
of multiprocessor system. Each CPU in such systems, which are now undergoing rapid development,

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has its own local main memory. Each memory, on the other hand, is assigned to a system-wide address
space. This means that each processor has access to the local memory of the others. Access to shared
variables is used to communicate across processors in this sort of system. It entails the execution of
a simple read or write instruction that converts shared variables in another processor’s memory. A
memory interface unit in each processor examines addresses used in current processor memory access
instructions. As a result, it routes instruction execution to the local main memory bus or transmits the
address and operation code to another processor’s local memory interface. Figure 4 shows the shared
memory multiprocessors:

M M M M

PE PE PE PE

Interconnection network

Figure 4: Distributed Memory Multiprocessors

15.4 MULTIPROCESSORS INTERCONNECTIONS

In a multiprocessor system, the processors must be able to share a set of main memory modules and I/O
devices. Interconnection structures can be used to give this sharing capacity. The following is a list of the
most frequent connectivity structures:
 Time-shared/Common bus (Interconnection structure in multiprocessor system): In a
multiprocessor system, the time shared bus interconnection provides a common communication
path connecting all the functional units such as processor, I/O processor and memory unit. Multiple
processors having a shared communication route are depicted in Figure 5:

Memory
Processor I/O Processor
Module

Common Bus

Memory
Processor I/O Processor
Module

Figure 5: Single-Bus Multiprocessor Organisation

 Cross bar switch: If the number of buses in the common bus system is expanded, a point is reached
when each memory module has its own route. Each module has its own route using the Crossbar
Switch (for multiprocessors).
A number of cross points are retained at intersections between memory module and processor bus
pathways in the Crossbar Switch system. The little square at each cross point symbolises a switch

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that obtains the path from a CPU to a memory module. Each switch point includes control logic that
establishes the memory-processor transfer route. It determines whether its specific module is being
addressed by calculating the address that is placed in the bus. It also eliminates numerous requests
for access to the same memory module based on a priority system. Figure 6 represents the crossbar
switch system:

Memory Modules

MM 4 MM 3 MM 2 MM 1

CPU 1

CPU 2

CPU 3

CPU 4

Figure 6: Crossbar Switch System

Figure 6 shows the functional design of a crossbar switch coupled to one memory module.
Multiplexers in the circuit choose data, address and control from a single CPU for communication
with the memory module. When two or more CPUs try to access the same memory, arbitration logic
establishes priority levels to pick one of them. The binary code generated by a priority encoder within
the arbitration logic can be used to manage the multiplexers. Crossbar switch is shown in Figure 7:

Data, Address and

Control form CPU 1
Data
Data, Address and
Control form CPU 2
Address
Memory Multiplexers and
Module Read/White Arbitration Logic Data, Address and
Control form CPU 3
Memory
Enable Data, Address and
Control form CPU 4

Figure 7: Crossbar Switch

Because each memory module has its own route, a crossbar switch system allows simultaneous
transfers from all memory modules. As a result, the switch’s hardware may grow to be rather
massive and sophisticated.
 Multiport memory: Control, switching and priority arbitration logic are dispersed throughout the
crossbar switch matrix, which is distributed at the interfaces to the memory modules, in a multiport
memory system.
 Multistage switching network: This is an n-cube binary architecture. We can join 2n processors here,
with each CPU becoming a node in the cube. A node can be a memory module or an I/O interface, but

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it is not always a CPU. A node’s processor has a direct communication link to n other nodes (total 2n
nodes). There are 2n different n-bit binary addresses in all.
 Hypercube system: A loosely linked system made up of N = 2n processors networked in an n-
dimensional binary cube is known as a hypercube (or Binary n-cube multiprocessor). Each CPU
creates a cube from scratch. Each processor creates a cube node. As a result, it is common to refer to
each node as having a processor, even if it really has a CPU, local memory and an I/O interface. Each
CPU has direct communication routes to n other processors in the immediate vicinity. The edges of
the cube are represented by these pathways.
Figure 8 shows the Hypercube structure for n = 1, 2 and 3:

011
111

01 11 010
0
110
001 101

1 00 10
000 100
One-cube Two-cube
Three-cube

Figure 8: Hypercube Structure for n = 1,2,3

15.5 TYPES OF MULTIPROCESSOR OPERATING SYSTEMS (MOS)

Following are two basic types of multiprocessors:
 Symmetric multiprocessor operating systems
 Asymmetric multiprocessor operating systems

15.5.1 Symmetric Multiprocessor Operating Systems

Each processor in these systems has a comparable copy of the operating system, and they all interact
with one another. All of the processors are in a peer-to-peer arrangement, which means that there is no
master-slave relationship between them.
The Encore version of Unix for the Multimax computer is an example of a symmetric multiprocessing
system.

15.5.2 Asymmetric Multiprocessor Operating Systems

Each CPU in an asymmetric system is assigned a certain duty. A master processor is in charge
of giving instructions to all of the other processors. A master slave relationship exists in an
asymmetric multiprocessor system. Prior to the invention of symmetric multiprocessors; asymmetric
multiprocessors were the only form of multiprocessor accessible. This is also the less expensive choice
now.

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15.6 MOS FUNCTIONS AND REQUIREMENTS

A multiprocessing operating system (OS) is one in which the computer’s functions are controlled by
two or more central processing units (CPUs). Each CPU has its own copy of the operating system,
which communicates with each other to coordinate operations. Because jobs may be shared amongst
processors, numerous processors allow the computer to do computations quicker. The component of
MOS are as follows:
 Central processing unit (CPU): sometimes known as the “brain” of a computer, is a collection of
circuits that performs the computer’s major operations and computations.
 Communication architecture: The design of computer components and circuitry that allows for
the speedy and efficient transfer of signals between different portions of the computer is known as
communication architecture.
 Parallel processing: Parallel processing is the dividing of a job across numerous processors that
operate at the same time to finish the task more rapidly.
 Processor coupling: Processor coupling is the practice of connecting numerous processors in a
computer so that they may work together to accomplish computations more quickly. Depending on
how dependent processors are on one another, this might be described as loose or tight.
 Processor symmetry: Multiple processors sharing equal access to input and output devices and
controlled by a single operating system is referred to as processor symmetry.

A multiprocessor operating system abstracts all of the available resources and scheduling functions to
make application execution and interaction with users easier.
A processor is one of the most critical and fundamental sorts of resources to manage. Processor
scheduling is required for optimal multiprocessor utilisation. Processor scheduling entails the following
responsibilities:
 Allocating processors among applications in a way that is compatible with the system design goals.
It has an impact on the system’s throughput. Co -scheduling numerous apps together increases
throughput by allocating fewer processors to each.
 Ensuring that the processors allotted to an application are used efficiently. This mostly influences
the system’s speed.

The aforementioned two goals are in some ways incompatible since maximal speedup necessitates
devoting a substantial fraction of a system’s processors to a single application 13, which reduces the
system’s throughput. The requirement for explicit programmer direction emerges to some extent due
to the difficulty of automating multiprocessor systems processes. Explicit and automated parallelism
is generally supported by language translators and preprocessors. The two main aspects of OS
multiprocessing support are:
 Interprocess and interprocessor synchronisation technique that is flexible and efficient
 creats and manags a large number of activity threads, such as processes or threads, in an efficient
manner.

Because parallelism is frequently achieved by breaking an application into independent, individually

executable subtasks that may be allocated to multiple processors, the latter component is critical.

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The management of memory is the second sort of resource that must be controlled. Memory management
in multiprocessor systems is largely reliant on the architecture and interconnection method.
 In loosely coupled systems, memory is generally controlled individually on a preprocessor basis,
whereas shared memory can be modelled in multiprocessor systems using a message passing
method.
 In shared memory systems, the operating system will provide a flexible memory model that allows
for efficient and safe access to shared data structures and synchronisation variables.

To simplify application porting between different multiprocessor settings, a multiprocessor operating

system should include a hardware independent, uniform architecture of shared memory. The Mach
operating system’s creators took use of the duality of memory management and inter-process
communication.
Device management is the third essential resource, although it has gotten little attention in
multiprocessor systems to date, because the major emphasis point before was speedup of compute
heavy applications, which do not create much input/output after initial loading. Multiprocessors are
now widely used. applied for more balanced generalpurpose applications, therefore, the input/output
requirement increases in proportion with the realised throughput and speed.

15.7 MULTIPROCESSORS OPERATING SYSTEM DESIGN AND IMPLEMENTATION ISSUES

In comparison to uniprocessors, developing a high-performance operating system for shared-memory
Multiprocessors is more complicated. Multiprocessors necessitate the consideration of a variety of
difficulties throughout the design process.
To limit the amount of cache misses, for example, the overhead of cache integrity necessitates careful
attention to data placement. Similarly, in big systems, the memory distribution across the system must
keep track of where data is stored and optimise memory access locality. The following are some of the
challenges that came up during the development of the multiprocessor architecture and operating
system.

15.7.1 Multiple Processors

The number of processors is the most significant distinction between shared-memory multiprocessors
(SMMPs) and uniprocessors. Although software for single-processor systems may already address
concurrency difficulties. Multiprocessors allow for appropriate parallelism, but they also introduce
problems that might impair the validity and efficiency of uniprocessor synchronisation schemes.
The concept may be used to synchronise uniprocessors in a variety of ways, such as deactivating
interrupts in the kernel or relying on a server thread’s non -preemption capabilities, but it is not
immediately relevant to multiprocessors. Although only one processor may be in the kernel at a time (or
only one process can be running in a server at a time), this serialises all requests and is not acceptable
for performance reasons.

15.7.2 Cache Coherency

Each CPU will have its own copy of the data in its cache if thread one in the first processor is working on
the same data as thread one in the second processor. The system must ensure that any modifications
made by any processor are accurately reflected in all copies by the threads. This is referred to as cache
coherency maintenance. The system hardware is in charge of these tasks.

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UNIT 15: Multiprocessor Systems

When each processor in a multiprocessor system has the same value of a data item in its cache as
the value in System Memory, this is known as cache coherency. If any CPU desires to change the data
value, this might lead to a skewed representation of memory. Although the programme is unaware of
the circumstance, maintaining it can have an impact on the software’s performance. The data values
in a processor cache or System Memory may not be changed until the data is accessed again in some
instances.
As a result, the value of a data item in a processor’s cache and System Memory may differ at any given
moment. When a data item is going to be accessed, the system detects it and performs the procedures
required to update the data item with the right value before allowing access to complete.

15.7.3 Snooping
The cache subsystem and each of its cache lines are tracked via snooping. This approach keeps track of
all system bus transactions and identifies when a read or write operation is performed on an address
in its cache. The cache subsystem switches the status of the cache line to “shared” when it “snoops” a
read on the system bus to an address in its cache. If it detects a write to that address, it will set the cache
line’s status to “invalid.”
The cache subsystem will know whether it has the only copy of a data item in its cache since it listens to
the system bus. The cache subsystem will alter the status of the cache line from “exclusive”to “modified”
if such a data item is updated by its own CPU. If the cache subsystem detects another processor accessing
that data item, it can block that access, update the data item in system memory, and then allow the other
CPU’s access to continue. It will also set the cache line containing the data item’s statusto “shared.”

15.7.4 False Sharing

The designer considers scenarios when data is exchanged between threads while choosing a
programming architecture. Various data objects accessed by separate threads are assigned to the same
cache line, resulting in false sharing.
Because data access causes the cache subsystem to read a full cache line from system memory, if one
data item in the cache line is shared, the caching subsystem will regard all of the data items in that
cache line as shared. Two threads executing on different cores might update two data items in unrelated
transactions, but if the two items are on the same cache line, the cache subsystem will have to update
the System Memory to preserve cache coherency, potentially causing pin ponging.
Data that will be accessible by numerous threads might be organised using an array of structures.
Following the domain decomposition concept, each thread may access one structure from the array.
Data sharing across threads will not occur if this approach is followed, and the system will avoid the
performance penalty of maintaining consistency between the caches of each thread’s core unless the
structures needed by the threads are in the same cache line.
Two structures will occupy one cache line if the cache line size is 64 bytes and the structure size of a
structure in the array is 32 bytes. If the two threads reading the two structures are on separate cores, a
modification to one of the cache line’s structures will require the entire cache line to be pushed to system
memory. The cache line in the second core’s cache will likewise be invalidated.
The second structure will have to be read from system memory the next time it is visited. If a series of
modifications are made to the structures, the system’s performance might suffer significantly.

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Using compiler alignment directives to align data items on cache line boundaries is one way to avoid
erroneous sharing. Overuse of this strategy, on the other hand, might result in cache lines that are only
partially used. True sharing refers to situations in which the programmer creator intends for data to be
shared between threads.

15.7.5 Processor Af�inity

CPU pinning is another name for processor affinity. It permits threads or processes to be allocated or de-
allocated to the same CPU. The CPU may manage its jobs in a particular amount of time by employing
this strategy. This occurs when one of the CPUs has many processors or cores.
Interrupt processes are assigned to a single CPU, implying that there is no affinity at all. On the other
hand, two CPUs are sharing processes to manage the burden on the other side of the figure. Processor
affinity is an example of this. A process or interrupt will be allocated to a certain CPU or core in this
manner.

15.7.6 Programming Models

In software design, there are two programming models: functional decomposition and data (domain)
decomposition. These are useful for allocating tasks to threads. The goal of functional decomposition
is to break down software work into smaller chunks, or threads. Although one thread carries several
actions, each thread has been assigned a specific purpose to accomplish quickly. Data sets are broken
into sections in data decomposition, and software works on each portion separately. Each thread works
on a different data component in concurrently.

Conclusion 15.8 CONCLUSION

 A multiprocessor system is made up of many processors and a way for them to communicate with
one another.
 The primary goal of employing a multiprocessor is to increase the system’s execution speed, with
fault tolerance and application matching as secondary goals.
 A multiprocessor is a computer system that has two or more central processing units (CPUs) that all
have full access to the same RAM.
 Multiprocessors are divided into two types: shared memory multiprocessors and distributed
memory multiprocessors.
 Shared Memory Multiprocessor refers to a system in which numerous CPUs “share” the same main
memory.
 Systems with distributed shared memory, often known as virtual shared memory, are the third type
of multiprocessor system.
 A multiprocessing operating system (OS) is one in which the computer’sfunctions are controlled by
two or more central processing units (CPUs).
 A multiprocessor operating system abstracts all of the available resources and scheduling functions
to make application execution and interaction with users easier.
 CPU pinning is another name for processor affinity. It permits threads or processes to be allocated
or de-allocated to the same CPU.

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UNIT 15: Multiprocessor Systems

15.9 GLOSSARY

 Multiprocessor system: A system made up of many processors and a way for them to communicate
with one another
 Homogeneous multiprocessing: A prevalent type of multiprocessing in computer systems, in which
two or more identical processors share a single main memory.
 CPU: A collection of circuits that performs the computer’s major operations and computations.
 Processor coupling: The practice of connecting numerous processors in a computer so that they may
work together to accomplish computations more quickly. Depending on how dependent processors
are on one another, this might be described as loose or tight.
 Processor af�inity: It permits threads or processes to be allocated or de-allocated to the same CPU

15.10 SELF ASSESSMENT QUESTIONS

A. Essay Type Questions

1. What do you understand by multiprocessors?
2. List down the classification of multiprocessor.
3. What do you mean by multiprocessor interconnections?
4. Explain the MOS functions and requirements.
5. Explain the design and implementation issues of MOS.

15.11 ANSWERS AND HINTS FOR SELF ASSESSMENT QUESTIONS

A. Answes to Essay Type Questions

1. A multiprocessor is a computer system that has two or more central processing units (CPUs) that
all have full access to the same RAM. Multiprocessors are divided into two types: shared memory
multiprocessors and distributed memory multiprocessors. Refer to Section Introduction to
Multiprocessors
2. There are two basic types of multiprocessors:
 Symmetric multiprocessors
 Asymmetric multiprocessors
Refer to Section Classification of Multiprocessors
3. In a multiprocessor system, the processors must be able to share a set of main memory modules and
I/O devices. Interconnection structures can be used to give this sharing capacity. Refer to Section
Multiprocessors Interconnections
4. A multiprocessing operating system (OS) is one in which the computer’s functions are controlled by
two or more central processing units (CPUs). Each CPU has its own copy of the operating system,
which communicates with each other to coordinate operations. Refer to Section MOS Functions and
Requirements

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5. In comparison to uniprocessors, developing a high-performance operating system for shared-

memory Multiprocessors is more complicated. Multiprocessors necessitate the consideration of a
variety of difficulties throughout the design process. Refer to Section Multiprocessors Operating
System Design and Implementation Issues

@ 15.12 POST-UNIT READING MATERIAL

 https://ecomputernotes.com/fundamental/disk-operating-system/multiprocessor-operating-
system
 https://www.tutorialspoint.com/Multiprocessor-Systems

15.13 TOPICS FOR DISCUSSION FORUMS

 Discuss multiprocessor systems and the real-time scenarios in which they are employed with your
friends.

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