Digital Systems

EENG20400
Dr. Roshan Weerasekera

Lecture 3: Combinational Logic Circuits and

Their Modelling
Lecture/Lab Schedule
Week Lecture Date Lab session Date

1 Course Logistics and Digital System Design Process 28/09/2023

2 HDLs: Introduction to VHDL 05/10/2023
3 Combinational Logic Circuits and Their Modelling 12/10/2023
4 Sequential Logic Circuits and Their Modelling 19/10/2023
5 Finite State Machines (FSMs) 26/10/2023
6 Reading Week (No Lecture) 02/11/2023
7 Datapath and Controller 09/11/2023
8 Hardwired vs microprogrammed control 16/11/2023
9 Timing Constraints for Digital Circuits 23/11/2023 Lab session 1 21/11/2023
10 Arithmetic Circuits 30/11/2023 Lab session 2 28/11/2023
11 Memories 07/12/2023 Lab session 3 05/12/2023
12 Revision 14/12/2023 Lab session 4 12/12/2023
Combinational Circuits
▪ combinational Logic → settles to a state entirely determined by the current input values and
therefore that cannot store information.
▪ Any change in the input causes a new state completely defined by the new inputs.

▪ Basic Combinational Circuits

✓ Encoders and Decoders; Priority
X (n-inputs) Y (m-outputs)
Encoders; Multiplexers

CL ▪ Arithmetic Circuits:
✓ Half and Full Adders
✓ An Adder/Subtractor
✓ Carry Look-ahead Adder

𝑌 = 𝑓(𝑋)
Combinational Circuit Modelling: Method (1)
▪ Truth table in case statement
– each case item refers to a minterm gives its truth table value (output)
– Must list all possible elements (why?)
a b c y begin
process (a,b,c)
0 0 0 0 begin
0 0 1 0 if (a=‘0’ and b=‘0’ and c=‘0’) then y <=‘0;
elsif (a=‘0’ and b=‘0’ and c=‘1’) then y <=‘0;
0 1 0 1 elsif (a=‘0’ and b=‘1’ and c=‘0’) then y <=‘1;
elsif (a=‘0’ and b=‘1’ and c=‘1’) then y <=‘0;
0 1 1 0 elsif (a=‘1’ and b=‘0’ and c=‘0’) then y <=‘1;
1 0 0 1 elsif (a=‘1’ and b=‘0’ and c=‘1’) then y <=‘0;
elsif (a=‘1’ and b=‘1’ and c=‘0’) then y <=‘1;
1 0 1 0 else y <=‘0;
end if;
1 1 0 1 end process;
1 1 1 0
Combinational Circuit Modelling: Method (2)
▪ Truth table in case statement
– each case item refers to a minterm gives its truth table value (output)
– Must list all possible elements (why?)
a b c y begin
0 0 0 0 process (a,b,c)
begin
0 0 1 0 if (a=‘0’ and b=‘1’ and c=‘0’) or (a=‘1’ and b=‘0’ and
c=‘0’) or (a=‘1’ and b=‘1’ and c=‘0’) then
0 1 0 1 y <=‘1’;
0 1 1 0 else
y <=‘0’;
1 0 0 1 end if;
end process;
1 0 1 0
1 1 0 1
1 1 1 0
Combinational Circuit Modelling: Method (3)
▪ After some logic minimization (using Karnaugh Map) a b c y
▪ Works for less logic variables and outputs 0 0 0 0
ba
0 0 1 0
c 00 01 11 10 0 1 0 1
0 0 1 1 1 0 1 1 0
1 0 0 0 0 1 0 0 1
1 0 1 0
y = ac + bc = (a + b)c 1 1 0 1

Boolean expression(s) → simple signal assignments

1 1 1 0

begin
y <= (a or b) and not c;
end
Combinational Circuit Modelling: Method (4)
▪ Boolean expression(s) → conditional signal assignments a b c a or b not(c) y
y <= ( a or b) when c =‘0’ else ‘0’;
0 0 0 0 1 0
▪ Listing the output for all possible outputs using with-select
0 0 1 0 0 0
with a & b & c select
0 1 0 1 1 1
y <= ‘1’ when “110” | “100” | “010” ,
‘0’ when others; 0 1 1 1 0 0
▪ Using process command (sequential code) using behavioural 1 0 0 1 1 1
descriptions
1 0 1 1 0 0
process(a, b, c)
begin 1 1 0 1 1 1
y <= '0'; 1 1 1 1 0 0
if a = '1' or b = '1' then y <= '1'; end if;
• Depending on the condition in statements a
if c = '1' then y <= '0'; end if;
new value for y will be scheduled.
end process; • In this case, there are several statements to
assign values to y. At the end of the process
the last scheduled value will be stored in y,
Multiplexers
▪ Multiplexers are used to switch one of many inputs to a single output. Typically they allow using
large, complex pieces of hardware.

4 Y
I

S
MUX example

http://www.ddvahid.com/
▪ Four possible display items:
– Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining
(M) -- each is 8-bits wide
▪ Choose which to display using two inputs x and y
▪ Use 8-bit 4x1 mux
VHDL code for 4-to-1 Multiplexor
4 Y
I

S
1 Dataflow style using when-else

You can try with-select construct as well.

What is the difference between them?

Y = I 0 . S0 . S1 + I1. S0 .S1 + I 2 .S0 . S1 + I 3 .S0 .S1

Behavioural style using case

2
Decoders
▪ A decoder takes a n-bit input and produces 2n single-bit outputs.
▪ The binary input determines which output will be 1, all others 0 → This is one-hot encoding.
DeMultiplexor (DEMUX)
Y

I 2N

N
S

Behavioural style
Ripple Carry Adder
1 0 0 0
1 0 0 0
1 1 0 1
1 0 0 1 1
Summary
▪ There are various ways to model a combinational circuit
Week Lecture Date Lab session Date

1 Course Logistics and Digital System Design Process 28/09/2023

2 HDLs: Introduction to VHDL 05/10/2023
3 Combinational Logic Circuits and Their Modelling 12/10/2023
4 Sequential Logic Circuits and Their Modelling 19/10/2023
5 Finite State Machines (FSMs) 26/10/2023
6 Reading Week (No Lecture) 02/11/2023
7 Datapath and Controller 09/11/2023
8 Hardwired vs microprogrammed control 16/11/2023
9 Timing Constraints for Digital Circuits 23/11/2023 Lab session 1 21/11/2023
10 Arithmetic Circuits 30/11/2023 Lab session 2 28/11/2023
11 Memories 07/12/2023 Lab session 3 05/12/2023
12 Revision 14/12/2023 Lab session 4 12/12/2023