Digital Systems

EENG20400
Dr. Roshan Weerasekera

Lecture 4: Sequential Logic Circuits and

Their Modelling
Lecture/Lab Schedule
Week Lecture Date Lab session Date

1 Course Logistics and Digital System Design Process 28/09/2023

2 HDLs: Introduction to VHDL 05/10/2023
3 Combinational Logic Circuits and Their Modelling 12/10/2023
4 Sequential Logic Circuits and Their Modelling 19/10/2023
5 Finite State Machines (FSMs) 26/10/2023
6 Reading Week (No Lecture) 02/11/2023
7 Datapath and Controller 09/11/2023
8 Hardwired vs microprogrammed control 16/11/2023
9 Timing Constraints for Digital Circuits 23/11/2023 Lab session 1 21/11/2023
10 Arithmetic Circuits 30/11/2023 Lab session 2 28/11/2023
11 Memories 07/12/2023 Lab session 3 05/12/2023
12 Revision 14/12/2023 Lab session 4 12/12/2023
What are Sequential Circuits?
▪ What if you were given the following design specifications?

When the button is pressed:

• Turn ON the light if it is OFF

• Turn OFF the light if it is ON

X (n-inputs) Y (m-outputs)
▪ What makes this circuit different from Combinational circuits?
– It requires memory to remember its current status

Present state Next state

▪ Other examples:
– Counters, sequence detectors Memory
Sequential Circuits
▪ sequential circuit → the output depends not only on the circuit’s current inputs, but also on the
previous values.
X (n-inputs) Y (m-outputs)
X (n-inputs) Y (m-outputs)
Combinational Combinational
Circuit Circuit

Present state Next state

𝑌 = 𝑓(𝑋) Storage
Elements

𝑌 = 𝑓(𝑋, 𝑆)
Sequential circuit classification depends on the times at which their inputs are observed. There are two classes:
• Synchronous → behaviour of output can be defined at discrete events of time. Synchronization is achieved
using a time device (clock generator)
• Asynchronous → behaviour of output can be decided at any instant of time (and the order in which the input
changes.
SR Latch
▪ Latch → storage elements that operate with signal levels (level sensitive devices)
▪ … is created by cross-coupling two NOR gates (NAND gates could also be used). The circuit
state includes the signals Q and Ǭ as these are the signals that are fed back into the circuit.

Complement inputs are required to set the state

D Latch
▪ One way to eliminate the undefined state in the SR latch is to make sure that inputs S and R
are never equal to 1 at the same time.

Clocked processes with a

sensitivity list must have
only the clock and any
asynchronous control
inputs (usually reset or set)
in the sensitivity list.

 As long as clk remains at ‘1’, any changes in D will change the state.
Flip-flops (FFs)
… are storage elements that are controlled by a clock transition (edge-sensitive)
Positive-edge triggered FF

Master
Slave

clk D Q(t+1)
0 - Q(t)
By removing this inverter a
negative edge-triggered FF 1 - Q(t)
can be made
 D D

clk’event and clk=‘1’ for data type bit

Attributes in VHDL
▪ Attributes provide additional information about signals, variables, types or components. Certain
attributes are predefined for types, array objects and signals.
▪ Following attributes are pre-defined for Signals
S'event True when signal S changes (boolean)
S'active True when signal S assigned to (boolean)
S'last_event When signal S last changed (time)
S'last_active When signal S was last assigned to (time)
S'last_value Previous value of S (same type as S)

▪ For very frequent conditions of Flip-flops one can use the following functions:
– clk’event and clk=‘1’ → rising_edge(clk)
– clk’event and clk=‘0’ → falling_edge(clk)
▪ More attributes are available in the reference material provided in BB or refer to
http://www.csee.umbc.edu/portal/help/VHDL/attribute.html
D Flip-flop with a Reset
▪ there’s a input signal (reset) which sets the state to ‘0’

Synchronous reset

Asynchronous reset
Registers
▪ 1 bit storage element is a flip-flop.
▪ a set of n flip-flops is used to store n bits of information and it is called a register.
Parallel load parallel out Register
D0 Q0 D1 Q1 D2 Q2 D3 Q3
D Q D Q D Q D Q

clk clk clk clk

resetn resetn resetn resetn

DataIn(0:N-1) DataOut(0:N-1)
D Q

clk
resetn
Parallel load parallel out Register Example
DataIn(0:N-1) DataOut(0:N-1)
D Q

clk
resetn

A structural description is not efficient.

Very efficient
Working with Vectors: others keyword
▪ others is a keyword used to refer to all elements not already mentioned

Example:
▪ Q <= “00000100” → Q(2 => ‘1’, others <= ‘0’)
▪ Q <= “11110000” → Q(7 downto 4 => ‘1’, others <= ‘0’)
→ Q(3 downto 0 => ‘0’, others <= ‘1’)
▪ Q <= “10000001” → Q(7|0 => ‘1’, others <= ‘0’)
▪ Q <= “00000000” → Q(others <= ‘0’)
Working with Vectors…
Shift Registers (Example)
DataIn DataOut(0:N-1)
D Q

clk
resetn
Counters
Summary
▪ HDLs are used for modelling and implementation of complex digital circuits using modular approach
▪ Discussed basic VHDL building blocks, Data types and concurrent and sequential VHDL constructs
▪ Not all the features in the language have been introduced/discussed. More will be introduced while working
on the worked examples…
▪ Next Lecture is about…