Lab Report: EEE 466 Department of EEE BUET

Lab R eport: EEE466

C ourse Title: Analog Integrated Circuits and Design
Laboratory

Lab title:
Study of Single Stage Common Source CMOS Amplifier
Design

P repared by:
Abdullah Jubair Bin Iqbal
1706058
Group #1
Section A
Level 4, Term 1

N am e(s) of G roup M em ber and

Student ID :
Mrinmoy Kundu - 1706001

D ate of Experim ent: 07/06/2022

D ate of R eport: 21/06/2022

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Lab Report: EEE 466 Department of EEE BUET

TA B LE OF C ON TEN TS

Contents
TABLE OF CONTENTS ................................................................................................................................... 2
ABSTRACT ......................................................................................................................................................... 3
INTRODUCTION ............................................................................................................................................... 3
THEORY .............................................................................................................................................................. 3
TOOLS USED ..................................................................................................................................................... 3
PROCEDURE ..................................................................................................................................................... 4
1-1. Common-Source (CS) Stage with Resistive Load ................................................................................. 4
1-2. CS Stage with Diode-Connected Load.................................................................................................... 4
1-3. CS Stage with Current Source Load ....................................................................................................... 5
1-4. CS Stage with Active Load ...................................................................................................................... 5
1-5. CS Stage with Triode Load ...................................................................................................................... 6
RESULTS AND QUESTION ANSWERS....................................................................................................... 7
1-1. Common-Source (CS) Stage with Resistive Load ................................................................................. 7
1-2. CS Stage with Diode-Connected Load ................................................................................................... 8
1-3. CS Stage with Current-Source Load....................................................................................................... 7
1-4. CS Stage with Active Load ...................................................................................................................... 8
1-5.CS Stage with Triode Load ....................................................................................................................... 9
CONCLUSION .................................................................................................................................................. 10
REFERENCES .................................................................................................................................................. 10

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Lab Report: EEE 466 Department of EEE BUET

ABSTRACT
Five different topologies of single stage CS amplifiers were studied in this experiment. The five
stages are- Common-Source (CS) Stage with Resistive Load, CS Stage with Diode Connected
Load, CS Stage with Current Source Load, CS Stage with Active Load and CS Stage with Triode
Load. For each, we have determined the bias voltage and then a very small AC signal of 10 mV
was superpositioned on the DC voltage and subsequently small signal AC analysis was performed
to determine the gain behavior of the amplifiers.

INTRODUCTION
Due to the unique advantage of extremely high input impedance and low noise output, common
source amplifiers are more widely used than any other amplifier circuits. Its simplicity and high
input impedance makes it a very popular choice for various applications like sensor signal
amplification and low noise RF applications. The goal of this lab is to familiarize ourselves with
common source CMOS amplifiers and simulate various different topologies. For each topology, we
find out the bias voltage and currents and then plot the small signal input, output and low
frequency gain.

THEORY
The precise input-output relationship for common-source amplifiers is quite complex and non-
linear. However, for practical purposes, a linear relationship can be approximated which greatly
simplifies the design and helps us take intuitive decision. Generally, a linear relation 𝑦(𝑡) = 𝑎0 +
𝑎1𝑥 (𝑡) can be found in sufficiently narrow range of 𝑥(𝑡). A small AC signal is superpositioned
with the DC bias input voltage so that despite the AC voltage swing, the total input voltage
remains in the linear region. Then, a small signal gain 𝐴𝑣 can be found by taking the slope of this
linear function.

The formula for Av can vary from topology to topology. For the five different circuits studied in
this experiment, the formulas are as below-

1. Common-Source (CS) Stage with Resistive Load: 𝐴𝑣 = −𝑔𝑚𝑅𝐷

2. Common-Source (CS) Stage with Current Source Load: 𝐴𝑣 = − 𝑔𝑚1 (𝑟𝑂1 || 𝑟𝑂2)
3. Common-Source (CS) Stage with Active Load
4. Common-Source (CS) Stage with Triode Load: 𝐴𝑣 = −𝑔𝑚1𝑅𝑜𝑚2
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5. Common-Source (CS) Stage with Diode Connected Load: 𝐴𝑣 = ((𝑊1 /𝐿1 ) /(𝑊2 /𝐿2 ))^0.5 1+𝜂
Since all the gains are negative, we expect that the output signal will be inverted in each case.

TOOLS USED
Cadence® Virtuoso® Simulation Software

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 Lab Report: EEE 466 Department of EEE BUET

PROCEDURE
1-1. C om m on-Source (C S) Stage w ith R esistive Load

First, we set up the dc bias circuit. Here, a resistor has been connected to the drain terminal of the
NMOS. 𝑉𝑑𝑐 = 1 and 𝑉𝑔𝑠 is being varied. From this circuit, we have generated the 𝑔𝑚 vs 𝑉𝑔𝑠 curve to
find the point of maximum gm. (Figure 7). Next, the small signal AC circuit was set up. Here, a small
sinusoidal signal (10 mV, 100 𝐻𝑧) has been added to the dc gate voltage and a 1 𝑀Ω load has been
connected to the drain terminal using capacitor coupling. Here, 𝑉𝐷𝐷 = 1.8 𝑉, 𝑉𝐺𝑆 = 0.45 𝑉, 𝑅𝐷 = 2 𝑘Ω
and Finger = 20. From this setup, the input and output signals have been plotted using transient
analysis (Figure 10), and gain vs frequency plot has been generated using frequency sweep method
(Figure 11).

1-2. C S Stage w ith D iode-C onnected Load

Replacing the resistor 𝑅𝐷 with a diode connected NMOS with 𝑊/𝐿 = 480/100, and finger =2 we
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obtain the circuit above. Here 𝑉𝐷𝐷 = 1.8𝑉. Here we have generated the gain vs frequency, setting
𝑉𝑔𝑠 = 450 𝑚𝑉 (figure 4).

1-3. C S Stage w ith Current Source Load

Here, 𝑅𝐷 has been replaced with a PMOS operating in saturation. After finding out the DC bias current
𝐼𝐷 and 𝑉𝐷 using DC analysis, we find out the input/output AC waveforms (figure 5). We have also
changed the parameters of the PMOS to 𝑊/𝐿 = 4800/400 and 𝑉𝑏 = 1 𝑉 and simulated the same
results to observe the changes.

1-4. C S Stage w ith A ctive Load

A complimentary CS stage topology has been set up where the PMOS can act as an amplifier as well.
Here, 𝑉𝐷𝐷 = 1.8 𝑉, 𝑉𝐺𝑆 = 0.87 𝑉, 𝑊/𝐿 = 4800/100 for PMOS and 𝑊/𝐿 = 2400/100 for nmos. As
before, we have simulated the DC bias voltage and currents, input/output waveforms (figure 8) and
calculated the small signal gain.

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1-5. C S Stage w ith Triode Load

In the final topology, the PMOS operates in the deep triode region. We have performed the exact same
works as before (figure 9). Here, 𝑉𝐷𝐷 = 1.8 𝑉, 𝑉𝐺𝑆 = 0.45 𝑉, 𝑉𝑏 = 1.1 𝑉, 𝑊/𝐿 = 4800/100 for NMOS
and 𝑊/𝐿 = 2400/100 for PMOS.

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 Lab Report: EEE 466 Department of EEE BUET

RESULTS AND QUESTION ANSWERS

1-1. C om m on-Source (C S) Stage w ith R esistive Load
i) Plotting drain current, output voltage and transconductance vs 𝑉𝐺𝑆.

Figure 1: CS with Resistive Load – ID, Vout and gm vs. VGS

ii) At 𝑉𝐺𝑆 = 810 𝑚𝑉, 𝑔𝑚 is maximum.

iii) For a large signal swing, the gain will vary with changing 𝑉𝐺𝑆, and thus,
there will be distortion in the output.
iv) To increase the output swing, I would increase 𝑉𝐷𝐷.
v) AC outputs:

Figure 2: CS with Resistive Load – AC input and output signal.

The gain is −25.5/10 = −2.55

From figure 1, 𝑔𝑚𝑚𝑎𝑥 = 1.25125, and from the circuit, 𝑅𝐷 = 2 𝑘Ω . So, theoretical 𝐴𝑣 = −𝑔𝑚 𝑅𝐷 =
2.5025, which is close to the simulated result.

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Lab Report: EEE 466 Department of EEE BUET

Figure 3: CS with Resistive Load – gain vs frequency

107.95
Here, 𝑔𝑎𝑖𝑛 = −7.95 𝑑𝐵 at 100𝐻𝑧. Which is: 20
= 2.497468, very close to the previous result.

1-2. C S Stage w ith D iode-C onnected Load

Figure 4: CS Stage with Diode-Connected Load – gain vs frequency

i) The gain is −7𝑑𝐵 or 𝐴𝑣 = 2.24

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ii) The gain is given by ((𝑊1 /𝐿1 ) /(𝑊2 /𝐿2 ))^0.5 1+𝜂 , to increase gain, we can increase 𝑊 /𝐿
for the first MOSFET and thereby increasing 𝑔𝑚 1 or decrease (𝑊 /𝐿) for the second
MOSFET and thereby decreasing the value of 𝑔𝑚2

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Lab Report: EEE 466 Department of EEE BUET

1-3. C S Stage w ith Current-Source Load

i) DC bias voltage VD = 629.448 mV.

ii) The small signal input and output waveforms are as below:

Figure 5: CS Stage with Current Source Load – input output waveforms (W/L = 4800/100 for
pmos)

iii) Here, gain, 𝐴𝑣 = −3.6/10 = −3.6

iv) The gain formula is 𝐴𝑣 = −𝑔𝑚1(𝑟𝑂1 || 𝑟𝑂2). Either 𝑟𝑂1 or 𝑟𝑂2 can be increased by
increasing channel length of the MOSFETs, resulting in a higher gain.
v) W/L for the PMOS was changed to 4800/400 and 𝑉𝑏 = 1 𝑉 and the following
input output waveforms were obtained-
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Lab Report: EEE 466 Department of EEE BUET

Figure 6: CS Stage with Current Source Load – input output waveforms (W/L = 4800/400 for
PMOS)

Here, gain 𝐴𝑣 = −59.8/10 = −5.98, which has significantly increased.

Increasing L2 also increases the overdrive voltage, and thus Vds required to maintain the PMOS
in saturation. This is why the gate voltage was lowered so that the MOS remains in saturation region.

1-4. C S Stage w ith A ctive Load

i) DC bias voltage VD = 804.195 mV. We had to increase the bias voltage VGS from 0.45 V
to 0.87 V because it is now common to both MOSFETs and the value 0.87V ensures
that both operate in saturation (for pMOS, 𝑉𝑠𝑔 = 1.8 – 0.87 = 0.93𝑉)

ii) The small signal input and outputs-

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Figure 8: CS Stage with Active Load – input output waveforms (W/L = 4800/100 for
PMOS)
iii) Small signal gain, Av = - 54.4559/10 = -5.44559, which is significantly higher than
that of CS stage with current source load with the same PMOS (which was -3.6)
iv) The demerit of this topology is that 𝑉𝐺𝑆 is not flexible, and needs to be
maintained at a carefully calculated intermediate value so that both FETs operate in
the saturation region. Thus, this tricky maintenance of the FETs in the saturation
region poses some design challenges.

1-5. C S Stage w ith Triode Load

i) From figure 6, DC bias voltage 𝑉𝐷 = 1.3914 𝑉. For the pMOS, 𝑉𝑆𝐷 =
1.8 – 1.3914 = 0.4086 𝑉, which is less than 𝑉𝑆𝐺 = (1.8 – 1.1) = 0.7 𝑉. So, it is
operating in the triode region

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ii) Small signal input and output:

Figure 9: CS Stage with Triode Load – input output waveforms

iii) Gain, 𝐴𝑣 = −26.8142/10 = −2.68142

CONCLUSION
The five topologies we have studied in this experiment comes with their own sets of advantages and
limitations. In the resistive load topology, it is very difficult to fabricate MOSFETs with such tight
resistance requirements. Hence, the other topologies replaced the resistor with another transistor which
are easier to fabricate. In addition to this, we have also looked at various techniques to enhance the
linearity of CS amplifiers. For example, increasing the DC bias voltage improves the operating range
and voltage swing tolerance at the cost of power efficiency. Then, changing 𝑊/𝐿 gives rise to 𝑔𝑚 and
consequently 𝐴𝑣 but it reduces the range of linearity. Again, in the last topology, we operated the PMOS
in deep triode region, which requires less gate voltage, while also deteriorating the gain. All these design
aspects can prove to be crucial while designing amplifiers for practical applications.

REFERENCES
1. Razavi, Behzad, Design of Analog CMOS Integrated Circuits, Tata McGraw-Hill Edition 2002,
Chapter 3
2. Gray, Paul R., Hurst, Paul J., Lewis, Stephen H, Meyer, Robert G, Analysis and Design of Analog
Integrated Circuits (4th Edition), John Wiley & Sons. Inc.

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