IEEE 1687-IJTAG

Ashwani Maurya
 Introduction.
Disadvantages of IEEE1149.1 & IEEE1500 in embedded module applications:

• No good trade-off between hardware scalability and access flexibility.

• Lack of a suitable language for describing the hierarchical connections of different typed embedded
modules.
• Lack of a suitable language to describe the operational procedure for embedded module testing
structures.
 Introduction.
Q. How to solve the difficulties of on-chip testing and
module access of highly integrated chips?

• By constructing a flexible and changeable interface.

• Use JTAG to complete data transmission and module
access through a unified standard interface.
 Introduction.
IEEE 1687 standard is for access and control of Instruments Embedded within a Semiconductor
Device.

• The IEEE 1687 standard defines an interface between JTAG's TAP and Embedded Modules.
• The IEEE 1687 standard proposes to define a new "Instrument Connectivity Language(ICL)".
• The IEEE 1687 standard proposes to define a new "Procedural Description Language(PDL)".
 IEEE 1687 Hardware Architecture.
1. Instruments:

Instruments are circuits embedded into a device intended for a specific control or data collection
purpose.
• Phase locked loops circuits.
• Clock control blocks.
• Memory BIST controllers.
• Logic BIST controllers.
• EFUSE blocks.
• On chip clock control.
• Embedded deterministic test.
 IEEE 1687 Hardware Architecture.
Single module network architecture example:
 IEEE 1687 Hardware Architecture.
Multiple module instrument access network example:
 IEEE 1687 Hardware Architecture.
2. Controller:
 IEEE 1687 Hardware Architecture.
3. SIB(Segment Insertion Bit):
• Function: Switch.
• Structure: one or more SIBs.

(a) SIB structure. (b) SIB open status. (c) SIB closed status.
 IEEE 1687 Hardware Architecture.
3. SIB(Segment Insertion Bit):

SIB configuration accessing an alternate scan chain.

 IEEE 1687 Hardware Architecture.
4. IEEE 1687 networks:

By combining multiple SIBs together, an IEEE 1687 network can be formed. According to the different
connection structure of the SIBs, the IEEE 1687 network is defined as the following three types:
• Single layer parallel network.
• Multi-layer parallel network.
• Hybrid multi-layer parallel network.
 IEEE 1687 Hardware Architecture.
IEEE 1687 Single layer parallel network:

All the SIBs are connected in series and the Host Interface Port(HIP) of each SIB is not connected to
other SIB devices, but directly connected to the accessed embedded module. This network structure
is called IEEE 1687 Single layer parallel network structure.
 IEEE 1687 Hardware Architecture.
IEEE 1687 Single layer parallel network:
All SIBs are in closed status.
 IEEE 1687 Hardware Architecture.
IEEE 1687 Single layer parallel network:
Simultaneous Accessing to Instruments I1, I2, I3, I4.
 IEEE 1687 Hardware Architecture.
IEEE 1687 Single layer parallel network:
 IEEE 1687 Hardware Architecture.
IEEE 1687 Multi-layer parallel network:
• Network SIB: SIB1, SIB2
SIB1 and SIB2 are like switches that control the on and off of the second and third layer of
the network and the main scan chain respectively.
• Instrument SIB: SIB3
Directly connected to the embedded module called as instrument SIB.

Layer-1

Layer-2

Layer-3
 IEEE 1687 Hardware Architecture.
IEEE 1687 Multi-layer parallel network: Accessing Instrument I1

• Control bit operation:

Sel > SIB1 > SIB2 > SIB3 > I1.
• Data flow direction(enable all SIBs):
TDI > I1 > SIB3 > SIB2 > SIB1 > TDO. Layer-1

Layer-2

Layer-3
 IEEE 1687 Hardware Architecture.
IEEE 1687 Multi-layer parallel network:
 IEEE 1687 Hardware Architecture.
IEEE 1687 Hybrid Multi-layer parallel network:

• Combining the first two network structures, SIB containing multiple parallel structures arranged in
multiple layers.
• In this example, 3 Embedded modules(I1,I2,I3) and 5 SIBS.
• SIB1 and SIB2 has activation signal provided by the JTAG controller.
• SIB4 is the interface between the second and third layer.

Layer-1

Layer-2

Layer-3
 IEEE 1687 Hardware Architecture.
IEEE 1687 Hybrid Multi-layer parallel network:

Accessing Instruments I1, I2, I3 in this example:

• Command Control:
Sel > SIB1 > I1
Sel > SIB2 > SIB3 > I2
Sel > SIB2 > SIB4 > SIB5 > I3
• SIB classification: Layer-1
SIB2 and SIB4 are network SIBs, that control the
on and off of the second and third network layer. Layer-2
SIB1, SIB3 and SIB5 are instrument SIB, that control
the access of Instruments I1, I2 and I3.

Layer-3
 IEEE 1687 Hardware Architecture.
IEEE 1687 Hybrid Multi-layer parallel network:

Accessing Instruments I1, I2, I3 in this example:

• Data flow direction: Enable all SIBs.
TDI > I1 > SIB1 > I2 > SIB3 > > I3 > SIB5 > SIB4 > SIB2 > TDO

Layer-1

Layer-2

Layer-3
 IEEE 1687 Hardware Architecture.
IEEE 1687 Hybrid Multi-layer parallel network:
 IEEE 1687 Operation Languages.

ICL - Instrument Connectivity Language-

• ICL describes the connectivity of the various on-chip IJTAG Network Architecture components with the
instruments present on the scan path.
• It also describes the hardware of TDRs and SIBs present on the chip. The connection of various scan
paths with TAP controller is also included.
• Additionally, it also describes all the active scan path present in the network.

PDL - Procedural Description Language-

• PDL is a command language that instructs the instrument on how to generate patterns; it is not a
pattern description language in itself.
• It creates portable test vector, which can be used with the embedded instrument, irrespective of the
hierarchy in which it is instantiated.
• This makes test vector re-usable, not having to go through the tedious task of pattern generation if the
instrument has to be embedded at different level of hierarchy.
 IEEE 1687 Operation Languages.
Illustrative example - ICL and PDL Description

• Every Network component of the IJTAG standard and every instrument have their corresponding ICL
description. Consider the IP given in Fig.
• The ICL description of TDR that controls its instrument can be described as follows:

Module TDR {
ScanInPort si;
ScanOutPort so; {Source R[0] ; }
ShiftEnPort se;
CaptureEnPort ce;
UpdateEnPort ue;
SelectPort sel;
TCKPort TCK;
ScanRegister R[7:0] {
ScanInSource si
}
}
 IEEE 1687 Operation Languages.
Illustrative example - ICL and PDL Description

Names of ports: si, so, se, ce, ue, sel, TCK, R

Name of Module: TDR
It is an 8 –bit TDR. The so is connected to the bit 0 of tdr. Hence the source of ScanOut Port is defined as
R[0].
PDL description of TDR can be given as:
iProcsForModule TDR
iProc write_to_tdr { value } {
iWrite R $value
iApply
}
iProc run_testX { } {
iCall write_to_tdr 0b10010110
iRunLoop 1000 –tck
iRead R 0xff
iApply
}

All the binding instructions of this PDL are applicable to the TDR module as well as its instantiations.
Tessent IJTAG Network Insertion Flow.
 IJTAG Network Insertion Example Dofile Script.

set_context dft -no_rtl The example starts by setting context to

##Read the libraries dft and reading libraries.
read_cell_library ./library/adk_complete.tcelllib The next step is reading in the Verilog
read_cell_library ./library/memory.atpglib netlist that has already been scan
##Read the netlist inserted and EDT IP inserted with the
read_verilog ./netlist/cpu_top_scan_tk.v PLL module already present. For the
read_verilog ./generated/cpu_top_edt.v PLL module, an ICL and PDL have been
read_verilog ./PLL/PLL.v -interface_only previously created and validated stand-
##Read ICL and PDL files before set_current_design alone. The PDL and ICLs for the PLL are
read_icl ./PLL/PLL.icl read in next. The level at which the
dofile ./PLL/PLL.pdl IJTAG network is inserted is specified
set_current_design cpu_top using set_design_level. In this example,
##Set design level before running set_system_mode analysis the IJTAG network is inserted at the top
of the design and so the TAP pins are
set_design_level chip
specified before running
##Specify the TAP pins using set_attribute_value
“set_system_mode analysis”.
set_attribute_value tck_p -name function -value tck
set_attribute_value tdi_p -name function -value tdi With create_dft_specification, the ICL
set_attribute_value tms_p -name function -value tms for the PLL and the EDT instruments is
set_attribute_value trst_p -name function -value trst automatically configured for insertion
set_attribute_value tdo_p -name function -value tdo into an IJTAG network. This network
set_system_mode analysis can be reported using
report_icl_modules report_config_data. If the IJTAG
##Automatically read any ICL from the directories that verilog is picked from network connection is desired then use
create_dft_specification process_dft_specification, otherwise
report_config_data use the editing commands or
##Use display_specification to edit or modify the specification or use editing commands display_specification with the Config
##if needed. Data Browser to edit. The last step is
process_dft_specification extract_icl that provides the ICL for the
extract_icl level that was set using
exit set_current_design.
Top Level IJTAG Network View.
 Note:
Instruments I1, I2 etc. has L and A numbers, that shows that the interface shift
register(TDR) length of L=3 flipflops, which are to be accessed A=5 times.

THANKYOU.