26th Conference Radioelektronika 2016, April 19-20, Košice, Slovak Republic

Implementation of a Custom Chua’s Diode for Chaos Generating Applications

Pavol Galajda1.), Milan Guzan2.), Jiří Petržela3.)

1.)
Department of Electronics and Multimedia Communications, Technical University of Košice, Park
Komenského 4, 042 00, Košice, Slovak Republic, pavol.galajda@tuke.sk
2.)
Department of Theoretical and Industrial Electrical Engineering, Technical University of Košice, Park
Komenského 3, 042 00, Košice, Slovak Republic, milan.guzan@tuke.sk
3.)
Department of Radio Electronics, Brno University of Technology, Purkyňova 118, 612 00 Brno,
Czech Republic, petrzelj@vutbr.cz
ABSTRACT based on spread spectrum [5], [6], [7] and its application
also found in the music industry as a tone generator [8].
The article presents design of operational amplifier circuit in The above mentioned possibilities of applications the
Austria Micro Systems, 350 nm SiGe BiCMOS technology, authors have led to the creation of CHD as an integrated
suitable for Chua’s diodes construction. By connecting an circuit, which could be easily implemented in the devices
external passive components it became the basis of Chua’s for the encryption, for generating tones and pseudo noise
circuit that can be used for example in communications and and for transmission of signals in communications and other
cryptography. The whole design is implemented in wireless services [9] and [10].
nanometer IC design kit from Mentor Graphics. The
development kit allows to implement both pre-layout 2. DESIGN OF CHUA’S DIODE IN COMPUTER
simulations but also close to the reality post-layout AIDED DESIGN TOOLS
simulations, based on accurate models of technology
processes which are available from the manufacturer of the The Mentor Graphics development tool consists of
integrated circuits in which they will be integrated. The several programs such as nanometer IC design kit, which
results obtained are presented in this article. allows design custom circuits in addition to the possibility
of pre-layout and post-layout simulation, through Eldo
Index Terms— ASIC, Custom Circuit, Chua’s Diode, Diagnostic Tool. In this development tool operational
Chaos. amplifiers (OA) circuit as the basic blocks of CHD was
designed. The designed amplifiers with an external resistors
1. INTRODUCTION connected have to exhibit precisely such an I-V
characteristic which is suitable for generating chaos [11].
Chua’s circuit (CHC) is the first physical circuit In Fig. 1 it is a circuit diagram of CHD. Fig. 2 illustrates
generating chaos, but now is not the only structure which a partial sequence of I-V characteristics (Fig. 2a, Fig. 2b) to
generates chaos. This is a simple circuit that for its produce a final I-V characteristics of CHD (Fig. 2c).
implementation is needed only two operational amplifiers
(Chua’s diode - CHD) and a few passive devices. Precisely
because of these characteristics, this circuit appears to be
suitable for integration on a chip. The chaos generated by
that CHC can be utilized for example in communications
and security applications. Chaotic system is beneficial in
these applications mainly because it is very sensitive to
initial conditions, thus with little change in initial conditions
will achieve very different results. Additionally, these
systems are dependent also on the value of circuit
parameters. The exact parameters of the chaotic circuit can
for instance be used as a key in the encryption system to
encrypt images, video, and speech [1] - [4]. Also, the system
was designed to communicate with a chaotic modulation
Fig. 1. Chua’s diode scheme
Research described in this paper was supported by Czech Science
Foundation (GACR) under project number GA15-22712S and by the Slovak In order to implement the CHD it is necessary to design
Cultural and Educational Grant Agency (KEGA) under contract No. the OA, which will consist of the following main blocks: a
062TUKE 4/2014.
978-1-5090-1674-7/16/$31.00 ©2016 IEEE
differential amplifier and the output amplifier stage (see
Fig. 3). The designed amplifiers will be manufactured in
350 nm SiGe BiCMOS technology. With the design of OA
was necessary to respect the conditions of low power circuit
consumption at ±1.8 V power supply and the use of CMOS
transistors.
Fig. 2. I-V characteristics of a) partial I-V characteristic of
the circuit with IC1, b) partial I-V characteristic of the
circuit with IC2 c) the I-V characteristic of the final Chua’s
diode
In Fig. 3 is a circuit diagram of OA circuit, while the
design was based on internal connection of operational
amplifier MC 14573. Considering the value of the supply
voltage of ±1.8 V and used 350 nm SiGe BiCMOS
technology, width (W) and length (L) of the conductive
channel for each transistor had to be calculated. This
parameters of the transistors was calculated so that as
indicated above, designed OA circuits properties enabling
an I-V characteristic of the resulting Chua’s diode (see
Fig. 2c)). The procedure is shown in the next section [12].
Fig. 3. Scheme of the designed operational amplifier circuit
2.1. The Differential Amplifier
For differential amplifier we require gain Ad=100, which
is given by
Ad  gm1 (rO5 || rO9 )  gm1.rO (1)
where gm1 is the transconductance of the transistors, ro5 and
ro9 are output resistance of the transistors T5 and T9,
respectively, connected in parallel. Parameter ro, the small-
signal output resistance is given by
rO  1/(.I DQ ) (2)
where IDQ is quiescent drain current and λ is the channel-
length modulation parameter. Finding of the Early voltage
from the output transistor characteristics we determine λ by
calculation
λ=1/VA (3)
Then from equation (2) were calculated parameters ro5,
ro9, ro a gm1. Usually in any given fabrication process, the
channel length is the same for all devices, so the channel
width W is the variable in circuit design. In our case, a
channel length of all transistors, 3.Lmin is chosen.
L=3.0,35 μm ≈ 1 μm. (4)
From the formula (5) we express the channel width W
for each transistor T4, T5, T8 and T9.
k` W
g m1  2 ( ) s I DQ (5)
2 L
2.1.1. Current mirror
Differential amplifier to work reliably, it is necessary to
design current mirror, formed by transistors T1 and T2. We
will use the Widlar current source in order to ensure a large
dynamic range. The current through current mirror is set to
30 μA. The voltage across the junctions of transistors
forming a current mirror should be as small as possible, and
we choose saturation voltage vDS=0.2 V. From equation (6)
we calculate the voltage vGS:
vGS  vDS ( SAT )  VTH (6)
where vDS(sat) is the drain-to-source voltage that produces
zero inversion charge density at the drain terminal and VTH
is the threshold voltage. To ensure a relatively high output
resistance of a current mirror and a small mistake of current
in its whole output voltage range [13] is chosen
L=5.Lmin=5. 0,35 μm = 1.75 μm (7)
 The width of the transistor T1, T2, and T3 are given by T11 implemented on the chip should be too large, therefore
the relationship we chose the minimum length of the transistor channel,
which is in used technology LT11=0,35 µm. After
2.I OUT .L recalculation, we received the following values:
WT1,T2,T3   45.2 μm (8) WT7=3.08 µm and WT11=144.5 µm.
k .(vGS  VTP ) 2
`
p

3. PRE-LAYOUT AND POST-LAYOUT

Resistor R1 can be determined from Ohm's law SIMULATIONS

VDD  VSS  VGS Through pre-layout simulation of properties of the

R1   91.6 kΩ (9)
ID designed OA were found different values of voltages VDST3
and VDST10. By appropriately adjusting the ratio W/L the
where ID is the current through current mirror, the VCC is a problems have been removed. Additionally, the asymmetry
positive supply voltag, VEE is a negative supply voltage and of I-V characteristics of CHD were also found. It was
VGS in this case is equal to VDS which is a voltage on the therefore necessary to adjust the width WT7. Tab. I
transistor T1. In the integrated form the resistor R1 can be summarizes the adjusted W and L of all transistors depicted
replaced by NMOS transistor. Width and length of the in Fig. 3.
transistors can be calculated as follows:
TABLE I. THE CALCULATED DIMENSIONS OF MOS
W ID TRANSISTORS USED IN THE DESIGN OA
 ` (10)
LT12 k N .(vGS  VTN )2
Transistor W L Transistor W L (µm)
(µm) (µm) (µm)
If the values of all parameters are apply into (10) we get T1 45 1.75 T7 15 0.35
for a transistor T12 W=0,7 µm and L=0,5 µm. T2 45 1.75 T8 1.12 1
T3 46.3 1.8 T9 1.12 1
2.2. Inverting and Output Amplifier T4 2.9 1 T10 2.53 1.15
T5 2.9 1 T11 144.5 0.35
Inverting amplifier comprised of transistors T3, T6 and
T6 1.4 1 T12 0.7 5
T10 forms the second stage of the proposed operation
amplifier circuit. This is a class AB amplifier. From
Layout of the designed OA circuit illustrates Fig. 4.
simulation of the differential stage, it was found
VGST10=0.9 V. When the selected current IDT6=30 µA, Compared with Fig. 2 it is seen that the transistor T12 in the
voltage V2=1.4 V, and the length of the channel of the scheme is not used. In the integrated form resistor R1 is
replaced by appropriate equivalent circuit with transistor
transistor according to (4) was to calculate the channel
width of the transistor T10 applying the formula: T12.

2.L.I D
WT10   2, 2 μm (11)
k N` .(VGS  VTHN ) 2

Similarly, the width of the channel of the transistor T6

was calculated.
For the transistors T7, T11 forming power amplifiers we
consider the length of the transistor channel L=1 µm. The
width of the transistor of output amplifier can be calculated
using the relationship:

2.L.I D 2.L. I D
WT11  WT7  (12)
V V
k `p .( 2  VTHP ) 2 kn` .( 2  VTHN )2 Fig. 4. The layout of the designed operational amplifier
2 2 circuit
A similar procedure was used for calculation of L and W If the parameters of the individual transistors have not
of other transistors depicted in the scheme diagram been modified, it would be I-V characteristic of CHD
according to Fig. 3. Given that the width of the transistor asymmetrical, as illustrated by Fig. 5a. After adjusting
T11, WT11 released equal to 413 µm, the PMOS transistor transistor parameters the I-V characteristics of CHD are
almost no different (except in outer areas characterized by a
positive differential resistance, as is evident from pre-layout
and post-layout simulation in Fig. 5b).
Fig. 5 a) I-V characteristic of the Chua’s diode before
(black) and after adjustment (red) size of the transistors T,
b) Comparison of I-V characteristics of the Chua’s diode
realized by pre-layout (black) and post-layout (red)
simulations.
If we worked with an asymmetrical I-V characteristic, then it
would be very unbalanced also chaotic attractor realized by
Chua’s diode. In Fig. 6a is a circuit diagram of CHC, and
Fig. 6b shows the unbalanced chaotic attractor mentioned.
a.)
b.)
Fig. 6 a) Simulated Chua’s circuit, b) chaotic attractor with
an asymmetric I-V characteristic. The values of the devices
are as follows: R1=200Ω, R2=220Ω, R3=2.2kΩ, R4=22kΩ,
R5=22kΩ, R6=3.3kΩ, C1=10nF, C2=106nF and L=18mH.
4. SIMULATIONS OF CHUA’S CIRCUIT WITH
SYMMETRIC I-V CHARACTERISTIC
To verify the proper operation of the Chua’s circuit the
simulations of the circuit after the design this circuit in
Austria Micro Systems (AMS), 350 nm SiGe BiCMOS
technology were carried out. According to Fig. 6a, resistor R
was chosen as bifurcation parameter. The circuit showed a
chaotic behavior (double-scroll CHA) when changing
resistor R from 1600 Ω to 1850 Ω. For R=1900 Ω the
double-scroll CHA became single-scroll CHA (see Fig. 7).
Final circuit, composed of integrated CHD on the chip
should therefore generate chaos. The authors therefore
consider that the first phase to be fulfilled, but will continue
to work on further optimizing and prepare all necessary
steps for a die fabrication. For completeness we are noted
that all the passive elements shown in Fig. 6a after
fabrication of the chip will be attached externally. Two on-
chip OA occupy an area 64,1x59,5 μm. For further analysis
of the Chua’s circuit will be interesting to see what will be
the boundary surface morphology [14] and [15], which will
separate the Chua’s attractor and stable limit cycle.
Fig. 7 Chaos generated by Chua’s circuit in post-layout
simulation
5. CONCLUSION
Introduced design of the operational amplifier, that
operates with supply voltage ±1.8 V, followed by
construction of the Chua’s diode, implementation of the
layout in Austria Micro Systems, 350 nm SiGe BiCMOS
technology and performed pre-layout and post-layout
simulation suggests that in this article described design of
the Chua’s diode will be used also if it will be integrated on
chip. This creates an area not only for theoretical analysis on
new parameters of Chua’s circuit [14]- [16], but also for
utilization of the Chua’s circuit into applications working on
the integrated chip. This creates area for new custom
devices intended for example in the field of cryptography
and communications.
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