library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.NUMERIC_STD.ALL;

entity display_box is
Port ( Code : in STD_LOGIC_VECTOR (7 downto 0);
Clk : in STD_LOGIC;
F0 : in STD_LOGIC;
Rdy : in STD_LOGIC;
display : out STD_LOGIC;
Note : out STD_LOGIC_VECTOR (7 downto 0);
ValidNote : in STD_LOGIC);
end display_box;

architecture Behavioral of display_box is

signal div: STD_LOGIC_VECTOR(7 downto 0);
signal wcisniete: STD_LOGIC := '0';
begin
process0: process(Code)
begin
case Code is
when X"15" => div <= X"63"; --c
when X"1E" => div <= X"43"; --cis
when X"1D" => div <= X"64"; --d
when X"26" => div <= X"44"; --dis
when X"24" => div <= X"65"; --e
when X"2D" => div <= X"66"; --f
when X"2E" => div <= X"46"; --fis
when X"2C" => div <= X"67"; --g
when X"36" => div <= X"47"; --gis
when X"35" => div <= X"61"; --a
when X"3D" => div <= X"41"; --ais
when X"3C" => div <= X"68"; --h
when others => div <= X"00";
end case;
end process process0;

process1: process(Clk, F0, Rdy)

begin
if rising_edge(Clk) then
if div /= X"00" and ValidNote = '1' then
if Rdy = '1' and F0 = '0' then
if wcisniete = '0' then
wcisniete <= '1';
display <= '1';
end if;
elsif F0 = '1' then
wcisniete <= '0';
display <= '0';
else
display <= '0';
end if;
else
display <= '0';
end if;
end if;
end process process1;
 Note <= div;
end Behavioral;