388 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 9, NO.

2, JUNE 2019

ReRAM-Based In-Memory Computing for Search

Engine and Neural Network Applications
Yasmin Halawani , Student Member, IEEE, Baker Mohammad , Senior Member, IEEE, Muath Abu Lebdeh,
Mahmoud Al-Qutayri , Senior Member, IEEE, and Said F. Al-Sarawi , Member, IEEE

Abstract— Resource-constrained computing devices such as

those used in IoTs require low-power, high performance, and
small size to be enabled to operate efficiently. Resistive ran-
dom access memory (ReRAM) is a promising technology for
building novel in-memory computing architectures, due to its
ability to perform storage and computation using the same
physical element with low energy and high density. ReRAM-
based search engines and neural network (NN) accelerators
have grown significantly especially for IoT devices. In this
paper, we propose a memristor-based voltage-resistance xnor
(VR-XNOR) cell. The advantages of this cell are demonstrated
through building a reconfigurable content-addressable memory
(CAM) architecture that can support binary-CAM (BCAM) and
ternary-CAM (TCAM) and enable approximate search opera-
tions. Moreover, the memristor-based VR-XNOR cell is utilized
for binarized convolutional neural networks (CNN) with focus
Fig. 1. An extension of the classification of Memristor-Based Logic
on the convolution operation. This is achieved by replacing the
Design found in [7] with multiple input data representation. The first letter
convolution module with XNOR-based filter banks. Simulations represents Input 1, the second letter represents Input 2. While the third letter
of the proposed architectures for search engine and feature represents the processing element. V: voltage, R: resistance, B: both voltage
extraction were carried out using VTEAM model in Cadence and resistance, M: memristor-only and H for hybrid CMOS-Memristor.
Virtuoso Analog Design Environment. The proposed filter bank ([∗ [8], [9]], [∗∗ [10]–[13]], [† [14]], [‡ [15], [16]], [$ [2]], [§ Proposed].)
architecture achieves a 1-ns extraction cycle time over N filters
and produces multiple output feature maps in a single processing
cycle. The filter uses two memristor devices to realize each XNOR capabilities, which makes it a potential building block for In-
gate and has shown a significant reduction in the number of Memory Computing (IMC) [2], [3]. With such capabilities,
multiply-add operations. ReRAM based computing systems have the ability to mitigate
Index Terms— Memristor, CNN, accelerator, in-memory com- the key bottlenecks of Conventional CMOS-based computing
puting, template matching, XNOR. designs that are based on the von Neumann architecture.
For example, data movement through Input/Output pins in
I. I NTRODUCTION CMOS-based architecture is estimated to consume 100× more
energy than a floating-point operation and can limit device

M EMRISTOR, a type of Resistive RAM (ReRAM)

device technology, promises to extend the trend of low
power while maintaining low cost with high density [1]. The
two-terminal device consists of a thin oxide film that has the
ability to store information with zero leakage current, high
endurance, relatively fast write time and small cell size. The
device has shown both storage and information processing
Manuscript received November 30, 2018; revised February 5, 2019;
accepted March 22, 2019. Date of publication April 4, 2019; date of current
version June 11, 2019. This publication is based upon work supported by the
Khalifa University of Science and Technology under Award No. [RC2-2018-
020]. This paper was recommended by Guest Editor J.-S. Seo. (Corresponding
author: Yasmin Halawani.)
Y. Halawani, B. Mohammad, M. Abu Lebdeh, and M. Al-Qutayri are with
the System-on-Chip (SoC) Center, Khalifa University, Abu Dhabi 127788,
United Arab Emirates (e-mail: yasmin.halawani@kustar.ac.ae).
S. F. Al-Sarawi is with the Centre for Biomedical Engineering, The
University of Adelaide, Adelaide SA 5005, Australia.
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JETCAS.2019.2909317
2156-3357 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
performance [4]. Furthermore, the continuous response of
memristor state variable to an applied input voltage makes
it an ideal candidate for multiply and accumulate operations
commonly needed in many digital image processing tasks.
When these devices are built in a crossbar architecture,
they result in an inherently parallel operations, and can
naturally realize the vector-matrix operation with potential
savings in energy, area and execution time. Hence, ReRAM-
based systems are ideal candidates for real-time search engines
and neural network accelerators, especially for resource-
constrained IoT nodes [5], [6]. ReRAM can be configured to
support analog matrix multiplication or bitwise search opera-
tions within memory. In this paper, we focus on implementing
an XNOR gate to enable a bitwise comparison for a CAM
search engine. Moreover, the same gate is utilized for feature
extraction in convolutional neural networks (CNN).
There are eight classes of resistive-memory based logic
designs depending on the input and output data representations

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HALAWANI et al.: ReRAM-BASED IN-MEMORY COMPUTING FOR SEARCH ENGINE AND NN APPLICATIONS
and the processing elements used [7]. We have extended the
classification to include a second input as illustrated in Fig. 1
that can either be resistance, voltage or both. This is in
contrast to [7] where the inputs are restricted to either volt-
age or resistance. Each architecture family has its advantages
and disadvantages depending on the application. For example,
resistive-resistive logic is appropriate for search applications
where both operands are stored in the memory. This is in
contrast to read the data first followed by the search operation.
While in case of real-time search operation it is better to have
the inputs as voltages from the sensor be compared against the
values stored in the memristor. In [5], we proposed the use of
stateful-input and stateful-output for memristor-based search
engine that is based on a novel heterogeneous memristive
XOR gate. In this case, control voltages are applied to the
XOR array to perform a comparison operation between two
memristor states. The output of such comparison is also stored
as a memristor conductance value. It is worthnoting that this
type of representation is ideal for the case when both inputs
(operands) are stored in memory.
In this paper, the proposed scheme has one input as voltage
and the second as resistance. The new cell/architecture enables
multiple database matching. To the best of our knowledge, this
is the first reporting of a reconfigurable cell that can output a
resistance value or a voltage. The contributions of this paper
can be summarized as follow:
• Reconfigurable voltage-resistance XNOR (VR-XNOR)
cell that has one operand in resistance representation
while the second operand is voltage representation. The
output can be in voltage or resistance representation.
• A CAM architecture that can be configured as BCAM,
TCAM or approximate search for 2D input.
• A memristor-based filter bank architecture that uses
XNOR cell to extract features for convolution neural
networks (CNNs). Demonstrating a significant reduction
in the number of multiply-and-accumulate operations than
the conventional methods.
• A parallelized and pipelined average pooling operation to
allow simultaneous pooling of sub-feature maps.
In the next section, the VR-XNOR cell design is presented
and discussed. The rest of the paper is organized as fol-
lows: The proposed memristor-based search engine architec-
ture is described and demonstrated in Section III. After that,
Section IV provides a brief background of convolutional layers
along with the simulated experimental results for multiple
filter architecture for CNNs are reported and discussed. Then,
Section V concludes the paper and discusses future research.
II. P ROPOSED VR-XNOR C ELL D ESIGN
Bitwise XNOR operation has been widely used to efficiently
implement data encryption, error detection/ correction, binary
to Gray encoding and search engines [13]. In this work,
we propose to use a VR-XNOR cell for CAM design and
feature extraction for CNN. In the proposed voltage resistance
(VR)-CAM cell demonstrated in Fig. 2, one operand is voltage
that is compared against a second operand that is resistance.
The output can be voltage or resistance. This is useful for real-
time applications where the input voltage, e.g. an image from
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389
Fig. 2. Two-input memristor VR-XNOR cell where one operand is voltage
(V A , V A ) that is compared against a second operand that is resistance (R B ,
R B ). Output can either be voltage V OU T or stateful R OU T . The switch SW
can configure if the output is voltage for BCAM and TCAM or resistance in
case of similarity search.
TABLE I
XNOR T RUTH TABLE (L OGIC ‘0’ → 0 V AND 10 M,
L OGIC ‘1’ → 0.6 V AND 10 k)
a sensor, can be fed directly to the non-volatile CAM structure
for a similarity check. The cell consists of 3 memristive
devices. One memristor stores the data while the other stores
its complement as RON and ROFF or vice versa. These two
memristors are used to perform the search operation. While
the third device is for the output.
The cell consists of computing and storage bipolar mem-
ristor devices with two different turn ON voltages (switching
time). The switching time for the computational devices is very
slow in order not to be disturbed during computation. While
the switching time for the output memristor is fast. Fabrication
of such structures has been reported in the literature through
having different oxygen vacancy concentration for the same
material [17]. The fabrication process implies that there is a
need to have an extra mask to enable device selection. The
sub-sections below explain the main operations namely the
compare and read.
A. Search Operation
The proposed cell can be used to build either BCAM,
TCAM or for similarity search. In the first, all cells are
contributing to the output. In the second case, depending on
the variable length of the input stream, if certain bits are
masked or have don’t care during the comparison operation,
then the corresponding input to the cells are left floating. The
output column will be fed directly to a comparator to identify
a match/mismatch in a BCAM or TCAM structure. In case
of a similarity search, the accumulation memristor will be
connected at the end of the column. Hence, a switch can be
used with the output accumulative memristor. So if the switch
is ON, the CAM structure is used for similarity search. While
if it is OFF, a BCAM/TCAM comparison is performed by the
CAM structure.
390 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 9, NO. 2, JUNE 2019

The design checks the input voltage that represents the data
entry against the conductance of one memristor as the second
one will be its complement. The matching operation is per-
formed according to the following XNOR Boolean expression:
V A R B +V A R B . The truth table of the XNOR cell is presented
in Table I. The input voltage levels V A and V A can be selected
based on the usage model. For example for BCAM and
TCAM, V A = 0.6 V and V A = 0 V or vice versa. But in
the case of similarity search where the comparison result is
written into ROUT then, V A = 1 V and V A = 0 V or vice
versa. This is to enable to write ROUT in the given time. It is
worth noting that the voltages used in these simulations were
chosen to achieve fast switching with good noise margin based
on reported real devices [18]. The 1 V was selected because it
allows a full switching of the output memristor when all inputs
match with the databases/filters. On the other hand, 0.6 V was
chosen because it provides an acceptable distinction between
matching and mismatching cells in case of BCAM/TCAM
where an output memristor is not used. The output memristor
is initialized to ROFF . When both the applied input voltage
and the stored data are matching, the voltage drop across the
accumulation memristor is high. Only when a matching occur,
it will be pushed to RON . It was chosen this way since most Fig. 3. Comventional CMOS-CAM array where each cell consists of 6T
SRAM cell and dynamic comparator to compute the match/mismatch signal.
of the time there will be more mismatches than matches and
hence the energy will be minimized. Otherwise, in the case
of a mismatch, the voltage drop will be small and the output costs at minimal. Conventional CMOS-based search engines
memristance will stay as ROFF . This will result in overall better suffer from density and power limitations.
power efficiency. The output voltage can be calculated through Most systems use software-based search engines, such
the following equation. as associative lookup tables (LUT). Such implementation is
restricted to the size of available physical memory, which
RB RB
VOUT = V A   + VA   leads to higher latency due to the need for external mem-
RB
RB + RB 1 + ROUT R B + R B 1+ RROUT
B
ory access [19]. Usually, these algorithmic software-based
(1) approaches are suitable for general purpose application, but
cannot be utilized for IoTs that need to process data in real-
time. Application specific integrated circuits (ASICs) hardware
B. Read Operation implementations are much faster than software approaches
In order to read the stored patterns in the memristor, and hence more appropriate to accommodate real-time search
the corresponding voltage can be applied only to the stored operations [20], [21]. ASIC also utilizes special type of CAM
data as there is no need to read its complement. If the output that can perform lookup operation in a single clock cycle.
voltage is high, then the stored bit is RON otherwise, the stored Conventional CMOS-based CAM, depicted in Fig. 3,
bit is ROFF . Read operation of the stored patterns for CAM is composed of a memory element combined with a com-
type applications is rarely performed. And if it to be done parison circuitry [20] that facilitate parallel search operation.
for the whole CAM structure, it should follow a bit-wise read The data is stored in the memory using a large number of
operation. This is a limitation of the proposed CAM structure transistors (10+) per bit. Once the input data is fed into the
as it requires multiple cycles to read a single database. Hence, CAM, the search operation is performed using a precharge-
a memristor-based memory crossbar with the same stored evaluate operations, similar to SRAM read operation [22].
database can be used in parallel to fetch the database with After that, the address of the matching data will be returned (or
the highest similarity score. the matching data itself in the case of associative memory).
BCAM and TCAM are two widely used search memories.
In the former, exact-match searches are performed. While in
III. S EARCH E NGINE S YSTEM A RCHITECTURES the latter, don’t cares are further utilized to improve matching
performance by performing partial or range matches [23].
A. State-of-the-Art Systems The major challenges for conventional CMOS-based CAM
Fast search engines are required for real-time decision mak- and TCAM designs are their low density and high power con-
ing in various fields including computer vision, machine learn- sumption. Implementations utilizing pre-charge phase increase
ing and object recognition. For IoTs and similarly resource power consumptions and increase complexity [24]. Further
constrained devices that need to implement fast search engines, research into lower power and higher density cells to align with
it is of paramount importance to keep both area and energy the continuing rapid growth in data has been sought. Moreover,

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HALAWANI et al.: ReRAM-BASED IN-MEMORY COMPUTING FOR SEARCH ENGINE AND NN APPLICATIONS
for media applications that deal with 2D images, as the image
size increases, circuit complexity increases. Traditional CMOS
implementation continue to be more expensive in terms of
area, power and processing time. For example, in [25] a 2D
pattern is divided into sub-patterns with a size that must
be small to be manageable for processing. The architecture
becomes impractical as pattern size increases.
To address the highlighted challenges, there is a growing
interest towards utilizing emerging non-volatile nano-devices
for search and match operations. In [26], the memory core is
composed of a CMOS transistor and a phase-change memory
(PCM) with 1T1R structure; where the PCM is used to store
the data. This is followed by a differential sense amplifier to
change the stored value into a corresponding voltage value
(i.e. GND or VDD). Then, a comparator is used to compare
the stored data with the input search voltage. The non-volatile
element is not part of the computation and only used as a
storage element. Researchers in [27] have proposed the use
of STT-RAM in CAM/TCAM. The design uses 1T1MTJ per
cell on each bitline and one reference resistor. The architec-
ture suffered from long delay. Hence, in [28] 14 transistors
and pentaMTJ are utilized to obtain a sub-1ns TCAM cell.
However, PCM is temperature sensitive [29]. The MTJ has
low noise margin between the two resistance states and long
search delay [30], which negatively affect the performance. In
addition to the aforementioned devices, researchers are looking
into utilizing the memristor for CAM application. Some of
the major resistive-based CAM cell implementations studies
utilize stateful logic, while others use complementary resistive
switches (CRS). Moreover, the designs vary in the numbers
of both nano-devices and transistors used to build the bit-cell
memory. Other implementations focus more on the endurance
issue and speed while relaxing on the energy consumption.
A memristors-based TCAM (mTCAM) cell consisting of
five transistors and two memristors is proposed in [3]. The
stored data is represented by resistance values of the memris-
tive devices as the data and its complement. Four search lines
are used per cell and only three are effective during search
mode. Initially, match lines are precharged to high. Delays
from the four search lines, TCAM cells with 5T2R structure,
and the ML would contribute to an increase in the search
latency as well as the energy consumption.
In [2], a transistor-free memristor TCAM structure for
comparing input data against a bank of stored words is
presented. This architecture can be used for intrusion detection
applications where packets are scanned to determine if they
are malicious or not. For N bits, the number of memristors
required are 4N+2. The design has shown ∼ 360 × reduc-
tion in area with competitive timing and energy compared
to CMOS-based CAM. In that structure, each bit requires
4 memristors; one connected to the input voltage, the second
to the input voltage complement, and the third and fourth are
connected to two bias voltages to account for the variations of
the memristance value. This is in addition to two bias voltages
per column.
Another approach for search using implication logic was
proposed in [19]. In this approach, eleven steps per CAM
cell are required to generate a cell match signal. In [31] CRS
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391
based stateful logic operations using material implication is
presented. For a two-input XOR implementation, the design
requires 4 CRS (8 memristor devices) and 6 steps to compute
the operation.
In [32], the search operation is performed by firstly pro-
gramming the CRS array with a template pattern. Then each
match line (ML) is pre-charged by a global reset signal. After
that, the ML is discharged by the result of correlation based
on the Hamming distance between the two input images.
Moreover, in [33] the search engine consists of two CRS and
cross-coupled switches with an analog correlator that flags the
Hamming distance for the image-recognition and classification
process.
Approximate TCAM (ACAM) is proposed for online learn-
ing in [30]. The authors use MTJ to tackle the endurance issue
associated with the wear-out of memories for online learning.
The architecture consists of a 5T-4MTJ TCAM followed
by an STT-RAM memory. Once the searched input data is
found, a clock gating signal is activated to stop the processor
computation. And finally, the corresponding line of the STT-
RAM memory to read the precomputed output data.
B. Proposed Search Engine System Architecture
The proposed VR-XNOR cell was used as the main building
block for the memritor-based CAM array architectures. The
crossbar architecture shown in Fig. 4 enables parallel lookups
of multiple inputs in multiple CAM banks. For N input bits,
the system requires 2N memristor devices to perform a com-
parison. And an analog memristor accumulator at the end of
each column. So each data entry requires a representation of its
value and its complementary value. Input data is represented
as applied voltages while the stored data is represented by
conductance value of the memristor. Each column corresponds
to a different database.
Multiple bank lengths can be traded-off between the number
of bits per share match line and the output voltage difference 
in (mV) output resistance between matching and mismatching
cells. As the bank length increases, the voltage difference
between all matching cells and a single mismatch starts to
decrease until it reaches almost zero when all bits mismatch
and hence no switching occurs to the output memristor. This
is due to the fact that when there is a mismatch the high
resistance bits are still contributing to the output voltage and
the combination of matching and mismatching cells result in
reduced voltage difference.
The output bank reading circuitry is illustrated in Fig. 4(c).
Depending on the desired application as explained previously
in Section II, if the architecture is used for BCAM/ TCAM
then the output voltage will be fed directly into the comparator
as shown in part (a) of the figure. While if a similarity search,
then the switch will be initially closed to write the output into
the memristor. Then the next step is to evaluate R OU T , so the
switch will open to read its value without disturbing the rest
of the cells and feed it into the comparator as demonstrated
in part (b) of the figure.
Logic ‘1’ corresponds to the memristor ON state, RON ,
while logic ‘0’ corresponds to the memristor OFF state, ROFF .
392 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 9, NO. 2, JUNE 2019

Fig. 4. Memristor-based multiple banks CAM architecture shown in a) and its digital equivalence is shown in b). The readout circuitry schematics for the
BCAM/ TCAM configuration and similarity search is shown in c), (en stands for the enable signal and Vre f is the reference voltage). The switch SW can
configure if the output is voltage for BCAM and TCAM (SW=OFF) or resistance in case of similarity search (SW=ON).

TABLE II maps yn that are results of element-wise multiplication

C OMPARISON B ETWEEN P ROPOSED A RCHITECTURES
AND C OMPETITIVE M EMRISTIVE CAM S
The ranges can be determined by dividing the whole resistance
spectrum in half equally or unequally depending on the voltage
difference [35].
The estimated area calculations for the memristor crossbar
was based on a fabricated full-pitch width of 400-nm from
[36]. For the first architecture that consists of multiple banks:
the 256 × 144 structure would be divided into 4 banks each
with 64 memristor devices (32 pairs) = 4 × 64 × 144. It would
occupy an area of [4×(400 nm × 64) × (400 nm × 144)] =
5898.2 μm2 that will accommodate 128 bits.
In the next section, CNN is briefly explained followed by
the XNOR-based CAM cell is utilized for feature extraction.
and summation between the filter and the specific block
of an image. This value represents whether the specific
feature exists in the particular part of the image.

yn = wi x i + bi , (2)
i
where n is the number of columns (filters), wi is the
weight of the filter, x i is the input and bi is the bias.
• Pooling layer: downsamples the feature maps into smaller
sizes which reduces the complexity of the whole archi-
tecture. If max pooling is used then prominent features
from a specific block are extracted. On the other hand,
average pooling gives a smoothed/blurred output of the
features from a specific receptive field.
f (x) = max (0, x), (3)
• Non-linear activation function: is responsible for mapping
the neurons output in terms of its input. Rectified linear
units (ReLU) has been widely used instead of sigmoid
and hyperbolic tangent, as ReLU is much faster to train
than these non-saturating nonlinearity [37].
• Fully connected (FC) layer: the final output stack is

IV. C ONVOLUTIONAL N EURAL N ETWORKS A PPLICATION
A. Basics of CNN
Convolutional neural networks (CNNs) are found to be
superior compared to other standard feedforward neural net-
works in terms of accuracy. Such network mimics the locality
found in human visual system (HVS) and have much fewer
connections and parameters, as a result they are easier to train
[37]. CNN structures are divided into two main stages: feature
extraction followed by classification. The following 4 main
layers are used in the implementation of a CNN:
• Convolution (ConV) layer: is the ability of the filters to
capture (detect) as many generic features as possible from
the training dataset that would help in classification (for
example) of the testing dataset. It consists of sliding N
filters each of size k ×k with randomly initialized weights
over a set of training images. This step produces feature
flattened to produce a 1D array to check the effect or sig-
nificance of each feature on the final classification stage
for the different classes. All neurons are connected to all
output neurons in the output layer.
The last step is to calculate the classification error and
update the weights using the backpropagation algorithms
according to the chain rule.
Convolutions are the computationally intensive operations
as they nominally account for nearly 90% of the total process-
ing task [38], with heavy reliance on floating point matrix
multiplication. This will cause an issue with general purpose
processors specially with the limited cache size. Hence, graph-
ics processing units (GPUs) have been widely used to accel-
erate the convolution operation due to their high parallelism
and floating point operations performance [39]. Nonetheless,
GPUs suffer from high power consumption which makes
them expensive to deploy during the inference/testing phase

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HALAWANI et al.: ReRAM-BASED IN-MEMORY COMPUTING FOR SEARCH ENGINE AND NN APPLICATIONS
of CNNs specially in mobile systems that require real-time
and low power consumption [40].
Thus, field-programmable gate array (FPGA) and applica-
tion specific integrated circuit (ASIC)-based CNN accelerators
are increasingly being used to achieve high accuracy with low
power consumption and highly reduced computational time
[39]. On the other hand, several schemes and versions of
CNN are being exploited in order to align with the rise of
IoT and mobile devices such as neuron pruning and weights
quantization [41].
Approximating the full precision floating point weights
through quantization has been studied lately. Lowering the
precision and utilizing an extremely compact data representa-
tion such as the binarized CNN (BNN) has shown the ability
to reduce memory resources and decrease computational time
[42]. In [41], the authors have shown 58× improvement in
convolution operations and 32× memory savings when both
the weights and inputs are binarized with 12.5% loss in
accuracy as compared to the full-precision using AlexNet.
Moreover, in [43] the network biases were removed as most
of them had magnitudes less than 1 after quantization which
did not affect the accuracy. As a consequence of the binariza-
tion, the convolution operation (multiply and add modules)
is reduced to XNOR and bitcount adders to realize the
convolution operation efficiently specially for systems with
limited resources [44]. Nonetheless, the neural weights still
require to be moved from the memory to the computational
unit which creates timing and power overhead. It is appreciated
that the binarization process causes accuracy loss and hence,
there are efforts to reduce this impact. For example, authors
in [40] proposed the use of the sign() function with shift
parameter inside in order to approximate the full precision
using binary bases. Thus, accuracy loss was reduced to around
5% compared to the state-of-the art implementations.
The proposed method reduces training time significantly
since the movement of weights has been eliminated in addition
to the binarization process [41]. Moreover, it reduces the area
by performing an unsigned bitwise operation instead of using
two crossbars to store negative and positive weights with a
subtract operation for every complementary bitline output [4].
Memristor crossbars have been widely used as neural net-
work accelerators as they perform in-memory computations
on the stored weights and hence eliminate their movement.
For example, in [45], the authors presented a memristor-
based architecture for on-chip training of deep neural net-
works (DNN). The architecture utilizes two memristors per
synapse for higher precision of weights. Moreover, the back-
propagation algorithm was used to train the autoencoders and
to fine tune the pre-trained weights. In addition, in [46],
the authors proposed the use of memristor-based CNN to par-
allelize the recognition phase. They assumed that the crossbars
are already trained and stored as conductance values. The
crossbars were used for analog vector-matrix multiplication
acceleration with each weight represented by two memristor
to account for both the positive and negative values. The filters
were expanded into large sparse matrices. In [47], the authors
presented ISAAC architecture, an analog CNN accelerator
where tiles containing memristor crossbars are partitioned
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393
across the layers. The dot-product operations involved in
convolution and classifier layers are performed on crossbar
arrays; those results are sent to then converted to digital
representation, and then aggregated in output registers after
any necessary shift-and-adds.
Moreover, Ni et al. presented in [48] a binary vector-matrix
multiplication where they use two pairs to represent an AND
and OR operations which translates to binary multiply and
add operations, respectively. This is followed by a voltage
comparator with a reconfigurable threshold voltage. The con-
volution part requires a 2N×N ReRAM-crossbar per filter. The
authors compared their RRAM-based BNN system to other
hardware (GPU, FPGA and CMOS) implementations and it
has shown 4 orders of magnitude, 4155× and 62× less power
respectively under similar accuracy. A digital RRAM-based
convolutional block that is capable of performing dot product
operations in a single cycle is proposed in [49]. The main cell
consists of 4 transistors and 1 RRAM (4TIMR) components.
The cell employs two pairs of NMOS and PMOS transistors
in order to trigger a set or a reset process to program the
memristor. The RRAM crossbar is followed by an XNOR
sensing circuit and then a combinational bitcount circuit.
Increasing the number of layer increases the accuracy as it
helps to represent complex features from local low-level ones.
Nonetheless, this also increases the number of multiply-and-
accumulate (MAC) operation as each connection to a neuron
represent a MAC operation. It has been reported in [38] that
AlexNet, which consists of 5 convolutional layers, requires
666 million MACs per 227×227 pixel size image. While
the VGG16 architecture that uses 13 convolutional layers,
requiring 15.3 billion MACs per 224×224 pixel size image.
B. Proposed CNN Architecture
One of the drawbacks of using analog memristors to carry
out computations is that the data stored will likely have less
precision when compared to typical 32-bit floating point data
representation [50]. Variations in memristor does impose a
challenge for analog computation. On the other hand, utilizing
a memristor for digital operation (high resistance, low resis-
tance), as it is the case for BNN, will provide a more robust
computation in face of device variability. For the endurance
of the devices, the number of read to write ratio is large
as reported in the literature [18]. Moreover, the devices are
programmed once after training in case of CNN applications
and for the databases in CAM. Hence, endurance effect is
minimal in the presented case.
To the best of our knowledge, this is the first paper to present
a VR-XNOR memristor-based template matching circuit for
BCNN with 2N memristor devices per bit. In addition to the
ability to perform the pooling operation with the convolution
process at the same time.
The storage memristor which is used to store the feature
map values is initialized to ROFF . This is because the features
do not exist in all patches of the input image set and conse-
quently there will be more mismatches than matches. So from
an energy point of view, initializing the output device to
ROFF minimizes the energy and results in better overall power
394 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 9, NO. 2, JUNE 2019
Fig. 5. Memristor-based multiple filter architecture that shows in a) a k×k
image patch being flattened to a 1D array and then a voltage generator will
translate the intensity of the pixels to voltages prior to applying them as input
to the XNOR-based filters. The output is the feature map value that is directly
written to the memristor crossbar shown in b). Then voltages are applied to
the crossbar seen in b) to perform average pooling. These average pooling
voltages can also be used as row selectivity to ground the active rows in order
to write the output to the feature map crossbar. The last row in the feature
map crossbar corresponds to the output of the image patch (shown in the
lower right corner of the input image) being XNORed with N filters.
efficiency. When there is a match between the image patch
pixel and the stored feature pixel, the voltage drop across the
accumulation memristor is high and pushes the state variable
x to RON . Otherwise, in case of a mismatch, the voltage drop
will be small and the output memristance will stay as ROFF .
It is worth noting that the main difference between the work
by Ni et al. [48] and ours is 1) they use 2N×N crossbar
to represent a single filter, while we use a 2N×M crossbar
size that can represent M filters since each column in that
crossbar is a different filter. And 2) in our proposed design the
native XNOR output is written directly to the pooling crossbar
instead of sensing and then writing.
The crossbar architecture shown in Fig. 5 enables parallel
operation over several N filters. For each bit, the system
requires 2 memristor devices to perform a comparison. And a
storage memristor at the end of each column to store the value
of the feature map. So each entry of the filter is represented by
its value and its complementary value. In addition, input data
from the image patch is represented as applied voltages while
the filter elements are represented by conductance value of the
memristor. Each column corresponds to a different filter.
In order to implement the proposed VR-XNOR for CNN
filtering operation:
• The N filters, are first converted to a 1D-array in order to
be able to implement the element-wise comparison and
addition from all filter members at once.
• The corresponding image patch is converted into a 1D-
array and applied to the terminal of the filter bank as
corresponding voltages.
• Applying the first image patch as voltages to the filter
bank shown in Fig. 5(a) produces the extracted feature
value from the first bank, the second column with the sec-
ond bank and so on. In the second clock cycle, the second
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TABLE III
VTEAM M EMRISTOR M ODEL PARAMETERS FOR C OMPUTATIONAL
D EVICES AND S TORAGE D EVICES
image patch will be applied. So for an 32 ×32 image size
and a 2×2 filter size with stride = 2, it will take 16×16 ns
to perform the convolution. Convolution can be further
optimized and completed within 16 ns at the expense of
more hardware resources. For example, a stack of filter
banks can be used where each bank is responsible for
a row from the image. This will also require a second
stage of analog output data to accumulate the matching
from all column that correspond to the same filter from
the stack.
• Once the convolution is being performed through com-
putation operation on the above crossbar layer presented
in Fig. 5(a), the result will be directly written to the
pooling layer shown in Fig. 5(b) in a row-by-row fashion.
This helps to first eliminate additional peripheral circuitry,
and secondly eliminate the select transistor in the pooling
layer as inactive rows are kept floating. It is expected
that conversion from analog to digital and vice versa can
consume 85% [4] in neuromorphic systems. It is worth
noting that there is a need to address the sneakpath current
when writing to the convolution layer devices. This can
be achieved by i) resetting the whole crossbar in a single
cycle and then write logic ‘1’ to the devices in a row-by-
row fashion where other inactive rows are kept floating
with either half or third of the supply voltage can be used
for the writing scheme as in [51], and ii) utilizing a 1T1R
structure with the same writing scheme as previous point.
Writing during operational phase is rare since the training
is performed offline.
C. Simulation Results and Analysis
The proposed filter bank design has been simulated and
verified using circuit design spice simulator from Cadence
tools. Two types of memristors have been utilized in the
VR-XNOR-filter bank as explained in Section III.A. VTEAM
spice model for memristor is used in the simulations [52]
with the values of the used parameters presented in Table III.
The storage memristor switches within 1 ns as has been
demonstrated by HP Group for 3 nm ×3 nm device sizes
[18], [53], [54]. Since from circuit-point-of-view CNN and
CAM share the same VR-XNOR-filter bank architecture; it
has been verified on CNN.
HALAWANI et al.: ReRAM-BASED IN-MEMORY COMPUTING FOR SEARCH ENGINE AND NN APPLICATIONS 395

TABLE IV
T RADE -O FFS B ETWEEN D IFFERENT F ILTER S IZES AND M ATCHING
M ARGIN FOR A 2×2 AND 3×3 S IZES

It can be noted that the energy decreases as the number of Fig. 6. Illustration for a convolution where the input is a binary image patch
bits per column increases (larger filer size). This is because compared against two filters stored in the memristor crossbar.
by having more voltage sources, this would cause the output
memristor to switch slightly faster than with the smaller
filter size. Moreover, the energy decreases as the number of
matching cells within the same filter increases since the current
is limited by the memristor storing the feature map values.
Different 2D-filter sizes were investigated as shown
in Table IV after reshaping them into 1D-array. The selected
sizes of 2×2 and 3×3 used in these simulations are utilized
because they are widely used for CNN. Nonetheless, other
sizes such as 5×5 and 11×11 have been reported in literature
[55]. As a result, the more parallel pairs added to the structure
the total resistance will decrease, resulting in reducing the dif-
ferentiable voltage margin between matching and mismatching
cases. Hence, there is a trade-off between the filter size
and the corresponding output resistance during matching and
mismatching operation. As the filter size increases, the column Fig. 7. Illustration for the output from 2 filter banks where one 100% matches
length increases, and the voltage difference between all match- with the input patch and the other matches with 55.5%.
ing cells case and a single mismatch starts to decrease until it
reaches almost zero when all bits mismatch. This is captured in 3. If implemented in ASIC, 9 multiplications and 9 additions
the output resistance value. This means that the learnt feature including the bias are required for each patch convolution.
stored in the filter does not exist in that part of the input Hence when convolving one image with a single filter it would
image and the high resistance bits are still contributing to the require (9×83×83) multiplications + (9×83×83) additions.
output voltage. With each mismatching bit between the filter While if memristor was used to implement the filter bank,
and the image patch, the voltage will drop by a , whose a 83 × 83 multiplications and additions are required for the
value is dependent on the length of the column. So the final same scenario. This shows a reduction in the number of
value of the output memristor, which will store the feature map operations by 18× for one filter. So if 96 filters were used
value, will correspond to the matching bits. In other words, as in AlexNet [38], then a significant reduction with 4 orders
the amount of current produced in each column represents the of magnitude are observed when the proposed architecture is
similarity between the input image patch and feature in the utilized. This is because the filter bank is capable of calculating
filter. the results for N feature maps in parallel.
An example of 2 different filters with two different features
of size 3×3 along with the feature map output is demonstrated
V. C ONCLUSIONS AND F UTURE W ORK
in Fig. 6. The input is a binarized image patch and is converted
to 1 V if the pixel is white and 0 V if it is black. The In this paper, a reconfigurable CAM and a feature extraction
output from the filters will represent how much the input architecture for filter learning have been proposed. The main
resembles the learned features and are stored directly into building block is a memristor-based VR-XNOR gate that is
the accumulative memristor. When the feature learned by followed by an inherent summation which will result in a
the second filter matches the image patch 100%, the memristor percentage reflecting the existence of the matching/similarity
is turned fully ON. While when the learned feature in the first feature. For CNN, the filter is followed by a pooling layer that
filter is different than the one presented in the image patch, downsamples the feature map for a reduction in computational
the conductance is not changed a lot as illustrated in Fig. 7. time. The proposed approach provides a significant area saving
In order to account for the savings in number of operations, and fast computational time as compared to the conventional
let’s assume the following scenario: an input image has a approaches. In the proposed work, we have focused on the
dimension of 249×249, a filter size of size 3×3 with a stride = convolution and pooling parts, as a result a direct comparison

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396 IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 9, NO. 2, JUNE 2019
with other implementation in the literature that use full system
implementations is out of the scope of this paper.
Future work will extend the proposed architecture to build
a full memristor-based BCNN system that implements all
layers. Moreover, the architecture will be expanded to account
for binary weight and ternary input as a trade-off between
complexity and performance. Co-optimization of learning
algorithms as well as Memristor-based in-memory computing
hardware architecture is the key for tackling the accuracy and
performance challenges especially for resource constrained
applications. Besides, implementation of multiple stages for
the reconfigurable CAM for wider data path.
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Yasmin Halawani (S’14) received the B.S. degree in electrical and electronics
engineering from the University of Sharjah (UOS), United Arab Emirates,
in 2012, and the M.S. degree in electrical and electronics engineering from
Khalifa University, United Arab Emirates, in 2014, where she is currently pur-
suing the Ph.D. degree in the area of memristor-based in-memory computing
architectures. Her research project focused on investigating the suitability of
emerging memory technologies, such as Memristor and STT-RAM for low
power applications.
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397
Baker Mohammad (M’04–SM’13) received the
B.S. degree from the University of New Mexico,
Albuquerque, the M.S. degree from Arizona State
University, Tempe, and the Ph.D. degree from The
University of Texas at Austin in 2008, all in ECE. He
was a Senior staff Engineer/Manager at Qualcomm,
Austin, TX, USA, for six years, where he was
engaged in designing high performance and low
power DSP processor used for communication and
multi-media application. Before joining Qualcomm,
he was with the Intel Corporation for 10 years,
where he involved in a wide range of micro-processors design from high
performance, server chips > 100Watt (IA-64), to mobile embedded processor
low power sub 1 watt (xscale). He has over 16 year’s industrial experience
in microprocessor design with emphasis on memory, low power circuit and
physical design. He is currently an Associate Professor of ECE and a Director
of the System-on-Chip Research Center at Khalifa University. His research
interests includes VLSI, power efficient computing, high yield embedded
memory, emerging technology such as memristor, STTRAM, in-memory-
computing, and hardware accelerators for cyber physical system. In addition,
he is engaged in microwatt range computing platform for wearable electronics
and WSN focusing on energy harvesting, power management, and power
conversion including efficient dc/dc and ac/dc convertors.
Muath Abu Lebdeh received the B.Sc. degree in
electrical and electronic engineering and the M.Sc.
degree in electrical and computer engineering from
Khalifa University, in 2015 and 2017, respectively.
He is currently pursuing the Ph.D. degree with the
Computer Engineering Laboratory, Delft University
of Technology. His research interests include CIM
circuits and architectures.
Mahmoud Al-Qutayri (M’86–SM’04) received the
B.Eng. degree from Concordia University, Montreal,
Canada, in 1984, the M.Sc. degree from the Univer-
sity of Manchester, U.K., in 1987, and the Ph.D.
degree from the University of Bath, U.K., in 1992,
all in electrical and electronic engineering. He was
with De Montfort University, U.K., and the Univer-
sity of Bath, U.K. He is currently a Full Professor
with the Department of Electrical and Computer
Engineering and the Associate Dean for Graduate
Studies with the College of Engineering, Khalifa
University, United Arab Emirates. He has authored/coauthored numerous
technical papers in peer-reviewed international journals and conferences. He
also coauthored a book entitled Digital Phase Lock Loops: Architectures and
Applications and edited a book entitled Smart Home Systems. This is in
addition to a number of book chapters and four patents. His current research
interests include embedded systems design and applications, design and test
of mixed-signal integrated circuits, wireless sensor networks, cognitive radio,
and hardware security. His professional service includes membership of the
steering, organizing and technical program committees of many international
conferences, and reviewer for a number of journals.
Said F. Al-Sarawi (S’92–M’96) received the general
certificate in marine radio communication and the
B.Eng. degree (Hons.) in marine electronics and
communication from the Arab Academy for Science
and Technology (AAST), Egypt, in 1987 and 1990,
respectively, and the Ph.D. degree in mixed ana-
log and digital circuit design techniques for smart
wireless systems with special commendation in elec-
trical and electronic engineering and the Graduate
Certificate in Education (Higher Education) from
The University of Adelaide, Australia, in 2003 and
2006, respectively, where he is currently the Director of the Centre for
Biomedical Engineering. His research interests include design techniques for
mixed signal systems in micro- and nano-electronictrons and optoelectronic
technologies for high performance radio transceivers, low power and low
voltage radio frequency identification (RFID) systems, data converters, and
microelectromechanical systems (MEMS) for biomedical applications. He
received the University of Adelaide Alumni Postgraduate Medal (formerly
Culross) for outstanding academic merit at the postgraduate level and the
Commonwealth Postgraduate Research Award (Industry) while pursuing
his Ph.D.