IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO.
4, DECEMBER 2020
Five-Level Transformerless Inverter for
Single-Phase Solar Photovoltaic Applications
Felipe Bovolini Grigoletto , Member, IEEE
Abstract— Transformerless inverters are extensively employed
in grid-connected photovoltaic (PV) generation systems due
to its advantages of achieving low cost and high efficiency.
However, the common-mode voltage issues have been motivated
the proposition of new topologies, control, and modulation
schemes. In common ground PV inverters, the grid neutral line is
directly connected to the negative pole of the dc bus. Therefore,
the parasitic capacitances are bypassed and the leakage current
can be eliminated. In this paper, a five-level common ground
transformerless inverter with reduced output harmonic content
for PV systems is proposed. In addition, the proposed inverter
can process reactive power and it presents a maximum dc-voltage
utilization in opposition to half-bridge-based topologies. The
operation modes of the proposed inverter, a simple modulation
strategy, as well as the design guidelines are analyzed in detail.
Finally, experimental results demonstrate the feasibility and good
performance of the proposed inverter.
Index Terms— Common ground voltage, multilevel inverters,
photovoltaic (PV) systems, transformerless inverters.
I. I NTRODUCTION
I N THE past decades, the concern about climate change
and the rising oil prices have triggered the development of
alternative power sources [1], [2]. Photovoltaic (PV) genera-
tion systems are particularly attractive due to their advantages
such as noiseless operation, relative small size, reliable, and
emission free [3]–[5].
Transformerless inverters became a compact and economic
solution for PV generation systems, but they have to address
inherent troubles associated with safety hazards. The galvanic
connection between the grid and the PV array results on a
resonant circuit [6]–[8]. This circuit consists on PV parasitic
capacitances, filter elements, and grid impedance. In its turn,
parasitic capacitance value depends on many factors such
as PV panel and frame structure, surface of cells, distance
between cells, whether conditions and type of electromagnetic
compatibility filter [9]. If the common-mode voltage generated
by the inverter includes frequencies close to the resonance of
the circuit, a ground current will be excited [6]. Fig. 1 shows
Manuscript received September 1, 2018; revised November 15, 2018;
accepted December 18, 2018. Date of publication January 10, 2019; date
of current version November 5, 2020. This work was supported by the
Instituto Nacional de Ciência e Tecnologia em Geração Distribuída and its
Funding Agencies CNPq under Grant 465640/2014-1, CAPES under Grant
23038.000776/2017-54, and FAPERGS under Grant 17/2551-0000517-1.
Recommended for publication by Associate Editor Kai Sun.
The author is with the Electronic Systems Research Group (GPSEl), Federal
University of Pampa (UNIPAMPA), Alegrete, Rio Grande do Sul (RS), Brazil,
CEP 97546-550 (e-mail: grigoletto@gmail.com).
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JESTPE.2019.2891937
2168-6777 © 2019 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
3411
Fig. 1. Common-mode circuit of a single-phase transformerless inverter [10].
(a) Transformerless Inverter. (b) Common-mode equivalent circuit.
a common-mode equivalent circuit of a generalized trans-
formerless inverter [10], where v cm and v cm−dm are given by
v 1N + v 2N
v cm =
2
L2 − L1
v cm−dm = (v 1N − v 2N ) . (1)
2 (L 1 + L 2 )
Several approaches have been proposed to mitigate the
leakage currents where freewheeling paths were created to
decouple the PV array from the grid at null states at ac
side (Heric) [11] or at dc side H5 [12], and H6 [13]–[15].
Although these topologies present a simple circuit structure,
the common-mode voltage depends on the parasitic parameters
of the leakage current loop, and it can bring an ineffective
leakage current reduction [8], [16].
In half-bridge (HB) topologies, the neutral terminal is
connected directly to the central point of split capacitors;
hence, the high-frequency common-mode voltage is near
to zero [4]. However, the main drawback is the need of
dc-link voltage be twice the grid peak demanding semicon-
ductors with larger voltage capacity. Moreover, neutral point
clamped (NPC)-based inverters present reduced voltage stress
on the semiconductors, lower output harmonic content, and
they can be employed as HB topologies [6], [17].
Several other topologies have been proposed to mitigate
ground currents [4], [18]–[20], such as unfold topologies [21],
[22], T-type [23], [24], flying inductor [25], modified H6 [26],
cascaded [27], CH7 [28], and H8 [29].
Alternatively, modulation techniques [26], [27], [30]–[34]
and control strategies [35] have been proposed to reduce the
common-mode voltages and consequently minimize or elimi-
nate the leakage currents.
The common ground inverter is an interesting topology to
reduce the leakage current [9], [36]–[40]. By connecting the
grid neutral line directly to the negative terminal of the PV
panels, the common-mode voltage is clamped to zero [4].
3412 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 4, DECEMBER 2020
Fig. 2. Single-phase common ground transformerless inverters. (a) Virtual
dc-bus [36]. (b) Common-mode inverter [9]. (c) Charge pump [37].
(d) Common ground type I [38]. (e) Multilevel common ground [2].
A common ground topology called virtual dc bus was pro-
posed in [36]. In this topology, a capacitor provides a virtual
dc bus which supplies the negative output voltages and it
is charged in some operation states. The current stress in
some switches is a relative disadvantage since it can be
limited by means a proper design. A charge-pump circuit
concept was proposed in [37], however, the two-stage charge
transfer process increases the number of power components.
An interesting common ground type inverter was presented
in [38]. It presents reduced switch count and a unipolar
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
Fig. 3. Proposed multilevel common ground topology.
pulsewidth modulation (PWM). In [2], the authors proposed a
multilevel common ground transformerless inverter which dis-
misses switched capacitors. The topology presents a reduced
number of switches; however, it needs larger input voltage
than full-bridge-based topologies. Fig. 2 shows a series of
topologies which employs the common ground concept.
This paper proposes a five-level transformerless for PV
generation systems. The proposed topology has the negative
of PV module connected to the neutral grid potential which is
characteristic of common ground inverters in order to mitigate
leakage currents. Moreover, the proposed converter employs a
flying capacitor leg plus a HB cell and consequently synthe-
sizes a multilevel PWM voltage with reduced harmonic con-
tent. This paper is organized as follows. Section II describes
the proposed topology, its operation modes, the proposed
modulation strategy, the precharge of dc capacitors, and the
common-mode behavior. Section III brings the semiconduc-
tor loss analysis, Section IV presents the design guidelines,
Section V presents a comparison among different topologies,
Section VI presents the simulation and experimental results,
and finally, Section VII presents the conclusion.
II. P ROPOSED T OPOLOGY
A. General Description
The circuit of the proposed inverter is shown in Fig. 3.
It can be seen that the neutral point of the grid is connected
directly to the negative PV array. The output stage employs a
HB cell and a diode similar to the topology proposed in [38].
The main contribution, here, is to aggregate a flying capacitor
leg in order to synthesize a multilevel PWM voltage with
reduced harmonic content. Thus, the transformerless inverter
mitigates the common-mode currents while minimizing the
output harmonic distortion.
The proposed topology employs three capacitors (Cin , C1 ,
and C2 ), six switches (s1 . . . s6 ), and one diode D1 . The
resistor R p and the switch s P compose a precharge circuit
for the capacitors C1 and C2 . In nominal conditions, v Cin =
v dc , v C1 = v dc /2, and v C2 = v dc .
The proposed inverter has eight switching states according
to Fig. 4. Table I shows the switching states represented by
v x , where x = {0A, 0B, 1, 2A, 2B, 3A, 3B, 4}. Each switching
state corresponds to an output voltage level v o synthesized by
the inverter.
GRIGOLETTO: FIVE-LEVEL TRANSFORMERLESS INVERTER FOR SINGLE-PHASE SOLAR PV APPLICATIONS 3413

Fig. 4. Switching states, output voltage, and currents of the proposed inverter. (a) v4 ; v o = v dc . (b) v3A ; v o = v dc /2. (c) v3B ; v o = v dc /2. (d) v0A ; v o = 0.
(e) v0B ; v o = 0. (f) v2A ; v o = −v dc /2. (g) v2B ; v o = −v dc /2. (h) v1 ; v o = −v dc .

TABLE I 2) v3A : The switches s1 , s3 , and s5 are ON and the inverter

I NVERTER S WITCHING S TATES , THE C ORRESPONDING O UTPUT V OLTAGE
L EVELS , AND C APACITOR C URRENTS
B. Switching States Description
The detailed description of each switching state is given in
the following.
1) v4 : The switches s1 , s2 and the diode D1 are ON and
together they form a path to charge the capacitor C2
with the current i ch . The switch s5 is ON and the inverter
synthesizes v o = v dc .
synthesizes v o = v dc /2. In this state, the current through
the capacitor C1 is i o . The diode D1 is reverse biased
since the voltage across it is v D1 = −v C2 −v C1 +v Cin =
−v dc /2.
3) v3B : The switches s2 , s4 , and s5 are ON and the inverter
synthesizes v o = v dc /2. In this state, the current through
the capacitor C1 is −i o . It can be noted that v3A and
v3B are redundant switching states because both states
synthesize the same output voltage v o and it results in
the current i C1 with opposite direction; therefore, they
can be used to regulate the voltage across C1 .
4) v0A : The switches s1 , s2 , s6 and the diode D1 are ON
and the inverter synthesizes v o = 0. The switches s1 , s2
and the diode D1 form a path to charge the capacitor
C2 with the current i ch .
5) v0B : The switches s3 , s4 , and s5 are ON and the output
voltage is v o = 0. The voltage across the capacitors
C1 and C2 are unchanged. The diode D1 is reverse
biased since the voltage across it is v D1 = −v C2 =
−v dc .
6) v2A : The switches s1 , s3 , and s6 are ON and the output
voltage is v o = −v dc /2. The output current i o flows
through the capacitors C1 and C2 .

Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
3414 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 4, DECEMBER 2020

Fig. 5. SV diagram composed by the regions, output voltage levels, switching

vectors, and corresponding active switches.
TABLE II
S WITCHING S EQUENCES A CCORDING TO THE R EGIONS

7) v2B : The switches s2 , s4 , and s6 are ON and the output

voltage is v o = −v dc/2 . The output current i o flows
through the capacitors C1 and C2 . In this switching state,
the output current flows in opposite direction through the
capacitor C1 , compared to the switching state v2A .
8) v1 : The switches s3 , s4 , and s6 are ON and v o = −v dc .
In this switching state, the capacitor C2 supplies the
output voltage, and it turn, the diode D1 reversed biased.
Furthermore, the output current i o flows through the
capacitor C2 .
Basically, an inverter can operate with nonunity power Fig. 6. Switching sequences according to the regions. (a) R1 . (b) R2 .
factor (PF) if it is capable to synthesize simultaneously positive (c) R3 . (d) R4 .
voltage and negative current or vice versa. Thus, all switching
states of the proposed inverter can synthesize both positive up–down carrier. Fig. 6 brings the up-down carrier, the mod-
output current and negative output current as indicated by ulation signals and the drive signals for all operating regions
the dotted lines in Fig. 4. This important feature makes the in one sampling period Ts = 1/ f s .
inverter capable to inject reactive currents into the grid under In order to define the drive signals of the switches s1 . . . s6 ,
low voltage ride through. the corresponding duty cycles have to be derived. Assuming
the sinusoidal output voltage reference v o∗ (t) and the corre-
C. Proposed Modulation Strategy sponding duty cycle d(t) given by
Space vector (SV) modulation approach is adopted in this v o∗ (t) = d(t)v dc
paper since it provides a degree of freedom to select switching
d(t) = Dm sin (ωt) (2)
vectors enabling the reduction of switching losses. Moreover,
the output harmonic distortion is minimized as long as it is where Dm is the modulation index. Suppose that the
used the nearest vectors of the voltage reference. It is important instantaneous voltage reference is on the region R1
to mention that the SV approach presented can be easily (−v dc ≤ v o∗ < −v dc /2). By analyzing Figs. 5 and 6(a), it can
implemented in PWM modulators found in commercial micro- be written the vector dwell times as
controllers. Fig. 5 presents a SV diagram where the switching    v dc   
d(t)v dc −v dc − d1 (t)
states give rise to voltage vectors along the output voltage = 2 (3)
space. The ON-state switches are represented in brackets next 1 1 1 d2 (t)
to the switching vectors. Furthermore, the SV diagram can
where d1 is the normalized dwell time of v1 , and d2 is the
be divided in the four regions R1 , R2 , R3 , and R4 . According
normalized total dwell time of both v2A and v2B , that is d2 =
to a desired voltage reference v o∗ , one region is selected by
d2A +d2B . For the sake of simplicity, in (3), the dwell times are
means a simple algorithm: R1 for −v dc ≤ v o∗ < −v dc /2, R2
normalized by Ts and the voltage amplitudes are normalized
for −v dc /2 ≤ v o∗ < 0, R3 for 0 ≤ v o∗ < v dc /2, and R4 for
by v dc . By solving (3), the dwell times can be expressed as
v dc /2 ≤ v o∗ < v dc , where v o∗ is the output voltage reference.
Once defined the switching vectors, they have to be placed d1 (t) = −2d(t) − 1
in a proper order by means a switching sequence. Table II d2 (t) = 2d(t) + 2. (4)
shows the proposed switching sequences for all regions of
the SV diagram. The modulation strategy is carried out by Note that the redundant vectors and v2A v2B
synthesize the
means the comparison of the signals ds1 , ds2 , ds5 with an same output voltage level, but result in opposite currents

Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
GRIGOLETTO: FIVE-LEVEL TRANSFORMERLESS INVERTER FOR SINGLE-PHASE SOLAR PV APPLICATIONS 3415

TABLE III
D EFINITION OF D UTY C YCLES dS1 , dS2 , AND dS5

Fig. 7. Block diagram of modulation scheme and control of v C1 .

through the capacitor C1 (see Table I). Thus, here, it is

proposed the use of the variable δ in order to distribute
the duty cycles of the redundant switching vectors v2A and
v2B as
d2A (t) = δd2 (t)
d2B (t) = (1 − δ)d2 (t). (5)
By substituting (4) in (5) and according to Fig. 6(a), the duty
cycles of the switches s1 , s2 , and s5 are, respectively,
ds1 (t) = d2A (t) = 2δ(1 + d(t))
ds2 (t) = d1 + d2A (t) = 2d(t)(δ − 1) + 2δ − 1
ds5 (t) = 0. (6)
The duty cycles ds1, ds2 , and ds5 for the regions R1 , R2 , R3 ,
and R4 are derived in a similar way and they are presented
in Table III. Furthermore, the switches s3 , s4 , and s6 are driven
with the complement of s2 , s1 , and s5 , respectively, that is:
s̄3 = s2 , s̄4 = s1 , and s̄6 = s5 . It can be seen from Table III and
Fig. 8 that the switches s1 . . . s4 operate at switching frequency Fig. 8. Output voltage v o , output current io , capacitor voltage v C2 , and duty
cycles: ds1 , ds2 , and ds5 .
f s while s5 and s6 operate at fundamental frequency f 1 .
Note that when δ = 0.5, the modulation strategy ensures
null average current i C1 over a switching period Ts . Ideally,
if the initial capacitor voltage v C1 is equal to v dc /2, this
condition would remain during the entire inverter operation.
However, in practice, the nonidealities can make the capacitor
voltage drift slowly from their nominal value. As result,
some compensation for the voltage imbalances must be
considered. Fig. 9. Equivalent circuits of the two steps for precharge of the dc capacitors.
In order to keep the voltage v C1 equals v dc /2, (a) v2A . (b) v4 .
a proportional-integral (PI) controller, here, is adopted, where
the control output acts over δ. Fig. 7 shows the complete dia- initial conditions v C1 = 0, v C2 = 0, and v Cin is equal to
gram block of the modulation technique for switching signals the open-circuit of PV string. Initially, the switch s p shown
generation, demonstrating its implementation simplicity. in Fig. 3 is open and the state v2A is applied. Note that
D1 is forward biased and both capacitors C1 and C2 are
D. Precharge of the Capacitors C1 and C2 connected in series with the input dc voltage and the resistor
In order to limit the semiconductor current at start of R p , as shown in Fig. 9(a). However, v C1 assumes greater
the normal inverter operation, a precharge process should voltage than v C2 due to the capacitance difference (C2 > C1 ).
ensure v C1 ≈ v dc /2 and v C2 ≈ v dc . Let us assume that in Consequently, when v C1 reaches its nominal value, the state

Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
3416 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 4, DECEMBER 2020

A. Conduction Losses on Semiconductor Devices

The conduction losses in the power switch y for y =
{1, 2 . . . 6} can be represented as

1 T
Pon_sy = |Von dsy (t)i o (t)|dt (8)
T 0
where i o is the sinusoidal output current given by
Fig. 10. Common-mode circuit of proposed transformerless inverter. i o = Im sin(ωt). (9)
By adopting the duty cycles given in Table III and consid-
v4 is applied and only the capacitor C2 is charged until to ering δ = 0.5 for steady state, the conduction losses for the
reach the input voltage. Fig. 9(b) shows the equivalent circuit switch s1 can be stated as
for this state. At end of the precharge process, the switch s P  T  T 
is closed bypassing R p and the inverter can start the normal Von 2
Pon_s1 = |d(t)i o (t)|dt + |(1+d(t))i o(t)|dt . (10)
operation. T 0 T
2

By substituting (2) and (9) in (10), it can be written

 T 
E. Common-Mode Behavior Von Im 2
Pon_s1 = |Dm sin (ωt)|dt
2
The common-mode circuit of the proposed topology is T 0
obtained by analyzing the generalized inverter model of Fig. 1.  
Von Im T
The proposed topology has the negative PV terminal connected +···+ |(sin(ωt) + Dm sin (ωt))|dt .
2
directly to the grid neutral point resulting in v 2N = 0. T T
2
Furthermore, there is only one output inductor meaning that
L 2 = 0 as shown in Fig. 10. The parasitic capacitances are (11)
short-circuited between the ac and dc grounds by assuming By solving (11) results in
low ground impedance Z G [38]. Im Von
Therefore, taking into account above considerations, and Pon_s1 = . (12)
π
substituting v 2N = 0 and L 2 = 0 in (1), the total common
voltage v tcm synthesized by the inverter is The conduction losses of the other switches of the proposed
inverter can be derived in a similar way.
As stated earlier, some switching states discharges the
v tcm = v cm + v cm−dm
v 1N v 1N capacitor C2 . On the other hand, in other switching states,
v tcm = − = 0. (7) the charging of the capacitor C2 causes some extra current i ch
2 2
on the power semiconductors s1 , s2 , and D1 . Therefore, this
From (7), it is evident that the inverter generates a constant charging process results in extra conduction losses Pext , which
null common-mode voltage. Once v tcm does not exhibit any have to be addressed. As demonstrated in [36], the average
high-frequency component, the inverter practically ensures the losses in a power switch (or diode) are proportional to the
absence of ground current. charge transported by it, that is
It is important to mention that thin-film solar panel suffers T
Von 0 |i on (t)|dt Von Q ext
from the corrosion damage when the voltage of the negative Pext = = . (13)
terminal of the solar module is lower than that of the ground. T T
This process can cause substantial power loss and can result Once the voltage across C2 keeps in balance over a grid
in reduced PV module lifetime [39]. Therefore, the proposed cycle, the extra charge Q ext is equal to the charge taken away
topology can be a good solution to this trouble, since the from C2 by i o , that is,
negative of PV panel is grounded.  t4  t3  T
Q ext = |i o (t)|dt + |d2 (t)i o (t)|dt + |d2 (t)i o (t)|dt. (14)
T
t3 2 t4

III. S EMICONDUCTOR L OSSES The instant t1 corresponds to the transition between the regions
R3 and R4 , as illustrated in Fig. 8. Therefore, this transition
This section gives a description of conduction and switching occurs when the instantaneous value of d(t) is 0.5, so it can
losses in the semiconductors. For the conduction loss analysis, be written
the ripple current is disregarded. Furthermore, for bipolar
Dm sin (ωt1 ) = 0.5 ⇒ t1 = sin−1 (0.5/Dm )/ω. (15)
devices such as insulated gate bipolar transistor and diode,
the conduction voltage drop Von is not significantly affected Due to the quarter-wave symmetry, the instants t3 and t4 can
by the conduction current and, therefore, can be considered be derived as
constant [36]. Moreover, the charging process of C2 results
in extra semiconductor losses, which will be addressed in this t3 = T /2 + t1
section. t4 = T − t1 . (16)

Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
GRIGOLETTO: FIVE-LEVEL TRANSFORMERLESS INVERTER FOR SINGLE-PHASE SOLAR PV APPLICATIONS 3417

By substituting (16) in (14) results Furthermore, let us assume the region R1 as the interval of
   significant discharge of the capacitor C2 . Therefore, according
T −t1 T
2 +t1
Q ext = Im | sin(ωt)|dt + 4Dm | sin2 (ωt)|dt . to Fig. 8, the voltage across C2 at the beginning of the
T
2 +t1 T
2 region R1 is v C2(t 3) and at the end of region R1 is v C2(t 4).
(17) In this way, it can be written
 t4
By solving (17) and substituting it in (13), Pext is derived 1
i C2 (t) = v C2(t 3) − v C2(t 4) ≈ 2v C2 . (26)
and can be expressed as C 2 t3
Im Von For the region R1 , i C2 = i o so by substituting (25) in (26) and
Pext =K1 (18)
π solving the integral, the capacitance C2 is
where K 1 for 0.5 < Dm <= 1 is Po T 1
 C2 = 4− . (27)
−1 0.5 3 1 2πv dc v C2 Dm Dm2
K 1 = Dm sin + 4− 2 (19)
Dm 4 Dm It can be noted that the capacitance C2 is directly proportional
and K 1 for Dm < 0.5 is to the output power, fundamental period, and modulation
 index, and inversely proportional to the voltage ripple. On the
0.5
K 1 = Dm sin−1 . (20) other hand, a small value of C1 is required since its charge
Dm can be kept constant over a sampling period Ts in steady-state
The total conduction losses of the switch s1 including Pext is operation.
Im Von
Pon_s1t = (1 + K 1 ) . (21) B. Voltage and Current Stress on Semiconductors
π
This section will give the guidelines to define the voltage
It is important to point out that (18) represents the additional
and current stress on the semiconductors. The switches s1 ,
losses for the switches s1 and s2 while the conduction losses
s2 , s3 , and s4 form a flying capacitor cell and the maxi-
of the diode D1 can be written as
mum voltage on each semiconductor is v C1 or (v Cin − v C1 )
Im VF according to the switching states shown in Fig. 4. Therefore,
Pext,d = K1 (22)
π the maximum voltage on each of them is v dc /2. On the other
where VF is the forward voltage of the diode. Finally, the total hand, the switches s5 and s6 form a HB cell and they can
conduction semiconductor losses of the proposed inverter can be submitted to v C2 . Thus, the maximum voltage on the
be expressed as semiconductors s5 and s6 is v dc . Finally, by analyzing Fig. 4,
   it can be noted that the diode D1 is reversed biased by v C2 in
2Im Von VF
Pon_t = 3+ + 1 K1 . (23) the states v0B and v1 , therefore, its maximum blocking voltage
π 2Von
is v dc . Thus, (28) and (30) summarize the voltage stress on
B. Switching Losses the semiconductor devices
v dc
The switches s1 . . . s4 and the diode D1 operate at carrier v s1,max = v s2,max = v s3,max = v s4,max = (28)
2
frequency while s5 and s6 operate at fundamental frequency. v s5,max = v s6,max = v D1,max = v dc . (29)
Thus, the switching loss is giving by
Common ground inverters which employ switched capac-
Psw = ∝ f sw Vsw(E ON + E OFF ) itors present additional current stress on the semiconductors
during the charge of the capacitor. In order to charge the
PD = ∝ f sw Vsw E rec (24)
capacitor C2 , the semiconductors are s1 , s2 , and D1 conduct
where f sw = fs for s1 . . . s4 and D1 , while f sw = f1 for s5 the additional current i ch , as shown in Fig. 4(a) and (d). The
and s6 . Vsw is the voltage across the semiconductors, E rec is maximum value of the current depends on the capacitance
the recovery energy of the diode, E ON and E OFF are the energy and resistance of the path. Note in Fig. 8 that i s1 presents
loss during ON and OFF transitions, respectively. the maximum value at start of the region R2 at t4 when the
switching state v0A is applied. Therefore, at t4 , from the path
IV. D ESIGN G UIDELINES of devices shown in Fig. 4(d) it can be written
A. Dimensioning of the Capacitor C2 −v Cin (t4) + i ch,max R + v C2 (t4) = 0 (30)
The operation of the proposed inverter depends on the
where
design of the capacitor C2 . In its turn, the capacitor C2
provides output energy during the region R1 resulting in R = Ron,s1 + Ron,s2 + Ron,D1 + ESR (31)
voltage oscillation at fundamental frequency, as seen in Fig. 8.
and ESR is the equivalent series resistance of capacitors Cin
Considering a unit PF operation, the output current i o can
and C2 . It is reasonable to assume that v Cin (t4 ) − v C2 (t4 ) ≈
be written as function of dc-bus voltage and the output power
2v C2 . Therefore, the maximum current can be defined as
Po as
2Po Po T 1
i o (t) = sin(ωt). (25) i ch,max ≈ 4− . (32)
v dc Dm πC2 v dc Dm R Dm2

Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
3418 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 4, DECEMBER 2020
C OMPARISON OF D IFFERENT T OPOLOGIES
Finally, the current stress on the devices is defined as
i s1,max = i s2,max = i D1,max = i ch,max + Im .
On the other hand, the devices s3 , s4 , s5 , and s6 are submitted
to the maximum output current Iom , that is
i s3,max = i s4,max = i s5,max = i s6,max = Im .
V. C OMPARISON W ITH D IFFERENT T OPOLOGIES
This section presents a comparison among several topolo-
gies in terms of number of active and passive elements, number
of levels, dc-link voltage, reported efficiency (η), and leakage
current. Here, the rms value of leakage current is considered
low when it is below 120 mA, whereas it is considered very
low when the leakage current is below 10 mA.
As given in Table IV, the proposed inverter has more
elements when compared with the other topologies, however,
it presents advantages over them: 1) when compared to T-Type
[24], the proposed topology has superior performance in terms
of leakage currents; 2) when compared to the multilevel
inverter [2], the proposed topology needs lower input dc volt-
age for the same output ac voltage; 3) when compared to NPC
HB topologies [6], the proposed topology needs lower input dc
voltages, it presents more output levels and exhibits superior
performance in terms of leakage current; 4) when compared
to the topologies [36], [38], the proposed topology presents
more voltage levels, and finally; and 5) when compared to
the topologies [11], [12], [14], the proposed topology presents
more voltage levels and superior performance in terms of
leakage currents.
The common ground topology proposed in [9] presents the
lowest number of switches, however, its bipolar PWM results
in higher output distortion. This fact leads to larger output
filters or higher switching frequencies to improve the harmonic
content.
In terms of reported efficiency, all topologies present values
above 95%, which is expected for transformers inverters. How-
ever, it is important to note that experimental setups reported in
the literature employ distinct semiconductor technologies and
different switching frequencies. Hence, these unequal aspects
can lead to an unfair comparison in terms of efficiency.
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
TABLE IV
(33)
(34)
Fig. 11. Prototype of the proposed inverter.
VI. S IMULATION AND E XPERIMENTAL R ESULTS
Simulation and experimental results have been carried
out to validate the operation of the proposed inverter.
A 1.2-kW-prototype was built and its parameters are given
in Table V. The controller board DS1103 from dSPACE
was employed to perform the control and to generate the
PWM pulses for the inverter. Fig. 11 shows a picture of the
experimental inverter.
The precharge of capacitors C1 and C2 is performed as
described in Section II-D where the value of precharge resis-
tance is R p = 7 . Initially, C1 and C2 are completely
discharged and v Cin is equal to 420 V, which corresponds
to the open-circuit voltage of input PV string. At start of
simulation presented in Fig. 12, s p is closed and the state v2A
is applied. After 10 ms, the capacitor C1 reaches its approx-
imated nominal voltage value, thus, the state v4 is applied.
Finally, C2 reaches its nominal value in less than 300 ms.
It can be seen that during the precharge process, the input
voltage v Cin decreases due to current source characteristic of
PV generation and the limited capacitance Cin . The precharge
dynamics depend on the characteristic of PV source, capaci-
tances, precharge resistance, and solar irradiation. On the other
hand, the transition between v2A and v4 can be determined by
a simple algorithm since v C1 is measured by the control unit.
GRIGOLETTO: FIVE-LEVEL TRANSFORMERLESS INVERTER FOR SINGLE-PHASE SOLAR PV APPLICATIONS
TABLE V
P ROTOTYPE PARAMETERS
Fig. 12. Results for precharge process of capacitors C1 and C2 .
Fig. 13. Block diagram of the current controller in grid-connected operation.
A grid-connected PV inverter has to process both active
power and reactive power as required by some standards
and grid codes. For example, according to EN 50 438,
a microinverter shall operate with PF between 0.95 lead and
0.95 lag [41].
In order to connect an inverter to the grid, it is necessary
a current controller. Generally, current controllers employ
proportional-resonant action in stationary frames or PI action
in synchronous frames. Here, a simplified current control
scheme was adopted to the inverter grid connection [42]. The
controller is performed in synchronous frames and it demands
a phase lock loop as shown in Fig. 13.
The active and reactive power grid capacity was verified
by simulations results. For this purpose, it was employed
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
3419
Fig. 14. Simulation results for grid-connected inverter operating with unity,
leading, and lagging PF.
Fig. 15. Experimental results for unity PF operation: output current io
(10 A/div), ac output voltage v o f (200 V/div), PWM output voltage v o
(200 V/div), capacitor voltage v C2 (200 V/div), and time scale (5 ms/div).
a PV string with the following characteristics: open voltage
of 420 V, short current of 5 A, rate of maximum power
of 1.2 kW with solar irradiance equals 1000 W/m2 .
Fig. 14 shows the results from the grid-connected inverter,
where a reference current with amplitude of 8 A was defined
for the operation with unity PF (0–34 ms), 0.55 leading PF
(34–68 ms), and 0.55 lagging PF (68–102 ms). This result
demonstrates the leading and lagging inverter operation as
well as the good dynamic performance during the transition
between the power operation modes.
In order to show the inverter operation with unity PF by
means the experimental setup, the output of the inverter was
connected to a resistive load (R = 35 ). Fig. 15 shows the
output current, the output voltage in phase as expected.
3420 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 4, DECEMBER 2020

Fig. 16. Experimental results for lagging PF operation: output current Fig. 18. Transient in modulation index from 0.4 to 0.9 showing the output
io (10 A/div), PWM output voltage v o (200 V/div), capacitor voltage v C2 current io (5 A/div), PWM output voltage v o (200 V/div), capacitor voltage
v Cin (500 V/div), v C1 (100 V/div), and time scale (10 ms/div).
(200 V/div), and time scale (5 ms/div).

Fig. 19. Main waveforms during a transient in the capacitor voltage: output
Fig. 17. Voltage across the switches and the diode: v s1 (200 V/div), v s5 current io (5 A/div), PWM output voltage v o (200 V/div), capacitor voltage
(500 V/div), v D1 (200 V/div), PWM output voltage v o (500 V/div), and time v C2 (500 V/div), v C1 (100 V/div), and time scale (50 ms/div).
scale (2 ms/div).

The capacity of reactive power processing was experimen-

tally tested by connecting an RL load at the output with cos
(ϕ) = 0.68, where R = 35  and L = 100 mH. Fig. 16
shows the experimental results for reactive power processing.
The leakage current of the inverter for both load conditions
was ≈0 mA.
In order to explore the different operation points in the
linear range of the inverter, it was applied a transient in
the modulation index from 0.4 to 0.9. Fig. 18 shows the
waveforms for this transient while the inverter feeds a resistive
load with half-nominal power. Fig. 20. Measured efficiency of the proposed inverter.
Fig. 17 shows the voltage stress across the switches and the
diode. The maximum voltage across the switches s1 . . . s4 is a restores the voltage capacitor to its nominal value v dc /2, which
half of v dc , 175 V, whereas the maximum voltage across the corresponds to 175 V, in less than 100 ms. Note that when v C1
switch s5 and the diode D1 is v dc , 350 V. It is important to is different from its nominal value, the output variables v o and
point out that some multilevel topologies brings the benefits i o present harmonic distortion, however, when v C1 reaches the
of asymmetrical approach, where the high-frequency switches nominal value, there is no harmonic distortion in the output
block lower voltages, while the low-frequency switches block variables.
higher voltages. The efficiency of the inverter was measured with a preci-
Fig. 19 shows the experimental results with the capacitor sion power analyzer Yokogawa WT3000. Fig. 20 shows the
voltage v C1 starting from 125 V. The proposed controller efficiency as function of load where the highest efficiency

Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
GRIGOLETTO: FIVE-LEVEL TRANSFORMERLESS INVERTER FOR SINGLE-PHASE SOLAR PV APPLICATIONS
achieved is 96.6%. The European efficiency value was approx-
imately 95.88%.
It is important to highlight that several high-efficiency
transformerless inverters employing different semiconductor
technologies have been proposed in the literature. However,
a tradeoff between efficiency and semiconductor cost has been
made. For instance, SiC devices result in superior efficiency
but at higher costs. On the other hand, the experimental
prototype presented in this paper employs mature semicon-
ductor technology because the major objective is to attest the
operation performance and do not to reach very high efficiency.
The total harmonic distortion of the output current i o at
nominal conditions is about 3.5%. For the same circumstances,
a three-level PWM (or unipolar) results in 5.6% and a two-
level PWM (or bipolar) results in 19%. This comparison
exhibits the good performance of the proposed inverter in
terms of output harmonic content. Moreover, the dc output
current is below 1%, which is in accordance with the IEC
61727:2004 standard.
VII. C ONCLUSION
This paper has proposed a five-level single-phase trans-
formerless inverter. The inverter provides the connection of
the grid neutral point with the negative point of the PV stack,
so the resulting leakage current is close to zero. Moreover,
a modulation strategy has been proposed to keep balanced the
voltage over the capacitors and it can be easily implemented
with usual PWM modulators. The five-level operation results
in a superior performance in terms of harmonic distortion
allowing filter reduction when compared to inverters with
fewer number of levels. Finally, the good performance of
the inverter was demonstrated by a 1.2-kW experimental
prototype.
R EFERENCES
[1] M. Islam, S. Mekhilef, and M. Hasan, “Single phase transformerless
inverter topologies for grid-tied photovoltaic system: A review,”
Renew. Sustain. Energy Rev., vol. 45, pp. 69–86, May 2015.
[Online]. Available: http://www.sciencedirect.com/science/article/
pii/S1364032115000192
[2] A. Kadam and A. Shukla, “A multilevel transformerless inverter employ-
ing ground connection between PV negative terminal and grid neutral
point,” IEEE Trans. Ind. Electron., vol. 64, no. 11, pp. 8897–8907,
Nov. 2017.
[3] E. Romero-Cadaval, G. Spagnuolo, L. G. Franquelo, C. A. Ramos-Paja,
T. Suntio, and W. M. Xiao, “Grid-connected photovoltaic generation
plants: Components and operation,” IEEE Ind. Electron. Mag., vol. 7,
no. 3, pp. 6–20, Sep. 2013.
[4] W. Li, Y. Gu, H. Luo, W. Cui, X. He, and C. Xia, “Topology review
and derivation methodology of single-phase transformerless photovoltaic
inverters for leakage current suppression,” IEEE Trans. Ind. Electron.,
vol. 62, no. 7, pp. 4537–4551, Jul. 2015.
[5] T. K. S. Freddy, N. A. Rahim, W.-P. Hew, and H. S. Che, “Compar-
ison and analysis of single-phase transformerless grid-connected PV
inverters,” IEEE Trans. Power Electron., vol. 29, no. 10, pp. 5358–5369,
Oct. 2014.
[6] R. González, E. Gubía, J. López, and L. Marroyo, “Transformerless
single-phase multilevel-based photovoltaic inverter,” IEEE Trans. Ind.
Electron., vol. 55, no. 7, pp. 2694–2702, Jul. 2008.
[7] Ó. López et al., “Eliminating ground current in a transformerless
photovoltaic application,” IEEE Trans. Energy Convers., vol. 25, no. 1,
pp. 140–147, Mar. 2010.
[8] L. Zhang, K. Sun, L. Feng, H. Wu, and Y. Xing, “A family of neutral
point clamped full-bridge topologies for transformerless photovoltaic
grid-tied inverters,” IEEE Trans. Power Electron., vol. 28, no. 2,
pp. 730–739, Feb. 2013.
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
3421
[9] N. Vázquez, M. Rosas, C. Hernándezand, E. Vázquez, and
F. J. Perez-Pinal, “A new common-mode transformerless photovoltaic
inverter,” IEEE Trans. Ind. Electron., vol. 62, no. 10, pp. 6381–6391,
Oct. 2015.
[10] H. Xiao and S. Xie, “Leakage current analytical model and application
in single-phase transformerless photovoltaic grid-connected inverter,”
IEEE Trans. Electromagn. Compat., vol. 52, no. 4, pp. 902–913,
Nov. 2010.
[11] H. Schmidt, C. Siedle, and J. Ketterer, “DC/AC converter to convert
direct electric voltage into alternating voltage or into alternating current,”
U.S. Patent 7 046 534 B2, May 16, 2006.
[12] M. V. Niestetal, F. G. Kaufungen, A. S. Bremicker, and U. Hubler,
“Method of converting a direct current voltage from a source of direct
current voltage,” U.S. Patent 7 411 802 B2, Aug. 12, 2008.
[13] J. C. Calahorra, R. G. Senosiain, J. L. Taberna, L. M. Palomo, and
P. S. Gurpide, “Single-phase inverter circuit for conditioning
and converting DC electrical energy into AC electrical energy,”
U.S. Patent 2 053 730 A1, Apr. 29, 2009.
[14] L. Zhang, K. Sun, Y. Xing, and M. Xing, “H6 transformerless full-
bridge PV grid-tied inverters,” IEEE Trans. Power Electron., vol. 29,
no. 3, pp. 1229–1238, Mar. 2014.
[15] W. Yu, J.-S. Lai, H. Qian, and C. Hutchens, “High-efficiency MOSFET
inverter with H6-type configuration for photovoltaic nonisolated AC-
module applications,” IEEE Trans. Power Electron., vol. 26, no. 4,
pp. 1253–1260, Apr. 2011.
[16] H. Xiao, S. Xie, Y. Chen, and R. Huang, “An optimized transformer-
less photovoltaic grid-connected inverter,” IEEE Trans. Ind. Electron.,
vol. 58, no. 5, pp. 1887–1895, May 2011.
[17] H. Xiao and S. Xie, “Transformerless split-inductor neutral point
clamped three-level PV grid-connected inverter,” IEEE Trans. Power
Electron., vol. 27, no. 4, pp. 1799–1808, Apr. 2012.
[18] Q.-C. Zhong, W.-L. Ming, W. Sheng, and Y. Zhao, “Beijing converters:
Bridge converters with a capacitor added to reduce leakage currents,
DC-bus voltage ripples, and total capacitance required,” IEEE Trans.
Ind. Electron., vol. 64, no. 1, pp. 325–335, Jan. 2017.
[19] Y. Tang, W. Yao, P. C. Loh, and F. Blaabjerg, “Highly reliable
transformerless photovoltaic inverters with leakage current and pulsat-
ing power elimination,” IEEE Trans. Ind. Electron., vol. 63, no. 2,
pp. 1016–1026, Feb. 2016.
[20] K. Kim, H. Cha, and H.-G. Kim, “A new single-phase switched-coupled-
inductor DC-AC inverter for photovoltaic systems,” IEEE Trans. Power
Electron., vol. 32, no. 7, pp. 5016–5022, Jul. 2017.
[21] S. Saha and V. P. Sundarsingh, “Novel grid-connected photovoltaic
inverter,” IEE Proc.-Gener., Transmiss. Distrib., vol. 143, no. 2,
pp. 219–224, Mar. 1996.
[22] B. S. Prasad, S. Jain, and V. Agarwal, “Universal single-stage grid-
connected inverter,” IEEE Trans. Energy Convers., vol. 23, no. 1,
pp. 128–137, Mar. 2008.
[23] Y. Wang, W. W. Shi, N. Xie, and C. M. Wang, “Diode-free T-type three-
level neutral-point-clamped inverter for low-voltage renewable energy
system,” IEEE Trans. Ind. Electron., vol. 61, no. 11, pp. 6168–6174,
Nov. 2014.
[24] G. E. Valderrama, G. V. Guzman, E. I. Pool-Mazún,
P. R. Martinez-Rodriguez, M. J. Lopez-Sanchez, and J. M. S. Zuñiga,
“A single-phase asymmetrical T-type five-level transformerless PV
inverter,” IEEE Trans. Emerg. Sel. Topics Power Electron., vol. 6, no. 1,
pp. 140–150, Mar. 2018.
[25] M. T. Azary, M. Sabahi, E. Babaei, and F. A. A. Meinagh, “Modified
single-phase single-stage grid-tied flying inductor inverter with MPPT
and suppressed leakage current,” IEEE Trans. Ind. Electron., vol. 65,
no. 1, pp. 221–231, Jan. 2018.
[26] B. Ji, J. Wang, and J. Zhao, “High-efficiency single-phase transformer-
less PV H6 inverter with hybrid modulation method,” IEEE Trans. Ind.
Electron., vol. 60, no. 5, pp. 2104–2115, May 2013.
[27] X. Guo and X. Jia, “Hardware-based cascaded topology and modu-
lation strategy with leakage current reduction for transformerless PV
systems,” IEEE Trans. Ind. Electron., vol. 63, no. 12, pp. 7823–7832,
Dec. 2016.
[28] X. Guo, “Three-phase CH7 inverter with a new space vector modu-
lation to reduce leakage current for transformerless photovoltaic sys-
tems,” IEEE J. Emerg. Sel. Topics Power Electron., vol. 5, no. 2,
pp. 708–712, Jun. 2017.
[29] R. Rahimi, S. Farhangi, B. Farhangi, G. R. Moradi, E. Afshari, and
F. Blaabjerg, “H8 inverter to reduce leakage current in transformerless
three-phase grid-connected photovoltaic systems,” IEEE Trans. Emerg.
Sel. Topics Power Electron, vol. 6, no. 2, pp. 910–918, Jun. 2018.
3422 IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN POWER ELECTRONICS, VOL. 8, NO. 4, DECEMBER 2020
[30] H. F. Xiao, K. Lan, and L. Zhang, “A quasi-unipolar SPWM full-bridge
transformerless PV grid-connected inverter with constant common-mode
voltage,” IEEE Trans. Power Electron., vol. 30, no. 6, pp. 3122–3132,
Jun. 2015.
[31] R. Selvamuthukumaran, A. Garg, and R. Gupta, “Hybrid multicarrier
modulation to reduce leakage current in a transformerless cascaded mul-
tilevel inverter for photovoltaic systems,” IEEE Trans. Power Electron.,
vol. 30, no. 4, pp. 1779–1783, Apr. 2015.
[32] X. Guo, M. C. Cavalcanti, A. M. Farias, and J. M. Guerrero, “Single-
carrier modulation for neutral-point-clamped inverters in three-phase
transformerless photovoltaic systems,” IEEE Trans. Power Electron.,
vol. 28, no. 6, pp. 2635–2637, Jun. 2013.
[33] X. Guo, R. He, J. Jian, Z. Lu, X. Sun, and J. M. Guerrero, “Leakage cur-
rent elimination of four-leg inverter for transformerless three-phase PV
systems,” IEEE Trans. Power Electron., vol. 31, no. 3, pp. 1841–1846,
Mar. 2016.
[34] D. Barater, G. Buticchi, A. S. Crinto, G. Franceschini, and E. Lorenzani,
“Unipolar PWM strategy for transformerless PV grid-connected con-
verters,” IEEE Trans. Energy Convers., vol. 27, no. 4, pp. 835–843,
Dec. 2012.
[35] J. C. Giacomini, L. Michels, H. Pinheiro, and C. Rech, “Active damping
scheme for leakage current reduction in transformerless three-phase grid-
connected PV inverters,” IEEE Trans. Power Electron., vol. 33, no. 5,
pp. 3988–3999, May 2018.
[36] Y. Gu, W. Li, Y. Zhao, B. Yang, C. Li, and X. He, “Transformerless
inverter with virtual DC bus concept for cost-effective grid-connected
PV power systems,” IEEE Trans. Power Electron., vol. 28, no. 2,
pp. 793–805, Feb. 2013.
[37] J.-F. Ardashir, M. Sabahi, S. H. Hosseini, F. Blaabjerg, E. Babaei, and
G. B. Gharehpetian, “A single-phase transformerless inverter with charge
pump circuit concept for grid-tied PV applications,” IEEE Trans. Ind.
Electron., vol. 64, no. 7, pp. 5403–5415, Jun. 2017.
Authorized licensed use limited to: National Institute of Technology Patna. Downloaded on March 14,2022 at 04:03:56 UTC from IEEE Xplore. Restrictions apply.
[38] Y. P. Siwakoti and F. Blaabjerg, “Common-ground-type transformerless
inverters for single-phase solar photovoltaic systems,” IEEE Trans. Ind.
Electron., vol. 65, no. 3, pp. 2100–2111, Mar. 2018.
[39] J.-M. Shen, H.-L. Jou, and J.-C. Wu, “Novel transformerless grid-
connected power converter with negative grounding for photovoltaic
generation system,” IEEE Trans. Power Electron., vol. 27, no. 4,
pp. 1818–1829, Apr. 2012.
[40] N. Vázquez, J. Vázquez, J. Váquero, C. Hernández, E. Vázquez, and
R. Osorio, “Integrating two stages as a common-mode transformerless
photovoltaic converter,” IEEE Trans. Ind. Electron., vol. 64, no. 9,
pp. 7498–7507, Sep. 2017.
[41] B. I. Crǎciun, T. Kerekes, D. Séra, and R. Teodorescu, “Overview of
recent grid codes for PV power integration,” in Proc. 13th Int. Conf.
Optim. Elect. Electron. Equip. (OPTIM), May 2012, pp. 959–965.
[42] U. A. Miranda, L. G. B. Rolim, and M. Aredes, “A DQ synchronous
reference frame current control for single-phase converters,” in Proc.
IEEE 36th Power Electron. Spec. Conf., Jun. 2005, pp. 1377–1381.
Felipe Bovolini Grigoletto (S’13–M’14) was born
in Restinga Sêca, Brazil, in 1985. He received
the B.Sc., M.Sc., and D.Sc. degrees in electrical
engineering from the Federal University of Santa
Maria, Santa Maria, Brazil, in 2007, 2009, and 2013,
respectively.
He is currently a Professor with the Federal
University of Pampa, Alegrete, Brazil. His current
research interests include renewable energy conver-
sion systems, grid-connected converters, and modu-
lation strategies for multilevel converters.
Dr. Grigoletto is a member of the IEEE Industrial Electronics Society.