9742 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 68, NO.

10, OCTOBER 2021

A Common Grounded Type Dual-Mode

Five-Level Transformerless Inverter
for Photovoltaic Applications
Md Noman Habib Khan , Student Member, IEEE, Yam P. Siwakoti , Senior Member, IEEE,
Mark J. Scott, Member, IEEE, Li Li , Member, IEEE, Shakil Ahamed Khan , Member, IEEE,
Dylan Dah-Chuan Lu , Senior Member, IEEE, Reza Barzegarkhoo , Student Member, IEEE,
Franciszek Sidorski , Student Member, IEEE, Frede Blaabjerg , Fellow, IEEE,
and Saad Ul Hasan , Member, IEEE

Abstract—This article presents a novel dual-mode five- I. INTRODUCTION

level common grounded type (5L-DM-CGT) transformerless
inverter topology for a medium-power application with a
wide input voltage range (200–400 V). It consists of nine
semiconductor switches, two inner flying-capacitors, and a
small LC filter at the output side. Due to the direct connec-
tion of the negative terminal of the photovoltaic to the neu-
tral point of the grid, there is no leakage current in the 5L-
DM-CGT. Depending on the magnitude of the input voltage,
the converter can operate in both buck and boost mode
to produce the same ac output voltage. The theoretical
analysis shows the advantages of the dual-mode inverter
for various industrial applications. Finally, the laboratory
test results are presented to verify the theoretical analysis.
Measurement results show that the proposed inverter rated
at 1 kW has around 97±1% efficiency over a wide range
of load with a peak efficiency of 98.96% at 130 VA in buck
mode and peak efficiency of 99% at 122 VA in boost mode.
Index Terms—Common ground, leakage current, multi-
level inverter, photovoltaic (PV) system.
Manuscript received April 29, 2020; revised July 23, 2020 and August
19, 2020; accepted September 16, 2020. Date of publication October 9,
2020; date of current version June 28, 2021. (Corresponding author: Md
Noman Habib Khan.)
Md Noman Habib Khan, Yam P. Siwakoti, Li Li, Shakil Ahamed
Khan, Dylan Dah-Chuan Lu, Reza Barzegarkhoo, and Saad Ul Hasan
are with the Faculty of Engineering and Information Technology,
University of Technology Sydney, Sydney, NSW 2007, Australia (e-mail:
mdnomanhabib.khan@student.uts.edu.au; yam.siwakoti@uts.edu.au;
li.li@uts.edu.au; shakil.khan@uts.edu.au; dylan.lu@uts.edu.au;
barzegar_sina@yahoo.com.au; saad.hasan@uts.edu.au).
Mark J. Scott is with the Department of Electrical and Com-
puter Engineering, Miami University, Oxford, OH 45056 USA (e-mail:
scottmj3@miamioh.edu).
Franciszek Sidorski is with the Faculty of Environmental Engineering
and Energy, Poznan University of Technology, 60-965 Poznan, Poland
(e-mail: franciszek.d.sidorski@doctorate.put.poznan.pl).
Frede Blaabjerg is with the Department of Energy Technology, Aal-
borg University, 9220 Aalborg, Denmark (e-mail: fbl@et.aau.dk).
Color versions of one or more of the figures in this article are available
online at https://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2020.3028810
URING the past decades, photovoltaic (PV) remains the
D most promising and demandable renewable energy source,
and the global installation is expected to reach the terawatt
level by 2022 [1]. There are many promising advantages of PV
systems. However, the generated power is highly dependent on
the environmental conditions (solar irradiance and temperature)
and PV terminal voltage. In certain cases, an inverter is used as
a cascaded unit to facilitate the maximum power point tracking
(MPPT), boost the PV voltage, and convert it to an ac voltage of
desired characteristics. On the other hand, grid-connected PV
systems require power converters as an interface between the
PV panel and the grid [2]–[6]. In residential PV systems with
low to medium power capacity, transformerless inverters have
become a compact and economic solution as they have relatively
lower cost, size/weight, and higher efficiency [7]. However, their
main drawback is an unwanted leakage current, which flows
through the null of the ac grid and the parasitic capacitor of
the PV array’s negative terminal due to the absence of galvanic
isolation [2]–[7]. Fig. 1 shows a general layout for a single-phase
transformerless inverter for small-scale PV systems. As it can be
seen, without a galvanic isolation, a direct ground-current path
may be formed between the PV panel and the grid. Due to the
presence of large stray capacitance (CPV ) between the PV and
grid grounds, the varying voltage (also known as common-mode
(CM) voltage) excite the resonant circuit formed by the parasitic
capacitor and inverter filter inductor, which produces a high CM
ground current icm . This capacitive icm comprises low line
frequency and high switching frequency components, which
inject harmonics into the grid current, increase the system losses,
impair the electromagnetic compatibility, and can cause serious
safety problems such as electric shock and hazard to the working
personals [7].
In grid-connected renewable energy systems, multilevel in-
verter topologies are highly recommended due to their advan-
tages of improved output current, reduced voltage stress, lower
switching losses, reduced electromagnetic interference, and low
dv/dt stress. However, the main drawbacks of multilevel inverters

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KHAN et al.: COMMON GROUNDED TYPE DUAL-MODE FIVE-LEVEL TRANSFORMERLESS INVERTER 9743

Fig. 2. Proposed 5L-DM-CGT transformerless inverter topology.

Fig. 1. General layout of a single-phase transformerless inverter with

an LC-filter.
experimental results for a 1 kVA prototype in Section IV. Finally,
Section V concludes this article.

are their complexities both in the structure and control tech-
niques [7]–[20]. In addition, they require a higher dc-link voltage
(twice the peak ac-output voltage), which needs an additional
front-end boost dc–dc converter with large voltage boost and
requires isolated dc supplies, or string of series connected PV
modules to lift the dc-link voltage up to 400 V for active power
control to the grid. However, multistage power conversion re-
duces the efficiency and reliability, while increasing the size and
cost of the system. The additional boost stage can be eliminated
by connecting PV modules in series (string) to produce a high
dc-link voltage, whereas the losses due to mismatch between the
modules and shading relatively forfeit the energy gain from the
system. A dual-mode six switch five-level (5L) boost active NPC
(ANPC) inverter is presented in [21] with five output voltage
levels in both buck and boost mode, but the required dc-link
voltage is in the range of 400–800 V.
Therefore, a single-stage dc–ac power converter with boost
capabilities offers an interesting alternative compared to the
two-stage approach [2], [3], [7]–[22]. To utilize the above mer-
its, a multilevel inverter of common grounded type provides
excellent performance to protect the system from the high CM
leakage current problem and to maintain all the advantages of
the multilevel converter [22]–[26]. On the other hand, some
topologies work only in the buck [3], [22], [27] or boost [2], [28]
mode, making it not suitable for a wide range of input voltage
changes. Considering this aspect, a novel 5L single-phase dual
mode inverter with a common ground is investigated in this
article for PV applications. The proposed topology can operate
in a wide range of input voltage, while generating the same
5L output voltage waveform. This unifies the filter design and
simplifies the overall converter design. The proposed circuit
structure reduces the number of semiconductor devices and the
dc-link voltage requirements by up to 25% over conventional
topologies like neutral-point-clamped (NPC) [18], ANPC [9],
cascaded H-bridge [15], and T-type [22], while fully eliminating
the concern of CM leakage current to the grid.
The remainder of this article is organized as follows. Section II
shows the circuit structure of the proposed topology, operating
principle, modulation technique, loss analysis, and gives design
guidelines for hardware implementation. Section III shows the
comparison with different topologies, which is followed by the
II. PROPOSED TOPOLOGY
A. Circuit Structure
The topology of the proposed dual-mode 5L common
grounded type transformerless inverter consists of nine switches
and two switched capacitors as shown in Fig. 2. The switched
capacitors are used to attain different voltage levels by charg-
ing and discharging in predefined switching states. During the
inverter’s operation, the capacitors are charged in one of two
fashions: either charged in parallel and discharged in series or
charged in series and discharged in parallel. The choice depends
on the input voltage and the desired magnitude of the output
voltage.
The voltage across capacitors C1 and C2 is half of the dc-
link voltage (VC1 = VC2 = Vdc /2) in buck mode and equal to
the dc-link voltage (VC1 = VC2 = Vdc ) in boost mode. Five
output voltage levels, as shown in (1), can be achieved, which
are defined, respectively as 0, ±1, and ±2.
⎧
⎨ 0Vdc , ± 12 Vdc , ±Vdc Buck mode
VPN = (1)
⎩
0Vdc , ±Vdc , ±2Vdc Boost mode.
Now, the rms value of the output voltage during different
modes of operation are given in (2), where M is the modulation
index.
⎧
M ×Vdc
⎪
⎨ 2√ 2 Buck mode
vrms = (2)
⎪
⎩ 2×M√×Vdc Boost mode.
2
To simplify the circuit analysis, the following conditions are
assumed:
1) PV panel is considered as a fixed dc power supply.
2) Capacitors are large enough to keep the voltage constant
in one switching period.
3) The power MOSFETs are treated as ideal. The ON-state
resistance and parasitic capacitances of the switches are
neglected. In addition, the forward voltage drop across
the antiparallel diode of each switch is ignored.
4) The equivalent series resistance of each capacitor is
neglected.

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9744 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 68, NO. 10, OCTOBER 2021

B. Operating Principle
The inverter operates in two modes, while producing the same
ac voltage over wide input voltage range. In addition, both modes
have five levels of output voltage, which simplify and unify
the output filter design. The details of each operation mode are
discussed as follows:
1) Buck mode: There are five modes of operation in buck mode
and each produces five different output voltages: 0Vdc , ± 12 Vdc ,
and ±Vdc . Fig. 3(a) shows State A where the inverter output
before the filter is + 12 Vdc . The capacitors C1 and C2 are dis-
charged in parallel through the switches S2 , S4 , S6 , and S8 .
Fig. 3(b) shows State B which produces a voltage level +Vdc and
simultaneously charges the capacitors in series via the switch S5 .
To prevent a short circuit in the capacitors, S4 turns OFF. State
C is the zero state [see Fig. 3(c)]. In this state, the capacitors
are charged in series through the switch S5 , and the capacitors
are charged up to + 12 Vdc . At the same time, switches S7 and S8
turn ON to form a bidirectional path for the current to flow during
the zero state. Fig. 3(d) shows State D where the capacitors are
discharged in parallel and the output current flows through the
switches S3 , S4 , S6 , and S7 . Hence, the output of the inverter
before the filter is − 12 Vdc . Fig. 3(e) shows the continuation of
the capacitor discharging in series which creates the voltage level
equal to −Vdc .
The variable dc-link voltage is represent by (3) using different
combinations of voltages across the capacitors for different
output voltage levels.
VPN
⎧
⎪
⎪ VC1 ||VC2 = 12 × Vdc || 12 × Vdc = 12 × Vdc , State A
⎪
⎪
⎪
⎪ VC1 + VC2 = 12 × Vdc + 12 × Vdc = Vdc , State B
⎪
⎪
⎨     0, State C
= VC1 || VC2 = − 12 × Vdc || − 12 × Vdc = − 12 × Vdc ,
⎪
⎪
⎪
⎪  1   1  State D
⎪
⎪
⎪
⎪ V C1 + V C2 = − × V dc + − × V dc = −Vdc ,
⎩ 2 2
State E.
(3)
2) Boost mode: In this mode, the inverter produces twice the
peak of the ac voltage as compared to the buck mode operation.
Hence, to keep the same ac voltage output, the dc-link voltage
can be reduced by half. There are also five operation modes
that produces five levels of output voltage, i.e., 0Vdc , ±Vdc ,
and ±2Vdc . Fig. 4(a) shows State F, where the inverter output Fig. 3. Switching states of the inverter in buck mode. (a) State A: +1-
before the filter is + 1Vdc . Capacitors C1 and C2 charge in level. (b) State B: +2-level. (c) State C: 0-level. (d) State D: −1-level. (e)
parallel through the switches S1 , S4 , S6 , and S8 . During this State E: −2-level.
state, C1 and C2 also serve as an additional dc-link capacitor.
Fig. 4(b) shows State G, which produces a voltage level +2Vdc
by discharging the capacitors in series via S5 . To prevent a short S8 are OFF. Assuming C1 and C2 are equal, the grid current splits
circuit the capacitors, S4 and S6 are OFF. State H is the zero equally between the two capacitors. Switch S1 is OFF during this
state [see Fig. 4(c)]. In this state, switch S2 is OFF, which allows state to prevent a short circuit on the dc input. Switch S2 remains
the capacitors to be charged in parallel. Switches S7 and S8 OFF for the complete negative cycle. Fig. 4(e) shows the State J
are closed to form a bidirectional path for the current to flow where the switching state is similar to State G.
during the zero state. Fig. 4(d) shows State I, where capacitors In this state, the capacitors are connected in series to boost
C1 and C2 are connected in parallel to provide a dc-link voltage the voltage level. However, S1 , S2 , and S8 are OFF, S3 and S7
of −Vdc . During this mode, S3 , S4 , S6 , and S7 are ON, and S5 and are ON, and the capacitors are connected with reverse polarity

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KHAN et al.: COMMON GROUNDED TYPE DUAL-MODE FIVE-LEVEL TRANSFORMERLESS INVERTER
Fig. 4. Switching states of the inverter in boost mode. (a) State F:
+1-level. (b) State G: +2-level. (c) State H: 0-level. (d) State I: −1-level.
(e) State J: −2-level.
to the output filter. In State G, the switch S4 and S6 are turned
OFF and S5 is turned ON. The capacitors are connected in series
rather than in parallel to the output filter, doubling the voltage.
During this mode, the current in C1 and C2 is equal to the grid
current. The resulting voltage −2Vdc is applied to the output
filter.
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9745
TABLE I
SWITCHING STATES OF THE PROPOSED INVERTER AND THE
CHARGING/DISCHARGING STATES OF CAPACITORS
Note: 1=switch ON, 0=switch OFF, = charging, = discharging.
On the other hand, the voltage level is generated through the
voltages across the capacitors as shown in (4) for the boost mode.
⎧
⎪
⎪ VC1 || VC2 = Vdc ||, State A
⎪
⎪
⎨ VC1 + VC2 = Vdc + Vdc = 2Vdc , State B
VPN = 0, State C
⎪
⎪
⎪
⎪ V C1 ||V C2 = (−V dc ) || (−V dc ) = −V dc , State D
⎩
VC1 + VC2 = (−Vdc ) + (−Vdc ) = −2Vdc , State E.
(4)
Table I shows the switching states in both modes where the
charging/discharging condition of the capacitors in the individ-
ual states are shown.
C. Modulation Technique
The inverter is controlled by a level-shifted sinusoidal
pulsewidth modulation technique as depicted in Fig. 5.
A sinusoidal reference (vref ) is compared with two level-
shifted triangular carriers (v̂tri ) for switching states computation,
followed by a combinational logic circuit, which is used to
compute switching signals for each power switch [see Fig. 5(a)].
Fig. 5(b) and (c) shows the switching signal generation for buck
mode and boost mode, respectively, that can be selected from
the operating principle of each mode. Through the switching
signal of each switch and parallel/series charging and discharg-
ing capability of flying-capacitors, a 5L output voltage can be
generated for both modes.
D. Thermal Analysis and Loss Calculation
The simulated average power loss distribution and the op-
erating junction temperature (Tj ) of the individual switching
elements are presented in Fig. 6. A constant ambient temperature
of 40 ◦ C is assumed and the uniform temperature distribution
across the heat sink is shown for buck and boost mode of the
proposed topology. It is expected that switches (S1 and S8 )
in the capacitor-charging path have a higher loss (conduction)
and hence relatively higher temperature (ΔTj ≈ 7 ◦ C) than
the other switches. Fig. 7(a) shows similar findings and the
loss distribution across the switching components. Finally, the
total conduction losses, switching losses, flying capacitor losses
9746 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 68, NO. 10, OCTOBER 2021

Fig. 6. Steady-state operating junction temperature of the semicon-

ductor devices in both modes for one fundamental period.

Fig. 5. Sinusoidal pulsewidth modulator implementation for proposed

topology. (a) Logical operation. (a) Switching signal generation for buck
mode. (c) Switching signal generation for boost mode.

(F CLoss ), and filter losses (FLoss ) are shown in Fig. 7(b) for
both modes, respectively.

E. Design Parameter and Guidelines

A component selection guideline is helpful to estimate and
select the parameters for the practical design. First of all, the
voltage and current rating of the active switches and diodes
must be selected just above the safety margin. Even though
the input dc-link capacitor helps to maintain a constant voltage
at the dc-link, there are some small spikes in practice across
the semiconductor devices. As a result, the voltage and current Fig. 7. Loss analysis of the proposed topology. (a) Switching and
rating of the selected semiconductor devices are 650 V and 50 A conduction losses. (b) Total loss distribution in full load condition.
accordingly.
To select the components of the proposed inverter, a few more
things need to be calculated such as dc-link capacitor (Cin ),
flying-capacitors (C1 and C2 ) and the output filter (Lf and Cf ). time period, and ΔVdc is the permissible voltage ripple across
The dc-link capacitors Cin can be calculated by (5) where the the supply voltage of the system. The voltage ripple across the
input power is greater than the output power by ΔP, αmax is the supply voltage can be selected between 5−10% of the rated
maximum hold-on cycle number (αmax > 1), tc is the per cycle input voltage. As a result, the selected capacitor value should be

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KHAN et al.: COMMON GROUNDED TYPE DUAL-MODE FIVE-LEVEL TRANSFORMERLESS INVERTER 9747

TABLE II
COMPARATIVE SUMMARY OF THE PROPOSED TOPOLOGY WITH CONVENTIONAL FIVE-LEVEL TRANSFORMERLESS INVERTER TOPOLOGIES

∗
More “+” represents the higher cost/size: “+” ࣕ low, “++” ࣕ medium, “+++” ࣕ high, and “++++” ࣕ extremely high.
In the above table, “S” represents switch, “D” represents diode, “C” represents capacitor, “L” represents inductor, “Vdc ” input voltage, “VPN ” dc-link voltage, “ηpeak ” represents
peak efficiency, “CGT” common ground type, “RPC” reactive power capability, “THD” reported total harmonic distortion, “NR” not recommended, “N/A” not available.

greater than 400 μF, which satisfies all working modes. Following this, the filter capacitor (Cf ) can be calculated by
(8) where the cut-off frequency (fc ) is set to be 10% of fsw and
2 × tc × ΔP × (αmax − 1) the calculated value is approximately 5 μF.
Cin ≥ . (5)
ΔVdc 2
1
The flying capacitors (C1 and C2 ) of the proposed topology Cf ≥ (8)
4× π2 × f c 2 × Lf
can be calculated using (6) through the capacitor discharging
time (tdis ) the average output current (iacavg ) and the voltage III. COMPARISON WITH CONVENTIONAL TOPOLOGIES
ripple requirements of the capacitor (ΔvC1 ).
This section systematically compares the proposed dual-mode
iacavg × tdis topology with conventional 5L transformerless inverter topolo-
C1 = C2 ≥ . (6)
ΔvC1 gies. It presents a detailed comparison list (see Table II) of
the proposed topology with selected 5L transformerless inverter
An LC filter was selected for this design. The required filter
topologies considering the required number of active and pas-
inductor depends on the output current ripple (Δiacmax ) which
sive components to design the inverter, number of required
is recommended to choose a value between 5–10% of the rated
dc sources, output filter type and its value, common ground
output current (iac ). Moreover, the filter inductor value depends
type, reactive power capabilities, total harmonic distortion, cost,
on the modulation type, and switching conditions. For the sys-
boosting ability, and efficiency. It can be seen that the proposed
tem, the switching frequency (fsw ) is selected at 20 kHz, and the
topology is operated in both modes with common grounded type
maximum output current is 5 A for 1 kVA rated output power.
configuration while [21] operates in both mode but the circuit is
As a result, the filter inductor can be calculated by (7) which is
not common grounded and the input voltage range is 400–800 V.
less than 0.6 mH.
√ The THD is comparatively low for the proposed topology (2.1%
0.03 × 2 × vac for boost mode and 2.3% for buck mode). The prototype cost and
Lf ≥ . (7)
fsw × Δiacmax size depends on the number of components used in the system

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9748 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 68, NO. 10, OCTOBER 2021

TABLE III
VOLTAGE STRESS COMPARISON OF SELECTED TOPOLOGIES

design. A careful analysis and comparison of the cost of the

mentioned topologies and the proposed topology reveals that
the cost and size of the proposed topology are reasonably lower
than [9], and [28] while being just a little larger than [2], [3],
5L-B-ANPC [14], and [22].
Moreover, the peak efficiency of the proposed topology is
99.01% at 122 VA in boost and 98.96% at 130 VA in buck mode.
Table III presents a comparative summary of the proposed 5L-
inverter with the conventional 5L-inverter topologies in terms of
voltage stress across the major components and the number of
required high-frequency switches. For the proposed topology,
the voltage stress of five switches (S1 − S3 , S7 , and S8 ) is equal
to the required input voltage, and the voltage stress of the other Fig. 8. Test bench of the experimental setup.
three switches (S4 − S6 ) is half of the required input voltage
when the proposed topology is operated in buck mode. On the
other hand, five switches (S1 − S3 , S7 , and S8 ) experience TABLE IV
voltage stress which is twice the input voltage and other three PARAMETERS AND COMPONENTS FOR SIMULATION AND
switches (S4 − S6 ) experience voltage stress equal to the input EXPERIMENTAL PURPOSES
voltage in boost mode. In boost mode of the proposed topology,
all switches experience fsw over a half power cycle. On the
other hand, in buck mode, five switches experience fsw over a
half power cycle, while other three switches experience fsw in a
full power cycle. Furthermore, the voltage stress on the switch
is either the same as or less than the conventional topologies.

IV. RESULTS AND DISCUSSION

A proof-of-concept 1 kVA hardware prototype as shown in
Fig. 8 was build and tested with the parameters and component
values listed in Table IV. Any buck or boost converter with
common ground can be interfaced at the front stage of the
proposed inverter for MPPT tracking.

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KHAN et al.: COMMON GROUNDED TYPE DUAL-MODE FIVE-LEVEL TRANSFORMERLESS INVERTER 9749

Fig. 10. Input voltage, inverter voltage without filter, output voltage,
Fig. 9. Voltage stress of the switches in buck mode. (a) Switch S1 − and current after the LC filter in the buck mode. (a) Resistive load (R).
S4 . (b) Switch S5 − S6 . (b) Reactive power condition (cos ϕ = 0.967).

Experimental results of the proposed topology in buck mode

conditions are shown in Figs. 9 –12. Figs 13 –16 demonstrate
the behavior of the inverter in boost mode. It can be seen that the
inverter is capable of generating a 5L output voltage with a clean
sinusoidal voltage and current after the filter in both modes.
Voltage stress on the switches is shown in Fig. 9 for buck and
Fig. 13 for boost mode of the proposed topology. The maximum
voltage stress on the switches is 400 V for S1 − S3 , S7 and S8 ,
and 200 V for the other switches (S4 − S6 ).
Fig. 10 (a) shows the waveform of the input voltage when the
inverter is run in buck mode. The inverter clearly has five levels
in the output voltage with a clean sinusoidal output voltage and
current after the filter. The rms value of the output voltage and
current is 230 V and 4.73 A. The reactive power operation mode
is also tested as shown in Fig. 10(b) with a power factor of 0.967
(inductive). The inverter still produces good-quality voltage and
current waveforms without high distortion (THD < 2.3%).
As shown in Fig. 11, the load is changed from R = 50 to 75 Ω
[see Fig. 11(a)], and from R = 75 to 50 Ω [see Fig. 11(b)]. This
result shows that the proposed structure can function in various
dynamic conditions and keep the inverter output voltage to five
levels. Additionally, the output voltage and current show a clear
sinusoidal waveform.
Figs. 12 and 16 show the waveform of the voltage across the
capacitors in buck and boost mode where it is shown that both Fig. 11. Dynamic performance in buck mode under sudden load
capacitors are kept constant for both modes. change. (a) 50 to 75 Ω. (b) 75 to 50 Ω.

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9750 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 68, NO. 10, OCTOBER 2021

Fig. 12. Voltage across the capacitors (C1 , and C2 ) in buck mode.

Fig. 14. Input voltage, inverter voltage without filter, output voltage,
and current after the LC filter in boost mode. (a) Resistive load (R).
(b) Reactive power condition (cos ϕ = 0.97).

Fig. 13. Voltage stress of the switches in boost mode. (a) Switch S1 −
S4 . (b) Switch S5 − S6 .

The required input voltage is 400 and 200 V for the buck mode
operation and boost mode, respectively, to obtain 230 V ac output
voltage. The measured voltage across the dc-link capacitors is
shown in Ch1 and Ch2 of the measured waveforms.
The measured peak-to-peak voltage ripple of the capacitor
is 4 V (4 V/196 V = 2%) and they are self-balanced due
to the series/parallel operation of the capacitors. Using this
charging/discharging of the capacitor, the topology can generate
5L inverter voltage. Fig. 14(a) shows the waveform of the Fig. 15. Dynamic performance in boost mode under sudden load
input voltage when the inverter operates in boost mode. In this change. (a) 50 to 75 Ω. (b) 75 to 50 Ω.

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KHAN et al.: COMMON GROUNDED TYPE DUAL-MODE FIVE-LEVEL TRANSFORMERLESS INVERTER
Fig. 16. Voltage across the capacitors (C1 and C2 ).
Fig. 17. Dynamics of the converter with the wide change of input
voltage. (a) Topology in [2] & [3]. (b) Proposed topology.
scenario, the required input voltage is 200 V to obtain 230 V ac
output voltage and 4.65 A output current.
The inverter output voltage and current waveforms with clear
5L in the output voltage have a clear sinusoidal output voltage
and current after the filter. The rms value of the output voltage
and current is 230 V and 4.65 A, respectively.
The operation of the converter delivering reactive power to
the ac side is also tested at ϕ = −13.5° as shown in Fig. 14(b).
The inverter still produces good-quality voltage and current
waveforms without high distortion (THD < 2.1%). As shown
in Fig. 15, the load changes between from R = 50 to 75 Ω [see
Fig. 15(a)], and from R = 75 to 50 Ω [see Fig. 15(b)].
This result shows that the proposed structure in boost
mode can function under various dynamic conditions while
maintaining five levels at the inverter’s output. Addition-
ally, the output voltage and current are a clean sinusoidal
waveform.
A comparison of the dynamics of the output voltage with the
step change in the input voltage from Vdc to 2Vdc is presented in
Fig. 17. With this step change, the peak of the output voltage in
the conventional system is two times as in the normal operation
input voltage of Vdc as shown in Fig. 17(a). In contrast, the
peak of the output voltage remains constant and stable despite
of the wide dc-link voltage change in the proposed converter
and modulation technique as shown in Fig. 17(b). To keep the
constant peak ac output voltage in the conventional system with
the dc-link voltage changes from Vdc to 2Vdc , the modulation
index needs to be reduced by more than 50%. However, this
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9751
Fig. 18. Measured efficiency curve of the proposed inverter in both
modes.
reduces the output voltage level from five levels to three levels
and considerably deteriorates the power quality. Additionally,
this complicates the filter design process as well as the overall
converter design process.
Finally, the curves for the overall efficiency of the proposed
converter are shown in Fig. 18. Both modes of the operation were
evaluated using resistive loads. The efficiency was measured
using a LMG640 power analyzer. The inverter has an efficiency
of 97 ± 1% over a wide operating range. The peak efficiency
was 98.96% at 130 VA in buck mode and 99% at 122 VA in
boost mode.
V. CONCLUSION
A new dual mode common ground-type 5L inverter was pre-
sented in this article with the detailed derivation, and theoretical
analysis and design guidelines. The proposed topology featured
many advantages when compared with various suggested single-
phase 5L inverter topologies, such as scalability, utilization
of a low number of semiconductors, low voltage stress, high
efficiency and power density, low cost and size, and simple
modulation control. The expected performance demonstrated
by 1-kVA laboratory prototype in both buck and boost mode
had been promising for a practical grid connected PV system.
The converter exhibited 97±1% efficiency over a wide range of
loads with a peak efficiency of 98.96% at 130 VA in buck mode
and 99% at 122 VA in boost mode.
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Md Noman Habib Khan (Student Member,
IEEE) received the B.Sc. degree in electri-
cal and electronic engineering from Ahsanul-
lah University Science and Technology (AUST),
Dhaka, Bangladesh, in 2010, and the M.Sc.
degree in electronics engineering from Interna-
tional Islamic University Malaysia (IIUM), Selan-
gor, Malaysia, in 2014. He is currently working
toward the Ph.D. degree in power electronics at
Department of Electrical and Data Engineering,
University of Technology Sydney, Sydney, NSW,
Australia.
From 2010 to 2011, he was a part-time Lecturer with AUST. From
2012 to 2014, he was a part-time Teaching Assistant with IIUM. Mean-
while, he was a Research Assistant with UMPEDAC Department, Uni-
versity of Malaya, Kuala Lumpur, Malaysia, with renewable energy
especially solar, hydro, wind, and hybrid for electrification issue until
2016. From 2016 to 2017, he was a Senior Lecturer with Uttara Uni-
versity, Dhaka, Bangladesh. His research interests include renewable
energy, dc/ac inverter, dc/dc converter, and grid-tied renewable energy
application.
Yam P. Siwakoti (Senior Member, IEEE) re-
ceived the B.Tech. degree in electrical engi-
neering from the National Institute of Technol-
ogy, Hamirpur, India, in 2005, the M.E. degree
in electrical power engineering from the Nor-
wegian University of Science and Technology,
Trondheim, Norway, and Kathmandu University,
Dhulikhel, Nepal, in 2010, and the Ph.D. degree
in electronic engineering from Macquarie Uni-
versity, Sydney, NSW, Australia, in 2014.
He was a Postdoctoral Fellow with the De-
partment of Energy Technology, Aalborg University, Aalborg, Denmark
(2014–2016). He was a Visiting Scientist with the Fraunhofer Institute for
Solar Energy Systems, Freiburg, Germany (2017/2018). He is currently
a Senior Lecturer with the Faculty of Engineering and Information Tech-
nology, University of Technology Sydney, Sydney, NSW, Australia.
Dr. Siwakoti is a recipient of the prestigious Green Talent Award from
the Federal Ministry of Education and Research, Germany, in 2016. He
serves as an Associate Editor of three major journals of IEEE (IEEE
TRANSACTIONS ON POWER ELECTRONICS, IEEE TRANSACTIONS ON INDUS-
TRIAL ELECTRONICS, and IEEE JOURNAL OF EMERGING AND SELECTED
TOPICS IN POWER ELECTRONICS) and the IET Power Electronics. He is
also a peer review college member of Engineering and Physical Science
Research Council, U.K.
KHAN et al.: COMMON GROUNDED TYPE DUAL-MODE FIVE-LEVEL TRANSFORMERLESS INVERTER
Mark J. Scott (Member, IEEE) received the
B.S., M.S., and Ph.D. degrees in electrical
engineering from the Ohio State University,
Columbus, OH, USA, in 2005, 2013, and 2015,
respectively.
He is currently an Assistant Professor with
Miami University, Oxford, OH, USA. He has
authored or coauthored more than 20 peer-
reviewed papers. His previous work experience
includes developing customized solutions for
material handling applications and performing
onsite installation of automated systems. He also conducted validation
testing of power electronics designed for transit buses and emergency
vehicles. His research interests include tradeoffs of using silicon carbide
and gallium nitride power devices in isolated dc/dc converters, single-
phase ac systems, and three-phase ac systems. He also examines
conditional monitoring techniques for power electronic hardware using
electromagnetic spectral analysis, machine learning, and digital signal
processing techniques.
Dr. Scott was the recipient of the 2017, 2018, and 2019 Air Force
Research Laboratory Summer Faculty Fellowship Program. He serves
as the Financial Chair for the IEEE Energy Conversion Congress and
Exposition—2018 to 2020, and he was the Publicity Chair for the
IEEE Workshop on Wide Bandgap Power Devices and Applications in
2018 and 2019. At Miami University, he is the Faculty Advisor for the
IEEE Student Organization and leads the ECE Department’s Outreach
Program.
Li Li (Member, IEEE) received the B.S. degree
from the Huazhong University of Science and
Technology, Wuhan, China, in 1996, M.S. de-
gree from Tsinghua University, Beijing, China, in
1999, and the Ph.D. degree from the University
of California, Los Angeles, CA, USA, in 2005, all
in electrical engineering.
From 2005 to 2007, he was a Research As-
sociate with the University of New South Wales
at the Australian Defence Force Academy. From
2007 to 2011, he was a Researcher with the
National ICT Australia, Victoria Research Laboratory, Department of
Electrical and Electronic Engineering, The University of Melbourne,
Melbourne, VIC, Australia. He was with the University of Technology
Sydney, Sydney, NSW, Australia, in 2011, and he is currently an Asso-
ciate Professor. His current research interests include control theory and
power system control.
Dr. Li held several visiting positions at various universities. He is
currently serving as an Associate Editor of IET Renewable Power Gen-
eration, IET Generation, Distribution and Transmission, and IET Smart
Grid.
Shakil Ahamed Khan (Member, IEEE) re-
ceived the B.Sc. degree in electrical and
electronic engineering from Rajshahi Univer-
sity of Engineering and Technology, Rajshahi,
Bangladesh, in 2009, the master’s degree in
power electronics from the University of Malaya,
Kuala Lumpur, Malaysia, in 2015, and the Ph.D.
degree in power electronics from the Univer-
sity of Technology Sydney (UTS), Sydney, NSW,
Australia, in 2020.
He is currently a Postdoctoral Research As-
sociate with the Centre for Electrical Machine and Power Electronics
research laboratory, UTS. His current research interests include elec-
tric vehicle power electronics, grid interface of solar and wind power
systems, nonlinear filtering techniques, multilevel power converters, and
power electronics modeling and control.
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9753
Dylan Dah-Chuan Lu (Senior Member, IEEE)
received the Ph.D. degree in electronic and in-
formation engineering from the Hong Kong Poly-
technic University, Hong Kong, in 2004.
In 2003, he was with the PowereLab Ltd. as
a Senior Design Engineer where he was re-
sponsible for industrial switching power supply
projects. He was a full-time Faculty Member with
the University of Sydney, Sydney, NSW, Aus-
tralia, from 2006 to 2016, where he currently
holds an Honorary position. Since July 2016, he
has been an Associate Professor with the School of Electrical and Data
Engineering, University of Technology Sydney, Sydney, NSW, Australia.
He has been a Head of Discipline of Electrical Power and Energy Sys-
tems since December 2018. He has authored and coauthored more than
100 international journals and held two patents in power electronics.
His research interest includes efficient and reliable power conversion for
renewable energy sources, energy storage systems, and microgrids.
Dr. Lu is currently serving as a Chair of Joint Chapter IAS/IES/PELS
(IEEE New South Wales Section) and an Associate Editor for the IEEE
TRANSACTIONS ON INDUSTRIAL ELECTRONICS.
Reza Barzegarkhoo (Student Member, IEEE)
received the B.S. degree from the University
of Guilan, Rasht, Iran, in 2010, and the M.S.
degree from the Sahand University of Tech-
nology, Tabriz, Iran, in 2012. He is currently
working toward the Ph.D. degree at the Fac-
ulty of Engineering and Information Technol-
ogy, University of Technology Sydney, Sydney,
NSW, Australia, all in electrical power engineer-
ing.
From 2016 to 2019, he was with the Guilan
Electrical Energy Distribution Company, Rasht, Iran, as a Senior Grid-
Exploiting Electrical Power Engineer. He has authored or coauthored
more than 15 journal/conference peer-review papers in the area of
power electronics. His research interests include the design and con-
trol of power electronic converters, multilevel voltage source invert-
ers, charge balancing control, switched-capacitor converters, photo-
voltaic transformerless grid-tied ac modules, and distributed generation
systems.
Mr. Barzegarkhoo serves as a frequent Reviewer of the IEEE TRANS-
ACTIONS ON INDUSTRIAL ELECTRONICS, IEEE TRANSACTIONS ON POWER
ELECTRONICS, IEEE JOURNAL OF EMERGING AND SELECTED TOPICS IN
POWER ELECTRONICS, and Journal of Power Electronics.
Franciszek Sidorski (Student Member, IEEE)
was born in Poland. He received the M.E. de-
gree in power engineering in 2017 from Poz-
nan University of Technology, Poznan, Poland,
where he is currently working toward the Ph.D.
degree in modern electrical and information en-
gineering at the Faculty of Environmental Engi-
neering and Energy.
He is currently working with Poznan Super-
computing and Networking Center affiliated to
the Institute of Bioorganic Chemistry, Polish
Academy of Sciences, Poznan.
9754 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 68, NO. 10, OCTOBER 2021
Frede Blaabjerg (Fellow, IEEE) received the
honoris causa degree from the University Po-
litehnica Timisoara, Timisoara, Romania and
Tallinn Technical University, Tallinn, Estonia, in
2017 and 2018, respectively, and the Ph.D. de-
gree in electrical engineering from Aalborg Uni-
versity, Aalborg, Denmark, in 1995.
He was with the ABB-Scandia, Randers, Den-
mark, from 1987 to 1988. He became an Assis-
tant Professor in 1992, an Associate Professor
in 1996, and a Full Professor of power electron-
ics and drives in 1998. From 2017, he was a Villum Investigator. He has
authored/coauthored more than 600 journal papers in the fields of power
electronics and its applications. He has coauthored four monographs
and is an editor of 10 books in power electronics and its applications. His
research interests include power electronics and its applications such
as in wind turbines, PV systems, reliability, harmonics, and adjustable
speed drives.
Prof. Blaabjerg was the recipient of the 32 IEEE Prize Paper Awards,
IEEE PELS Distinguished Service Award in 2009, EPE-PEMC Council
Award in 2010, IEEE William E. Newell Power Electronics Award 2014,
Villum Kann Rasmussen Research Award 2014, Global Energy Prize in
2019, and 2020 IEEE Edison Medal. He was the Editor-in-Chief of the
IEEE TRANSACTIONS ON POWER ELECTRONICS from 2006 to 2012. He has
been a Distinguished Lecturer for the IEEE POWER ELECTRONICS SOCI-
ETY from 2005 to 2007 and IEEE INDUSTRY APPLICATIONS SOCIETY from
2010 to 2011 as well as 2017 to 2018. In 2019–2020, he serves as a
President of IEEE POWER ELECTRONICS SOCIETY. He is a Vice-President
of the Danish Academy of Technical Sciences too. He is nominated
in 2014–2019 by Thomson Reuters to be between the most 250 cited
researchers in Engineering in the world.
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Saad Ul Hasan (Member, IEEE) received
the B.S. degree in electrical engineering from
Bahria University, Islamabad, Pakistan, in 2010,
the M.S. degree in electrical engineering from
Xi’an Jiaotong University (XJTU), Xi’an, China,
in 2013, and the Ph.D. degree in electronics
engineering from Macquarie University, Sydney,
NSW, Australia, in 2018.
From September 2011 to July 2013, he was
with the Power Electronics & Renewable Energy
Research Center as a Graduate Student with
XJTU. He is currently working with the University of Technology, Sydney,
NSW, Australia and Western Sydney University, Sydney, NSW, Australia
as a Research Associate and Sessional Lecturer, respectively. During
the summer of 2017, he was a Visiting Scholar with Miami university,
Oxford, OH, USA, where worked on novel common-ground transformer-
less inverters for grid connected PV systems. His research interests
include dc–dc and dc-ac power converters, EMI suppression in power
converters, and wide bandgap (GaN/SiC) based high-frequency power
converters.
Dr. Hasan is a frequent reviewer of APEC, ECCE, IET Power Elec-
tronics, JESTPE, and IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS.
He is currently serving as a committee member with IEEE NSW section.