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FPGA Implementation of True Random Number Generator Architecture Using

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FPGA Implementation of True Random Number

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Huirem Bharat Meitei & Manoj Kumar

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IETE JOURNAL OF RESEARCH
https://doi.org/10.1080/03772063.2021.1963333

REVIEW ARTICLE

FPGA Implementation of True Random Number Generator Architecture Using All

Digital Phase-Locked Loop

Huirem Bharat Meitei and Manoj Kumar

National Institute of Technology, NIT Langol Manipur 795004, India

ABSTRACT KEYWORDS
This study is a unique approach for the design and implementation of True Random Number ADPLL; DCO; DSO-X3012A;
Generator (TRNG) using ADPLL, on Field-Programmable Gate Array (FPGA) board Artrix-7 (XC7A35T- FPGA; Ring Oscillator; TRNG
CPG236-1) and the simulation was done on Vivado v.2015.2 design suite. TRNG is solely based on the
different seeds of entropy like Jitter, and metastability was produced from Ring Oscillator, Flip Flop
(FF) and other primitives. In this paper, we have realized and implemented two architectures based
on the use of ADPLL. TRNG with single ADPLL is represented as Novel design-1 (ND-1) and TRNG
with two ADPLL as Novel design-2 (ND-2) cascading with other primitive like ring Oscillator com-
bined with FF. Different from other approaches, this proposed TRNG architecture has higher speed,
consumes less power in spite of employing 2 Look-Up-Tables (LUTs) and 1 slice block without com-
promising the overall throughput producing at 680.7 Mbps for ND-1 (Single ADPLL) and 676 Mbps
for ND-2 (Two ADPLL). Comparing with other existing designs in the Field of TRNG and found out
to have higher throughput and less power consumption, less complexity by employing a reduced
FPGA hardware resource. Digital storage oscilloscope (DSO) is used to capture output waveform and
FFT waveform for both ND-1 (single ADPLL) and ND-2 (two ADPLL). The randomness of the gen-
erated bitstream output of the design architecture is validated by passing the NIST SP 800-22 test
which evidences that the proposed ADPLL-based TRNG can be better suited for different industrial
applications such as security Network system, cybersecurity, Banking security, IIOT, IOT.

1. INTRODUCTION
In this fast and rapidly changing environment of com-
munication network where the use of the internet has no
boundary, securing the internet has become a paramount
task for today’s data-driven world. A new generation of
fast computing and escalating is used for consumer elec-
tronics, which focuses on mobile computing, the internet
of things (IoT) and even the internet of everything (IoE).
People find embedded and glued themselves in various
electronic devices such as laptop, Smartphones, comput-
ers, smart devices, sensors and actuators. Such electronic
devices are interlinked through a local network and Fog
or connected in a wider space through the Internet and
cloud. Considering ever-increasing data dependency on
different applications and various smart devices and sen-
sors, the security of the communication link becomes the
prime concern. The security and privacy of the end-user
must be well protected with a secure yet strong method
of Random Number Generator (RNG) like True Ran-
dom Number Generator (TRNG). To make TRNG highly
secure, a stringent security protocol must be laid down
while generating unpredictable random key [1]. Highly
secure TRNG is the ultimate result of a higher degree
of random bitstreams that are generated from differ-
ent sources of hardware entropy. This hardware-based
design is more secure, more strong and more easy to
enact on TRNG-based design and also competent for
many applications in the field of the financial market,
Banking Security, Cyber Security, and the most recent
emerging field of Internet of Technology (IoT) and Indus-
trial Internet of Thing Technology (IIoT) [2]. Nowadays,
implantable sensing devices for the health sector and
other wearable devices in consumer electronics are con-
sidered to be one of the prominent IoT applications that
have the tremendous potential to transform the whole
world in future [3]. Moreover, the constraints of Pseudo-
Random number generator (PRNG) using different types
of macroscopic and microscopic aspects like the elec-
trical disturbance as a root of randomness which may
produce predictable results [4,5] that can be easily over-
come by our proposed ADPLL-based TRNG. Consider-
ing the crucial contribution of True Random number on
various smart devices connected with multiple sensors,
new opportunity and challenges arise in designing more
versatile random generator, which can fit with the present
demand of more secure data protection.

© 2021 IETE
2 H. BHARAT MEITEI AND M. KUMAR: FPGA IMPLEMENTATION OF TRUE RANDOM NUMBER GENERATOR ARCHITECTURE
Figure 1: General architecture diagram for TRNG based on Ring
Oscillator
The arrangement of ring oscillator, comprising an odd
number of invertors, is shown in Figure 1. XORing the
sum of output jitter is generated by ring oscillators. Mem-
ory element like flip flop (FF) sampled the output pro-
duced XOR at a frequency fs which ultimately generates
a raw data sequence as the final output of TRNG based
on the ring oscillator [2].
2. BACKGROUND
The unpredictability of the Random number used in
RNG devices established on analogue noise disturbances
is sometimes attacked which is vulnerable to the security
of the information produced by the users [6]. So, another
new approach based on ADPLL is introduced for the gen-
eration of highly secure random bitstream. TRNG based
on FPGA Digital Logic architecture has greater flexibility,
higher speed with reduced area and less complexity when
compared to its Analog Circuit Base Counterpart [7].
Due to different seeds of entropy employed in the gen-
eration of random bitstream like the accumulated Jitter
[8–10], Metastability [2] and Transition effect [11] from
different sources such as PLL, Ring Oscillators (RO), flip-
flop (FF) and other primitives greatly help in deciding
the speed of TRNG. The highly secure cryptographic sys-
tem lies in the generation of the unpredictable and totally
unique digital key sequence [12]. Unpredictability can
be defined as the characteristic of random occurrence
which is estimated in a bit of information entropy. More-
over, Entropy is a measure of the unpredictability, in other
words Entropy in information postulate is described as
a standard criterion that assesses the uncertainty of an
occurrence in a probability space [13]. According to the
complexity level and the unpredictability of random data,
RNG can be classified into two main categories: PRNG
and TRNG. PRNG uses a deterministic algorithm and
deterministic process that generate a series of output
from the previous seed of entropy. The development of
PRNG is done using a specific software code and called
through subroutine [14] which generates a determinis-
tic output sequence of a bitstream. Generally, the output
is a long periodic and repeatable sequence of bitstream
resembling the previously generated properties of Ran-
dom Number. Due to the deterministic and probable
nature of the number produced by PRNG, it is some-
times vulnerable to the attack of such devices if the seed of
entropy selected is faulty and makes the bitstream prone
to hackers. On the other hand, TRNG generates unpre-
dictable a Random number from the physical process
and uses a non-deterministic source to produce Random
data. A Hardware-based TRNG generates Random bit-
stream Sequence described by an equally probable and
stochastic nature in the process of data generation. The
exclusion of similarity among the last generated data
sequences with the previous one [2] makes TRNG more
secure than PRNG. This paper aims for the design and
implementation of TRNG based on ADPLL, as discussed
in the following sections: 1. Introduction, 2. Background
analysis of the sources of entropy, 3. Design and imple-
mentation of TRNG based on ADPLL, 4. Experimental
results, and 5. Conclusion.
3. DESIGN AND IMPLEMENTATION OF TRNG
BASED ON ADPLL
Considering the overall Seed of entropy for the genera-
tion of Random Bitstream for the proposed TRNG, our
design architecture containing ADPLL is cascaded with
Ring Oscillators, FF and other primitives.
ADPLL is essentially a digital circuit system in which
the basic digital block can be reproduced functionally on
FPGA [15]. In other words, ADPLL is a complete digi-
tal version of Phase-locked loop (PLL) [16]. It consists of
three building blocks: (i) Phase Detector (PD), (ii) Loop
Filters (LF), and (iii) Digital Control Oscillators (DCO).
Figure 2 shows the basic ADPLL block diagram and all
the blocks are in a digital form [17,18]. Here, XOR-Gate
acts as PD [19,21]. ADPLL is interlocked between the
input phase V1 , output phaseV2 ’ and the frequency. So
to minimize the difference between two signals used in
ADPLL, PD is employed [22].
A loop filter K-Counter is employed [18–20] for remov-
ing noise or undesirable frequency components. DCO
changes the frequency depending on the output of the
signal produced from LF. Representation of an overall
circuit diagram of the first-order ADPLL is shown in
Figure 3. Here, ID Clock, which equals 2Nfo, is the clock
signal of the system. The XOR out an output of XOR gate
is fed to K counter together with the K clock, resulting in
 H. BHARAT MEITEI AND M. KUMAR: FPGA IMPLEMENTATION OF TRUE RANDOM NUMBER GENERATOR ARCHITECTURE
Figure 2: Basic ADPLL block diagram
Figure 3: Circuit diagram of the first-order ADPLL
a carry signal ca as an output [16]. The clock for the K
counter and ID counter is the same.
3.1 PD
Figure 4 represents the PD, also known as phase com-
parator, since it compares the output signal of DCO with
the input signal. The output signal produced by the PD
has low- and high-frequency components and the out-
put also relies on the phase error; EXOR gate can be used
as a PD [16]. When the input signals are symmetrical
square waves, the output is a 50% duty cycle square
wave, and the state is said to be locked, as shown in
Figure 5.
3
Figure 4: EXOR gate as a PD
Figure 5: PD waveforms
3.2 K Counter as Loop Filter (LF)
K-Counter is a form LF or integrator which works with
EXOR or JK phase detector as shown in Figure 6. It
contains two independent counters i.e. Up counter and
Down counter that are counted in an upward direc-
tion. K-counter contains modulus k that ranges from
0 to k−1 and the frequency of the counter clock is M
times multiple of center frequency where M value is
8,16,32 . . . For enabling Down counter the DN/UP state
must be kept at high logic state and for enabling Up
counter DN/UP state must be kept at low logic state [22].
Both counters reset when the contents reach k−1. The
“Carry” signal is the MSB of the Up counter, whereas
the “Borrow” signal is the MSB of the Down counter.
When contents of the Up counter ≥ k/2 “Carry” are high,
when contents of the Dn counter ≥ k/2 “Borrow” are
high. The positive edges of the Carry and Borrow control
the DCO.
3.3 Digital Control Oscillator (DCO)
DCO is a form of a modified oscillator which changes the
frequency of the signal with the output of the loop-filter
Figure 6: Block diagram of K Counter loop filter
4 H. BHARAT MEITEI AND M. KUMAR: FPGA IMPLEMENTATION OF TRUE RANDOM NUMBER GENERATOR ARCHITECTURE

produced [22]. In Figure 7 the initial value of T, an input

of TFF, is “0”. Toggling of the initial value depends on
the applied clk signal. Here ID clock, which equals 2Nfo,
is taken as clk signal of the DCO circuit and the output
of the K-counter loop filter is taken as the carry signal.
Moreover, division by N-counter gives the output signal
depending on the input id_out signal. Here id_out is the
final output produced by DCO [16].

3.4 Implementation of TRNG based on ADPLL

The Proposed Ring Oscillator, shown in Figure 8, con-
tains odd numbers of NOR gates that are used in our
novel design of TRNG. The output of the proposed ring
oscillators is then fed as the input to XOR operator.

Figure 9 shows a pulse generator, containing a chain of

51 invertors, which is used in our design for generating
Figure 10: TRNG based on single ADPLL (ND-1)
pulsating signals. The proposed Ring oscillator shown in
Figure 8 is used as a ring oscillator in Figures 10 and
11. TRNG based on ADPLL is implemented on Xilinx
Baysys-3 (XC7A35T-CPG236-1) Artrix-7 FPGA board

Figure 7: DCO Circuit Diagram

Figure 11: TRNG based on two ADPLL (ND-2)

Figure 8: General architecture for the proposed Ring Oscillator
and the simulation of the design is performed on Vivado
v.2015.2. Considering all the main entropy sources such
as the Jitter from ADPLL [15] and proposed Ring Oscil-
lators [2] as well as metastability state of the flip-flop [2],
the jitter produced by the Ring oscillator is sync with that
produced by ADPLL as a source of Entropy.

Figure 10 shows the block diagram of the proposed

TRNG architecture based on single ADPLL (ND-1). Here
100 MHz is employed as the system clock and passed to
Figure 9: Pulse Generator circuit be divided by 2 counters of the pulse generator. Now an
 H. BHARAT MEITEI AND M. KUMAR: FPGA IMPLEMENTATION OF TRUE RANDOM NUMBER GENERATOR ARCHITECTURE 5

output of 50 MHz signal is produced from the pulse gen-

erator whose pulsating output oscillates between two lev-
els of a voltage: true and false. Performing XOR operation
on the signal produced by ring oscillator with 400 MHz
ID_out signal from ADPLL (ND-1) along with the feed-
back loop produced from Q1 of DFF1. The output from
Q1 of DFF1 is then fed to d2 of DFF2 along with the signal
generated by the counter as Clk signal. Finally, the output
of Q2 of DFF2 is the generated raw bitstream. In ADPLL
circuit design [17,18,20] of ND-1(single ADPLL), we
used 50 MHz as the center frequency fo with a modulus
value of k as 4. K clock is equal to Mfo, where fo is the cen-
ter frequency N is equal to 8 and M = 16. ID-clock is the
clock signal for DCO which is equal to 2Nfo [16]. Simi-
larly, For ND-2 (two ADPLL) the center frequency fo for
both ADPLL1 and ADPLL2 is 50 Mhz and the parameters Figure 12: Simulation waveform of TRNG using single ADPLL
for ADPLL1 are k = 8, M = 16, N = 8 and the parame-
ters for ADPLL2 are k = 4, M = 8 and N = 4 as shown
in Table 1.

The outputs obtained from the above operation provide a

random variation of the same probability since no biased
noise is present. Moreover, any differences in the operat-
ing temperature, input voltage or overall Jitter produced
from different sources [2] can overwhelmingly increase
the final entropy of the proposed TRNG.

TRNG base on two ADPLL designs (ADPLL1 and

ADPLL2) is shown in Figure 11. The pulsating wave-
form of 50 MHz generated from the input system clock of
100 MHz is directly fed to the ring oscillator as an input
signal. The output of the ring oscillator is then split and
Figure 13: Simulation waveform of TRNG using two ADPLL
fed directly to ADPLL1 and ADPLL2 which produced
IDout1 of 400 MHz and IDout2 of 200 MHz, respectively.
After XORing and sampled by FF finally produced a raw The quality of the random number produced by the pro-
bitstream as the ultimate output of the proposed TRNG posed design is assessed by a set of statistic tests. Digital
with two ADPLL. Oscilloscope (DSO-X3012A) has been used to capture
the generated output waveform and FFT waveform of the
random bitstream and to analyze the Jitter produced from
4. EXPERIMENTAL RESULTS
the different entropy source. To evaluate the randomness
The Simulation waveform performed on Vivado v.2015.2 of the output data generated, we collect the data sequence
for single ADPLL (ND-1)-based TRNG is shown in of output Random bitstream. The statistical analysis of
Figure 12. The Simulation waveform for double ADPLL the generated bitstream is done by using the NIST suite
(ND-2)-based TRNG is shown in Figure 13. (SP 800-22). ND-1 (Single ADPLL) design takes a data
path delay of 1.469 ns producing a maximum frequency
of 680.7 MHz which generates an overall throughput of
Table 1: Parameter of the ADPLL Design used in the Pro-
posed TRNG 680.7Mbps. But ND-2 (Two ADPLL) design allowed a
(ND-1) Single ADPLL Design (ND-2) Two ADPLL Design
data path delay of 1.479 ns with a maximum frequency of
676 MHz that produced a throughput of 676 Mbps. For
Parameter Design Parameter (ADPLL)1 (ADPLL)2
NIST test a P-value greater than or equal to 0.001 of a
K 4 K 8 4
M 16 M 16 8 sequence is considered as a pass with a randomness con-
N 8 N 8 4 fidence level of 99.9% [23]. NIST test of the proposed
Center Frequency fo 50 MHz Center Frequency fo 50 MHz 50 MHz
TRNG is shown in Table 2 for ND-1 (single ADPLL) and
6 H. BHARAT MEITEI AND M. KUMAR: FPGA IMPLEMENTATION OF TRUE RANDOM NUMBER GENERATOR ARCHITECTURE

Table 2: NIST Test Result of ND-1 Figure 15. The schematic diagram is generated by using
(Single ADPLL) TRNG Vivado v.2015.2 simulated on xc7a35tcpg236-1 device
NIST Test P-value Result (Artrix -7) FPGA board.
Frequency 0.0136 Pass
Block Frequency 0.9134 Pass
DFT 0.0136 Pass 4.1 DSO Output Waveform
Run 0.000594 Fail
Rank 0.0000453 Fail Overall testing and measurement of the signals were
accomplished through an Agilent technology DSOX-
Table 3: NIST Test Result of ND-2 3012A 3000 X-series digital oscilloscope. Other impor-
(two ADPLL) TRNG tant characteristics of DSO are the 100 Mhz bandwidth
NIST Test P-value Result 2G sample/s per channel,4G sample/s for half chan-
Frequency 0.4561 Pass nel. Moreover, it used auto probe interference which
Block Frequency 0.0124 Pass
DFT 0.3049 Pass is user-friendly. The DSO output waveform and Fast
Run 0 Fail Fourier transform (FFT) waveform of ND-1 are shown
Rank 0.000199 Fail
in Figure 16(a,b), respectively. Similarly for ND-2 the
DSO output waveform and FFT waveform are shown in
Table 3 for ND-2 (Two ADPLL) which confirmed that the Figure 17(a,b), respectively.
generated sequence is Random data sequence.
Comparison of performance among different TRNGs
Schematic diagram of the proposed TRNG based on is shown in Table 4 and Synthesis report compari-
single ADPLL (ND-1) is shown in Figure 14 and that son among different TRNG architectures is shown in
based on two ADPLL (ND-2)-based TRNGs is shown in Table 5. Our proposed design used fewer number of

Figure 14: Schematic for single ADPLL-based TRNG (ND-1)

 H. BHARAT MEITEI AND M. KUMAR: FPGA IMPLEMENTATION OF TRUE RANDOM NUMBER GENERATOR ARCHITECTURE 7

Figure 15: Schematic for two ADPLL-based TRNG (ND-1)

Table 4: Performance comparison among TRNG architecture

Reference Entropy source Device Hardware resource Throughput Post processing
[2] Metastability/Jitter Xilinx XCKU040 1 PLL; 5 Primitives; 5 Slices 100 Mbps Yes
[24] Metastability Altera Cyclone III 511 LUTs 133 Mbps yes
[25] Ring oscillator Xilinx XC5VLX50T 147 LUTs 100 Mbps yes
[26] RS-Latch Xilinx XC4VFX20 580 Slices 12.5 Mbps no
[27] Chaotic ring oscillator Xilinx XC6SLX16 256 LUTs 125 Mbps no
[28] PLL jitter Altera Stratix 120 LE > 1 Mbps yes
Proposed ND-1 Metastability/Jitter Ring oscillator Xilinx XC7A35T-CPG236-1 2 LUTs; 1 Slice 680.7 Mbps no
Proposed ND-2 Metastability/Jitter Ring oscillator Xilinx XC7A35T-CPG236-1 2 LUTs; 1 Slice 676 Mbps no

Table 5: Synthesis result Comparison among different TRNG architectures

Parameter Paper [29] Paper [30] Paper [31] Paper [32] Proposed ND-1 Proposed ND-2
Speed 10 M Hz 125 MHz 1.4 MHz 10 MHz 680.7 MHz 676 MHz
Power Consumption 0.0023 W 0.1900 W 0.0039 W 0.0036 W 0.076 W 0.078 W
Post Processing NO NO NO Yes NO NO
Final Throughputs Rate 10 MbPS 125 Mbps 1.4 Mbps 10 Mbps 680.7 Mbps 676 Mbps

LUT, Slices and other hardware resources. Moreover, for 5. CONCLUSION

ND-1 (Single ADPLL) power consumption is 0.076 W
By employing all the seeds of entropy produced from
and for ND-2(two ADPLL) power consumption is
ADPLL, Ring Oscillator, Flip-flop and other primi-
0.078 W which is very less when compared to other
tive, more secure and reliable base TRNG is produced.
literatures. Using fewer hardware resources and less
ADPLL-based TRNG produced more secure random
power consumption doesn’t compromise with the overall
bitstream compared to analog noise source [6]. By
throughput of the design as observed from the table, pro-
using ADPLL in TRNG design, less power and fewer
ducing 680.7 Mbps throughput for ND-1 and 676 Mbps
hardware resources utilizing only 2 LUTs and 1 slice
throughput for ND-2.
of FPGA board but producing high throughput when
8 H. BHARAT MEITEI AND M. KUMAR: FPGA IMPLEMENTATION OF TRUE RANDOM NUMBER GENERATOR ARCHITECTURE

compared with other existing literatures as shown in

Tables 4 and 5. The output waveform and FFT waveform
are captured and analysed by using digital oscilloscopes
(DSO-X3012A). Implementation and simulation are
done on Xilinx Artrix-7 (XC7A35T-CPG236-1) FPGA
board using Vivado v.2015.2. With this Novel Design, we
greatly achieved high throughputs of 680.7 and 676 Mbps
with single and two All Digital Phase Locked Loops
(ADPLLs), respectively. We also achieved less power
consumption of 0.076 W for ND-1(single ADPLL) and
0.078 W for ND-2(two ADPLL) when compared to other
designs in the field. Finally, all the data bitstream passed
NIST test, which shows a high degree of randomness.
With these works, the future of securing the security by
using ADPLL-based TRNG holds high which makes it a
reliable and more secure candidate in many applications
such as cyber Security, IoT, IIOT and Industry 4.0.

ACKNOWLEDGEMENTS
The author conveys his deepest gratitude to Dr. Manoj Kumar
for his continuous support and advice while writing this
article.

ORCID
Huirem Bharat Meitei http://orcid.org/0000-0002-3218-4874
Manoj Kumar http://orcid.org/0000-0001-9394-0170
Figure 16: (a). DSO Output waveform and (b). FFT waveform for
ND-1
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AUTHORS
Huirem Bharat Meitei is now a Ph.D. stu-
dent at the National Institute of Technol-
ogy, Manipur (India) and he earned his
M.Tech degree in Electronic and Commu-
nication Engineering from JNTU Kaki-
nada, Andhra Pradesh. TRNG, IoT, FPGA
design, and network security are among
his research interests. He is also an asso-
ciate member of The Institute of Engineers India (IEI).
Corresponding author. Email: thinktank453@gmail.com
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source for smartcard microcontrollers,” IEEE Trans. Cir-
cuits Syst. I, Vol. 50, November, pp. 1373–1380, 2003.
doi:10.1109/TCSI.2003.818610
Dr. Manoj Kumar is currently working as
an Assistant Professor in the Department
of Electronics and Communication Engi-
neering, National Institute of Technology,
Manipur. Having completed his B.Tech
Degree from NIT Calicut, and MTECH
degree from Indian Institute of Infor-
mation Technology (IIIT), Allahabad, he
started working as Assistant Professor in NIT Manipur and
received his PhD degree from National Institute of Technology
Manipur. He has published several research articles in national
and international reputed journals and attended various con-
ferences across India. His research area includes VLSI design,
VLSI-DSP, Digital Electronics and Communications. He has
published over 25 scientific articles in International, National
journals of repute and in several conferences.
Email: manojara400@gmail.com