Laboratory Guide For Electronics 3 Opera

Laboratory Guide for
Electronics III
Operational Amplifiers
Prepared by
Engr. Rafael U. Gaid, Jr.

Francisco G. Glover
Engr Reyman M. Zamora
Version 1.1
Electronic and Communication Engineering

Ateneo de Davao University
November , 2003
Electronics III
1: Op-Amp Fundamentals {EL3-A}
2: Op-Amp: Practical Circuits {EL3-B}
3: Op-Amp: Frequency Response {EL3-C}
4: Active Filters {EL3-D}
5: Instrumentation Amplifier {EL3-E}
6: AC / DC Millivoltmeter {EL3-F}
7: Digital to Analog Converter {EL3-G}
8: Positive Feedback {EL3-H}
9: Analog to Digital Converters: I {EL3-I}
10: Analog to Digital Converters: II {EL3-J}
11: The 555 Timer {EL3-K}
12: Voltage Controlled Oscillator {EL3-L}
13: Phase and Phase-lock {EL3-M}
i
Preface
This present work, Electronics III : Operational Amplifiers,

is intended to accompany thirteen laboratory modules designed
and produced by the Ateneo de Davao University. It presumes
the student is familiar with the contents of the prior Electronics
I: Basic Components and Electronics II: Amplifiers and
oscillators. The material presented here is normally covered
during the fourth year of an ECE degree program.
All the experiments center on the operational amplifier, in

itself or in various applications. Four particular applications
occupy almost half the manual; analog-to-digital conversions,
digital-to-analog conversion, voltage-controlled oscillators, and
phase-locked loops. Commercially, these configurations are
available in single-chip implementations. However, to deepen
the student’s understanding of their operation , each circuit is
presented as a particular configuration of individual operational
amplifiers. Our intention is to assist the student not only to
observe how the circuit in operation, but also to understand
why the individual components and overall configuration
behave as they does, a mind-set that may be useful to the
student throughout an entire career in electronics.
The authors gratefully knowledge the following Ateneo

ECE students who have evaluated the experiments: Nemil
Bongalos, Brent De Vela, Eugene Grandeza, Irish Patricio,
Joshua Reyes and Eileen Toe.
ii
ELECTRONICS III EL3-1
Op-Amp Fundamentals
Equipment: Module EL3-A, EL3 Power-source, two multimeters, connectors
Electronics II presented two circuits which are basic to our present work.
EL2-2 Cascade Amplifiers used two transistors in series to increase overall gain, and
EL2-7 Differential Amplifiers used two transistors in parallel to provide an output
proportional to the difference between two inputs. The operational amplifier (Op-Amp)
considered here is a single integrated circuit combining the features of both circuits
mentioned above, namely, an extremely high gain output, proportional to the difference
between two input signals. Output impedance is low, typically 50 ohms, while input
impedance is high, typically several megohms. This experiment investigates op-amp
basic properties.
Different types of IC’s have different supply
voltage requirements, for instance, TTL
(Transistor-Transistor-Logic) integrated circuits
require a +5.0 supply voltage, and CMOS
(Complementary Metal-Oxide-Semiconductor)
chips operate with a supply voltage from +3 to +15
volts. In the case of op-amps a dual supply
voltage is required, typically 10 to 15 volts above
and below ground potential. Although this causes
some inconvenience in circuit design, it provides the capability of having a positive or
negative input and output voltage signals. In the diagram, two terminals are marked (+)
and (–). Voltages at the supply terminals are held constant, whereas voltages at the
inputs may vary.
Although the input terminals are marked (+) and (–), the input voltage at either
terminal may be positive, negative or zero with respect to ground potential . If the (+)
input voltage is greater than the (–) input voltage, the output goes positive. This is so,
even if both inputs happen to be negative, provided the (–) input is more negative than
the (+) input. And if the (+) input voltage is less than the (–) input voltage the
output goes negative. The (+) input is also known as the non-inverting input, the (–)
input as the inverting input.
Input Offset Voltage

Ideally the output is zero only if both inputs are at the same potential. But in
practice to obtain this zero output the (+) input voltage must be a little above or a
little below the (–) input voltage. This difference in input voltages is called VIO , input
offset voltage.
1
1: Op-Amp Fundamentals
Obtaining small voltages To measure this small input offset voltage
an accurate voltage source in the micro-volt range
( ≈ 10-6 volts) is needed. The side-bar box at the
left presents a method of obtaining such voltages.
In the activity that follows, you will measure the
Input Offset Voltage using the voltage divider
provided on the left side of Module EL3-1.
NOTE:
A voltage divider is
To give you a short description of Module EL3-
often useful to obtain a known A, the left side of the module is a voltage divider
fraction of a larger voltage. If network designed to give small voltages which the
there is no output current the power supply cannot provide. If you notice the
expression shown above is links at every node, they give you the capability to
valid. It is convenient to select transfer from different levels. If you need smaller
the ratio R1/(R1+R2) to be values, just go down the scale or if you need
some power of 10. For larger values but too small for the supply voltage
example, if we connect in to provide, you go up the scale. Also, with
series between Vin and regards to the supply voltage of the op-amp itself,
ground 990kΩ, 9.00kΩ, 900Ω you need to place a link between the V+ terminal
, 90.0Ω and 10.0 Ω resistors and the one labeled 7. The same thing should be
done with V– terminal. Lastly, all ground terminals
and take R2 as the sum of are internally connected.
resistors to
ACTIVITY 1-1
1. Apply power to the module. The two LEDs
should light up.
2. Place links between V+ and 7, as well as V–
and 4. Do not remove this until Activity #8.
3. Apply a variable external voltage, VDC on the
voltage divider network and monitor this with a
voltmeter.
4. Monitor the output, Vo with an oscilloscope set
the right of the junction marked to 5 V/div, DC mode.
10-4 and take R1 as the sum of 5. Ground the (–) terminal and use the terminal
resistors to the left, then R2 = labeled 10–3 or 10-4 as an input to the (+)
100 and R1+R2 = 1,000,000 so terminal.
the ratio is just 10-4, which is 6. Adjust the applied voltage VS until VO becomes
the label at the junction. By zero (the trace may be shaky; this is due to
adjusting Vin to a value the induced voltages in the environment).
between 1 and 10, and When this condition is reached, multiply VS by
10-4 and record this in the Data Sheet as Input
selecting the appropriate
Offset Voltage. However if the trace makes no
junction as output, voltages response, repeat step 6 but this time reverse
down to 10 microvolts are the polarity; ground the (+) terminal and use
easy to obtain. the (-) as input.
7. Disconnect the input links.
Null-offset
2
Activity 1-1 simply verifies that to have a zero output, there should be a small voltage
difference at the input. It’s quite ironic, right? So to counter this required offset voltage,
a number of op-amps have two additional pins (in the LM741 these are #1 and #5) to
provide a null-offset, an adjustment that sets to reduce the input offset voltage to zero.
ACTIVITY 1-2
1. Ground both inputs of the op-amp, and

connect pins 1 and 5 to the
potentiometer as shown in the diagram
on the left.
2. Monitor the output with the oscilloscope
in the mV range.
3. Adjust the potentiometer until Vo sets to
zero.
4. Disconnect links.
However there is a limit to what the null-offset can do. If the offset voltage is too
large, either positive or negative the output cannot be brought to zero; the wiper arm is
at the extreme of the potentiometer. The acceptable range of values, from positive to
negative, is defined as the offset voltage adjust range.
Offset voltage adjust range

To measure this offset voltage adjust range we will have to use again the voltage divider
connection as was done in Activity 1-1.
ACTIVITY 1-3
1. First ground the terminal you used as ground in Activity 1-1. Apply the voltage offset obtained from
Acitivity 1-1 as input.
2. Monitor the output with an oscilloscope set to 5 Volts/div, DC mode.
3. Fully rotate the Null Offset to one of its extreme end and slowly increase (or decrease) the applied
voltage until the output settles to zero, then record this input voltage (the fine control is a great
help). If the supply voltage is at its maximum capacity, scale up your input by moving from the 10 -4
to the 10-3 terminal.
4. Repeat step 2 but the whole thing will be reversed; rotate the Null Offset to the other extreme, and
correspondingly adjust the variable voltage to achieve a zero output.
5. The difference between these two maximum input values is the Offset Voltage Adjust Range.
3
Large Signal Differential Voltage Amplification
The ratio of a change in output voltage to a change in input voltage difference
is defined as the large signal differential voltage amplification, or open loop gain, often
expressed in units of volts / millivolts . High gain and stray wiring capacitance make it
difficult to obtain Vout=0 with the null offset . Do the following measurement procedure:
ACTIVITY 1-4
1. Ground the inverting input. Apply a metered adjustable voltage (set to minimum) through the
voltage divider and use the 10-4 terminal as input to the non-inverting input. Measure Vout
with an oscilloscope (vertical DC gain set to 5.0 volts per square).
2. If the op-amp has a positive offset voltage, adjust the Null Offset so that the trace is just
about to reach its lower limit (around –10 volts), otherwise, adjust for the upper limit (10
-4
volts) . Record the input voltage (remember you are in the 10 range).
3. Slowly increase the input voltage until the Vout would just get to the other extreme end and
record the input voltage. (make use of the fine control to obtain more accuracy)
Repeat steps 2 and 3 several times to get an average value of Vin+ and Vin–. ΔVout = 20
volts; ΔVin = (Vin+ – Vin–). Compute open loop gain =  ΔVout / ΔVin  then record it on
4.
the Data Sheet.
Common Mode Rejection Ratio

Frequently, telephone signals travel along a pair of conductors, where the
information is contained in the voltage difference between the pair. A stray changing
magnetic field may induce a voltage in the pair. This transient voltage can raise the
potential with respect to ground of both wires yet leave unchanged the difference in
potential between the pair. What is the behavior of an op-amp with signals from such a
pair?
Ideally, if both inputs are raised or lowered by the same voltage with respect to
ground, the output should remain unchanged. But for most real op-amps, there is a
change. The ratio of the change in output to the change in the common input is defined
as the common mode voltage gain. Compared to the differential mode voltage gain
already considered, the common mode gain is extremely small.
ACTIVITY 1-5
1. To measure this common mode voltage gain, use the same method as for open-loop
gain (Activity 1-4), but instead of grounding the (–) input, connect it to the (+) input.
NOTE: in adjusting the input voltage, you may not need the voltage divider.
2. Compute for the CMRR as stated below.
4
The common mode rejection ratio, (CMRR) is defined as
CMRR = differential mode voltage gain / common mode voltage gain
It is desirable to have a minimal common mode voltage ratio, therefore, the higher the
CMRR the better. This quantity is sometimes expressed in decibel units:
CMRR (log) = 20 log1 0 CMRR .
Input Bias and Offset Current

As mentioned above, an op-amp is a form of differential amplifier, with a pair of
input transistors. Recall that bi-polar transistors are current-operated devices; the output
current is proportional to the input. If the input transistors are NPN the input current
flows into the op-amp; if PNP the flow is out of the chip. What then is the input current
+ –
or input bias current at either input, IIB or IIB ? The currents are too small to
measure. On the 400 milliamp range of a four-digit multimeter, the display reads to a
tenth of a milliampere, so another method must be used to measure the input bias
currents,
An ideal voltmeter draws no

current at its input terminals. A real
voltmeter, digital or analog, does
draw some input current so it may
be used as an ammeter. The real
voltmeter may be modeled as an
ideal voltmeter, VM, in parallel with
an input resistor, RM. In the next
activity, measuring the input current
is like measuring the voltage across
the input terminals since it has an
equivalent configuration as shown in the diagram above.
ACTIVITY 1-6
1. To measure the RM of the voltmeter, a separate multimeter is needed. Set first the
voltmeter to the 400 mV range. Using the other meter, measure the resistance
between its + and – terminals. For a reasonably good digital voltmeter R M may be
107 ohms.
2. Measure the voltage at the + input terminal with the – input terminal grounded.
3. Compute IB+ using ohm’s law, Ib= VM / RM . Record it in the Data Sheet.
4. Repeat steps 2 and 3 for IB- . This time the + input terminal is grounded.
5. Compute for the bias current and offset current using the formulae shown below.
Disconnect links.
Input bias current is defined as the average of these two input currents:
-
Input bias current = IIB = (IIB+ + IIB ) / 2
5
A knowledge of input current can be important if an input is grounded through a resistor
because even a small current can significantly affect the input potential if the resistor is
large.
Another quantity of interest, input offset current IO , is defined as the absolute
value of the difference in input current at the two inputs:
-
Input offset current = IIO = | IIB+ - IIB |
Input impedance
When a voltage is applied to either input of an op-amp, the resulting current is
extremely small, indicating a very high input impedance, typically of the order of several
megohms. Such current measurements will be considered after feedback has been
discussed.
Output Impedance
The op-amp output is always
connected to something, and so its output
impedance is important. In the model
shown at right, the output is driven by an
ideal voltage source, V, controlled by the
input voltage, Vi , in series with the output
resistance, Ro . If there is no load
(RL = ∞) the output voltage. Vo , equals the source voltage, V. If the load is set equal
to the output impedance, Ro = RL , then the same voltage drop occurs across both
resistors, and Vo = ½ V . This suggests an easy way to measure the output
resistance, Ro . The technique shown in the next activity is another application of a
voltage divider action.
ACTIVITY 1-7
1. Ground the (–) input terminal and apply variable input voltage through the voltage
divider on the (+) input terminal of the op-amp (use 10-4).
2. With no load, monitor the output voltage. Slowly increase the input until the output
gets to its maximum. Record the maximum voltage as V.
3. Next, attach a load resistor RL (set to maximum) to the output. Then slowly
decrease this load until the output voltage equals V/2. When this condition is
reached, RL equals the output impedance.
Supply Voltage, Current and Power

For the op-amp to function properly, a positive and negative ( with respect to
+
ground potential) supply voltage must be provided. This can be measured as VCC and
– –
VCC at the indicated terminals. The corresponding currents ICC+ and ICC can be
measured by removing a link and inserting a milliammeter. Ground both inputs when
6
making these measurements. Vary the null-offset to make measurements when Vout
has extreme + and – values. Calculate power in each case ( e.g., P = VCC ICC )
+ + +
Activity 1-8
1. Ground the (–) and (+) inputs. Monitor Vout with an oscilloscope set to 5
Volts/div, DC mode.
2. With a voltmeter, measure V+ and V–.
3. Remove the link between V+ and 7 and insert a milliammeter.
4. Adjust the Null Offset to set Vout to maximum. Record the corresponding
current.
5. Adjust the Null Offset for minimum Vout . Record the corresponding current.
6. Compute and record power for both currents (P=IV).
7. Repeat steps 3 – 6 for the V– terminal.
8. Disconnect all links and supply voltages.
7
Data Sheet Experiment EL3-1
Op-Amp Fundamentals
Name: ________________________________Date:______
Activity 1-1:
input offset voltage___________
Activity 1-2 and 1-3:

offset voltage adjust range ___________
Activity 1-4:
large signal differential voltage amplification
__________
Activity 1-5:
common mode voltage amplification __________
CMRR ____________ CMRR(log) __________
Activity 1-6:
-
IIB+ _____ IIB _____ IIB _____ IIO _____
Activity 1-7:
Output Resistance ___________
Activity 1-8:
+ –
VCC _______ VCC ________
+ – – + –
ICC+ P ICC P P +P
Max Vo
Min Vo
8
Op-Amp: Practical Circuits
Equipment: Module EL3-B, EL3 Power source, Two multimeters, connectors
An op-amp alone is a wild thing, it has its

Feedback own extreme and uncontrollable behavior. Its gain
is extremely high and changes with input signal
Feedback, as applied to
frequency, and worse, even with a constant input,
amplifiers, means the signal
the gain varies from one op-amp to another of the
applied to the amplifier is a
same model. But like any wild animal, it can be
combination of the signal
tamed. Remember that an op-amp does only one
certain fraction, , of the output,
applied to the circuit, Vin , and a
thing: it keeps on putting out an output voltage
so long as the input voltages are not equal. By
Vout. If it is added it is positive adding external circuit elements to the basic op-
feedback when subtracted amp, we can manipulate this basic behavior to
negative feedback. take control of its gain and frequency response
resulting into a practical amplifier with an
adjustable gain, constant over a wide frequency
range. This experiment explores methods to
control the op-amp gain with constant input; a
subsequent experiment deals with varying input.
The certain fraction, , of the amplifier

The key concept for this gain control is feedback.
Let A represent the gain of the output mentioned in the box at the left may be
amplifier alone, and Vout/ Vin easily obtained by a voltage divider, formed by the
diagram below, the value of  is R1 / ( RF + R1).

the gain of the entire circuit. series combination of RF and R1. As shown in the
Vout = A(Vin + Vout) or

For positive feedback
Vout/ Vin = A / ( 1 – A
Vout = A(Vin – Vout) or

For negative feedback
Vout/ Vin = A / ( 1 + A)
However the triangular amplifier symbol at

the left box, shows one input while the op-amps
above have two inputs, so which input is used for
9
feedback? For positive feedback, use the non-inverting (+) input; for negative
feedback use the inverting (–). Practical op-amps use both; positive for oscillators,
negative for amplifiers.
Positive Feedback
In positive feedback configuration, the output has two stable states, Vmax or
Vmin, these are actually the extreme values the output voltage can have which is within
a volt or two of the positive or negative supply voltages. The first activity to perform
illustrates this behavior of positive feed back.
ACTIVITY 2-1
1. On module board EL3-B set up the positive feedback configuration shown in
the previous diagram with RF = 50 k and R1 = 50 k
2. Monitor the output with an oscilloscope and set to 5 ms/div and 5 volts/div DC.
3. Unground the (–) input, touch it with your hand. The input impedance at either
op-amp input is quite high, so the 60 hertz induced voltage on your body
alternately drives the (–) input above and below the (+) input.
4. Sketch the output on the data sheet.
NOTE: The fact that we use the voltage induced in our body as our input signal only
shows that leaving a terminal open does not mean a zero input!
While positive feedback has two stable states, in negative feedback, there is a
single stable state Vout = 0. A more thorough discussion of positive feedback will be
dealt with in later experiments.
Negative feedback
For an ideal op-amp with negative feedback, if the (+) input is at ground
potential, the (–) input should also be at ground potential. But because of non-zero
input currents, this is not always true for real op-amps.
ACTIVITY 2-2
1. Set up the negative feed back configuration with RF = R1 and ground
the (+) input.
2. With multimeter set to 400 mV (DC) to monitor the output, first adjust the null-
offset to set Vout = 0 then measure the potential at (–) input. It may not be zero!
3. Next use the null-offset to set (–) input to zero and measure Vout . It, too, may
not be zero.
4. Check for possible oscillations at the output with an oscilloscope. You may
have to decrease the Volts/div and Time /div to have a clear output.
10
With negative feedback, the portion of the output signal is always returned to the
(–) input. As shown above, the external signal may be applied to either, or both, inputs.
To avoid distortion, the output signal can never range outside the supply voltages, V+ or
V–. Since the gain of the op-amp can be 100,000 or more, to avoid distortion the
difference between the + and – inputs must be less than V+ / 100,000 .
In practice assume the (+) an (–) inputs are at the same potential
Non-inverting amplifier
In the diagram above, resistors RF and R1 act as a voltage divider for the voltage
at the (–) input, which is Vout R1 / (R1 + RF). Since it is assumed that the + and –
inputs must be at the same potential, then:
V1 = Vout R1 / (R1 + RF) or Vout = V1 ( 1 + RF / R1 ) (1)
The sign of the output voltage , Vout , is always the same as that of the input, V1;
hence the name non-inverting. Since the input current to an op-amp is of the order of
nano-amperes, the input impedance for this configuration, V1 / Iinput , is very large
atleast in the meg-ohm range. However if R1 or RF are quite large, even a tiny current
change through them produces a voltage drop, so Eq. (1) is then slightly in error.
ACTIVITY 2-3
1. In the data sheet, a table is provided for you to complete. Configure a negative
feedback non-inverting amplifier (just the follow the diagram shown above), but
use the values of the resistors indicated in the table, with the corresponding V1.
2. Connect VA to the (+) input.
3. Measure Vout and Vin with a meter and compute the actual gain (Vout/Vin) and the
theoretical gain (1+RF/R1).
4. Record the results in the data sheet.
11
If we set Rf = 0 (short circuit) and let R1 approach infinity (open circuit) as shown in
the diagram below, Eq. (1) shows unity gain ( Vout = Vin). This circuit, a voltage
follower, is used as an impedance transformer, or current booster. Recall the input
current at either op-amp input is very small in the order of 1 microampere while the
output current can run as high as 25 milliamperes. No change in voltage, tremendous
change in current.
ACTIVITY 2-4
1. To verify the voltage follower gain, connect VB
directly to the (+) input as VIN, and VO to the (-) input.
Apply different values of Vin as indicated in the data
sheet and record Vout. Disconnect all links.
2. To verify the current gain, connect VO to the (–)

input as before. Connect VB to (+) input through a
10 k as shown in the diagram. Apply an external
voltage to VB and set to 10.00 V. With the meter in
the mV range, measure and record voltage across
the 10 k V then apply Ohm’s Law to
compute for Iin.
3. Measure with a milliammeter the output current

passing through the adjustable load resistor, RL.
Gradually decrease RL until Vout starts to drop below
10.00 volts. This gives the maximum output current,
Iout . Compute the current gain, Iout/Iin .
Inverting amplifier
Looking back at the diagram of an inverting amplifier in the previous page, the
voltage at the grounded (+) input , v+, is zero, it follows that the voltage at the ( –) input,
v– , must also be zero. By Kirchoff’s Current Law and neglecting the very small amount
of current going into the op-amp, the same current should pass through R1 and RF, so
by applying Ohm’s law to each:
(V1 – v–) / R1 = (v– – Vout) / RF or Vout = – V1 ( RF / R1 ) (2)
Notice the negative sign in the expression for Vout . If V1 is above ground, the
output, Vout, should be below ground, so that the (–) input is at the same potential as
the (+) input, although in reality, the inverting (–) input should be just a tiny bit above
the (+) input to cause Vout become negative.
12
ACTIVITY 2-5
1: Connect the module as an inverting amplifier, with RF = 100 k , R1 = 50 k and use VA
as input. Vary VA from –4.00 v to + 4.00 v in one-volt steps. Graph the results ( VA on x-axis
and Vout on y-axis) on the data sheet. Scale the horizontal from –4 to 4 in one-volt step and
the vertical from –10 to 10 in two-volt step.
2: Repeat step 1 above, with RF = 50 k , R1 = 20 k. Compare the steepness of both
graph.
3: Set R1 = RF = 50 k Verify the results with the VA values shown on the data sheet.
The values of RF and R1 in step 3 in Activity 2-5 gives a voltage gain of –1, that is Vout=
–VIN. Such a circuit is a simple voltage inverter.
The input impedance of the non-inverting amplifier is in the meg-ohm range,

since the signal is applied directly to the (+) input. For the inverting amplifier the signal,
Vin, is applied to one side of R1 and its other side is at ground potential. Therefore the
input current, Iin , is Vin / R1 , so the input impedance equals R1 . Notice the difference
in input impedance between the voltage follower and the voltage inverter.
Several variation of the basic inverting amplifier are considered:
Inverting: Summing Amplifier

Experiment #8 of Electric Circuits I treated the principle
of superposition.
The superposition theorem states that in a resistive
network with two or more voltage sources, the current in any
branch (or voltage at any node, with respect to the ground
node) is the algebraic sum of the currents in any branch (or
voltages at any node) measured one at a time with one
voltage source present and all other voltage sources
replaced by a short circuit.
The summing amplifier diagrammed here is easily understood in terms of

superposition. The (–) input is effectively at ground potential. If VB is replaced by a
short circuit, the voltage at either end of RB is zero so no current passes through it.
The circuit behaves as if it were not there. By Eq.(2) Vout = –VA (RF / RA). A similar
argument holds if only VB were present. So by superposition, if both sources are
present, the output is the sum of the separate outputs, as indicated in the diagram. The
inputs need not have the same sign. In the summation process, voltages are given
different “weights”; the smaller the R value, the greater the “weight” given to the input
voltage. If desired a voltage inverter could be added to the output.
13
ACTIVITY 2-6
1. Set up the module as shown in the diagram above for a summing amplifier. Use
RF=50 K, RA=10 K K and RB= 10 K K.
2. Use an external voltage supply for VB.
3. Fill out the table in the data sheet for the different values of VA and VB as indicated in
the table.
4. Record the measured VOUT and the computed output .(Refer to the equation in the
diagram).
5. Repeat steps 1 to 4 for RA=50 K K and RB= 20 K K.
It is also possible to make a summing amplifier by applying signals to both the

inverting and non-inverting inputs. The difference amplifier, to be considered later,
uses this approach.
Inverting : Current to voltage

The output voltage, Vout , may be
controlled by the input current, Iin , The (–)
input is at ground potential so Vout equals the
voltage drop across RF . Since no current
enters the (–) input, the entire input current,
Iin, passes through RF. Therefore Vout = –
Iin RF. For positive Iin, Vout is negative with
respect to the (–) input. Set up this circuit. Adjust VA to give desired Iin .
ACTIVITY 2-7
1. Set up the circuit shown in the diagram above with RF = 50 K.
2. Use VA as input and adjust it to obtain the current indicated in the data sheet.
3. Record the corresponding output voltage and its expected value (Vout= –IINRF).
4. Repeat Step 2 and 3 for the remaining values of IIN.
Inverting : Voltage to current

It is also possible for the input
voltage to control the output current. In the
diagram the load current, IL, also passes
through R1. This current is (VA – 0) / R1
for the (–) input is at ground potential so we
have IL= VA /R1. Within limits, this load
current, IL, is independent of the load, RL,
and depends on VA alone.
14
ACTIVITY 2-8
1. Set up the circuit shown in the diagram above with R1 = 10 K.
2. Adjust VA to obtain the input voltage indicated in the data sheet.
3. Record the measured current for both the minimum load (fully CCW) and
maximum load (fully CW) and its expected value (VA/R1).
4. Repeat Step 2 and 3 for the remaining values of VA.
Difference Amplifier
In the configurations already considered, one of
the inputs is always at ground potential. For the
difference amplifier neither input need be at ground
potential. Basically, the difference amplifier is a
superposition of an inverting and a non-inverting
configuration . The key to the analysis is the
superposition principle and the requirement,
RF / R 1 = R4 / R3 .
Let Vout be the sum of Vo1 (output, if input V2 = 0) and Vo2 (output, if input V1 =
0). If V2 = 0, then the (+) input, at the junction of R3 and R4 , is grounded. This
circuit is inverting so use Eq. (2) to obtain
Vo1 = – V1 (RF / R1). (3)
Next, let V1 = 0. Here the circuit is non-inverting, although the full amount of V2 is
not applied to the (+) input. Resistors R3 and R4 form a voltage divider so the voltage
at the (+) input is V2 R4/(R3 + R4) which can also be written as V2(R4/R3)/(1 +
R4/R3). Use the non-inverting Eq. (1) to obtain:
Vo2 = [V2 (R4/R3)/(1 + R4/R3)] ( 1 + RF/R1)
Substitute RF / R1 for R4 / R3 since they should be equal according to the

requirement stated above. The result becomes:
Vo2 = V2 ( RF/R1) (4)
So, by superposition,
Vout = Vo1 + Vo2 = ( RF/R1) (V2 – V1).
In words this says that the output of the difference amplifier equals the difference
between the two inputs, multiplied by the familiar gain factor ( RF/R1).
15
ACTIVITY 2-9
1. Set the circuit as shown in the diagram above. Use RF = 100K, R1 = 50K,
R3 = 10K R4 = 20 K.
2. Use VA as V1 and VB as V2.
3. Set both input voltage to the values indicated in the data sheet (Suggestion:
Set V2 before V1).
4. Record the measured VOUT and its expected value (RF/R1)(V2 – V1).
5. Repeat steps 3 and 4 for all other values.
Input Offset Voltage, revisited

In Experiment EL3-1 input offset voltage, the voltage difference between the
(+) and (–) inputs of a real op-amp necessary to produce a zero output voltage, was
examined. By using the null offset (pins 1 and 5 of the LM741) this input offset voltage,
if not too great, can be reduced to zero. In that experiment, after disconnecting the
null-offset pins, a very small measured input voltage was applied to the input to reduce
the output to zero. Without feedback, if the two inputs are shorted to ground, the
output moves out range and cannot be measured.
An alternate, and easier, approach is to use negative

feedback to significantly reduce the op-amp gain, so that when
the inputs are set to zero and the null-offset not used, the
output voltage, Vout, is measurable. Then the input offset
voltage equals Vout / gain . If the null-offset is used, the
offset voltage adjust range may be measured by the same
method. Apply zero voltage to both inputs, set the null-offset
potentiometer to either extreme and measure the
corresponding Vout . The difference in the extreme Vout levels,
divided by the gain with feedback, gives the offset voltage
adjust range.
ACTIVITY 2-10
1. Connect the circuit in negative feedback configuration with the (+) input grounded
as shown above, use RF = 50 K and R1=10 K.
2. Set the Null Offset knob fully CCW and record V out. with a the multimeter in the
mV range. Do the same with the knob fully CW.
3. Divide the difference of these two outputs by the gain (VO1 – VO2)/(RF/R1).
16
Input Offset Current, revisited…
In Experiment EL3-1 input offset current was also
examined. The bias currents at either input were
measured directly and their difference gave IIO, the
input offset current. With feedback the measurement
is simpler. As shown in the diagram, identical
resistors, R1 , are connected directly to each op-amp
input. The input bias currents through either
effectively apply a voltage to each input, IIB RF,
which appears at the output, multiplied by the op-amp gain. Using the superposition
principle to obtain Vout as the sum of two outputs Vo+ and Vo– :
Vo+ = R1IIB+ ( 1 + RF/R1) ≈ R1IIB+ (RF/R1)

Vo– = R1IIB–. ( – RF/R1)
Vout = Vo+ + Vo– = RF (IIB+ – IIB–.) = RF IIO
If the feedback resistor, RF, is large, the input offset current, IIO , can produce
a significant output effect.
ACTIVITY 2-11
1. Set the circuit as shown in the diagram above. Use R1= 10 K and RF=100 K.
2. Measure VO+ and VO– with a multimeter in the mV range; from these compute
IIB+ and IIB– and also IIO
17
Data Sheet Experiment # EL3-2
Op-Amp Practical Circuits
Name: ________________________________Date:______
Activity 2-1: Activity 2-2::

positive feedback negative feedback
Oscilloscope Display (+) grounded:
with Vout = 0 (–) input _____

with (–) input = 0 Vout _____
Oscillations (yes / no)? _____
period ______
Vpeak-to-peak _____
Activity 2-3:
RF R1 Vout V1 Vout/ V1 1 + RF/R1

100k 20 k 1.50
50 k 10 k 1.50
50 k 20 k 2.50
100 k 50 k 3.00
50 k 50 k 4.00
18
Data Sheet Experiment # EL3-2 (continued)
Activity 2-4:
Vin – 4.00 – 2.00 0.00 2.00 4.00
Vout
V10k _________ Iin ________ Iout _______ Current gain ______
Activity 2-5:
RF = 100k , R1= 50k RF = 50k = R1 RF =50k, R1 = 20k
VA Vout
–3.00
–2.00
–1.00
0
1.00
2.00
3.00
Activity 2-6:
RF = 50k
RA = 10k RB = 10k RA = 50k RB = 20k
VA VB Vout VA VB Vout
measured expected measured expected
0.50 0.50 3.00 2.00
1.00 0.50 2.00 2.00
-0.50 1.00 -2.00 2.00
19
Activity 2-7: Activity 2-10:
RF = 50 k Input offset adjust

range __________
Iin Vout
Milliamperes Measured Expected
– 0.20 Activity 2-11:
– 0.10
0.00 Input offset current
0.10 __________
0.20
Activity 2-8:
R1 = 10 k
VA Iin milliamperes
With minimum RL With maximum RL Expected
– 4.00
– 2.00
0.00
2.00
4.00
Activity 2-9:
RF = 100 k R1 = 50 k R4 = 20 k R3 = 10 k
V1 V2 Vout
Measured Expected
3.00 6.00
2.00 5.00
1.00 4.00
0 3.00
– 1.00 2.00
– 2.00 1.00
– 3.00 0
20
Op-Amp Frequency Response
Equipment: Module EL3-C, EL3 Power-source, multimeter, connectors
In prior experiments, the op-amp input signal was constant with time. With
constant inputs various circuits inverted or did not invert the output. Here time varying
inputs are considered. The diagram below shows different Op-Amp configurations with
time varying input. Since, by Fourier analysis, any periodic signal may be represented
in terms of sines or cosines, attention is focused on sinusoidal input. Recall that
inverting a sine or cosine wave is the same as a phase shift of +/– 180o.
sin ( ± 180o) = –sin  cos ( ± 180o) = –cos 
The amplitude of the output is expected to the different from the input, but it is
desirable to maintain the basic shape. Different factors may cause this change in
output shape, or distortion:
1. Clipping: The output signal cannot exceed the supply voltage and is
usually one or two volts less. If the system gain is too high, the tops
and bottoms of the output wave are clipped off.
2. Slew rate: Even apart from clipping, a sinusoidal output of an op-
amp shows distortion if the product of the wave frequency and
amplitude exceeds a certain critical value, thus, to avoid distortion at
higher frequencies the output amplitude must be reduced. The limit to
how quickly the output voltage can change, called slew rate, is usually
measured in volts per microsecond.
3. Frequency dependent gain and phase shift: By Fourier
analysis, any periodic wave may be represented by a set of sines or
cosines , each with a frequency of some multiple of the fundamental
frequency, and fixed amplitude and phase angle. An op-amp
introduces in the output a change in amplitude and phase which
depends on input frequency. Therefore a periodic wave formed from
more than one Fourier component will be distorted by the op-amp,
since the op-amp has different response for every unique frequency,
although for a single frequency wave (monochromatic), phase and
amplitude changes will not affect the basic shape.
3: Op-Amp: Time varying input 1

The R–C voltage divider
Before we discuss more about Op-Amp, it is
important to first understand how RC circuits
responds to frequency. In feedback circuits we used
the voltage divider concept with two resistors in
series; the R–C divider considered here uses a
resistor and capacitor in series. When used with
sinusoidal signals both the magnitude and the phase
of Vout are different from Vin. The ratio, Vout/ Vin, is
a complex number, and is sometimes referred to as a transfer function, which is shown
in the diagram below. Since transfer functions play a key role here and also in active
filters, to be covered in a later experiment , we look at them more closely.
The ratio of input and output signal amplitude is given by the magnitude or
absolute value of the complex transfer function; the signal phase shift equals the
arctangent of the ratio of the imaginary to real part of the complex function. Recall that
the magnitude of a complex number equals the square root of the sum of squares of the
real and imaginary parts. In the present case first rationalize the denominator by
multiplying both numerator and denominator by the same quantity (1 – jRC) before
taking the square root of the squares and we let C = 1/ RC.
| Vout / Vin | = 1/[1+( RC ) 2]1/2 = 1/[1+( /c )2]1/2 (1)
phase angle =  = tan-1(– RC ) = – tan-1( /c) (2)
For c  1 (very low frequency)

Based on the equations above, and with the following approximations:
|Vout / Vin| ≈ 1.0
For c  1 (very high frequency) |Vout / Vin| ≈ 0 .
we may obtain a graph for the gain (|Vout / Vin|) against :
decreases with increasing frequency. As for the phase angle,  the action lies between
The diagram above shows that the RC filter behaves such that the gain
–5o and –85o, where the tangent changes from 1/10 to 10. However, the interval for 
is by the thousands and in many cases we would be interested small values of in

frequencies which cannot be easily shown from a conventional graph. In such cases a
useful approximation is a Bode plot in which the horizontal and vertical scales are
expressed in logarithms. A discussion about bode plots is appended at the end of this
experiment. The activity that follows verifies the behavior of the RC filter.
ACTIVITY 3-1
1. Measure R and C for the voltage divider on module EL3-C . Calculate and record
fC=1/2RC .
2. Monitor Vout with an oscilloscope set to 5 Volts/div, AC mode. Adjust the time/div
to have a convenient view of the trace.
3. Apply as large as possible a 100 Hz input without causing distortion. Record its
peak-to-peak value as Vin.
4. Monitor Vin with a multimeter.
5. Apply input with the frequencies indicated in the Data Sheet and record the
corresponding peak values (VP) of Vout. VP=VP-P/2.
Activity 3-1 simply verifies the effect of an R–C filter on an applied signal.
Observe the output measured voltages; the amplitude is attenuated as the frequency
increases. And as frequency approached the critical frequency, fC , the output is close
to half the input voltage.
What does all this R-C business have to do with real op-amps ? Everything!
Every real op-amp is equivalent to an

ideal op-amp whose output passes
through an internal R–C circuit.
This equivalent R–C circuit explains the frequency response of the op-amp and is
deliberately included by the manufacturer, to prevent self oscillations at high
frequencies. Even though we cannot get inside the op-amp to measure directly R and
C, still we can determine their product by indirect means.
Slew rate
When charging or discharging a capacitor through a
resistor there is a maximum rate of change of the capacitor
voltage, dV/dt = Vo /RC, as shown in the derivation in the
diagram at the left. So, the internal equivalent R–C network
of the op-amp works in just the same way.
Suppose an op-amp output is a sine wave, Vo sin t.
derivative, Vo  cos t ,with maximum value, Vo , and is

The rate of voltage change with time is given by the
called the slew rate. Any signal with a voltage rise rate
greater than this will be distorted. The following activities
shows two methods to determine the slew rate.

ACTIVITY 3-2
1. Set RFA to 0. and apply 200 Hz input signal to the (+) input of OP-AMP A and
monitor the input and output with an oscilloscope set to 1 Volts/div, AC.
2. Set the input amplitude to the value indicated in the Data Sheet.
3. Set the oscilloscope to dual mode so you can simultaneously monitor the
input and output. Slowly increase the frequency until the output begins to
appear distorted (i.e. the wave shape differs from the input). Record this
frequency and calculate Vo 2f, where Vo=Vpp/2 and f is the corresponding
frequency.
4. Repeat steps 2 and 3 for other input levels; then compute for the average
-6
slew rate. Multiply the average by 10 to express it in Volts/S.
A more direct measurement of slew rate is to input a square wave on any

convenient frequency, so that clipping occurs at the output. The op-amp output cannot
follow the almost instantaneous voltage rise at the input.
ACTIVITY 3-3
1. With the same set-up with Activity 3-2, apply a square
wave input.
2. Adjust the oscilloscope vertical gain and sweep speed
as well as the input frequency and amplitude to produce
a trace similar to the diagram at the right. You may have
to continuously adjust the HOLDOFF knob of the
oscilloscope to have a clear output.
3. The slope of the screen trace, in volts per microsecond,
is the op-amp slew rate.
Activities 3-2 and 3-3 presented two different methods of obtaining the slew rate
and they should be close, if not equal. However the important thing here is to
understand how the slew rate limits the performance of the Op-Amp: increasing the
voltage level of the signal decreases the bandwidth. The reason for this will be
shown later, just remember that in the proceeding activities, try to keep a low input.
Time varying input

The diagram below compares different op-amp configurations:

In Experiment El-3-1, the basic op-amp without any surrounding circuit was
considered. It is refered to it as the open loop configuration. The input signal was
constant , =0. The gain Ao (signal out / signal in) was found to be quite high.
the closed loop configuration. Only constant input, =0 , was considered . The loop
In Experiment El-3-2, the circuit surrounding the op-amp was also considered,
gain with feedback, Af, could be adjusted by selecting values for the surrounding
elements.
In this experiment open loop gain, A(), and closed loop gain, Af(), are again
consider but now for time varying sinusoidally input with; ≠0.
Open loop Egain

E
with frequency
Referring back to Equation (1) and the associated diagram, at zero frequency
Vout equals Vin since the reactance of the capacitor is infinite. The equation may be
re-written to show explicit frequency dependence:
V() = V(0) / [1+(/c)2]1/2 (3a)

and
log V() = log V(0) – ½ log [1+(/c)2] (3b)
Where V() is the output of the RC filter for any frequency  and V() is output when
=0. Our real op-amp model is an ideal op-amp followed internally by an R–C filter, so
the output involves both the ideal op-amp constant gain as well as the attenuation due
express op-amp gain, A():

to the R–C filter. With some algebraic manipulation Equation (3b) may be modified to
log A() = log A(0) – ½ log [1+(/c)2] (3c)
Take note, A() is the open-loop gain for any frequency

while A(0) is the open-loop gain for a zero frequency input.
the value of c may be less than 20.

For real op-amps A(0) can be greater than 100,000 while
A frequency of
open-loop gain is unity, lets denote it as f1, (1 = 2f1).

some interest is the frequency at which the op-amp
In this condition, the output amplitude equals the input
Then log A() = log 1 = 0 . Therefore, from Equation (3c)

amplitude (although the phases may be quite different).
0 = log A(0) – ½ log [(/c)2]
/c
and so
A(0) = (4)

Clearly 1 is many times greater then c. And now, for all frequencies, /c >> 1 ,
≈ log /c – ½ log [(/c)2] = log (/c) / (/c)

Equation (3c) may be written as
A() =  /  
log A()
A()  = 
and The final result is
(5)
constant, the unity gain or bandwidth,  Note that A() is not the amplitude of the
In words, this states that the gain at any frequency multiplied by that frequency is a
output but rather the gain of the op-amp. Activities 3-4 and 3-5 will verify this equation.
It may happen that the sine wave output of the

generator may have a non-zero component which
could affect the op-amp bias, thus, the 0.1f capacitor
show in the diagram is used to block this DC
component. Notice also that both op-amp inputs have
identical 1 k resistors to ground, to balance the
effects of the input bias currents.
ACTIVITY 3-4
1. Set up the circuit shown in the diagram above. Set RFA to infinity ().
2. Set channel 1 in the to 10 mV volts/div, channel 2 to 5 Volts/div,and MODE to
dual. Also adjust the sweep rate for a clear output.
3. Apply a 200 Hz, 20 mVp-p input signal (Use external voltage divider). If the
output is clipped, try adjusting the Null Offset so that the peaks of the output is
no longer clipped. If it doesn’t work, increase the frequency a little then adjust
the Null Offset. Keep doing this until you obtain a sinusoidal output shape.
4. Notice that the ratio of Volts/div settings of the oscilloscope will give us the
gain if the input and output waveforms would have the same height on the
trace. We shall take advantage of that to compute for our gain.
5. Slowly increase the frequency until both waveforms have the same height (in
the case of a 20 mVp-p input, a span of two squares). When the condition is met,
record the gain and the frequency. For each frequency adjustment recheck
input amplitude.
6. Reduce the volts/div of channel 2 to the next lower range. Repeat step 5.
7. Repeat steps 5 and 6 until the volts/div of channel 2 is just the same with
channel 1 (unity gain) or when the function generator is already at its
maximum.

Closed loop gain with frequency
Two main ideas regarding op-amp gain have been considered, feedback and
R-C frequency response:
Feedback is completely characterized by the constant , (up to now a real
internal R-C filter is completely characterized by C and is conceptually unrelated to the

number) which is independent of frequency. The op-amp frequency model with an
concepts. To obtain Af() , the op-amp gain with feedback at frequency  insert the
notion of feedback. The next logical step is to blend together these two different
expression for A() of Equation (7) in place of Ao of Equation (6). Details are shown in
the shaded box. The result is:
f (8)
Comparing this with Equation (7), the open-loop
[1 + A(0)] while the corner frequency, C, is

gain at zero frequency is decreased by a factor
increased by the same factor. More feedback, , means

less gain, but greater corner frequency or bandwidth.
The feedback constant, , is R1 / Rf and in this

experiment will not exceed 50. Since A(0) is one hundred
thousand or more, the following approximation is quite
valid:
A(0) / [1+A(0)] ≈ 1/ = Rf/R1
In the next activity, we will determine the corner frequency

of different gain settings. To do so, for fixed input
amplitude, we will continually increase the
frequency until the output drops to 70% of its
original magnitude. It is important to begin with a
low frequency to ensure that the output is not yet
attenuated when computing for the70% level.
Further, a blocking capacitor is added to prevent

any undesirable DC voltage from reaching the input. Because the function generator
output amplitude may decrease somewhat with increasing frequency, monitor both the
input and output amplitude with a dual-channel scope. At the higher frequencies, the
input may have to be decreased, because of slew rate limitations.
Activity 3-5
1. Set the circuit as shown in the diagram above. Measure the exact values of R1
for each op-amp. Monitor the input and output with an oscilloscope.
2. Set the input frequency to 200 Hz. Set RFA to 2 K. Apply a 100 mVP-P input
voltage and determine the corresponding output. Also compute the 70% of the
output then record all the values considered.
3. Slowly, increase the frequency until the output gets down to 70 % of its original
1 by the formula 2fc(Rf/R1). [Note: this step is also used in the next activity.]
value. Record the frequency when the condition is met. Compute and record
4. Repeat steps 2 and 3 for several values of RFA. Be sure to set the frequency
back to 200 Hz before setting the input voltage.
Note that there is limit of accuracy of a few percent when reading from the
oscilloscope screen. It is not practical to use a digital multimeter on the AC VOLTS
range, since most multimeters have a poor AC response above 20 kHz.
Cascading
For op-amps, the greater the gain set by feedback, the less the corner frequency,
fc or bandwidth. Consider an op-amp with a unit-gain frequency, f1, of 720 kHz. With
feedback the gain may be set to 16 but the resulting bandwidth, f, from Equation (5) is
A(f) f = f1 or 16 f = 720 so f = 45 khz. However if we settled for a gain of only 4,
the bandwidth goes up to 180 kHz. In the case of cascading, connecting two or more
op-amps in series, higher gain may be obtained without sacrificing bandwith. Each op-
amp retains the bandwidth proper to its own gain setting. Since the output of one is the
input to the other, the total gain is the product of the individual gain values. Cascading
two of the op-amps cited above, each configured for a gain of 4 (with corresponding
180 kHz bandwidth) the total gain is 4 x 4 = 16 while still retaining the 180 kHz
bandwidth.
The following activity is to verify this concept of cascading.
ACTIVITY 3-6
1. With the same configuration as in Activity 3-5, set RFA to 16 kΩ. Then with the same
procedure as in Step 3 of Activity 3-5, obtain the corner frequency.
2. Set RFA to 4 kΩ then obtain the corner frequency.
3. Obtain the corner frequency of Op-Amp B.
4. Connect both Op-Amp in cascade by connecting the output of A to input of B.
Measure and record the gain and corner frequency of the combination.

Is the corner frequency of the cascaded amplifiers lesser than the individuals? If
so, consider the effect of slew rate. For a certain input voltage, an increase in gain
corresponds to a decrease in bandwidth. But, for the same gain, with an increase in
input voltage, a lower bandwidth results. In Activity 3-6, we measured the bandwidth of
both with the same input signal and we may had a pretty much the same bandwidth, but
in cascading the two, the input to the other is the amplified output of one, and so the
decrease in the total bandwidth.
APPENDED TOPIC:
Bode plots
2 1/2
The equation Vout = Vin / [1+(/c) ] may be expressed in logarithmic form as
log Vout = log Vin – ½ log [1+(/c) ] . the diagram above is a Bode plot of this
2
equation.
that the two straight line approximations intersect at Vo and C and the oblique line
The X indicate the actual values, the straight lines are the approximation. Note
has a slope of –1. The subscript C stands for corner frequency; for the R–C plot
C = 1/RC . Notice how the Bode plot presents a more detailed picture at the low-
frequency as well as a much broader view in the high frequency region. Quite often the
vertical axis is expanded by a factor of 20, so that decibel units may be used (the value
of V in dB is 20 log V) . With this notation, the value of V changes by – 20 dB as the
frequency increases by a factor of 10.
Activity 3- 7
1. Using the logarithmic value obtained in Activity 3-2, plot them on a log-log graph, or
use the application program BODEPLOT.EXE if it is available.

Generalized Bode Plot
N P
Any function of the form Y(x)=Y0[1+x ] where Y0, N and P are real
constants, may be approximated on a log-log plot by two straight lines, one
horizontal and the other with slope of NP, which intersect at the point [log 1, log
Y0]. To show this, take the common logarithm of both sides of the equation:
log Y(x) = log Y0 + P log [1+xN].
If (x<<1) then,
P log [1+xN] ≈ P log [1] = 0
so
log Y(x) = log Y0
a horizontal line on a log-log graph.
If (x>>1) then,
[1+xN] ≈ xN and log xN = N log x
so
log Y(x) = log Y0 + NP log x
the equation for a straight line with slope NP on a log-log graph.
On a log-log graph, the origin [0,0] is at [log 1,log 1]. Thus, the Y intercept
is at point [log 1, log Y0]. This point satisfies both linear equations, although at
x=1, the true and approximated values differ only by P log 2 or (0.301)P. In our
present application, N = 2 and P = –1/2. For a later treatment of active filters, N =
2, 4,6… .

Op-Amp Time varying input
Name: ________________________________Date:______
Activity 3-1:
f Vp log f log Vp R _____
100 2.80
159 3.00 C ______
251 3.20
398 3.40
631 3.60 fC _____
1000 3.80
1590 4.00 Vin ______
2510 4.20
3980 4.40
6310 4.60
10000 4.80
15900 5.00
25100 5.20
Activity 3-2:
VP-P f at first distortion VO x 2f
2
3
6
8
10
12
Average
rise (V/cm) _____ run (s/cm)_____ slew rate (V/ s) ______
Activity 3-3:

Data Sheet Experiment # EL3-3 continued
Op-Amp Time varying input
Activity 3-4:
Channel Volts/div
Ch #1 Ch #2 f gain f1 / f
10 mV 5V 500
10 mV 2V 200
10 mV 1V 100
10 mV 0.5 V 50
10 mV 0.2 V 20
10 mV 0.1 V 10
Activity 3-5: R1 ______

Rf/R1 VIN VOUT 0.70 x VOUT fc 2fc(Rf/R1)
at 200 Hz
Activity 3-6:
Op-Amp A, gain = 16 fcA-16 __________
Op-Amp A, gain = 4 fcA-4 __________
Op-Amp B, gain = 4 fcB-4 __________
op-amps cascaded :
gain _______________
fc _________________
Activity 3-7: Submit graph

Active Filters
Equipment: Module EL3-D, EL3 Power-source, multimeter, connectors
The decrease of op-amp gain with frequency is due to a built in R-C circuit
configured as a Low-pass filter, as was considered in detail in the preceding
experiment. Even apart from op-amps a simple R-C circuit can serve either as a Low-
pass or High-pass filter. Below is a diagram of a low-pass and high-pass and along
with it is a mathematical analysis and their corresponding bode plots.
If a complex quantity has an expression such as A + jB in the denominator ( A and B

real), multiply the term by its conjugate (A-jB)/(A-jB), to make the denominator real, A2
+ B2 . The magnitude of the complex quantity is the square root of the sum of the
squares of the real and imaginary coefficients. Note that a zero or negative value for
log |Vout| does not mean zero or negative signal. The logarithm of 1.0 is zero, the
logarithm of a number between 0 and 1.0 is negative.
In deriving the basic R-C filter response, it is assumed that the same current
flows through both elements configured as a voltage divider. If Vout supplies current to
a load, the above analysis is no longer valid. But since filters are often supposed to
4: Active Filters 13
deliver an output current, the filter can be coupled to the non-inverting input of an op-
amp which can provide the current (with optional gain). Of course the bandwidth of the
op-amp alone must be greater than the filter frequencies of interest. Such a filter op-
amp pair is an active filter. It is called active since it is coupled to an active device
which can provide amplification to the filtered signal. One filter configuration is shown.
Two or more active filters, with the same or different values of c, may be
connected either in series by cascading, or in parallel, feeding a common summing
amplifier. Two common filter of such arrangements are band pass and band stop.
For band pass the Low and High-pass filters may be cascaded, in any order; for band
stop the filters must be in parallel
Activity 4-1
1. On module EL3-D, with no power supplied, measure C2A, R2A, C2B, R2B with a
multimeter and compute fc = 1/2RC for each op-amp.
2. Configure each op-amp for unity gain by directly connecting output to the ( – ) input.
3. Apply a 0.80 VP-P sine wave; minimum function output frequency, to the input side of
C2A and R2B (just connect them in parallel).
4. Set both channels to 0.2 Volts/div and use channel 1 to monitor the output of Op-Amp A
and channel 2 for B. Adjust the vertical position of channel 1 and set its ground level to
two squares above the middle and channel 2 two squares below then set mode to dual;
that way, we can observe both outputs simultaneously.
5. Notice that every division of the oscilloscope screen is subdivided into five smaller parts,
let’s denote that one small part 1 unit. Gradually increase frequency until either or both
of the two output signals change by 1 unit ( one decreases while the other increases).
Then record that frequency.
6. Repeat step 4 for different signal levels at one unit interval until one reaches the
maximum and the other the minimum. Observe how one signal is allowed to pass while
suppressing the other as we change frequencies.
7. Use the program BODEPLOT.EXE to plot the data. Indicate the values of fc and slope.
NOTE: A decibel is a logarithmic ratio measure of signal, A, to reference signal, Aref.
decibels = 20 log A/Aref
Decibel value, dB, is positive for A > Aref , negative for 0 < A < Aref.
Second order filters

The slope of the slanted portion of the graph line
on the log-log display is either plus or minus one: that is,
a change in frequency by a factor of 10 produces a
change of gain also by a factor of 10 (recall log 10 = 1).
Filters with such a response are called first order. A
second order filter has a log-log slope of 2: that is, a
change in frequency by a factor of 102 produces a change
of gain by a factor of 10. Several possibilities are shown in
the diagram at the right. In (a) the feedback resistor, Rf,
now consists of the parallel R-C pair, which has an
impedance of magnitude R [1+(c)2]-1/2. So as
frequency increases, gain due to feedback decreases in
the same manner as the decrease in signal at the non-
inverting input .
In (b) the two R-C circuits are in series, the output
of one is the input of the other, thus multiplying the effect
of signal decrease with frequency. However note that the
output of the R’-C’ pair is not feeding an infinite
impedance, which complicates somewhat the analysis.
The circuit shown at (c) is an example of a

Butterworth filter. The capacitor of the first R-C pair is not
connected to ground but to the output. While it may
appear strange, yet it has advantages that make it a popular choice among circuit
design engineers.
Butterworth analysis
The generic Butterworth second order configuration is set for unity gain (R1 = ∞,
Rf = 0) and uses two resistors, and two capacitors. The diagram indicates the
admittance, Y, of the components (admittance is the reciprocal of impedance). Notice
that for a low-pass filter, YA is the resistive element and YB is the capacitive while the
reverse is true for a high-pass filter. Both the inverting and non-inverting inputs are at
the output potential, Vo. The symbol, T, is introduced as a convenient abbreviation. We
seek an expression for the filter output, Vo, in terms of the input signal, Vi. At the node
marked V’, and at the non-inverting input apply Kirchoff’s current law, which states that
the current entering a node must equal the current leaving. Recall that the current
through any circuit element is the product of the voltage across the element and the
element’s admittance, Y. For the V’ node:
(Vi.–V’) YA = (V’–Vo)(YA+2YB) or Vi YA= V’ 2(YA+YB) – Vo(YA+2YB)
which may be expressed in terms of T as
Vi = V’ 2(1+jT) – Vo(1+j2T) (1)
For the node at the non-inverting input :
(V’–Vo)YA = VoYB ; V’ = Vo(1+YB/YA) ; V’ = Vo(1+jT) (2)

Substitute (2) into (1) to eliminate V’ :
Vi = Vo(1+jT) 2(1+jT) – Vo(1+j2T) = Vo [(1–2T2) + j(2T)] (3)
Finally take the absolute value of the complex expression (the square root of the sum of
squares of the real and imaginary terms)
|Vi| = |Vo|[ (1–2T2)2 + (2T)2]1/2 or |Vi| =|Vo| [ 1 + 4T4 ]1/2 (4)
This may be expressed in a form suitable for a Bode plot:
log |Vo| = log |Vi| – ½ log [ 1 + 4T4 ] (5)
In this form we recognize the corner frequency, at which [1 + 4T4] = 2. At much lower
4
frequencies 4T <<1, the ½ log term is effectively zero ( log 1 = 0) and at much higher
4
frequencies 4T >>1, it is effectively – 2 log T√2 . Just at the corner frequency, T =
1/√2 , so from the definitions of either Butterworth configuration:
Low-pass:  = 1/(RC√2) = 0.707 (6)
 = √2/(RC)
(1/RC)
High-pass : = 1.414 (1/RC)
Comparing the Butterworth second order filter with a first order filter, the Low-pass
corner frequency is lowered, the High-pass corner frequency is raised, and the slope
of the oblique portion of the approximation line is doubled (40 dB per decade).
Activity 4-2:
1. With no power supplied, measure C2A, R2A, C3A, R3A, C2B, R2B C3B, R3B, use
Equations (6) to compute for the corner frequency for each op-amp. Record the
values.
2. Link C2A to the top of R3A and R2B to the top of C3B. Follow steps 2 through 7 of
Activity 4-1 but apply the inputs to C3A and R3B.
Play it by Ear
Thus far we have considered filters acting on a single frequency. But music and
human speech involve a wide spread of frequencies ranging from near 15 Hz to some
30,000 Hz, from deep bass through mid-band and up to very high pitched treble
sounds. Filters treat each range in a different manner. Sound characteristics, are
perhaps better described by words rather than numbers. Module EL3-D contains a FM
radio receiver and small amplifier for exploring filter action on music.
Activity 4-3:
1. Set the Amplifier Gain to minimum. Connect the FM Receiver OUT terminal to
terminal AB of the AMPLIFIER, and adjust the amplifier gain to a level just
enough for you to hear the FM radio. Tune the FM Receiver to a music station of
your choice. Make a mental note of the sound quality with no filters in use.
2. First order high pass filter: Remove prior connections. Connect the FM OUT
to C2A and configure OP-AMP A for unity gain and connect output to terminal AB
of the amplifier. Describe the sound quality by placing a checkmark in the
appropriate box in the Data Sheet.
3. First order low pass filter: Remove prior connections. Connect the FM OUT to
R2b and configure OP-AMP B for unity gain and connect output to terminal AB of
the amplifier. Describe the sound quality.
4. Second order low pass and high pass filters: Remove prior connections.
Configure both Op-Amps to their second order filter configuration with unity gain.
Connect the FM OUT to the left terminal of C3A and R3B. Connect the output of
Op-Amp A and Op-Amp B to terminals A and B of the Amplifier. Describe the
sound quality.
5. After doing all these, change the gain to a variable one by connect the ( – ) input
to RFA. Try different levels and observe they affect the sound quality. Also try
different combination of filters; set one for second order and the other for first
order. Observe what happens. You may also monitor terminal AB with an
oscilloscope so you can see the waveform of the music you hear.
6. Even the simplest radio or sound system has a volume and tone control. By
means of a block diagram suggest a possible relation between these controls and
the filters described above.
Active Filters
Name: ________________________________Date:______
Activity 4-1:
C2A ____ R2A ____ fcA____ C2B ____ R2B ____ fcA____
Low Pass High Pass
Frequency (Hz) No. of units Frequency (Hz) No. of units
decrement increment
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Activity 4-2:
C3A ____ R3A ____ fcA____ C4B ____ R4B ____ fcA____
Low Pass High Pass
Frequency (Hz) No. of units Frequency (Hz) No. of units
decrement increment
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
Activity 4-3
2: First order high pass filter: Rate the relative sound qualities:
Bass: ‫ٱ‬Soft ‫ ٱ‬Medium ‫ ٱ‬Loud
Mid range ‫ٱ‬Soft ‫ ٱ‬Medium ‫ ٱ‬Loud
Treble ‫ٱ‬Soft ‫ ٱ‬Medium ‫ ٱ‬Loud
3: First order low pass filter: Rate the relative sound qualities:
4: Second order high and low pass filters : Rate the relative sound qualities:
5: Volume and tone controls:
Instrumentation Amplifier
Equipment: Module EL3-E, EL3 Power-source, multimeter, connectors
An ideal voltmeter should be able to measure the difference in potential (voltage)

between any two points in a circuit without changing in any way the circuit currents. To
accomplish this, the meter itself must have a very high input impedance. Often an
op-amp can be used for this purpose
Consider a differential DC amplifier that
is used to measure the voltage across a signal
source. Its gain is expressed as Vout /Vin =
(RF / R1) in which R1 , Rf , R3 and R4 are
related as shown in the diagram. If the signal
source E, has a high internal impedance Rint
and the amplifier has a low input impedance,
then the amplifier will give incorrect results.
Therefore, the input impedance of the
amplifier should be very high compared to
Rint.
In analyzing the circuit shown above, negligible current enters the two op-amp
inputs, thus, the same current I flows from Vout, through all the resistors in series and
into ground. Also, since the inverting and non-inverting op-amp inputs are effectively at
the same potential, we may express Vin as E - I Rint and also as I (R1 + R3) .
Combine these two to eliminate I :
Vin = E (R1 + R3) / (Rint + R1 + R3) (1)
To have Vin approximately equal to E , Rint should be very small compared with
(R1+R3). This is difficult to do because we cannot modify Rint since it is internal to the
system. But we can get around this by increasing R1 and R2 to a very high impedance,
a basic characteristic of op-amps.
Instrumentation amplifier
The instrumentation amplifier circuit
provides dual high impedance differential inputs with
continuously variable gain. Op-amp D is a
conventional difference amplifier, with Vin applied
either at the primed or double-primed resistors, R1
and R3, providing a fixed gain. The dual inputs, V1
and V2 enter the non-inverting terminals of op-amps
A and B; this provides the high input impedance of
5: Instrumentation Amplifier 20
the circuit. The variable resistor, RP, changes the gain of the A, B pair.
Since the + and – op-amp input voltages are effectively equal, the difference of
potential across RP is V2 – V1 . Also since no current enters the op-amp inputs, the
same current, I, flows through RP as through each R. Therefore,
I = (V2–V1)/RP = Vin/(2R+RP)
or
Vin = (V2–V1)(1 + 2R/RP). (2)
Since Vin is the input to the difference amplifier, the overall gain of the instrumentation
amplifier is
Vout = (V2–V1)(1 + 2R/RP) (Rf / R1) (3)
where R1 represents either R’1 or R”1 . If the adjustable resistor, RP, is set to 2R, the
variable gain is two; decreasing RP increases the variable gain. Fixed gain is adjusted
by selecting the primed or double-primed pairs.
A limitation
Notice that in all the op-amp configurations already considered, one or other
input is connected to ground either directly or through a resistor. This is not the case for
op-amps A and B of the instrumentation amplifier. In the circuit shown, the small but
finite input offset currents have no place to go. This introduces instability in Vout. A
solution is to add a path to ground ( direct or through a 250 k resistor) at either input.
Any current produced by the source, E, will not flow through this path to ground but will
return to the source. If Rint is quite large, it may be necessary to provide a path to
ground at both inputs so the input offset currents do not flow through Rint.
Remember also in Experiment 1 Op-Amp Fundamentals there is something
about Common Mode Rejection Ratio. The last part of the activity touches on CMRR
since we are putting together different Op-Amps and the effect of their combined CMRR
should also be considered.
Activity 5-1
1. With no power supplied, measure R’1 , R”1 , Rf , R’3 , R”3 , R4. After measuring,
power up the module.
2. Use the double-primed inputs (R”1 and R”3) and compute the gain RF/R1 of op-amp
D. Use any convenient DC voltage as Vin (but not too high) then measure actual gain
Vout / Vin.
3. Repeat step 2 using the single-primed inputs (R’1 and R’3).
4. With no power supplied, measure R and the maximum and minimum values of RP then
put back the power. Use equation (2) to calculate the maximum and minimum values of
the gain and Vin/(V2–V1) for the actual gain. Remember that for maximum gain, Rp
should be minimum and vice versa.
5. Connect point A to R’3 and B to R’1 . Connect a external 1.5 V or 3.0 V battery in
series with the external voltage (which acts as Voffset) as shown in the diagram below.
Connect terminals e to V2 , f to V1 and g to ground. Record Vout for different values
of Voffset as indicated in the Data Sheet.
Instrumentation Amplifier
Name: ________________________________Date:______
1: R’1 __________ R”1 _________ Rf __________

R’3 __________ R”3 __________ R4 __________
2: [with double-primed inputs] Computed gain _________

Vout ______ Vin _______ Measured gain _________
3: [with single-primed inputs] Computed gain _________

Vout ______ Vin _______ Measured gain _________
5: R _________ RP min _________ RP max __________
Vin / (V2 – V1)minimum Vin / (V2 – V1)maximum

Computed: Computed:
Actual: Actual:
6:
Voffset 0 0.5 1.0 1.5 2.0 2.5
Vout
AC/DC Millivoltmeter
Equipment: Module EL3-F, EL3 Power-source, multimeter, connectors
An ideal voltmeter should have infinite input impedance (no current enters its
terminals); an ideal ammeter should have zero input impedance (no voltage drop
appears across its terminals). Almost-ideal meters are available but are quite
expensive. Low-priced analog (moving pointer type) meters contain a meter movement
of the moving-coil type. A pivoted coil attached to a pointer is mounted within a
permanent magnetic field: any current passing through the coil experiences a force
which moves the pointer proportional to the current. Such meters are not ideal, for the
coil has neither infinite nor zero impedance .
A low-priced bare analog meter movement, (for example, the small meter on
Module EL3-F) has a typical coil resistance of some 200 and requires about 1 mA for
full scale deflection, the so-called full scale deflection current. The voltage needed for
full scale deflection, by Ohm’s law is (0.001 A)( 200 ) = 0.20 volts or 200 millivolts. By
adding a series resistor the full scale voltage reading may be increased (add 19,800 in
series to obtain 20-volt full scale deflection). By adding a shunt resistor in parallel with
the meter, the full scale current reading may be increased (place a 1.00 resistor in
parallel to obtain a 200 milliampere full scale deflection).
Activity 6-1 Basic meter

movement
1: Connect an external variable voltage
source and external ammeter as shown in
the diagram.(RRef is used only for protection)
2: Adjust the variable voltage so that the
meter movement pointer is full scale. The
reading of the external ammeter gives the
full scale current. In this experiment we use this basic
3: Remove the external ammeter. Connect a meter movement and an op-amp to
voltmeter between points a and b. Adjust construct a high impedance voltmeter
again the variable voltage source so that the capable of measuring voltages in the
meter movement pointer is full scale.. The 1/1000 volt range, that is, a
voltage between a and b is the full scale millivoltmeter.
voltage.
4: From Ohm’s law calculate the coil
6: AC/DC Millivoltmeter 24
DC Millivoltmeter
The circuit shown here is basically an op-amp
using negative feedback and input applied to the non-
inverting (+) input terminal, providing a voltage gain of
(1 + RF / R1). Since op-amp input bias current is quite
small the input impedance seen by Vin is very high. The
voltage. Vb, at point b equals the input voltage
multiplied by the op-amp gain, Vin (1 + RF / R1). By
Ohm’s law the current through resistor RS is given by
Vb/RS. The feedback path resistance, RF+R1 ,is
normally many thousand times RS, so, effectively, the
entire op-amp output current, Im, passes through both the meter movement and the
resistor, RS:
Im = Vin (1 + RF/R1)/RS (1)
As an example, suppose the gain expression, (1 + RF / R1). is 10 and RS =
10 Then an input voltage, Vin, of 1 millivolt produces a current through the meter
movement, Im, of one milliampere, a typical full scale deflection current. We then have
a sensitive millivoltmeter with a high input impedance.
Activity 6-2: DC Millivolt meter
1: Without any power supplied, measure RDC, RF and RS. Take R1=RDC and calculate the gain
factor, (1 + RF/R1) / RS.. Apply power to the module.
2: Connect the circuit shown above for a millivoltmeter, with R1 as RDC on the module. Make
sure that point a is connected to the + side of the meter and point b to the – side.
3: To provide an input voltage in the millivolt range, apply a variable voltage supply through the
100 K and 10  to the + terminal. The voltage divider is set such that it will convert a 10 V
voltage divider provided at the left side of the module. Then connect the junction between the
input down to 1 mV.

4: Set the variable input voltage to 0 V then adjust the Null Offset so that the meter in Module
EL3-F also reads 0 V. Next, set the input voltage to the values indicated in the Data Sheet and
record the meter reading and the percent difference.
[The percent difference can be can be obtained by ((input – meter reading)/input) x 100.]
AC Millivoltmeter
Op-amps respond to DC as well as AC. However an alternating voltage applied to the
meter coil could cause the needle to swing back and forth. Therefore to make our circuit
respond to AC, the meter movement is inserted within a full-wave diode bridge is placed
around
The meter coil is actually driven by the average current driven through it. For full-
wave rectification Iaverate = (2/) Ipeak . Also AC meters normally display root-mean-
square (RMS) rather than either peak or average values: V RMS = (2–1/2) Vpeak . Of
course Eq (1) holds at every instant, so it is also true for the moment of peak values:
Ipeak = Vpeak (1 + RF/R1)/RS (1)
and substituting for peak values we obtain
Iaverage (/2) = VRMS (21/2) (1 + RF/R1)/RS
Iaverage = VRMS (23/2 / ) (1 + RF/R1)/RS
(2)
(3)
The factor (23/2 / )=0.90 so the AC gain is only 90% that of the DC gain (1+RF/R1)/RS .
To increase the AC gain we might either increase RF or decrease RS or R1 . In the
module only R1 is decreased for AC operation.
Activity 3-3 AC Millivolt meter

1: Measure RAC, Rf and RS. Use R1=RAC and calculate the gain factor, (1 + Rf/R1) / RS.
2: Use the same circuit connection as in Activity 3-2 but with R1 as RAC . Connect points a
and b to the bridge terminals marked with ~ . Connect the + meter terminal to D and the
– terminal to C.
3: As signal source use the multi-tap AC source in the EL3 Accessory Module ,
connected through the voltage divider network
4: Start with the 0 tap of the Accessory Module, and adjust the Null Offset so that the
module meter also reads 0 V.
5 Repeat for the other voltage taps of the EL3 Accessory Module
Millivoltmeter
Name: ________________________________Date:______
Activity 6-1: Full-scale current

Im (Full Scale) ____________
Activity 6-2: DC Millivolt meter

RDC ____________ RF ____________ RS ____________
(1 + Rf/R1) / RS ______________
VIN mV VMETER % diff. VIN mV VMETER % diff.

0.1 0.6
0.2 0.7
0.3 0.8
0.4 0.9
0.5 1.0
Activity 6-3: AC Millivolt meter

RAC ____________ RF ____________ RS ____________
(1 + Rf/R1) / RS ______________
VIN mV VMETER % diff.

0.3
0.6
0.9
1.2
1.5
Digital to Analog Converter
Equipment: Module EL3-G, EL3 Power-source, multimeter, connectors
Humans count with

base 10 numbers, that is, Decimal (base 10) Binary (base 2)
only 10 symbols or digits
are used, 0, 1, 2,…, 9 . 730,245 101011
Computers count with base
2 numbers, only two 5 x 100 = 5 1 x 20 = 1 x 000001 = 1
1
symbols ( BITS or Binary 4 x 10 = 40 1 x 21 = 1 x 000010 = 2
digITS) are used, 0 and 1. 2 x 102 = 200 0 x 22 = 0 x 000100 = 0
0 x 103 = 0 1 x 23 = 1 x 001000 = 8
Larger numbers are
3 x 104 = 30,000 0 x 24 = 0 x 010000 = 0
expressed in multiples of 7 x 105 = 700,000 1 x 25 = 1 x 100000 = 32
the base. The computer 32
parallel port output total = 730,245 total = 101011 = 43
presents numbers in binary
mode.
One application of an op-amp is a digital

to analog converter, a circuit that converts
binary digital output into corresponding analog
voltage levels. Such a circuit is basically a
summing op-amp and a resistor ladder network.
The Ladder Network

Referring to the diagram at left, a ladder
network is composed of any number of joined
identical segments and a single terminator. A
segment has three ports, IN, OUT and Gnd
(ground). Resistance between IN and OUT , RIN-
OUT , is R, while resistance between IN and Gnd,
RIN-Gnd , is 2R. The terminator has no OUT port,
and RIN-Gnd = R . What is special about this
network is that the resistamce to ground, RIN-Gnd,
of a segment joined to a following terminator is
the same as that of a terminator alone. So we
may join together more and more segments, and
the input resistance value, R, is unchanged
provided that the last element is a terminator.
Activity 7-1 will verify this concept.
7: Digital to Analog Converter 28

Activity 7-1 Ladder network
1: Set all bit switches to “0” position and connect the terminator resistor (node G) to the free
node of segment F ( node adjacent to node G).
2: Measure and record the resistance from node F to ground. Next place a link across F
and the free end of segment E and measure the resistance from node E to ground. Repeat
for D, C, B and A without removing previous links already placed.
Such a ladder network really has effectively only two terminals, IN and the
common Gnd. A current, I0, entering at IN must leave the network and enter ground,
but the amount of current leaving through the various Gnd terminal will differ.
As shown in the diagram at right,

the incoming current, I0, at node A
sees two paths to ground, one through
2R to A’, the other through the
series combination of R and the
remaining ladder network, with
resistance to ground of R. Since both
outgoing paths at A have the same
resistance to ground, 2R, I0 divides into two equal parts. The same equal division of
incoming current happens at nodes B and C.
The Summing Op-Amp
Notice that the relationship between currents across each segment is the same
as that of a binary number, the weight of each binary bit is half the weight of the
proceeding bit and twice the weight of the bit following. In a ladder network, the Most
Significant Bit , MSB is represented by the segment with the largest current (IO/2 at
segment A) and the Least Significant Bit, LSB, by the least current (IO/64 at segment
F). Therefore to evaluate a binary expression, let each bit control a two-way switch at
nodes, A’, B’, C’, … If the bit is 0 the current goes directly to ground; if the bit is 1, the
current is sent to the virtual ground input of a summing op-amp as shown in the
diagram below.
Since both input terminals of an op-amp, configured for negative feedback, are
always at the same potential and here the (+) terminal is grounded, the (–) terminal is
also at ground potential, the virtual ground. Also no current enters the inverting (–) op-
amp input, so the entire current from the ladder network passes through the feedback
resistor, R, and equals the op-amp output voltage divided by R. This current is
determined by the individual bit switch settings, so we have a digital to analog converter

The total input current from the 6.40 V reference source, I0, has a magnitude of
6.40/R , for R is the resistance to ground of the ladder network. At each node, A,…F,
half the incoming current goes down to ground, and half moves on horizontally. If all the
bit switches are in the 0 position, the entire current goes to the “real” ground, nothing to
the op-amp. If all are in the 1 position, I0/2 + I0/4 + I0/8 + I0/16 + I0/32 + I0/64 = 63/64I0
gets to the inverting input of the op-amp, the virtual ground, while 1/64 I0 flows to the
real ground, through the terminator. Since no current enters the op-amp’s inverting
input, which is effectively at ground potential in this case, it all flows through the
feedback resistor, R, so the op-amp analog output is 63/64 I0 R. Substitute the value of
I0 to get an output of 63/64 [6.40 /R] R = 6.30 volts.
So the analog output never quite equals the reference input . If the digital value
to be converted has N bits (in our case N = 6), the maximum output voltage, VMAX is
VMAX = Vreference (1 – 2–N)

The output will be at one of 2N possible levels, and these level step sizes are
N
Vreference / 2 .
Activity 7-2 D-A Converter

1: With the same connections as before, connect P to A. Set reference voltage to 6.40
volts, as measured between node A and ground.
2: Measure the voltage between node A and ground with the bit switch marked as 25 in the
1 and 0 positions. Repeat for nodes B to F, with the corresponding bit switch in both
positions.
3: Set the bit switches to the patterns shown on the Data Sheet, calculate the decimal
equivalent of the binary number, and measure the corresponding voltage at the analog
output.

Digital to Analog Converter
Name: ________________________________Date:______
Activity 7-1: Ladder network

F E D C B A
Activity 7-2: D-A Converter

Bit switch A B C D E F
0
1
bit decimal analog bit decimal analog

pattern value output pattern value output
000000 010101
000001 101010
000010 100000
000011 010000
000100 001001
000101 011101
000110 100110
000111 001101
001000 010010
001001 110011
001010 010000
001011 010001
001100 111101
001101 110000
001110 110101
001111 110001

1211212
Positive Feedback
Equipment: Module EL3-H , EL3 Power-source, two multimeters, connectors
Previous experiments considered op-amps in a negative feedback circuit. There are
also useful op-amp circuits using positive feedback or no feedback at all (open loop)..
In previous negative feedback analysis we often used the principle that both inputs are
at the same potential, and were careful that Vout never reached the negative or positive supply
voltages, V+ or V– . It is different with no feedback or positive feedback.
negative feedback
+ and – inputs always equal + and – inputs never equal
V– < Vout < V+ Vout = V– or V+
input offset current ≈ 0
With positive feedback we move from analog circuits ( signal may vary continuously
over a given voltage range ), and enter the world of digital circuits ( signal may assume only
one of two discrete levels, high or low ).
Negative Feedback
Before taking a closer look at positive feedback, it may be helpful to summarize what
has already been seen regarding negative feedback.
In applications Vref and Vin may be interchanged.
8: Positive Feedback 32
The levels for the saturation voltage, Vsat are normally a volt or two less than the
corresponding positive and negative supply voltages and their absolute values may not be
exactly the same. The output, Vout, can never exceed Vsat .
Activity 8–1 Negative Feedback

1: Use op-amp B . Use RB2 as R1 and RFB1 as Rf . Measure R1 and Rf.
2: Measure ± Vsat . Connect (+) input to the variable voltage source, Vin . Connect (–) input
to ground. Increase Vin to maximum positive value and measure Vout as + Vsat. Decrease Vin
to maximum negative value and measure Vout as – Vsat.
3: Connect RB2 as Rf between the (–) input and Vout . Connect RFB1 as R1 between the (–) input
and Vref. Connect the (+) input to Vin. Set Vref to 4.00 volts.
Vary Vin from –8.00 volts to +8.00 volts in 1.00 V steps and measure corresponding values for
Vout . For each change in Vin make sure Vref remains at 4.00 V . Display results on a graph.
Compare the slope of the graph line with [1 + Rf/R1] . Compare the vertical axis intercept with
–Vref[Rf/R1].
4: If Rf = 0, what effect does Vref have on the output Vout ?
No Feedback
With no feedback Vout equals +Vsat if

the voltage at the inverting input, V(–) , is less
than that at the non-inverting input, V(+).
Otherwise Vout equals –Vsat. In the diagram
Vref is shown as positive.
Activity 8-2 No Feedback

1: Use op-amp A . Connect the (+) input to Vref, and the (–) input to Vin.
2: Set Vref = +3.00 V. Vary Vin from –8.00 volts to +8.00 volts in 1.00 V steps and measure
corresponding values for Vout For Vin ≈ 3.00 view Vout on an oscilloscope. There is a small
amount of 60 hertz noise at Vin. and Vref due to the power lines, which causes rapid
change or fluctuations in Vout
3: Sketch a graph of output, Vout ,versus input, Vin.
Positive Feedback
Vref = 0
In many positive
feedback configurations the
feedback resistor, Rf, is
connected between the op-amp
output, Vout, and the non-
inverting (+) input. Since Vout
equals either +Vsat or –Vsat , it
follows that the voltage at the
have two different values, ± V, as shown above ( Rf and R1 form a simple voltage
non-inverting input, V(+), can
divider between Vout and ground). If Vin increases starting from a large negative value,
then Vout = +Vsat and the output transition to -Vsat occurs at +V. If, however, Vin
decreases, starting from a large positive value, then Vout = –Vsat and the output
transition back to +Vsat occurs at –V.
Activity 8-3 POSITIVE Feedback Vref = 0

1: Use op-amp A . Use RA2 as R1 and RFA1 as Rf . Measure R1 and Rf.
2: Measure +Vsat and –Vsat, and from these values calculate +V and –V.
3: Connect RA2 between the non-inverting input, (+), and ground.
Connect RFA1 between the non-inverting input, (+), and Vout .
Connect the inverting input, (–), to Vin.
4: Vary Vin from –8.00 volts to +8.00 volts in 1.00 V steps and measure corresponding
values for Vout. Next vary Vin from +8.00 volts to –8.00 volts in –1.00 V steps and measure
colors for each graph line). On the same graph draw vertical lines at ± V.
corresponding values for Vout . Plot both sets of values on the same graph (use different
Positive Feedback
Vref ≠ 0
If a reference voltage, positive
or negative, Vref, is applied to R1 the
pattern is shifted right or left. As
always, if V(–) < V(+) then Vout =
+Vsat. Use the principle of
superposition to verify the expression
for V(+) the shown in the diagram.
Activity 8-4 POSITIVE Feedback Vref ≠ 0
1: Use op-amp A . Use RA2 as R1 and RFA1 as Rf . Measure RA2 and RFA1.
2: Connect RA2 between the non-inverting input, (+), and Vref.
Connect RFA1 between the non-inverting input, (+), and Vout .
Connect the inverting input, (–), to Vin.
3: Set Vref = 3.00 volts. Measure +Vsat and –Vsat, and calculate +V and –V and VR
.
4: Vary Vin from –8.00 volts to +8.00 volts in 1.00 V steps (Maintain Vref = 3.00 volts) and
measure corresponding values for Vout. Note that Vout may remain unchanged over
several input steps. Next vary Vin from +8.00 volts to –8.00 volts in –1.00 V steps and
± V
measure corresponding values for Vout . Plot both sets of values on the same graph (use
different colors for each graph line). On the same graph draw vertical lines at and
VR.
Bi-Stable Element R-S FlipFlop

In the positive feedback configurations already
considered, Vin and Vref always had definite values
and neither input was “floating” or not connected. It is
also possible to build a circuit with a certain degree of
“memory”, so that even with “floating” inputs, the
output remains at the last input state.
If the Reset input is floating, V(–) = 0 (apart from any small

’
voltage drop due to input bias current through R 1) ; if the Set
input is floating , V(+) = ±Vsat R1 /(R1+Rf).
If a High voltage ( greater than Vsat R1 /(R1+Rf ) ) is applied
briefly to the Set input, Vout = +Vsat and remains in this state
even after Set becomes floating: a High voltage applied briefly
the Reset input makes Vout = –Vsat. If a Low voltage (less
than –Vsat R1 /(R1+Rf ) ) is applied to Set, then Vout = –Vsat.
However if both inputs go High or Low at the same time the
output is indeterminate.
This circuit configuration popular in digital electronics, is known as
an R-S FlipFlop. The conventional circuit symbol is shown. The Q
corresponds to Vout and Qˉ ( “Q-bar”) is the electrical opposite of Q.
Activity 8-5 R-S FlipFlop
1: Using Op-Amp A, Connect the circuit shown above for the RS Flip Flop, where RF is the
series combination of RFA1 and RFA2, R1 is RA2 and R’1 is RA1. Take the Set input as V(+)
and the Reset input as V(–).
2: Set VIN = +10 V and VREF = –10 V and use these as High and Low inputs respectively.
3: Apply High and Low inputs to the Set and Reset terminals of op-amp A, as indicated in
the Data Sheet.
4: Apply High and Low inputs to the Set and Reset terminals of the R-S Flip-Flop diagram
on the module, as indicated in the Data Sheet.
R-C Circuits
For the R-S Flip-Flop, changing the Reset input between High and Low changes
the output in the opposite direction. If the output were fed back into the input , perhaps
with some fixed delay, would it be possible for the output to continuously switch
between high and low levels? A capacitor charging and discharging through a series
resistor might provide the fixed delay. Consider two different ways of charging /
discharging the pair.
The square-wave source provides a constant voltage that reverses each half
cycle. In both circuits shown above, the same current flows through C and R. The
magnitude of the voltage across the R-C combination is constant for the constant
voltage circuit: As the voltage across R increase, that across C decreases to maintain a
constant sum. The capacitor charges and discharges exponentially.
In the constant current circuit with negative feedback, the voltage at the (–)
input is effectively zero, so the magnitude of the voltage across R and the current
through R are constant; the capacitor charges and discharges linearly. These two
different approaches will be used in the basic clock circuit and basic ramp circuit.
Activity 8-6 R-C Circuits
Constant voltage
1: Measure and record the value of the capacitor, C.
Connect the variable resistor, R, between the function generator ( frequency = 500 Hz ) and
the capacitor, C.
Connect the free sides of the function generator and the capacitor to ground.
2: Adjust the square wave amplitude to 8.0 volts, peak-to-peak, as measured by an
oscilloscope.
3: Connect the oscilloscope across the capacitor to display VC. Adjust R to maximum
resistance. Record the oscilloscope display.
4: Describe how the display changes as R is varied.
Constant current
5: Connect the variable resistor, R, between the function generator ( frequency = 500 Hz )
and the (–) input of op-amp A. Connect the free sides of the function generator and the op-
amp (+) input to ground. Connect the capacitor, C, between Vout and the (–) input of op-
amp A. .
6: Repeat steps 2 to 4
Basic Clock
The basic clock circuit uses both positive and negative feedback. The positive
feedback makes Vout = ±Vsat and
V(+) = ±VsatR1/(R1 + Rf). The
negative feedback circuit alternately
charges and discharges C through R.
In the diagram VM represents the
maximum voltage the capacitor can
attain.
However the capacitor switches
between charge and discharge

whenever V(–) = V(+) so the
capacitor voltage never attains ±VM.
This transitional voltage level, VT, is
±VsatR1/(R1 + Rf). From the
diagram below, it follows that while
charging, VM = Vsat–(-VT) = Vsat +
VT and while discharging VM = VT –(–Vsat) = Vsat + VT. The charge and discharge
cycles have the same VM (assume the positive and negative saturation voltages have
the same magnitude). Again referring to the diagram, the charging / discharging
continues until the capacitor voltage has changed by 2 VT. Represent this time for this
change by the symbol H, one-half the basic period of the clock. We seek an
expression for T ( =2H), the basic clock period.
2VT = [Vsat–VT][1– e–H/RC] move e–H/RC to left side
e–H/RC = [Vsat–VT] / [Vsat+VT] = [1 – VT/Vsat] / [1 + VT/Vsat]
e–H/RC = [1 – R1/(R1+Rf)] [1 + R1/(R1+Rf)] from definition of VT
e– H/RC = Rf / (2R1 + Rf) Next, take the reciprocal of each side
H/RC
Period = T = 2H = 2RC ln(1 + 2R1/Rf)

Notice that the basic clock circuit contains only four passive components, 3
resistors and a capacitor. The clock period (and frequency) depend on the value of each
component. The voltage at Vout is a square wave; the voltage V(+) at the non-inverting
input is an exponential rise and fall.
Activity 8-7 Basic Clock

1: Use op-amp A. Measure C, RA1, RFA1, RFA2.. Use RFA1 and RFA2 in series as Rf. Use RA2 as
R1.
2: Connect Rf between Vout and (+) input. Connect RA1 between (+) input and ground.
Connect C between (–) input and ground. Connect R between (–) input and VO.
3: Test #1: Adjust R for maximum resistance. Measure period, T, and compute by formula
4: Test #2: Adjust R for minimum resistance. Measure period, T, and compute by formula
5: Test #3 and #4. Use RFA1 and RFA2 in series as Rf and repeat Tests #1 and #2 above.
Basic Ramp
The constant current configuration of Activity
#6 illustrates a triangular wave generator. The
period was controlled by the square wave input
signal. Such a triangular waveform may be viewed
as a sequence of ascending and descending
ramps. The basic ramp circuit is shown. The
feedback mode is negative.
If Vref < 0 the output voltage, Vout , increases while the (–) op-amp input
remains at ground potential. A positive Vref causes Vout to decrease. Of course as
Vout reaches ±Vsat there is no further charging / discharging of capacitor, C. The
charge / discharge rate (volts / second ) is linear since the op-amp is in a constant
current configuration, with I = Vref / R.
Let Q represent the change in capacitor charge during the time interval, t.
Q = I t. = (–Vref / R) t
The capacitor voltage, VC, ( = Vout ) is Q / C so Vout = Q/C . Combine these to get
Vout / t = – Vref / RC and dVout/dt = – Vref / RC
Triangular wave generator

If an additional positive feedback stage is
added to the basic ramp configuration, a
portion of its output can serve a ±Vref so
the circuit can oscillate by itself. Notice in
the diagram that op-amp A uses negative
feedback while op-amp B uses positive
feedback. Since the (+) and (–) inputs of op-
amp A are both at ground potential, Vout-A
equals the capacitor voltage, VC. Vout-B
equals ±Vsat and it switches between positive and negative whenever the (+) and (–)
inputs of op-amp B are zero.
Let VT be the value of Vout-A when

this switching occurs. Since the same
current flows in R1 and Rf, it follows that
VT / R1 = ±Vsat / Rf or VT = ±Vsat
(R1/ Rf) . From the graph it is clear that
the magnitude of the slope is (2VT)/(T/2)
or 4 Vsat (R1/ Rf)/T . For the basic ramp
we found an alternate slope expression,
Vref / RC . For our circuit Vref is some
fraction, k, of Vsat or Vref = k Vsat.
(slope) 4 Vsat (R1/ Rf)/T = k Vsat / RC

and
(triangular wave period) T = 4 RC (R1/Rf) / k.
Activity #8 Triangular wave
1: Measure and record RB1, RFB2, RFB3, C.
2: Configure the circuit for the triangular wave generator shown above where R
is the variable resistor R, RB1 as R1, RFB2 as Rf. Use Op-Amp A, Op-Amp B
and the potentiometer provided below Op-Amp B on the module.( Vout-B to P,
Q to free end of R) Monitor with an oscilloscope VOUT-A.
3: Vary Vf by adjusting the potentiometer and describe the amplitude and
period change in the ramp signal at VOUT-A.
4: Vary R and describe amplitude and period change in ramp signal.
5: Test #1 Set Vf = Vsat (in this case k=1.0) Set R to maximum resistance
(remember: always isolate R to measure resistance with a multimeter). Measure
period by using the frequency range of the multimeter and also compute
theoretical value.
6: Test #2 Set Vf = ½ Vsat or k = 0.5 and repeat Test #1
7: Test #3 Repeat Test #1 with Rf = RFB2 + RFB3.
8: On which variables does the signal amplitude depend?
Positive feedback
Name: ________________________________Date:______
Activity 8-1 Negative Feedback
R1_____ Rf.______ + Vsat ______ – Vsat ______
Vin -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0
Vout
Vin 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Vout
[1+Rf/R1] ____ Slope____ Vref[Rf/R1] ____ Intercept _____
If Rf = 0________________________________________________
Activity 8-2 No Feedback
Vin -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0

Vout
Vin 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Vout
Activity 8-3 POSITIVE Feedback Vref = 0

R1_____ Rf.______ + Vsat ______ – Vsat ______ + V_______ – V_______
Vin -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0
Vout
Vin 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Vout
Vin 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0
Vout
Vin –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0
Vout
Activity 8-4 POSITIVE Feedback Vref ≠ 0
R1____ Rf.____ + Vsat ____ – Vsat ____ + V____ – V_____ VR______
Vin -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 -1.0
Vout
Vin 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Vout
Vin 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0
Vout
Vin –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 –7.0 –8.0
Vout
Activity 8-5 R-S FlipFlop

For op-amp A For R-S diagram
S R Q Qbar S R Q Qbar
↑ --- ↑ ---
↓ --- ↓ ---
--- ↑ --- ↑
--- ↓ --- ↓
Activity 8-6 R-C circuits C ________

Constant voltage Constant current
Amplitude: Amplitude:
volts/cm_____ volts/cm____
Time: Time:
msec/cm____ msec/cm___
Display change with R ?: Display change with R ?:
Activity 8-7 Basic Clock

C _______ RA2 ________ RFA1 _______ RFA1+FA2. _________
Test R1 Rf R T(measured) T(computed)
#1
#2
#3
#4
Activity 8-8 Triangular wave

C _________ RB2 __________ RFB2 ___________
RFB3 ________ Vsat. _________
Change in Amplitude / period with change in V f ________________
_________________________________________________
Change in Amplitude / period with change in R ________________
_________________________________________________
Test Vf Rf R T(measured) T(computed)

#1
#2
#3
#4
On which variables does the signal amplitude depend? ____________
Analog to Digital Converters: Part I
Equipment: Module EL3-I, EL3 Power-source, multimeter, connectors
Real world measurements, apart from counting, are mainly analog . Various forms of
transducers express a measured quantity as a voltage continuously variable over some
given range, which may be displayed as the angular deflection of an analog meter pointer or
the pen position of a chart recorder. But microprocessors communicate in binary digital (0 or
1) not analog, form; also newer hand-held multimeters display results in decimal digital (0…9)
forms. This is the field for A/D or Analog to Digital converters.
The difference in displays, as indicated above, is similar to the difference between a

ramp and a stairway. Moving along a ramp you can be at any height above ground; going up
stairs you can be at only certain fixed heights above ground, depending on the step size. In the
diagram above, any input voltage value in the range 0.5 <= Vinput < 1.5 gives the same digital
display of 1. Of course each digital value could signify tenths of a volt, millivolts, kilovolts, etc. ,
depending on the external circuits. The number of discrete values depends on the number of
digits used: 3 decimal digits can display 1000 ( =103) values from 000 to 999 ; 3 binary digits
(bits) can display 8 ( = 23) values from 000 to 111.
Basic conversion process

An analog-to-digital conversion process involves a control counter, a comparison
voltage generator, and a voltage comparator. The diagram below outlines this process.
9: Analog to Digital Converters: I 44

Basically, the conversion process is a cycle of guessing a value which stops only when
guest value equals the input. An initial digital number from the control counter is fed to the
comparison voltage generator which produces a proportional voltage. This voltage is then
compared with the external voltage to be converted. Depending on the comparator output, +
or –, either a new digital number is selected by the control counter and the process repeats,
or the process terminates and the current counter content is sent to the display.
In this experiment, two approaches will be considered in studying A/D converters and
they differ in:
A: how the control counter selects the next digital value, and
B: how the comparison voltage is generated.
Selecting the next value

Supposing you were to guess a two-digit decimal value. The smart way to do this is
to pick the first number as 50, the mid-range between 00 and 99. Depending on whether the
picked number is above or below the unknown value, pick the next number as either 25 or 75.
Then repeat the process. After eight tries, at most, two adjacent numbers are obtained, one
less than and the other greater than (or equal to) the unknown value. This is the
successive approximation method.
The dumb way is to pick the first number as 1. Depending on the comparison result,
either pick the next number as 2 (incrementing the prior number by one) or stop the process if
the values are equal. The number of trials can vary between 1 and 99. This is the
sequential method and is certainly slower than the successive approximation, but it is also
simpler.
In the block diagram above, the selected number and the unknown are represented by
the output of the comparison voltage generator and the external voltage, respectively. The
equality of the selected and unknown values is determined by the comparator: low if equal
and high if otherwise. A high output tells the counter to generate a new value; a low ends
the process.

Generating the comparison voltage
With the sequential (dumb) method, the comparison voltage may be generated by:
A) A ladder network in which a binary counter selects various taps on a ladder
network to produce, in sequence, the comparison voltage values.
B) A ramp voltage with a given slope (voltage versus time) which, at sequential time
intervals is compared with Vinput . The comparisons stop once the ramp voltage
exceeds Vinput.
In this experiment we analyze in detail the ladder network method, and also study the
operation of a commercial chip, ADC0804, which uses successive approximation. The ramp
approach is explored in Analog to Digital Converters: Part II.
The Counter
The counter used with the ladder network is a 74LS390 with (dual sets of) four digital
outputs, “weighted” as 8, 4,2 and 1. A high output voltage level (close to 4 volts) represents a
binary one, a low level (less than 1 volt) represents a binary zero. Two inputs of interest are
clock and clear; the clock input is negative edge-triggered,
that is, the action is performed only when the signal goes from
a high to low level. A clock input advances the binary count by
one unit. After a count of nine, 1001, the next count is back to
zero, 0000. The clear input is level sensitive, active high, that
is, as long as the input is high, all counting ceases, and all four
digital outputs are set low.
The four counter outputs, either high or low, are displayed by individual LEDs (Light
Emitting Diode). The output is also fed to a 74LS47 , which controls the 7-segment decimal
digit display.
Ladder Networks
A previous experiment on
D/A converters explained the
basic ladder network formed
by one or more segments
and a terminator, each or
resistance R. The input
resistance to a terminated
ladder network with any
number of segments is R . A
current entering any segment
divides equally, half to ground, half continuing to the next segment (or the terminator).

In previous experiments we focused on currents
ina ladder network; here we look at voltages. In the
diagram above, the voltage drop between nodes B and
C, VBC, is one half VAB and twice VCD. So a ladder
network may be used as a special form of voltage divider
since the relationship of voltages across each segment
is similar to the binary counting system. The resistance,
looking into a terminated ladder network, is always R .
In the ladder network we considered in
Experiment EL3-7, Digital to Analog Converters, the
input current is at the end opposite the terminator and
we took the output currents at the legs of each segment.
Thus, we had a single-input, multi-output network. In
this experiment the reverse is true. We provide the input
currents at the legs of each segment and take the output
at one end. Thus, we have a multi-input, single-output
network.
In this experiment we use a modified ladder network which is completely symmetric,

and in which current may enter through one or other terminal formerly connected to ground.
Referring to the diagram above, Node E, viewed from the left, presents a terminated
ladder network. Likewise the views from the left for nodes D, C and B also present
terminated ladder networks. And because the network is completely symmetric, the same is
true for nodes B, C, D and E as viewed from the right.
If A’ is disconnected from ground, its resistance through the network to ground is 3R,
the series combination of two R resistors (between A’ and A, and between A and B) and a
terminated ladder network as viewed at B. Likewise if B’ is disconnected from ground, its
resistance through the network to ground is also 3R. Looking left from B there is the series
combination of two R resistors; looking right from B there is the series combination of R and
a terminated ladder network. The parallel combination of these two 2R branches gives a
resistance of R, which added to the 2R between B’ and B gives a total of 3R resistance
between B’ and ground. Similar results follow for all other nodes C’, … , F’.

If any ground node, for example, C’, is connected to a voltage source 3V (other ground
nodes remain connected to ground) the input current is I0 = 3V/3R = V/R. The voltage drop
across the 2R resistor between C’ and C is I0 2R = (V/R) 2R = 2V so the voltage at C,
with respect to ground, is V. Now since the current I0 entering node C divides equally (half
left, half right) the voltage drop between C and either of its adjacent nodes, B or D, is (½
I0)R = ½ V. And since the current entering any node from left or right divides equally (half
forward, half to ground), the voltage at A and E (each two nodes away from C) is ¼ V.
These results are shown in the following table.
Neatly divided voltages are available at node B, depending on where the 3V constant
voltage is applied.
3 V applied at voltage at B
B’ V
C’ ½V
D’ ¼V
E’ 1/8 V
F’ 1/16 V
Notice the difference between the ladder networks here and in the prior experiment. There
the lower end of every 2R resistor was grounded (real or virtual) and a constant current
entered the un-terminated end of the ladder. Here a constant voltage is applied to one (or
more) of the un-grounded 2R resistors.
Recall the superposition theorem considered in experiment EL1-8.
The superposition theorem states that in a resistive

network with two or more voltage sources, the current in any
branch (or voltage at any node, with respect to the ground
node) is the algebraic sum of the currents in any branch (or
voltages at any node) measured one at a time with one voltage
source present and all other voltage sources replaced by a
short circuit.
Apply this to our present case and the table-data shown. For example, if 3V is applied
to both C’ and F’, the voltage at B is (½ + 1/16) V; if 3V is applied at the same time to C’,
D’, E’, and F’, the total voltage at B is (15/16) V. This modified ladder network is actually
a digital to analog converter, in which a four-bit binary number determines to which nodes
the 3V is applied..

Activity 9-1: Ladder network voltage generator
1: On the module, isolate the ladder network by removing all connecting links and
measure the exact value of each resistor.
2: Connect nodes B’, C’, …, F’ to ground and measure RA’ the resistance
between A’ and ground. Repeat for each following node, B’, C’, … .
3: Apply voltages to the indicated nodes, and record voltage VB at node B.
The complete converter

The diagram shows
how all components fit
together (note the ladder
network turned upside
down) . The AND gate
provides a high voltage
output at c if and only if
both a and b inputs are
high. In this module the
comparator supply voltage
is +5.00 and 0.00 volts, so
a high output is close to
5.00 volts and a low close
to ground. The ladder is
connected to the counter by
links at B’,…,E’.
Node B is used as
the output of comparison
voltage generator and since
the maximum voltage at
ladder node B is about
one volt the analog voltage
to be converted, Vinput, is normalized (V’) by passing it through a voltage divider.
Pressing clear sets B’, C’, D’ and E’ to zero, so the voltages at B and the
comparator inverting input, (–), are also zero. If V’ is greater than zero (assuming there is an
input) the comparator output is high (LED lamp lights). The pulse produced by pressing and
releasing the count button can pass through the AND gate since inputs at a and b are both
high, as indicated by the adjacent LED; The trailing edge of this pulse, entering the binary
counter, increases the counter total to 0001, and the decimal digit is changed to 1. The

Activity 9-3 Automatic counting
1: Press clear. Set VIN to minimum. Switch to AUTO. Monitor the + and – inputs of the
comparator with an oscilloscope set to DUAL mode.
2: Next slowly increase VIN stepping through the digit display from 0 to 9,and measure
and record the voltage at node B just as the display digit increases. (you may need a bit
of practice to get exact readings). This process is a one way trip; it only works with
increasing input, if you make a mistake start back to zero. Observe the how the voltage +
and – levels exceed each other in the oscilloscope as you increase VIN.
voltage at E’ goes to 3 volts, at E to 1 volt, and at B to 1/8 volt. If this is less than V’, the
comparator’s output is still high, so pressing again the count button repeats the process and
the binary counter advances to 0010 and the decimal display to 2. The process continues until
the voltage at B is greater than V’. The comparator’s output then goes low, which closes the
AND gate; pulses from the count button can no longer reach the counter. The final binary and
decimal display is the converted Vinput .
Of course in commercial counters, pushing a count button is done automatically and

more than four binary digits are normally used. In this module counting is done manually so
the step-by-step operation is easier to understand.
Activity 9-2 The manual A / D counter

Note: connecting / disconnecting a voltmeter at certain terminals can produce random transient pulses,
causing the counter to advance erratically. This is because the comparator is very sensitive. Avoid
unnecessary contact with the terminals.
1: Connect B to the (–) input. Connect B’, C’, D’ and E’ to QD, QC, QB, QA respectively.
Connect A’ and F’ to ground. Apply approximately 9 volts at VIN . Monitor node B with a
multimeter. Switch to manual.
2: Press clear to clear the counter (it should display a zero), then with the count button step
through the full counting range. As you keep counting measure and record voltage levels at
node B.
3: Press clear. Set VIN to some value less than 9 V, say 5 V, and press clear. In this
condition the comparator’s (+) input is greater that the (–) input so the comparator output is
high. Press count repeatedly until further pressing of count has no effect. In this condition
the (–) input is greater than (+) input so the comparator output is low.

In step 3 of Activity 9-2, every time you press count (clock), the counter is incremented as long
as the (+) input is higher than (–) input. The reverse is done in automatic counting. The
count (clock) is kept at a high state, and the counter is incremented as you increase VIN.
Switching to AUTO (connecting b to VCC), makes the AND gate always open to the
comparator’s output. As you slowly increase Vinput, at a certain point the (+) comparator input
just exceedes the (–) input and the comparator output switches high. Since the AND gate is
kept open, the transition in voltage triggers the counter to advance. However the comparator
output remains high for a very short time; the counter advance also changes the ladder
network inputs, increasing the level at B and (–). Once again (–) exceeds (+) so the
comparator output goes low. As Vinput is further increased, the process a repeated again and
again and the display steps through 3, 4, and so on.
Successive Approximation
As mentioned above, another approach is that of successive approximation. The
ADC0804 is an Analog to Digital Converter chip, manufactured by National Semiconductor,
that uses such approach. Its specification sheet and functional description is available at
http://www.national.com. This chip is used in the present module. VREF is used to vary the
dynamic range of the analog input. Ideally, setting VREF to 2.56 V will give a resolution of 0.02
V, that is, for every increment of 0.02 V the binary counter increments by 1. Likewise, setting
VREF to 1.28 will give a resolution of 0.01 V.
Activity 9-4: Successive approximation A / D counter

1: Set VREF to 2.56 V.
2: Apply a variable input voltage VIN (set to minimum) and monitor it with a multimeter.
3: Slowly increase VIN and observe the counting of the chip until all LEDs are lit up. What is
the resolution? What is the maximum value?
4: Fill in the bit pattern / VIN for the different values of VIN / bit pattern as indicated in the
Data Sheet.
5: Repeat step 2 for a VREF of 1.28 V.

Analog to Digital Converter - I
Name: ________________________________Date:______
Activity 9-1: Ladder network voltage generator
1: RAB _____ RBC _____ RCD _____ RDE _____ REF_____

RAA’_____ RBB’____ RCC’____ RDD’____ REE’____ RFF’____
2: RA’_____ RB’____ RC’____ RD’____ RE’____ RF’____
VB’ VC’ VD’ VE’ VB VB’ VC’ VD’ VE’ VB

0 0 0 0 3.0 0 0 0
0 0 0 3.0 3.0 0 0 3.0
0 0 3.0 0 3.0 0 3.0 0
0 0 3.0 3.0 3.0 0 3.0 3.0
0 3.0 0 0 3.0 3.0 0 0
0 3.0 0 3.0 3.0 3.0 0 3.
0 3.0 3.0 0 3.0 3.0 3.0 0
0 3.0 3.0 3.0 3.0 3.0 3.0 3.0
Activity 9-2: The manual A / D counter
Vinput _______ V’ ________ Vinput / V’ _________
Decimal Voltage at B Decimal Voltage at B

Count Count
0 5
1 6
2 7
3 8
4 9

Data Sheet Experiment # EL3-9 continued
Analog to Digital Converter - I
Activity 9-3: Automatic counting

Decimal Voltage at Decimal Voltage at
Count (+) input Count (+) input
0 5
1 6
2 7
3 8
4 9
Activity 9-4: Successive approximation A / D counter
VREF = 2.56 V VREF = 1.28 V

Max VIN = ______ Max VIN = ______
Resolution = ______ Resolution = ______
VIN D7 D6 D5 D4 D3 D2 D1 D0 VIN D7 D6 D5 D4 D3 D2 D1 D0
1.00 0.50
2.00 1.50
3.00 2.00
0 0 0 1 0 1 1 0 0 0 0 1 0 1 1 0
0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
1
Data sheets for the 74LS390 and 74LS47 may be obtained at http://www.fairchildsemi.com .
Data sheets for the ADC0804 may be obtained from http://www.national.com

1211212
Analog to Digital Converters: II
Equipment: Module EL3-J , EL3 Power-source, two multimeters, connectors
As already noted an analog to digital (A/D) converter involves a counter,
comparator, and some form of comparison voltage generator. The prior experiment
used a ladder network as the comparison voltage generator ; in this experiment a
ramp is used for the same purpose. Ramps were discussed in Experiment #8. Two
styles of ramp converters are explored: single slope and dual slope.
Single Slope
The block diagram above shows the simplified “slow motion” single slope
converter used in this experiment . An voltage source ( 0 to 10.0 volts) is applied at Vin
and the reset button is pressed. As long as reset is pressed the counter display is held
at 00 and the capacitor within the ramp generator is discharged through a transistor.
When reset is released, the ramp output

voltage, Vramo , rises linearly from 0 to
approximately 10.5 volts and remains at that level
until reset is again pressed. While Vramp < Vin
the op-amp comparator output will be high. The
clock is running continuously (reset does not
change the clock) producing an output alternating
between high and low. As long as the op-amp
output is high, the clock signal can pass through
the AND gate and reach the counter. But once
Vramp exceeds Vin, the comparator output goes
low, the AND gate closes and counting stops.
10: Analog to Digital Converters II 54

The ramp slope (rate of change of voltage
with time) was shown in El-3-08 to be –Vref /RC.
The diagram shows that Vref , R and C are all
constants. Vref is negative so Vramo rises with
time. As reset briefly goes to +12 volts at the start
of each new cycle, the emitter-base junction of the
transistor across the capacitor will be forward
biased, so the capacitor will be completely
discharged.
The clock speed is variable. It should be adjusted so that the time for Vramp to
rise from 0 to 10.0 volts is just 100 clock pulses. To make this adjustment, apply a
constant 9.00 volts to Vin , press and release reset . If the display stops before reaching
90, increase clock speed (turn knob slightly in the F direction); if the display goes beyond
90 decrease clock speed (turn knob slightly in the S direction). After this clock
adjustment, the display should give the correct numerical value of any voltage applied to
Vin within the range from 0 to 10.0 volts
Activity 10-1 Single slope A/D converter

1: Move the toggle switch to SINGLE SLOPE position.
2: Measure with an oscilloscope the longest and shortest clock period . For this measurement
rotate the clock knob to either end
3: Measure with a multimeter the maximum value of Vramp.
4: Measure with an oscilloscope the ramp slope. To do this connect the oscilloscope DC
input between Vranp and ground (gain 2 V/cm, sweep = 1 Ms/cm). Press and release reset
and measure ( with a wrist-watch or stop-watch) the time for the horizontal trace to rise
through just 10.0 volts. The ramp slope is then 10.0 volts / time
5: Apply 9.0 volts between Vin and ground. Adjust the clock, as already described, so the
display reads 90.
6: Apply various voltages to Vin and record the corresponding display
Dual Slope
For a capacitor with constant charging current, I, the charge, Q, is given by Q = I t
, where t is the time for the charge to change from zero to the final value Q. In the ramp
configuration this constant charging current, I, , is I = Vref / R . For the capacitor, Vcap
= Vramp = Q / C . Combining these we have
Vcap = Q / C = I t / C = Vref t / RC = Vramp
For the dual slope configuration the ramp values of C and R are the clock period
fixed while Vref and t vary. During the first (charge) cycle the capacitor, C, is charged
from zero by Vref = Vcharge = Vin for exactly 100 time units as generated by the fixed
clock. During the second (discharge) cycle C discharges back to zero by the adjustable
Vref = Vdischarge taking a measured t time units.
The diagram shows three different

measurement cycles, #1, #2 and #3 with
three different values of Vin (= Vref).
During the charge cycle the larger the
value of Vin, the steeper the ramp slope.
However for all three the time is the same,
100 clock pulses. All three discharge
cycles have the same slope since Vref
( = adjustable Vdischarge) remains the
same. However the number of clock
pulses is different for each discharge
cycle.
Clearly the value of Vramp is the same at the end of the charge cycle and the start
of the discharge cycle. Therefore
Vramp = Vref t / RC = Vin 100 / RC = Vdischarge t / RC
Vin 100 = Vdischarge t
To set the appropriate Vdischarge value apply 10.0 volts between Vin and ground, and
adjust Vdischarge so that at the end of a complete measurement cycle (charge +
discharge) the display reads 00. Then for any other input voltages, as Vin = 5.5 V or 7.9
V, the display should show 55 or 79.

The measuring cycle begins by pressing briefly
the reset button, which produces a high (+12 volts )
on the reset line. This high signal, applied to the S
input of the counter latch raises the Q output ,
which, while high, clears the counter display to 00
and prevents counting. The high on the reset line is
also applied to the S input of the switch latch, which raises the Q output and lowers the
Q-bar output, thus connecting Vin to Vref through the charge / discharge switch. The
switch details are shown in the diagram .
The circuit is designed to accept a positive Vin not
exceeding 10.0 volts. Therefore during the charge cycle
Vrmp goes negative. Since Vramp enters the inverting (–)
input of the comparator, the signal to the AND gate is high,
permitting the clock pulses to reach the counter. Prior to
pushing reset, Vref equals the negative Vdischarge so Vramp
should go high. However a diode is added, so Vramp can never exceed 0.6 volts. Only
after Vramp goes negative (and the comparator output goes high) is the counter latch
reset (Q goes low) and the clear & hold signal is removed from the counter so the
display increases with each clock period.
The counter is built around a dual decade counter
integrated circuit, 74LS390. Pin #7 of this IC goes high
at the count of 80 and returns low at the count of 100
(=00). The count 100 circuit convert this high to low
transition at count 00 to a single brief positive pulse
which resets the charge latch , switching the negative
Vref to Vdischarge to begin the discharge cycle .
Once the capacitor has fully discharged and Vramp goes positive, the comparator
output goes low, and the AND gate is closed. Counting stops, but the numerical display
remains, until reset is once again pressed. Notice that, unlike the single slope converter,
the clock period is not important; it could be greater or less without changing the results,
as long Vramp has not reached its maximum negative value before the count of 100.
Activity 10-2 Dual slope A/D converter

1: Move the toggle switch to DUAL SLOPE position.
2: With an oscilloscope set to DC measure the maximum negative value of Vramp. With a multimeter
measure the maximum positive value.
3: With an oscilloscope set to DC observe the input and output signals at the count 100 circuit.
4: Adjust Vdischarge so that with Vin = 9.00 the counter will display 90. Record this value of Vdischarge.
5: Using an oscilloscope and wrist-watch (or stop-watch) measure the ramp slope (rate of change of
voltage with time) for the charge and discharge cycles with Vin =
2.00v, 5.00v and 9.00v
6: Apply various voltages to Vin and record the corresponding display

Analog to Digital Converters - II
Name: ________________________________Date:______
10-1: Single slope

Longest period ___________ Shortest period _________
Max Vramp _______ ramp slope ____________
Vin 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00
Display
10-2: Dual slope
max negative Vramp __________ max positive Vramp __________
Vdischarge _____________
V1n 2.00 5.00 9.00

Charge rate
Discharge rate
Vin 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00
Display

8 1211212
The 555 Timer
Equipment: Module EL3-K , EL3 Power-source, two multimeters, connectors
In previous experiments we
viewed various timing circuits. A single
integrated circuit, the 555 timer,
combines several components into a
single useful timing device. The heart of
the device is a pair of voltage
comparators (op-amps without
feedback) feeding an R-S data latch.
The chip requires a voltage Vcc
between 5 and 15 volts (pin #8 is Vcc,
pin #1 is ground). A series combination
of three identical resistors forms a
precision voltage divider. The inverting
input (–) or the upper comparator is
held at 2/3 Vcc; The non-inverting (+)
input of the lower comparator is held
at 1/3 Vcc . Notice that the 1/3 and 2/3
ratios are maintained, independent of
the actual value of Vcc.
In operation sensing voltages are applied to the free inputs of the two
comparators. If pin #6, the (+) input of the upper comparator, rises above 2/3 Vcc the
R-S latch is reset, and Q-bar goes high and remains high until pin #2, the (–) input of
the lower comparator, drops below 1/3 Vcc and Q goes high (recall that Q and Q-bar
are always opposite each other).
Whenever Q-bar is high the output and dump transistors conduct, which brings
low the output, pin #3, and provides a short circuit between dump, pin #7, and ground.
Also a low on reset . pin #4, lets the PNP transistor conduct , resetting the R-S latch
and therefore short circuiting to ground the dump pin #7.
The charging / dis-charging of a capacitor through a resistor has been at the

heart of the timing circuits already considered (ramp, clock, A/D converter). Notice that
the 555 timer contains no capacitance. For all timing applications an external capacitor
and resistor(s) must be added. The basic timing relations for charging and discharging
a capacitor, C, through a resistor, R, are shown below. The product, RC, has the
physical dimensions of time, and is often referred to as the time constant of the circuit.
11: The 555 Timer 59

Monostable operation
An op-amp with positive feedback, as we have seen, has two stable states, either
approximately equal to the + or – supply voltage. It is said to be bi-stable A
monostable circuit has only a single stable state. If disturbed, it will return to the stable
state after a definite time interval . Such monostable circuits are useful for generating a
precise time interval of definite duration. The 555 can be configured for monostable
operation with only a single resistor-capacitor pair. The timing interval is determined by
a voltage, Vcc, charging through a resistor, R, an initially uncharged capacitor, C, until
the capacitor voltage equals 2/3 Vcc.
2/3 Vcc = Vcc [ 1 – e–t/RC ]
2/3 = [ 1 – e–t/RC ]
1/3 = e–t/RC
ln 1/3 = –t/RC = –1.098
t ≈ 1.1 RC
Notice that the charging voltage,

Vcc, does not appear in the final
expression for t.
An initial low pulse to the
lower comparator sets S high and
Q-bar low, so the two NPN
transistors do not conduct. This
makes output high and removes
the short-circuit at dump. The
capacitor, C, starts to charge
through R until in reaches 2/3 Vcc.
At this point Q-bar goes high, the
transistors conduct, output goes low
and the charge on C is dumped to
ground.

The initial low pulse at pin #2 started the cycle by setting S
high. Further low pulses at pin #2, before the end of the cycle,
have no effect. However a low pulse at reset, pin #4, interrupts the
cycle and brings output low. It may be hard to view this single
operation on an oscilloscope, since it happens only once for each
trigger pulse at pin #2. Therefore it is convenient to use a square
wave signal which has been re-shaped into a series negative
going pulsed. The internal circuit of the pulse shaper is shown.
Recall for the R-S latch, a high input at S makes Q high, and Q will remain high
until a high input is applied to R (which makes Q low and Q-bar high). Observe the
wave shapes at points R and Q-bar of the R-S latch. R remains high for only a brief
moment, until the capacitor is discharged; Q-bar remains high until the next trigger
pulse is applied at pin # 2.
The module contains a real 555 timer chip and also an equivalent circuit
configuration of comparators and transistors to illustrate the chip functions.
Activity 11-1 Monostable

1: Measure the exact value of the capacitor, C, on the module. Also measure Rmax and
Rmin, the maximum and minimum values of the variable resistor.
2: Calculate the time intervals, t ( =1.1 RC) using measure Rmax and Rmin.
3: Connect to the pulse shaper a square wave of approximately 200 Hz. View on an
oscilloscope and record the wave form at the input and output terminals of the pulse shaper.
4: Connect R and C as shown in the monostable diagram above, using the equivalent
circuit configuration
Connect together pins # 6 and #7.
Connect C between pin # 7 and ground.
Connect the variable R between pins #6 and #8.
5: For R = Rmax view and record the wave forms at pins #7 and #3 (oscilloscope
settings: horizontal = 1 msec/cm, vertical = 2 v/cm)
6: Repeat step 5 for R = Rmin.
7: Ground briefly pin #4, reset, and note the oscilloscope pattern
8: Repeat the above steps using the real 555 chip (no need to record results)

Astable or Free Running
The monostable 555 configuration requires a trigger pulse to produce a single
time interval. In the astable or free running configuration the process repeats itself
automatically. For monostable, the initially uncharged capacitor, C, charged through a
resistor, R, until its charge was 2/3 Vcc and then discharged, ending the cycle. For free
running, the capacitor charge varies between 1/3 Vcc and 2/3 Vcc ; also it charges
through one resistance value and discharges through a different value. The output is a
continuing series of high and low, each of different time duration.
The astable configuration is shown at the right. Notice the

two comparators both measure the same capacitor voltage. When
dump is inactive the capacitor charges through the series
combination of Ra+ Rb until 2/3 Vcc. At this point dump becomes
active, effectively connecting the junction of Ra and Rb to ground,
allowing C to discharge through Rb. But once the capacitor voltage
decreases to 1/3 Vcc dump again becomes inactive and the
charging process begins all over again. Because of the difference
in resistance the charging and discharging times are somewhat
different.
In either case the capacitor starts

charging / discharging through a voltage
difference of 2/3 Vcc but stops when it is half
way there.
Charging: 1/3 Vcc = 2/3 Vcc [1–e–t/RC]
Discharging: 1/3 Vcc = 2/3 Vcc e–t/RC
Both relations reduce to:

½ = e–t/RC ;
ln ½ = – 0.693 = –t/RC ;
t = 0.693 RC
In charging, R = Ra + Rb while in discharging R = Rb . Therefore the total time for a

complete charge-discharge cycle is
t = 0.693 (Ra + 2Rb) C

Activity 11-2 Astable
1: Use the 10k resistor as Ra and the 1k resistor as Rb. Measure and record their exact
values;
2: Use the 555 timer chip and connect is in the astable configuration:
Connect Ra between pins #7 and #8
Connect Rb between pins #7 and #6
Connect together pins #2 and #6
Connect C between pins #1 and #2
Connect the oscilloscope to pin #3
3: Measure the time for the high output (charging) and compare with 0.693(Ra+Rb)C
4: Measure the time for the low output (discharging) and compare with 0.693RbC
5: Measure again and record Rmin and Rmax the minimum and maximum values of the
variable resistor.
6: Use the 1k resistor as Ra, and Rmin as Rb and repeat steps 3 and 4
7: Use the 1k resistor as Ra, and Rmax as Rb and repeat steps 3 and 4

The 555 Timer
Name _______________________________ Date__________
Activity 11-1: Monostable

C _________ Rmin ___________ Rmax __________
tmin _______ tmax _________
____ V/cm ____ V/cm

_ ____ms/cm ____ms/cm
Pulse shaper Input Pulse shaper output
R = Rmin
V/cm___ __ ___V/cm
mS/cm____ms/ ___mS/cm
Pin #7 Pin # 3
R = Rmax
V/cm___ ____ ____V/cm

mS/cm___ ____ mS/cm
Pin #7 Pin # 3

Data Sheet Experiment # EL3-11 (cont.)
The 555 Timer
Activity 11-2: Astable or Free Running
Ra _______ Rb _________
Charging (high) time; _________ 0.693( Ra+Rb) C ___________
Discharging (low) time; _________ 0.693 Rb C ___________
Rb = Rmin ___________
Rb = Rmax ___________

1211212 Voltage controlled oscillator
Equipment: Module EL3-L , EL3 Power-source, two multimeters, connectors
The voltage controlled oscillator, VCO, is almost the same as the triangular wave
generator considered in Experiment EL3-8.
The diagrams from there are repeated here.
The same current, I, through R charges or
discharges the capacitor C, for the inverting
input of op-amp A has approximately infinite
impedance. It is at ground potential. Also I =
Vf / R. The voltage, VC, across the capacitor
is given as the ratio of charge to
capacitance, Q/C. The rate of change of this
capacitor voltage, dVC/dt is:
dVC/dt = d(Q/C)/dt = (dQ/dt)/C = I/C = Vf/RC (1)
Likewise the slope of the line on a

capacitor voltage against time graph is dVC/dt
= Vf/RC. For the circuit shown, Vf, and the
value of the switching voltages, VT+ and VT–,
are determined by the circuitry around op-amp
B. In the voltage controlled oscillator the Vf is
provided by an external controlling source,
Vctrl. Suitable circuitry in place of op-amp B
must be provided to set the values for VT+ and
VT– and alternate the polarity of Vf .
As shown in the diagram the +/– switch
accepts a positive control voltage, Vctrl, in
the range 0 to +5 volts and alternately
outputs Vf , at twice the magnitude of Vctrl
but with alternating polarity.
For both the triangular wave generator
and VCO, the switching voltage levels, VT+
and VT– are set by VSat(R1/Rf). For the
VCO, the control voltage, Vctrl, is applied
externally while in the triangular wave generator it is determined by the voltage divider
at the output of op-amp B.
12: Voltage controlled oscillator 66

The rate of change of capacitor
voltage with time, dVC /dt, given by Eq. 1, Details of the +/– switch
also represents the slope of the line on a
voltage vs. time graph. The values of R
and C are determined by the circuit
components. From the discussion in the
box at right, Vf = kVctrl, where k=2.0 .
Switching action occurs twice each
cycle, when VC = VT+ or VT– . The slope
of the graph line may be expressed in
terms of the period of oscillation, :
dVC/dt = (VT+ – VT–) / (T/2) (2) The same positive control voltage, Vctrl, is
applied to the inverting and the non-inverting
The oscillator frequency, f = 1/T , follows inputs of the two op-amps. Each has a gain of
by combining Eqs. 1 & 2 : two but of opposite sign. Output from the
upper, non-inverting, op-amp is positive so the
f = {kVcontrol/(VT+–VT–)}(1/2RC) (3) NPN transistor conducts when Vctrl is high,
making Vf positive. Output from the lower,
Module EL3-L contains a model inverting, op-amp is negative so the PNP
VC composed of discrete components to transistor conducts when Vctrl is low, making
illustrate the action of a commercial Vf negative. Both op-amps have a gain of 2
integrated circuit (IC) chip. Because the
model uses op-amps with a finite slew rate there is a time delay between the op-amps
input and output signal. For this reason the model VCO is accurate only at frequencies
below a few thousand hertz. However the model permits direct measurement at key
points in the circuit. Both our model and a commercial IC permit the user to select the R
and C components and adjust the control voltage, Vctrl.
VCO Parameters
For any ready made VCO, the user normally determines Vctrl , R and C while
the k, VT+ and VT– of Eq. (3) are determined by the manufacturer. There is a
practical range of values for Vctrl which may include positive or negative values.
Normally some mid-range value is selected as a reference value for Vctrl. The
corresponding center frequency, f0, depends on the values of R and C alone. It is
convenient to rewrite Eq. (3) as
f = Ko f0 Vctrl (4)
Here Ko depends on the circuit construction and is expressed in units of reciprocal
volts.

Another quantity of interest for every VCO is the rate of change of frequency
with output voltage:
df/dVctrl = Ko f0 (5)
Recall that 1 hertz = 2 radians/second . Due to capacitive effects there are also
The term df/dVctrl may be expressed in units of hertz / volt or (radian/sec) / volt.
practical limits for f0 which depends on R , C and circuit construction.
The Model VCO

A diagram of the model VCO
is shown at right. The externally
applied DC control voltage, Vctrl,
can range from 0 to +5 volts.
Exceeding 5 volts will not damage
the circuit but produces no further
change in VCO output, since op-
amp A (LM741) saturates with input
beyond ±10 volts (10 = 2x5).
The switches at points (2),(3) and (4),(5) permit four different R/C combinations,
corresponding to four different center frequency values, f0. The selected capacitor
charges / discharges at a constant rate, producing at (7) a triangular voltage swinging
between VT+ and VT–. Op-amp B is an LM393 comparator rather than a LM741, to
give faster switching time. Its output at (9) switches between +Vsat and –Vsat as its
non-inverting input (8) passes through zero. Since the same current , I, flows in Rf and
R1, at the moment of switching I = VT+/R1 = +Vsat / Rf or VT+ = +Vsat (R1 /
Rf). For real op-amps the positive and negative values of Vsat are slightly different, so
VT+ and VT– must be measured individually.
Activity 12-1 Model VCO

1: Connect a +4.00 v source at Vctrl. Ideally the voltage at point (1) should then alternate
between +8.00 and –8.00. With an oscilloscope measure actual values at (1).
2: Measure and record values for Ra, Rb, Ca, Cb . For these measurements position the
corresponding switch so the element measured is isolated from the circuit.
3: Measure the exact values of R1 and Rf and with an oscilloscope at point (9) measure
Vsat+ and Vsat– for op-amp B. From these values compute the expected values for VT+ and
VT– and compare these with actual values measured with an oscilloscope at point (7).

Activity 12-1 (cont.) Model VCO
4: Position the switches to select Ra and Ca . Vary Vctrl from +1.00 to +4.00 volts in 0.50
volt steps, and record corresponding VCO frequency, measured at (9). Compute the difference
in frequency for each change of Vctrl and the average df/dVctrl . Select the center
frequency, f0, as the frequency corresponding to Vctrl = 2.50V. Use Eq (5) to compute Ko for
this Ra Ca pair.
5: Repeat Step (4) for Ra and Cb , Rb and Ca , Rb and Cb.
6: For each R - C pair use Eq (3) to compute the predicted value of f for Vctrl = 2.50V.
Wave shaping
An op-amp output ranges between the positive and negative supply voltages,
typically ±12 volts. The input voltage for a TTL integrated circuit is limited to 0 to +5
volts. As shown in the diagram, a zener diode can be used to transform the 20 Vp-p
square wave output of the model VCO (A) to an acceptable TTL level (B). A simple R-
C circuit differentiates the square wave, providing a series of positive and negative
spikes (C). Either the
positive or negative spikes
may be removed with a
standard diode (D), which
may then be shaped with
a TTL buffer (E) and
turned upside down by a
TTL inverter (F).
Real diodes, either zener of standard, are not ideal. Unlike the precise response
of a op-amp comparator, they do not start conducting exactly at forward bias, nor stop
conducting with reverse bias. The simple circuits of this module lets you view the actual
response.
Activity 12-2 Wave shaping
1: Connect the VCO output (9) to the first shaper input (A). Use the Ra - Cb combination and
set Vctrl to 2.50 volts.
2: Connect successively an oscilloscope to points (A) to (F). Record the oscilloscope display,
indicating the gain V/cm and time mSec/cm setting for each axis.

Sine wave
The non-ideal property
of the diode is not helpful in
clipping applications, but is
quite useful for shaping a
triangular wave into a sine
wave. As suggested in the
diagram, as the forward diode
voltage increases beyond
about 0.4 volts, the diode
resistance steadily decreases
(resistance = reciprocal of slope of current-voltage graph). So if is small amplitude
triangular wave is clipped by a pair of real diodes (one for upper half, the other for
lower) the result is a reasonable approximation of a sine wave of the same frequency .
The amplitude of the triangular

output of the model VCO is about
2.5 volts. The voltage divider
formed by the fixed and variable
10k resistors reduce the
triangular wave amplitude before
clipping. The op-amp is used both to increase the sine wave amplitude and also to
amplitude of the triangular wave should be  / 2 times that of the sine wave.
maintain a constant infinite impedance for the output of the shaping circuit. Ideally the
Activity 12-3 Sine wave shaping

1: . For the VCO use the Rb - Cb combination and set Vctrl to 2.50 volts.
2: Connect the input and output of the shaper circuit to different channels of a dual-trace
oscilloscope (the channels may have different gain settings). Adjust the knob (a variable 10
k resistor) to provide the best looking sine wave.
3: Adjust the position and gain settings of the two channels so that the two wave shapes
overlay each other as suggested in the diagram above. Draw the screen display and
measure the amplitude of the displayed sine and triangular waves

Voltage controlled oscillator
Name _______________________________ Date__________
12-1: Model VCO

1: (Vctrl=+4.00) Positive and negative voltages at (1) : ______ _______
2: Ra _______ Rb ________ Ca __________ Cb _________
3: R1 ________ Rf _________ Vsat+ ________ Vsat __________

Computed VT+ ____ VT– _____ Measured VT+ ____ VT– _____
4:
Vctrl Ra Ca Δf Ra Cb Δf Rb Ca Δf Rb Cb Δf
1.00 --- --- --- ---
1.50
2.00
2.50
3.00
3.50
4.00
--- --- --- ---
Ra Ca Ra Cb Rb Ca Rb Cb
Avg. Δf
Δf/ ΔVctrl
Ko
f from Eq.3

Voltage controlled oscillator
12-2: Wave shaping
12-3: Sine wave shaping
Triangular wave amplitude: ________ Sine wave amplitude_________ Ratio _______

1211212 Phase and phase-lock
Equipment: Module EL3-M , EL3 Power-source, two multimeters, connectors
The present experiment deals with phase-lock loops which find a number of
applications in electronic communication systems. The basic phase-lock loop contains
three elements: a voltage-controlled oscillator (VCO), an RC filter and a phase
detector. The first two of these elements have already been considered in some detail.
Here we first examine the notion of phase and the properties of several phase
detectors. Only then may we connect together all three elements into a phase-lock loop
and examine its properties
Frequency and period
In electronics, interest is centered on voltages and

currents that vary with time. Any function of time, f(t),
that repeats itself after a time interval, T, is said to be
periodic with a period T. Some common wave forms
already considered are shown, all with the same period,
T. The frequency, f, of these periodic functions is defined
as
frequency = f = 1/ T = 1/ period
The peak-to-peak value for these wave forms is the
difference between the highest and lowest value (in terms
of voltage or current). For the sinusoidal wave
amplitude is defined as half the peak-to-peak value. In
prior experiments we have seen how to obtain a square
wave from a sine wave, and an approximate sine wave
from a triangular wave. The present module includes
shapers to convert sinusoidal to square waves and shift
their voltage levels.
13: Phase and phase-lock 73

Phase
The idea of phase comes in when two waves, each of
the same frequency, are compared. The diagram shows two
square waves of the same period, T. Note that wave (A) goes
to zero one-fourth period sooner than wave (B); (A) leads
(B) by T/4 , which may also be stated as (B) lags (A) by
the same amount.
From a different point of view (A) goes to zero
three-fourth period later that (B): (A) lags (B) by 3T/4 or (B)
leads (A) by the same amount . So for an two waves of the
same frequency if (A) leads (B) then (B) lags (A) by the
same amount . Whether (A) is considered to be leading or
lagging (B), the sum of the two values always equals the
period T. The phase difference is taken as the smaller of the two time values. Here the phase
itself whenever its argument is changed by 2 radians or 360 ; sine (θ ± 2) = sine (θ). For
difference is T/4 rather than 3T/4. Mathematically a sinusoidal (sine or cosine) function repeats
o
radians or degrees. A phase difference of one-quarter period, T/4, is equivalent to /2 radians
this reason phase differences, even for non-sinusoidal waves, are normally expressed in
or 90o . A dual-trace oscilloscope is useful for illustrating phase shifts. However if the two
waves are produced by separate function generators it would be difficult to maintain the
frequencies exactly equal. For this reason a phase shifter is placed on this module.
Phase Shift Magic…

Let V(–) and V(+) represent the voltage at the inverting
and non-inverting inputs of the phase shifter op-amp. From
the expression for an R-C voltage divider of Experiment El3-3
we have
V(+) = Vi 1/(1 + j RC)
where  is the angular frequency, 2f , of the input
signal. Since the feedback is negative, V(–) = V(+).
The same current flows in the two identical resistors,
R’ , so the voltage drop across each is identical:
Vi – V(–) = V(–) – Vo or Vo = –Vi + 2 V(–)
Substitute the expression for V(–)
Vo = Vi [ –1 + 2 / (1 + j RC) ] .
Express this in terms of a common denominator:
Vo = Vi [(1 – j RC) / (1 + j RC)]
Notice that the magnitude of (1–jRC) and (1 +j RC) are equal, so Vo has the same
amplitude as Vi . Recall the tangent of the phase angle of a complex number is the ratio of
the imaginary to the real part of the number. Therefore the phase angle of the numerator term
is –arctan RC and that of the denominator is +arctan RC And so the phase angle of the
quotient is the difference of these angles, or  = 2 arctan RC .

The output wave of such a phase shifter has the same frequency and amplitude
as the sinusoidal input, but with phase shifted by a controllable amount, depending on
 = 2 arctan 2 fRC
R, C and f
The circuit is basically an R-C voltage divider with output fed to the non-inverting
input of a unit-gain op-amp. The details are shown in the box above. It is interesting to
recall that a simple R-C divider can vary the output phase from 0o to 90o, while the
phase shifter shown can vary the phase from 0 o to 180o. The arctan A approaches 900
as A approaches infinity. Therefore to use this phase shifter at quite low frequencies the
product RC must be large if measurements close to 180o are to be made.
This circuit operates only on sinusoidal waves, since waves of other shapes
behave as a superposition of a set of sinusoidal waves with frequencies an integral
multiple of some fundamental value so each frequency component would be shifted by
a different amount. The output waveform would be quite distorted.
Measuring phase difference with an oscilloscope

A: Sine wave shift
Connect a sine-wave source directly to channel #1
of a dual trace oscilloscope and indirectly, through the
phase shifter, to channel #2. Adjust the vertical position
control of each channel so that each wave pattern is
symmetric with the horizontal center line of the screen. Set
the synch or trigger to channel #1. Since on an
oscilloscope screen time increases toward the right, wave
A leads wave B. Measured by screen units, the period, T,
of either wave is 10 screen units while the phase difference
of the two waves in only 2 screen units. Therefore the phase difference is (2/10) 360 o or
72o If the two waves are not positioned symmetrically about the same horizontal screen
line the method does not work.
B: Square wave shift
We can avoid the need for symmetric positioning by

inserting a sine-to-square shaper just before the
oscilloscope inputs. Wave periods and phase difference
are unchanged. Adjust the horizontal timing so that one-
half wavelength of wave A just fits within the 10 squares of
the screen. Set the synch or trigger to channel #1. The
peak-to-peak voltage may have any convenient value, and
the exact vertical position on the screen is unimportant.
Position wave B anywhere on the lower portion of the
screen, as shown. For this screen display 10 squares represents T/2 seconds. Note

that wave B rose approximately 6.6 squares later than wave A, so the phase difference
is (6.6/10.0) T/2 = (0.66) 180o = 119o. The advantage of the square wave method is
that vertical position and vertical gain are not important. The disadvantage of both
methods is the difficulty of obtaining precise measurements from the oscilloscope
screen.
C: Trigonometry
The trigonometric formula for the sum of two angles, α and β , is given as
sin α + sin β = 2 sin (α + β)/2 cos (α – β )/2
Now let α = ωt and β = ωt + φ . We then obtain in terms of wave behavior
sin(ωt) + sin(ωt + φ) = {2 cos φ/2} sin(ωt + φ/2)
The left side of this equation represents two sine waves of equal amplitude and
frequency with a phase difference φ. The right side represents a single wave of the
same frequency but with amplitude 2 cos φ/2. For φ = 0 , the cosine term equals
o
1.00 so the resulting wave amplitude is 2.00 units, the maximum possible value. At
the other extreme, for φ = 180 the cosine term is zero, so the resulting wave
o
o
amplitude is zero. Represent the amplitude of the sum by A; then A(0 ) = 2 units
and
A(φ) = A(0 ) cos φ/2

o
φ = 2 cos–1 [A(φ)/A(0o)] (1)

To use Eq.(1) with the oscilloscope, display both waves in separate oscilloscope
channels, and set their amplitudes exactly equal (adjust the vertical gain of either
chanel). A convenient value for each is four squares, peak-to-peak. Then press the
oscilloscope ADD button to display the sum of the two channels. Set the phase shifter
to 0o and measure on the screen the wave amplitude (or peak-to-peak = 2 x amplitude)
as A(0o). As the phase change is increased from 0o the screen amplitude is seen to
decrease, and the corresponding phase difference, φ , is given by Eq.(1),
Activity 13-1 Phase difference from oscilloscope display

1: Measure the value of C and the maximum and minimum values of R. From the equation
derived in the phase shifter box, θ = 2 arctan RωC, calculate the maximum phase shift for
a 1 kHz and 2 kHz sine wave. View on a dual-channel oscilloscope the shaper input and
output . Experiment with a square-wave input.
2: Connect the function generator (2.00 kHz, sine wave 6.0 Vpeak-to-peak) through the
phase shifter to oscilloscope channel #2. Also connect the function generator directly to
oscilloscope channel #1 Use the sine wave shift method to determine the maximum shift
value provided by the phase shifter and compare with step 1. If the inputs to the two
channels are interchanged, is there any difference in the results?

Activity 13-1 (cont.)
3: :Use the connections of step 2 but pass the signal entering each channel through a
separate sine-to-square shaper .Use the square wave shift method to determine the
maximum shift value provided by the phase shifter and compare with step 1;
4: Return to the configuration of step 2, use the trigonometry method to determine the
maximum shift value provided by the phase shifter and compare with step 1;
Phase difference as an output voltage

The phase difference measurements already discussed rely on size
measurements made on the oscilloscope screen. These methods are not suited for a
phase-lock loop circuit where phase must be measured automatically. Other methods
provide phase measurement in terms
of a voltage level. Such methods
considered here start by converting the
sine waves to square waves, using
methods already discussed. Frequency
and phase information is preserved,
independent of the initial wave
amplitude. The three methods
presented here use common logic gate
integrated circuit chips; AND, XOR
and R-S flip-flop.
For TTL logic gates a high level, H, is above 3 volts and a low, L, is below one
volt. For the AND and XOR (eXclusive OR) the output, C, depends of the present levels
of inputs A and B. For the R-S, the output levels depend on the transition in input levels
at R and S, and remain until a new input transition occurs
The two input sine waves, converted to

square waves, A and B, are applied to the two
inputs of an AND , an XOR and a RS gate. If the
waves are exactly in phase, the AND output is high
during one half cycle while the XOR and R-S
outputs remains low for the entire cycle . As the
waves shift out of phase, the time during each
cycle the AND output is high decreases, while that
of the XOR and R-S is high increases. For the R-
S, the Q-bar output is always just opposite Q. As
the phase difference increases the duration of the
AND output decreases and the XOR and R-S
outputs increase, as shown in the following
diagram for two full cycles.

Notice that even though the
phase difference is constant,
the output of these gates
repeats every cycle. In a
half- or full-wave power
supply a resistor-capacitor
pair smoothes out the ripple;
so here we may feed the
outputs of any of these gates
to a resistor-capacitor filter
to obtain an average voltage.
The peak values for
each gate differs, as well as
the phase difference at which the peak occurs. At 0o
phase difference between the two waves, the AND gate
is high for half a period while at 180 o phase difference the AND gate is continuously
low. At 0o the XOR gate is continuously low while at 180o it is high for the entire cycle.
Notice the diagrams above display voltage against time. The diagram below
displays voltage averaged over many cycles against phase difference.
The high output level for TTL gates is slightly less than four volts. At zero phase
difference the AND gate is high for one half of each period so its filtered output voltage
is just 50% of the high level. At zero phase difference the XOR gate is low for the entire
cycle so its filtered output voltage is zero.
For the AND and XOR gates there are two phase shift values corresponding to a
given output voltage . This is because these gates give the phase difference,
irrespective of which input is leading or lagging (interchanging the two input terminals
causes no change in output). However the RS gate output depends not only on the
phase difference but also if the S input signal leads or lags the R input, so for a given
filtered output voltage there is one and only one phase difference. For the AND and

XOR ,increasing phase difference may either increase or decrease the filtered output
voltage. For the RS-Q , phase difference and filtered output go together (RS-QBAR is
always just opposite RS-Q)
The slope of the graph lines shown above is defined as the phase detector
sensitivity, KD, in units of volts per radian or volts per degree (1 radian = 57.3o) .
Δ (filtered output voltage) = KD Δ (phase difference)
Activity 13-2 Phase difference from output voltage

1: Connect the function generator (2.0 kHz, sine wave 6 Vpeak-to-peak) indirectly through
the phase shifter to one sine-to-square shaper and directly to the other sine-to-square
shaper.
2: Connect the AND gate to the sine-to-square shapers and view the gate output on
one oscilloscope channel. Vary the phase shift control and compare the scope pattern with
the diagrams shown above.
Next connect the output of the AND gate to the filtering circuit input and measure
its output with a DC voltmeter. At the same time use the method of Activity #1, step 3 to
measure the phase difference between the signals coming from the two sine-to-square
shapers. Set the phase difference to n x 180 o for n=0 to n=0.9 in ten steps and record the
corresponding output from the filtering circuit. Calculate KD in volts / degree and volts /
radian. Is there a difference if the AND inputs are interchanged?
3: Repeat step 2 using the XOR gate.
4: Repeat step 2 using the R-S gate. Compare the Q and Qbar outputs
The Filter
The voltage pattern from the phase detector ( AND, XOR or RS ), repeated every
cycle, is smoothed by the filter circuit to a constant output voltage, directly proportional
to the phase difference of the input signals. If the input signal’s phase difference
changes, the filter output likewise changes.
(t) = 2(2
Now a uniformly changing phase is equivalent to a change in frequency.
Suppose the phase changes at a uniform rate of 720o each second, or
cos [ 2000 (2 (t) ] = cos [ 2002 (2

Then
o
]

To verify this, send to the XOR phase detector two signals of slightly different
frequency, one from the square-wave generator (approximately 1000 hz) on the
module and the other from an external square-wave at almost the same frequency .
The signal just before the filter, viewed on an oscilloscope, is the slowly changing XOR
pattern. Viewed after the filter, it is a DC signal slowly changing between the low and
high TTL levels, in accord with the diagrams of filtered voltage output against phase
difference, shown above. When the input signals differ by just 2 hertz, the filter output
will vary at two cycles per second. If the input signals differ by 20 hertz, the filter output
appears as a sine wave with a frequency of 20 hertz . (Adjust the horizontal sweep
speed speed to view this more conveniently).
But recall that the filter resistor-capacitor circuit is actually a low pass filter, so
the greater the input frequency, the more the output amplitude is attenuated. As the
difference in the two frequencies increases, the filter output sine wave increases in
frequency but its amplitude decreases. It is this particular behavior of the phase detector
- filter combination that makes the phase-lock loop practical.
Activity 13-3 Changing phase difference

1: Connect the 1000 hz generator through a sine-to-square shaper to the XOR gate. Also
connect an external function generator (sine wave, 1000 hz, 6 V p-p) through the second sine-to-
square shaper to the XOR gate. Connect the XOR gate to the filter. View on the oscilloscope
channel the signal before and after the filter.
2: Vary the function-generator frequency so the difference in input frequencies changes,

and measure the corresponding amplitude of the filter output. For small frequency difference
use the DC-input scope setting (use slowest sweep speed). For larger differences it may be
convenient to use the scope AC-input, and adjust both horizontal sweep speed and vertical
gain. The maximum peak-to-peak voltage should be approximately the difference of TTL
levels.
3: Is there any difference if the external function generator frequency is greater or less than
that of the fixed 1000 hz module source?
4: If a signal is applied to only one input, while the other input is grounded, describe the signal
before and after the filter.

The VCO
The voltage controlled oscillator on the
present module is rather similar to that of the
previous module, and the equations derived
there are also applicable here. The capacitor,
C, has a fixed value, R is a 10 k variable
resistor, and Rf/R1 = 10.0 . Referring to
Eq.(3) of Experiment EL3-12, the k term equals 2.0 and the (VT+ – VT–) equals the
peak-to-peak value of Vtriangle. Therefore frequency, f , of Vsquare is given by
f = ( Vctrl / RC ) / Vtriangle
The peak-to-peak value of Vsquare is fixed at approximately 20 volts, which can be
reduced to TTL levels by the sine-to-square shapers.
How could you set the VCO output to 2.00 kHz ? Of the four quantities which
determine f, you are free to choose two, namely R and Vctrl, while C and Vtriangle were
fixed when the module was made. Suppose your measurements give C = 100 nf =
1.00 x 10–7 farads and Vtriangle = 2.0 volts. (Since Vtriangle is measured from the
oscilloscope screen, it is the least accurate). This gives us
Vctrl / R = f C Vtriangle = (2.00x 103)(2.0)(1.00x10–7) = 4.0x10–4
You next select any convenient R and Vctrl combination. A few possibilities are shown:
for f = 2.0 kHz
R Vctrl
2.0 k 0.80 volts
4.0k 1.60 volts
8.0 k 3.20 volts
Activity 13-4 Setting the VCO

1: Measure the value of C and the range of R. Apply 1.0 volt DC to the VCO input. With the
oscilloscope measure the peak-to-peak value of Vtriangle.
2: Set Vctrl to 1.00 volt, using the variable voltage source on the module, and adjust R so
the VCO output approximately 2.0 khz. Measure R (turn off power when measuring R). Next
vary Vctrl from 0.50 to 3.50 volts, in 0.50 volt steps, and record the corresponding VCO
output. From this data determine the best value of Vtriangle as Vctrl/(fRC). Compare this
with the value determined in step 1.
3: Make a neat graph of the data gathered in step 2 (Vctrl along horizontal axis). Measure
its slope in hertz/volt. This is the sensitivity of the VCO and is different for other values of
R and C.

Phase-lock loop
The phase-lock loop links together the three elements
we have been considering: a phase detector ( AND,
XOR or RS gate ), filter and a VCO. Input to the loop
is at one terminal of the phase detector, output from
the loop is at the VCO output. However VCO output
is also fed back to the other terminal of the phase detector. The object of the basic
circuit is to maintain the output frequency identical with the input frequency. The
amplitudes may differ, the phases may differ, even the wave forms may differ ( input a
sine wave, out a square wave ) but the frequencies must be the same. Perhaps the
circuit may have better been called frequency-lock rather than phase-lock !
Suppose the external signal to input A of the phase detector has the same
frequency (but perhaps differs in phase) as the feedback signal at B; then the constant
voltage from the phase detector, passing through the filter, acts as the control voltage,
Vctrl, for the VCO. Since the VCO output frequency depends on Vctrl and R, if R has
just the right value signals A and B can exactly match in frequency. The system is in
balance!
Although balanced, is it stable or unstable? If frequency A begins to increase by
a very small amount, this is equivalent to an increase in phase difference between A
and B. The phase detector output ( and therefore Vctrl ) must also change. But which
way, increase or decrease? That depends on 1) the type of detector, and 2) the initial
phase difference.
Look back at the diagrams of the filtered output voltage against phase difference
for the AND, XOR and RS gates. If an AND gate is used as phase detector, and the
phase difference is less than 180o, then the filtered output voltage decreases with
increasing phase. For the XOR gate (phase difference less that 180o) and the RS
(everywhere) the filtered output voltage increases with increasing phase
For the VCO on the module, any increase in Vctrl increases the output frequency
(other VCO circuits act oppositely). So if you are using an XOR as detector and the
initial phase difference is less than 180o, then the slight frequency increase in A
produces a slight increase in Vctrl , which in turn causes a slight increase in the VCO
output frequency, which is also fed back to the B input so its frequency catches up with
A. The input and output frequencies are said to be locked If the input frequency at A
had decreased slightly, the phase difference between A and B would decrease,
decreasing Vctrl and slightly decreasing the VCO output, matching frequency B with A.
The input and output frequencies are still locked.
Suppose the initial phase difference with an XOR had been somewhere between
180o and 360o ? Then an initial slight frequency increase in A would cause a slight
decrease in B, so the phase difference increases and the frequency difference between
A and B grows without bounds. The frequencies are no longer locked .

The lock range
Even if there is no input signal, A, an XOR detector still provides an output signal
due to feedback at B from the VCO. The filter output to the VCO will be a DC voltage
approximately midway between a high and low TTL level. The corresponding VCO
output is defined as the free-running frequency, fo, and is determined by the R
and C values of the VCO.
If the input signal, A, happens to equal this free running signal, fo, the loop is
locked, since the input and output frequencies are identical. By how much may the
input frequency differ from fo, either greater or less, while the VCO output frequency
remains equal to the input, that is, while the loop remains locked. This frequency range
is defined as the lock range.
Can we calculate this lock range? Assume an XOR detector. When locked the
phase difference at the detector must be between 0o and 180O (and not too close to the
end points of this interval). The data obtained in Activity #2, step 3 gives the range of
Vfilter ( = Vctrl ) for this range of phase differences. And from the graph obtained in
Activity #4, step 3, obtain the VCO output frequencies corresponding to this range of
Vctrl. This is the lock range. A similar method may be used to determine the lock
range associated with an AND or RS detector
For each phase detector type you were asked in previous activities to measure
its sensitivity, KD, in volts / degree. For the VCO you were also asked to measure its
sensitivity, KO, in hertz / volt for a particular R and C combination. The product of these
two, KO KD, in hertz / degree is defined as the loop gain for this RC combination.
To determine the lock range experimentally, start with an input frequency of
approximately fo , the free-running frequency. Monitor the loop input and output
frequencies to verify the lock condition. Then very slowly increase the input frequency
until the loop becomes unlocked, that is, input and output frequencies no longer match.
Record this frequency. Next repeat the process, but this time decrease the input
frequency until the lock condition is lost. The difference of these two frequencies gives
the lock range. The three graphs of filtered output voltage ( = Vctrl ) against phase
difference for the three detectors can be helpful in determining the lock range. For
locking to be possible, Vctrl must increase with increasing phase difference so we are
restricted to ranges where the graph line slope is positive. From these graphs we find
absolute maximum limits that may not be exceeded:
gate Vctrl range Phase difference range

AND 0 to ½ TTL high 180o to 360o
XOR 0 to TTL high 0o to 180o
RS 0 to TTL high 0o to 360o
In practice these limits are less, due to random voltage variations.

While searching experimentally for the lock range it is helpful to monitor Vctrl with
a voltmeter, and also view on an oscilloscope the input and output wave shapes (pass
the input wave through a sine-to-square shaper before entering the oscilloscope, to
make phase comparison more convenient). Sample measurements are presented
below.
XOR : lock range measurement:
minimum f = 310 hz, Vctrl = 0.18 volts
midrange f = 2070 hz, Vctrl = 0.99 volts
maximum f = 7.09 khz, Vctrl = 3.40 volts
lock range = 7.09 – 0.31 = 6.78 khz
The capture range

The output voltage pattern of all three detectors varies between TTL low and
high levels with a frequency given by the difference in frequency of the two inputs. If
this detector output frequency is large, the low pass filter blocks the variations and only
an average value reaches the VCO, and its output frequency is more or less constant.
The loop is not locked. However when the input frequency comes close to the VCO
frequency, the detector output frequency is much less, so the variations begin to get
through the low pass filter, causing the VCO frequency to sweep back and forth over a
limited range. And once this sweep range includes the input frequency, just for a
moment the two phase detector input frequencies are identical. That brief moment is
sufficient for the loop to lock!. This sweep range is defined as the capture range. Its
width depends on the sensitivity of the VCO (the KO term) and on the cut-off frequency
of the low pass filter.
To measure the low end of the

capture range, with the loop unlocked
start with a very low input frequency
and slowly increase until the system
locks. For the high end, with the loop
unlocked start with a very high input
frequency and slowly decrease until
the system locks. The difference of
these two values is the capture range. While making these measurements it may be
convenient to monitor the loop input and output waveforms and Vctrl.

Activity 13-5 Phase-locked loop
1: Using the computed values of Ko and KD, determine the loop gain for each of the
three phase detectors. From this determine the theoretical maximum possible lock range
with each detector. Because of noise and random interference, the actual lock range is less
than this
2: Use the AND detector. Determine the lowest and highest possible frequencies for lock
(actual lock range} . Also determine the actual capture range.
3: Repeat step 2 for the XOR detector.

4: Repeat step 2 for the RS detector.
Frequency Multiplication
One application of phase-lock loops is frequency multiplication; the loop output
frequency is an integral multiple of the input frequency. Digital circuits can readily divide
frequency, but cannot directly multiply it. The filtered phase detector output is constant if
its two inputs have identical frequency. The VCO output depends on Vctrl as well as on
RC. For a fixed value of Vctrl the VCO output can be made to vary widely simply by
changing R or C.
For the XOR detector considered,

a 90o phase difference gives a filtered
output of about 1.8 volts. Now suppose
the input frequency, fin, is in the
neighborhood of 1 khz, and we wish the
output, fout , to be exactly 2 x fin. Set the
R value of the VCO so that a Vctrl
voltage of 1.8 volts gives an output near
3 khz . Next, insert into the feedback path a digital frequency divider that gives one
count out for every two counts in. Now both phase detector inputs receive the same
frequency so the system is locked. Take fout from the VCO output but before entering
the digital divider. Since the system is locked, fin can vary over the entire lock range
and fout will still be exactly 2 x fin . If the digital circuit divides by four or eight, then fout
will be exactly four or eight times fin. Usually the RC value should be adjusted if the
digital divide ratio is changed..

Frequency shift keying (FSK)
Voltage controlled oscillators (VCO) and phase-locked loops (PLL) are used in
an information transmitting system called frequency shift keying, FSK. Digital data
conveys information through a time series of high and low voltages. If such digital data
is sent through wireless by amplitude modulation, fading and random noise often
produce errors. Frequency shift keying converts the input high and low voltage levels
to a carrier whose frequency shifts between two values, corresponding to the high and
low input voltages. Amplitude changes in the received signal then have no relevance.
On the transmit side a VCO changes the two voltage levels of the input signal to
two separate frequencies normally rather close together, suitable for wireless
transmission. On the receive side, the phase-lock system has a capture range that
includes the two transmitted frequencies. The VCO output frequency changes to lock
with the current input frequency. The output signal is not the VCO output but rather the
Vctrl voltage input to the VCO which reproduces the original input signal.
Activity 13-6 Frequency multiplication

1: Explore the digital divider. Connect an external function generator, through a sine-to-
square shaper to the input of the digital divider. View on a dual-trace oscilloscope the input
and the three different outputs.
2: Apply to the VCO input a 1.80 volt Vctrl and adjust R so the VCO output is
approximately 3 khz. Then configure the module as shown in the phase-lock frequency
multiplier diagram. Use the “2” divider output. fin is the signal from an external function
generator (6 VP–P, sine wave, 2 khz). Vary fin to lock the loop. Find the upper and the lower
frequency values of lock range. When approaching the end values vary fin slowly and
smoothly, for any “noise” in the Vctrl voltage can spoil the lock.
3: Repeat step 2, but first adjust R so the VCO output is approximately 7 khz, and use the
“4” divider output
4: Repeat step 2, with VCO output to approximately 15 khz. Use “8” divider output

Phase and phase-lock
Name ______________________________ Date__________
13-1: Phase difference from oscilloscope display
Rmin___ Rmax _______ C ___________
φ max @ 1 khz _____ φ max @ 2 khz _____
A: Sine wave: φ max @ 2 khz _____
B: Square wave: φ max @ 2 khz _____
C: Trigonometry : φ max @ 2 khz _____
13-2: Phase difference from output voltage :
AND XOR
n x 180o Vfilter ΔVfilter n x 180o Vfilter ΔVfilter
0.0 0.0
0.1 0.1
0.2 0.2
0.3 0.3
0.4 0.4
0.5 0.5
0.6 0.6
0.7 0.7
0.8 0.8
0.9 0.9
KD : Volts / degree ________ KD : Volts / degree ________
Volts / radian _______
Volts / radian _______

RS Q RS Qbar
n x 180o Vfilter ΔVfilter n x 180o Vfilter ΔVfilter
0.0 0.0
0.1 0.1
0.2 0.2
0.3 0.3
0.4 0.4
0.5 0.5
0.6 0.6
0.7 0.7
0.8 0.8
0.9 0.9
KD : Volts / degree ________ KD : Volts / degree ________
Volts / radian _______ Volts / radian _______
13-3: Changing phase difference

frequency Vpeak-to peak frequency Vpeak-to peak
2 100
5 200
10 500
25 1000
50 2000

13-4: Setting the VCO
C ________ Rminimum __________ Rmaximum _________
Vtriangle from oscilloscope ___________ R ___________
Vctrl f f/Vctrl Vctrl/(fRC)
0.50
1.00
1.50
2.00
2.50
3.00
3.50
sum
average
slope = Ko hertz/volt __________

13-5: Phase-locked loop
AND XOR RS
loop gain
theoretical
maximum lock range
Actual ranges for ….
AND
min flock ____ max flock ____ lock range _____
min fcapture ____ max fcapture ____ capture range ______
XOR
RS

Activity 13-6 Frequency multiplication

minimum maximum
fin fout Vctrl fin fout Vctrl
2x
4x
8x

Ateneo de Davao University
Electronic Communication Series

Electric Circuits I: Direct Current
Electric Circuits II: Alternating Current
Electronics I: Basic Components
Electronics II: Amplifiers and Oscillators
Electronics III: Operational Amplifiers
Communications I: AM and FM
Communications II: Digital Communications
Digital Logic Circuits, with Verilog HDL
Industrial Electronics
LOGO! PLC: Learning a Programmable Logic Controller
We are a university in a Third World country, the Philippines. We

believe that more than chalk and whiteboard pens are needed to train a
communication engineer for today’s world. “Hands on” is a must for every
student. Excellent student laboratory equipment is readily available on the
world markets. Yet the funding necessary for us to purchase such
equipment, and in the quantity we desired, was completely unavailable.
Our only viable option was to design and fabricate locally the materials of
which before we only dreamt. For each item of laboratory equipment
student instructional material had to be prepared, as shown in the above
listing. With a view to share with other institutions the fruit of our own
endeavors, we are making these student manuals freely available.
Permission is given to copy this material, and to suitably modify it to the
needs of a particular institution
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Laboratory Guide For Electronics 3 Opera

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Laboratory Guide for

Engr. Rafael U. Gaid, Jr.

Electronic and Communication Engineering

1: Op-Amp Fundamentals {EL3-A}

2: Op-Amp: Practical Circuits {EL3-B}

3: Op-Amp: Frequency Response {EL3-C}

4: Active Filters {EL3-D}

5: Instrumentation Amplifier {EL3-E}

7: Digital to Analog Converter {EL3-G}

8: Positive Feedback {EL3-H}

9: Analog to Digital Converters: I {EL3-I}

10: Analog to Digital Converters: II {EL3-J}

11: The 555 Timer {EL3-K}

12: Voltage Controlled Oscillator {EL3-L}

13: Phase and Phase-lock {EL3-M}

This present work, Electronics III : Operational Amplifiers,

All the experiments center on the operational amplifier, in

The authors gratefully knowledge the following Ateneo

Input Offset Voltage

1. Ground both inputs of the op-amp, and

Offset voltage adjust range

the Data Sheet.

Common Mode Rejection Ratio

Input Bias and Offset Current

An ideal voltmeter draws no

Supply Voltage, Current and Power

Activity 1-2 and 1-3:

An op-amp alone is a wild thing, it has its

The certain fraction, , of the amplifier

diagram below, the value of  is R1 / ( RF + R1).

Vout = A(Vin + Vout) or

Vout/ Vin = A / ( 1 – A

Vout = A(Vin – Vout) or

Vout/ Vin = A / ( 1 + A)

However the triangular amplifier symbol at

V1 = Vout R1 / (R1 + RF) or Vout = V1 ( 1 + RF / R1 ) (1)

2. To verify the current gain, connect VO to the (–)

3. Measure with a milliammeter the output current

(V1 – v–) / R1 = (v– – Vout) / RF or Vout = – V1 ( RF / R1 ) (2)

The input impedance of the non-inverting amplifier is in the meg-ohm range,

Inverting: Summing Amplifier

The summing amplifier diagrammed here is easily understood in terms of

It is also possible to make a summing amplifier by applying signals to both the

Inverting : Current to voltage

Inverting : Voltage to current

Vo2 = [V2 (R4/R3)/(1 + R4/R3)] ( 1 + RF/R1)

Substitute RF / R1 for R4 / R3 since they should be equal according to the

Input Offset Voltage, revisited

An alternate, and easier, approach is to use negative

Vo+ = R1IIB+ ( 1 + RF/R1) ≈ R1IIB+ (RF/R1)

Activity 2-1: Activity 2-2::

Oscilloscope Display (+) grounded:

with Vout = 0 (–) input _____

Oscillations (yes / no)? _____

RF R1 Vout V1 Vout/ V1 1 + RF/R1

Activity 2-7: Activity 2-10:

RF = 50 k Input offset adjust

3: Op-Amp: Time varying input 1

For c  1 (very low frequency)

3: Op-Amp: Time varying input 2

Every real op-amp is equivalent to an

derivative, Vo  cos t ,with maximum value, Vo , and is

3: Op-Amp: Time varying input 3

1: R’1 ______ R”1 _ Rf ______

5: R _____ RP min _ RP max ______