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TOPICAL REVIEW
Semiconductor nanowires
Wei Lu1,4 and Charles M Lieber2,3
1
Department of Electrical Engineering and Computer Science, University of Michigan, Ann
Arbor, MI 48109, USA
2
Department of Chemistry and Chemical Biology, Harvard University, Cambridge, MA
02138, USA
3
Division of Engineering and Applied Sciences, Harvard University, Cambridge, MA 02138,
USA
E-mail: wluee@umich.edu
Abstract
Semiconductor nanowires (NWs) represent a unique system for exploring
phenomena at the nanoscale and are also expected to play a critical role in
future electronic and optoelectronic devices. Here we review recent
advances in growth, characterization, assembly and integration of
chemically synthesized, atomic scale semiconductor NWs. We first
introduce a general scheme based on a metal-cluster catalyzed
vapour–liquid–solid growth mechanism for the synthesis of a broad range of
NWs and nanowire heterostructures with precisely controlled chemical
composition and physical dimension. Such controlled growth in turn results
in controlled electrical and optical properties. Subsequently, we discuss
novel properties associated with these one-dimensional (1D) structures such
as discrete 1D subbands formation and Coulomb blockade effects as well as
ballistic transport and many-body phenomena. Room-temperature
high-performance electrical and optical devices will then be discussed at the
single- or few-nanowire level. We will then explore methods to assemble
and integrate NWs into large-scale functional circuits and real-world
applications, examples including high-performance DC/RF circuits and
flexible electronics. Prospects of a fundamentally different ‘bottom-up’
paradigm, in which functionalities are coded during growth and circuits are
formed via self-assembly, will also be briefly discussed.
(Some figures in this article are in colour only in the electronic version)
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core/shell and core/multi-shell form along the radial direction Figure 5. Ge/Si core/shell NWs. (A) Schematic of a cross-section
[22–24], have been realized on VLS–CVD grown NWs. through the Ge/Si core/shell nanowire. (B) Band diagram for a
Si/Ge/Si heterostructure. The dashed line indicates the position of
To understand the rational formation of nanowire
the Fermi level, EF . (C) HRTEM image of a Ge/Si core/shell
heterostructures within the context of the VLS method, nanowire with 15 nm Ge (dark grey) core diameter and 5 nm Si
consider the possible effects of a change in reactant vapour (light grey) shell thickness. Scale bar: 5 nm [23].
once nanowire growth has been established (figure 4). If
vapour decomposition/adsorption continues exclusively at the band edge of the Ge core (figure 5(B)). In the Ge/Si core/shell
surface of the catalyst nanocluster site, crystalline growth of nanowire heterostructure, the pseudomorphic strain in the
the new semiconductor will continue along the axial direction epitaxial core and shell materials is relaxed along the radial
(figure 4(c)). On the other hand, if the decomposition of direction [22], yielding a type II staggered band alignment [27].
the new vapour/reactant on the surface of the semiconductor The light hole and heavy hole bands are expected to split due
nanowire cannot be neglected, a shell of material will grow on to the effects of strain and confinement [27]. This hole-gas
the original nanowire surface (figure 4(d)). Repeated changing system will be discussed in detail in section 3.2, as novel
of reactants in a regime favouring axial growth will lead to the phenomena and high-performance transistors are realized on
formation of a nanowire superlattice, as shown in figure 4(e), such core/shell NWs.
while changing reactants in a radial-growth regime will result Other types of core/shell nanoires have also been studied.
in core-multi-shell radial structures, as shown in figure 4(f). For example, GaN based core/multi-shell NWs [24, 29] have
It is important to mention that there are few constraints on been grown using MOCVD. High-efficiency light-emitting
the composition of the shell growth; any material suitable diodes were obtained on these core/multi-shell structures using
for planar film deposition can be deposited on the surface of bandstructure engineering and modulation doping [24, 29].
a nanowire, and crystalline radial heteroepitaxy [22] can be In a different approach, silicon/silica core/shell NWs were
achieved as the nanowire surface is crystalline. produced through thermal oxidation of as-grown SiNWs
[30, 31]. By treating either the silica shell or the silicon
2.2.1. Radial nanowire heterostructures. Radial core/shell core as a sacrificial material, silica nanotubes [31] or parallel
heterostructures can be achieved if dissociation of the reactants array of silicon NWs with controlled spacing [30] have been
is promoted at the grown nanowire surface (figure 4(d)) [22], demonstrated, respectively.
analogous to the layered growth of planar heterostructures.
Compared with NWs in the simple homogeneous form, 2.2.2. Axial nanowire heterostructures. Unlike radial het-
core/shell heterostructure NWs offer better electrical and erostructures in which the shell growth does not involve reac-
optical properties as they can now be tailored through band tion with the nanocluster catalyst, axial nanowire heterostruc-
structure engineering. For example, similar to the formation tures can be obtained by alternative introduction of vapour
of two-dimensional electron [26] and hole gases [27] in high- phase reactants that react with the same nanocluster catalyst,
electron mobility transistors (HEMTs), 1D electron and hole as illustrated in figures 4(c) and (e). A critical requirement of
gases can be achieved in core/shell heterostructure NWs. Lu the axial nanowire heterostructure growth is then that a single
et al observed that a 1D hole gas [23] will be formed if a Si shell nanocluster catalyst can be found which is suitable for growth
is epitaxially grown on top of a Ge core, as shown in figure 5. of the different components under similar conditions. For a
The valence band offset of ca 500 meV between Ge and Si at the wide range of III–V and IV materials, Duan et al observed [10]
heterostructure interface [27, 28] then serves as a confinement that Au nanoclusters can meet this requirement. Using Au
potential for the quantum well, and free holes will accumulate nanoclusters as catalysts and a laser-assisted catalytic growth,
in the Ge channel when the Fermi level lies below the valance Gudiksen et al [20] have successfully obtained GaAs/GaP axial
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Figure 6. Axial GaAs/GaP nanowire heterostructures. (a) HRTEM of a GaAs/GaP junction grown from a 20 nm gold nanocluster catalyst.
Scale bar: 10 nm. Inset, two-dimensional Fourier transforms of the entire image. (b) TEM image of another junction. Scale bar, 20 nm.
(c)–(e) Elemental mapping of the Ga (shown grey), P (red) and As (blue) content of the junction shown in (b). (f) Line profiles of the
composition through the junction region, showing the change in composition as a function of the distance. Ga: black, P: red and As:
blue [20]. (Colour online.)
nanowire heterostructures (superlattices) with GaAs and GaP variation (figure 6(f)) however, shows, that the junction
targets at temperatures of 700–850 ◦ C at 100 Torr in a contin- is not atomically abrupt but rather makes the transition
uous argon flow. between GaP and GaAs phases over a length scale of
Figure 6(a) shows a TEM image of a typical GaAs/GaP 15–20 nm. This length scale is consistent with the hypothesis
junction region obtained by Gudiksen. The nanowire axes that the ∼20 nm diameter Au catalyst must re-alloy with
was found to lie along the 111 direction, in agreement GaP after initial GaAs growth. The observed composition
with previous studies of single-component systems [7, 10, 32]. variation has several potentially important implications. First,
Two-dimensional Fourier transforms calculated from high- composition variation at the interface can relieve strain and
resolution images containing the junction region (figure 6(a), may enable the defect-free junctions and superlattices that
inset) show pairs of reciprocal lattice peaks along the different were observed in the GaAs/GaP system which has a relatively
lattice directions, while such transforms calculated from the large lattice mismatch. Second, the observed composition
regions above and below the junction (not shown) exhibit only variation could be substantially reduced in smaller-diameter
single reciprocal lattice peaks. Analysis of these peak data NWs when abrupt interfaces are required in certain photonic
yields lattice constants, indexed to the zinc blende structures and electronic applications. For example, a 5 nm diameter
of GaP and GaAs, of 0.5474 ± 60.0073 nm and 0.56686 ± nanowire superlattice should have variations of 5 nm across
0.0085 nm and are in good agreement with the values for both the junction interfaces. Alternatively, it should be possible to
GaP (0.5451 nm) and GaAs (0.5653 nm), respectively. use different nanocluster catalysts or variations in the growth
Local elemental mapping of the heterojunction by energy temperature when reactants are switched to obtain sharper
dispersive x-ray spectroscopy (EDS) was carried out to probe interfaces.
composition variations across the heterostructure junction By repeating the modulation process, nanowire superlat-
(figures 6(b)–(e)). The elemental maps show that Ga is tices can be produced in which the number of periods and repeat
uniformly distributed along the length of the NW, while P spacing can be readily varied during growth. For example,
(figure 6(d)) and As (figure 6(e)) appear localized in the Gudiksen et al demonstrated a 21-layer GaAs/GaP superlat-
GaP and GaAs portions of the nanowire heterostructure, tice with arbitrary repeat spacing, with the lengths of the seg-
respectively. Quantitative analysis of the P and As composition ments controlled by the number of pulses delivered to each
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Figure 11. (A) SEM image of a typical SiNW device with four contacts used in the four-probe transport measurement. (B, C) Ids versus Vds
data recorded on a SiNW using two-probe (thin green) and four-probe (thick red) contact geometries; the Si/P ratio is 500 : 1 for (B) and
4000 : 1 for (C). (D) Measured (blue triangles) and intrinsic (red circles) mobility values versus doping level [74]. (Colour online.)
Figure 12. (a) CB oscillations observed at 4.2 K with Vsd = 0.5 mV. Inset: scanning electron microscopy (SEM) image of the device. Scale
bar: 500 nm. (b) Greyscale plot of ∂I /∂Vsd versus Vsd and Vg recorded at 4.2 K; the light (dark) regions correspond to low (high) values of
∂I /∂Vsd . (c) Gate capacitance versus source–drain separation (channel length) for 5 representative devices showing single-island CB
behaviour. The line is a fit to the data with a slope of 28 ± 2 aF µm−1 [69].
3.1.2. Single-electron devices. Zhong et al realized that current (I ) versus gate voltage (Vg ) data recorded with a 0.5 mV
the Schottky barriers at the metal/Si contacts can serve as source–drain bias (Vsd ) at 4.2 K was plotted for a device with
tunnel barriers [69]. At low temperatures the nanowire device source–drain separation of 400 nm. The I –Vg curve exhibits
effectively acts as a single-electron transistor (SET) when the regular oscillations over a broad range of Vg , in which the
charging energy e2 /C becomes larger than the thermal energy current peaks are separated by regions of zero conductance
kB T , where C is the total capacitance of the SET [76]. SET with an average peak-to-peak separation of 0.015 ± 0.001 V.
behaviour was first observed on InP nanowire devices [77] in The heights of the observed peaks vary with Vg , although this
an earlier study,. However, the tunnel barriers in these devices
variation has no obvious periodicity. The position and heights
were formed by random defect potentials along the nanowire
of the peaks are very reproducible on repeated Vg scans in
channel, resulting in multiple, randomly formed islands in
series, with little control of the device parameters [77]. this and similar devices. These observations indicate that
In Zhong’s study, single crystal p-type SiNWs with the results are intrinsic to transport through the SiNWs and
diameters of 3–6 nm were synthesized by gold-nanocluster are moreover, consistent with the Coulomb blockade (CB)
mediated VLS growth, using silane and diborane [11, 69, 78]. phenomena resulting from single charge tunnelling through a
Unlike the studies on InP NWs [77], Zhong observed single single quantum structure (e.g. the SiNW) with discrete energy
island behaviour with the two tunnel barriers formed at the levels [76, 79]. To define better the length-scale of the SiNW
patterned S/D contacts, as evident in figure 12. In figure 12(a), structure responsible for the CB oscillations, Zhong measured
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deformation potential, ρ is the mass density and vs is the conformal top gate structure was confirmed by cross-sectional
velocity of√sound. The √ density of states can be calculated as transmission electron microscopy (TEM) images, as shown in
D(E) = ( 2m∗ /πh̄ E)(1/πr 2 ) for the first subband using figure 15(b). Compared with previous back-gated devices,
the effective mass for heavy holes, m∗ = 0.28me [27, 70], the top gate structure approaches an ideal cylindrical gate
where me is the free electron mass. τap ∼ 4.9 × 10−12 s geometry and together with the high-κ dielectrics produces
was estimated at room temperature for a 10 nm core diameter a much more efficient gate response [98].
nanowire at EF = 10 meV, using an average sound velocity A large number of Ge/Si NWFET devices with L
of 5400 m s−1 and deformation potential of 3.81 eV for Ge varying from 1 µm to 190 nm were fabricated and measured.
[27, 88]. The mean free path calculated
√ using this value of τap Essentially all the devices exhibited high performance
and the Fermi velocity, vF = 2EF /m∗ ∼ 1.1 × 105 m s−1 , behaviour and testify to the reproducibility of the Ge/Si NWs
is 540 nm. This estimate is consistent with the experimental and contacts to this material. Representative data obtained
results and, moreover, suggests that room-temperature ballistic from a device with a channel length, L = 1 µm, and a
transport in Ge/Si NWs is possible on a 0.5 µm scale, assuming total diameter of 18 nm (device A) and another device with
other scattering processes are suppressed. Room-temperature L = 190 nm (device B) are plotted in figures 15(c)–(e).
ballistic transport has been reported previously in metallic The Id –Vg transfer curve recorded for device A at Vds =
and semiconducting CNTs [89, 90] and was attributed to the −1 V (figure 15(d)) shows that the NWFET has a peak
topological singularity at k = 0 due to its unique band structure transconductance, gm = dId /dVg , of 26 µS and a maximum
in metallic nanotubes [91, 92]. Reduced acoustic phonon drain current Idmax of 35 µA at Vg = −2 V. An even better
scattering in 1D explains room-temperature ballistic transport performance was achieved for device B due to the reduced
in Ge/Si NWs, although a more detailed theoretical analysis, channel length, with gm = 60 µS, and Idmax = 91 µA. These
including the confinement effects of phonon modes, will be values represent the best performance reported to date in single
needed to quantify the limits of this interesting behaviour. semiconductor NWFETs [12, 66].
The small size and long mean free path of the 1D hole To compare the performance of NWFETs with planar
gas offer unique opportunities to explore new phenomena in devices in which a single voltage Vdd sets the range of Vg and
nanoscale, low-dimension systems. For example, a small Vds , a universal definition of the on and off current values needs
feature has been found to be always present below the to be adopted. Following conventions in planar devices, the
first conductance plateau in the Ge/Si system, as illustrated on and off current values are defined as the values measured
by the arrow in figure 14(a). Such a feature, termed at Vg (on) = VT − 0.7Vdd and Vg (off) = VT + 0.3Vdd , so
the ‘0.7 structure’ from its height with respect to the full that 30% of the Vg swing above the threshold voltage VT
conductance on the plateau, has been observed previously on is applied to turn the device off, while the remaining 70%
quantum point contacts and quantum wires formed in clean sets the operation range of the on state. Similar methods
2D electron gas samples [84, 93, 94]. This feature is generally have been proposed in benchmarking nanoscale FET devices
believed to be caused by spontaneous spin polarization in in general [99, 100]. Using this convention, gm = 60 µS,
low-dimensional interacting electron gas systems [93] due to Ion = 37 µA (Vdd = 1 V) were obtained for device B. These
the formation of a spin gap [94] or a localized spin [84]. values correspond to scaled gm and Ion of 3.3 mS µm−1 and
Temperature-dependence data in figure 14(a) show that the 0.7 2.1 mA µm−1 , respectively, using the total nanowire diameter
feature initially increases in magnitude and then broadens as as the device width. Notably, these values are 3–4 times
temperature is increased to 50 K, consistent with the spin-gap better than the values of 0.8 mS µm−1 and 0.71 mA µm−1
hypothesis [94]. These results suggest that the 0.7 structure recently reported in state-of-the-art, sub-100 nm silicon p-
is not restricted to electron gas samples but is a universal MOSFETs employing high-κ dielectrics [101]. The geometric
phenomenon in 1D systems. In this regard, the heavier gate capacitance per unit area in the NWFETs was estimated to
effective mass of holes in Ge/Si NWs will yield a larger be at most 29% larger than in Si p-MOSFETs [97]. Therefore,
interaction parameter compared with electrons [95, 96]; this the large improvement in gm and Ion cannot be accounted
together with the strong confinement effects and a uniform for by the increase in gate capacitance alone. Moreover,
confinement potential along the channel should make Ge/Si the hole mobility for device B, 730 cm2 (V s)−1 , extracted
heterostructure NWs an ideal platform to study such novel from the peak gm = 3 µS at 10 mV bias using the charge
effects in the future. control model represents more than a factor of 10 improvement
At room temperature, these Ge/Si NWs are expected to over that of the Si pMOSFET with HfO2 gate dielectric
be suitable in ultra-high performance transistor applications, (50–60 cm2 (V s)−1 ) [101] and is also more than twice the
due to the long mean path and transparent contacts to reported mobility of Ge and strained SiGe heterostructure
these devices. To further explore their potential, Xiang PMOS devices [102,103]. Improved mobility was consistently
et al fabricated transistor devices using thin HfO2 or ZrO2 observed for Ge/Si NWFETs with channel lengths from
high-κ gate dielectrics and metal top gate electrodes [97] 0.19 to 1 µm, with an average of 640 cm2 (V s)−1 . These
(figures 15(a) and (b), so that gate coupling in the transistor improvements over planar device structures, obtained with
devices is further improved. Atomic layer deposition (ALD) benchmarked transistor data, clearly verify the performance
was used to deposit a thin high-κ dielectric film using benefit in clean Ge/Si heterostructure NWs.
Tetrakis (dimethylamino) hafnium [Hf(N(CH3 )2 )4 ] or tetrakis The subthreshold region of the Id –Vg data was
(dimethylamino) zirconium as precursors [97]. Following also analysed and yields values of the slope, S =
the fabrication of source/drain contacts, a second electron [d(log10 Id )/dVg ]−1 , of 105 mV/decade and 100 mV/decade
beam lithography step was used to define the top gate. The for the L = 1 µm and 190 nm NWFETs, respectively, at
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Figure 15. (a) Schematic and (b) cross-sectional TEM image of a top-gated Ge/Si core/shell nanowire FET device. (c) Id –Vds data for
device A (L = 1 µm) with Vg = −2–2 V in 0.25 V steps from top to bottom. (d) Id –Vg for device A, with blue, red and green data points
corresponding to Vds values of −1 V, −0.5 V and −0.01 V, respectively. Inset, linear scale plot of Id versus Vg measured at Vds = −1 V.
(e) Id –Vg data for device B (L = 190 nm) with blue, red and green data points corresponding to Vds values of −1, −0.1 and −0.01 V,
respectively. Inset: Linear scale plot of Id versus Vg measured at Vds = −1 V. Adapted from [97]. (Colour online.)
Vds = −1 V (figures 15(d) and (e)). The observed S values the fundamental RC delay of the device and provides a fre-
show little bias voltage dependence for both devices, an quency limit for transistor operation that is relatively insensi-
indication that good control of short channel effects [104] can tive to gate dielectrics and device width and thus represents a
be obtained on the NW devices down to at least L = 190 nm. good parameter for comparing different types of devices [104].
In general, an FET with a small S is essential for modern Xiang et al found that the Ge/Si nanowire devices show clear
logic circuits as it reduces the off-state current and minimizes speed advantage at a given L versus Si p-MOSFETs, and length
static power dissipation. The value of S can be estimated [70] scaling of τ is also more favourable for the Ge/Si NWFETs than
by 2.3kB T /eα, where α is the gate-coupling factor, which for the Si MOSFETs [97]. Such a difference can be attributed
yields a room-temperature minimum (α = 1) of 60 mV dec−1 . to a suppression of scattering in the quasi-1D quantum con-
The values of S determined for the L = 1 µm and 190 nm fined Ge/Si NWs versus MOSFETs [23], although additional
Ge/Si NWFETs are superior to the best value (140 mV dec−1 ) studies will be needed to support this hypothesis.
reported previously [105] for NWFETs but still larger than the
theoretical minimum. The non-ideal gate coupling (α < 1), 4. Assembly and integration techniques
which causes this larger S, is likely due to a finite trap state
density at the NW/high-κ interface [106]. Optimization of the As can be seen in the case of Ge/Si core/shell NWs, the
high-κ deposition process during fabrication or growth of a quasi-1D transport nature and clean material structure of
cylindrical high-κ shell on the Ge/Si NW prior to fabrication the nanowire system result in superior device performance,
should yield improved interface quality and enable ideal compared with even state-of-the-art planar devices [97].
subthreshold behaviour in the future in these NWFETs. However, the discussions so far are limited to the individual
The performance of the Ge/Si nanowire devices are also device level. To fully explore the potential of NW building
compared with planar Si devices using the intrinsic delay blocks for integrated devices and circuits, efficient and scalable
benchmark [100], τ = CV /I , where C is the gate capacitance, strategies are needed to assemble large amount of NWs
V = Vdd and I is the on current Ion . As defined, τ represents into increasingly complex architectures. In this regard, two
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5. Nanowire circuits
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are logic circuits that can use an address code to select and
transmit signals from multiple input wires to a single output
wire (or from a single input wire to one of several output wires).
The scaling advantage of a decoder is that it only requires n
pairs of address wires to select and control 2n NWs, e.g. ten
pairs of address wires can in principle control 1024 (210 ) NWs.
As a result, 20 pairs of address wires might be sufficient to
completely address a 1 Mbit crossbar memory [118].
DeHon et al [120] proposed that if modulation doping
along the nanowire axis can be achieved that results in
controlled shifts in the threshold voltages VT , individual NWs
can be uniquely addressed with a set of microscale control
wires. Furthermore, DeHon argued that if the coded NWs
are chosen at random from a sufficiently large population, a
large fraction (>99%) of the selected NWs will have unique
addresses, even without knowledge of the specific locations of
the coded regions [120]. Such a stochastic decoding scheme
is ideally suited for nanowire-based crossbar applications,
since during the assembly (flow-alignment or LB alignment)
process, the registry of the NWs is generally lost, resulting in
arrays of aligned albeit randomly positioned NWs.
Zhong et al obtained the first prototype nanowire decoder
in which the shifts in VT were achieved through surface
modification at the corresponding crosspoints [128]. In a
recent study, Yang et al demonstrated that modulation doping
of the NWs can be achieved during growth, hence paving the
way for an all-nanowire-based system [15]. A local substrate
heater (versus a tube furnace reactor) was used in Yang’s
study to minimize spontaneous dissociation of the precursors
away from the catalysts, since coating of doped Si over the
nanowire surface will interfere with the axial modulation
doping effects. Furthermore, the growth was carried out in a
H2 atmosphere, which further suppresses the decomposition
of silane and inhibits deposition on the nanowire surface
[12,13]. To verify that modulation doping was indeed achieved
along the nanowire growth direction, Yang used scanning
gate microscopy (SGM) [20, 129] to measure gate response
of different regions within a single nanowire. In such a
study, a conducting atomic force microscopy probe with
an applied voltage (Vtip ) functions as a spatially localized
gate, which enables the conductance of the nanowire with
pre-fabricated source and drain contacts to be varied and
Figure 18. (A) Hierarchical patterning of crossed NW arrays by mapped. Results obtained from SGM studies on modulation
photo-lithography, where NWs are removed from regions outside of doped n-type SiNWs are shown in figure 19, in which the
the defined array pattern. (B) Dark-field optical micrograph of dark regions correspond to lightly-doped n regions which
crossed NWs deposited uniformly on a 1 cm × 1 cm substrate. Scale
bar: 50 µm. (C) SEM image of patterned crossed NW arrays. Scale
show excellent gate response and bright regions correspond to
bar: 10 µm. (Inset) Large area dark-field optical micrograph of the heavily-doped n+ regions which show little gate response [15].
patterned crossed NW arrays. Scale bar: 100 µm. (D) SEM image The SGM studies clearly verified that modulation doping along
of an ultra-high density crossed NW array. Scale bar: 200 nm [113]. the nanowire axis can be achieved with full control of the
size, spacing and number of the modulated regions during
enabled by the LB approach. Array geometries and tiling the growth process. Prototype crossed nanowire/microscale-
patterns more complex than square structures are also believed control-wire decoder arrays were also fabricated and tested in
to be achievable [113]. Yang’s study, and behaviours of such devices were shown to
follow DeHon’s proposal [15, 120].
5.2. Address decoders The demonstration of modulation doping, along with the
success in producing axial and radial nanowire heterostruc-
In order to communicate and control the very large number tures [20, 22, 23], implies that specific functions can be built
of NWs used in each crossbar array with a limited number of into the system during growth, instead of having to be defined
conventional, microscale control wires, address decoders are by intermediate lithographic patterning and/or electrical con-
necessary which serve as a needed interface. Address decoders tacts fabricated after growth. For example, many of the wiring
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[150,152]. Such topics are beyond the scope of this review and
interested readers are referred to the corresponding references
listed above.
Acknowledgments
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