CONFIDENTIAL Ref. No.

: EE603/ES/2021/05

Indian Institute of Engineering Science and Technology, Shibpur

B. Tech. (EE) 6th Semester Final Examination, May-2021
Microprocessor and Microcontroller (EE603)
Full Marks: 70 Time: 1 hour 30 minutes
(i) Use a single answer-script for both halves
(ii) All parts of a question MUST be answered in the same place

First Half
Answer Qs. No. 1 and ANY TWO from the rest
Two marks are reserved for neatness

1. Answer the following:

(a) In which mode can the bits of a single port of 8255 operate independently? Name the port and the
mode.
(b) What is the data and address bus size of an 8086 microprocessor?
(c) On what factors do the resolution of an ADC depend?
(d) What are the two units of the 8086 processor that operate simultaneously to enable higher speed of
operation?
(e) The Interrupt on Terminal Count occurs in which PPI chip and in which mode?
(f) Name the basic memory element that stores a bit as a voltage.
[2+2+2+2+2+1 = 11]

2. Design a memory interfacing of an 8085 based system, having a memory size of 2KB of EPROM
and 1KB of R/W M. The monitor program of the system is stored in the EPROM. The R/WM can be
mapped from 0800H to FFFFH in this system. The available R/WM chips are of 1024x8 bits and the
EPROM chip is numbered as 2716. The memory map should be clearly defined, all necessary
hardware arrangement together with control signals should be clearly labeled. In this connection, will
a case of fold back memory arise? If yes then point out the reasons suitably. [11]

3. (a) Show with the help of a schematic diagram how the ADC 0809 is interfaced with the 8085
microprocessor. Indicate if any additional chip is necessary. Clearly indicate the control signals
involved.
(b) Draw a flowchart to show the sequence of activation of the control signals and thereafter data
reading from the ADC.
[6 + 5 = 11]

4. (a) Draw the diagram to indicate how the active low MEMR, MEMW, IOR and IOW signals are
generated from the Control signals of the 8085.
(b) Show with the help of a diagram how the following data can be stored permanently in a ROM.
The register NO 2 stores 02H and register NO 9 stores F0H.
[6 + 5 = 11]
5. Write short notes on [any two]:
(i) The Register Structure of the 8086 Microprocessor
(ii) The Data Acquisition Circuit for Monitoring of Power using a Microprocessor
(iii) The timing diagram of the PPI 8253 in Mode1.
[5½ × 2 = 11]

Page 1 of 3
Name of the Paper: Microprocessor and Microcontroller (EE-603)
Name of the Examination: 6th Semester Final Examination, May-2021
Name of the Paper Setter: Prof. K. D. Bhattacharya (1st Half) & Prof. D. Ganguly (2nd Half)

Signature of the Moderator: S. Dalapati (with date)

CONFIDENTIAL Ref. No.: EE603/ES/2021/05

Second Half
Answer ANY THREE questions
Two marks are reserved for original answers

6. (a) A number is represented as C2628000H in IEEE 754 format. What is its decimal value?
(b) If the accumulator contains 3A H, then find the status of all the flags in an Intel 8085 if the
instruction ACI 7C H is executed. Show all steps.
(c) Write an 8085 assembly language program to perform a parity check on a byte stored in location
4000H. If the parity is odd, store DDH in location 4001H, otherwise store EEH in the same
location.
[3 + 4 + 4 = 11]
7. (a) Name one 8085 instruction which includes 1 opcode fetch and 3 memory read machine cycles.
Draw the timing diagram for the same. Also find the execution time of the instruction assuming a
system clock of 3 MHz.
(b) Find the contents of the Program Counter(PC), HL register pair and DE register pair after the
execution of the PCHL instruction in the following program. (Show all intermediate steps).
2000 : LXI D, 204A H
2003 : MVI A, 05 H
2005 : STAX D
2006 : LXI H, 2048 H
2009 : XCHG
200A : PCHL
200B : JMP 200B H

(c) Find another 8085 instruction each that does the same job as the following instructions:
(i) ANI FFH (ii) XRI FFH (iii) ORI FFH
[(1 + 3 + 1) + 3 + 3 = 11]
8. (a) What is the function of ‘RST n’ instruction? How is it useful in the execution of INTR interrupt?
(b) If the stack pointer is initialized at 4000 H and the PUSH D instruction is executed, which two
memory locations carry the contents of D and E registers respectively?
(c) What are the maskable and non-maskable interrupts in Intel 8085? Which of these is ‘non-
vectored’ and why?
[(3 + 2) + 2 + 4 = 11]
9. (a) Distinguish between the following:
(i) LHLD 2000 H and LXI D 2000 H instructions of 8085
(ii) RIM and SIM instructions of 8085
(iii) SJMP and AJMP instructions of 8051
(iv) Carry flag and Overflow flag of 8051
(b) What is the content of the accumulator at the end of execution of the following 8051 program?
Show all intermediate steps.
MOV A, #80H
SETB C
MOV R1, #05H
LOOP: RRC A
DJNZ R1, LOOP

Page 2 of 3
Name of the Paper: Microprocessor and Microcontroller (EE-603)
Name of the Examination: 6th Semester Final Examination, May-2021
Name of the Paper Setter: Prof. K. D. Bhattacharya (1st Half) & Prof. D. Ganguly (2nd Half)

Signature of the Moderator: S. Dalapati (with date)

CONFIDENTIAL Ref. No.: EE603/ES/2021/05

[4 × 2 + 3 = 11]
10. (a) Which signals and registers of the 8051 are necessary for accessing external memory?
(b) Write a program in 8051 assembly language to fill a block of 10 consecutive memory locations
in internal memory (starting from 40H) with zero.
(c) Give brief answers to the following:
(i) Find the time taken by the 8051 timers to count up by 1 (Assume 12 MHz clock)
(ii) What is the default value of SP in 8051 and why should this be changed?
(iii) Which are the SFRs associated with 8051 interrupts?
(iv) How many I/O ports does the 8051 have and which is the only usable port?
[3 + 4 + 4 = 11]

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Page 3 of 3
Name of the Paper: Microprocessor and Microcontroller (EE-603)
Name of the Examination: 6th Semester Final Examination, May-2021
Name of the Paper Setter: Prof. K. D. Bhattacharya (1st Half) & Prof. D. Ganguly (2nd Half)

Signature of the Moderator: S. Dalapati (with date)