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A B C D E

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2
LCFC NM-D041 2

Y550 M/B Schematics Document


Renoir H-Processor with DDR4 + NV N18P-G61/G62 GPU

3
2020-02-24 3

REV:1.0

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Cover Page


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y550 1.0

Date: Monday, February 24, 2020 Sheet 1 of 83


A B C D E
A B C D E

nVidia N18P-G61/G62
HDMI Conn. Memory BUS (DDR4 non-ECC)
1
Page 44 PCI-Express 8X Gen3 Channel B 1

DDR4-SO-DIMM x1
Page 12,13
GDDR6*4 4GB 1.2V DDR4 2933MT/s TBD
Page 33~38
eDP x4 Lane UP TO 16G x 1
Memory BUS (DDR4 non-ECC)
Channel A
DP x4 Lane
eDP Conn
eDP x4 Lane MUX eDP x4 Lane
DDR4-SO-DIMM x1
Page 12,13
FHD PS8331B 1.2V DDR4 2933 MT/s TBD
Page 39 Page 60
sw
UP TO 16G x 1
USB redriver
+ Switch
PS8747 USB 3.1 1x
USB Type-C USB Repeater USB Right
Conn.
Page 40 SUB-Board
Page 42 USB2.0 1x USB3.1 Port4 USB20 Port3
USB 3.0 1x 5Gbps
TypeC PDC USB Left(AOU
CC Logic RTS5457T HDD Conn.
SATA Gen3 AMD APU USB3.1 port x1)
2 Page 46 SATA Port4 USB2.0 USB3.1 Port1 USB2.0 Port1 2
Page 41
USB3.1 USB Back port x2
SSD M.2 Conn.
PCIe 4x Gen3
Renoir USB2.0 USB Hub USB3.1 Port2 USB2.0 Port2
/Optane Memory
SATA Gen3
Page 45 PCIe Port 9-12

USB2.0 1x
SSD M.2 Conn. EC IT8176 int. keyboard
/Optane Memory PCIe 4x Gen3 Lidless BGA
PCIe Port 17-20
25mm*35mm
Page 45

USB 2.0 1x M.2 Card (WLAN&BT)


LAN Realtek PCIe 1x
RJ45 Conn. RTL8111H-CG PCIe 1x PCIe Port13 USB2.0 Port10
Page 53 PCIe Port14

Int. Camera USB2.0 1x


Page 39 USB2.0 Port6

HD Audio
IIC SPI BUS SPI ROM
Page 14~22
USB2.0 PORT7 16MB
3 Page 18 3

LPC
SPK Conn. Codec
Page 56 ALC3287
Page 55
SMBUS TPM
EC
int. DMIC conn ITE IT8227-LQFP128 SLB9670VQ2.0 Sub-board
Page 51 Page 50 Reserved
Page 51

HP&Mic Combo Conn. USB3.1 x1 DB


Page 55

Touch Pad G-sensor Battery Thermal Sensor Thermal Sensor CPU FAN
Reserved F75303M F75303M GPU FAN
Page 51 Page 57 Page 67 Page 58 Page 58 Page 58

RGB KB conn
for RGB SKU
Page 63
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Block Diagram


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 2 of 83
A B C D E
A B C D E

Voltage Rails ( O --> Means ON , X --> Means OFF )


SIGNAL
+5VS STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
+3VS
Power Plane Full ON HIGH HIGH HIGH HIGH ON ON ON ON
VCCIO
VCCSA S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VCCSTG
1
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 1

+3VALW
VCCCPUCORE S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
B+ +3VALW_PCH +1.2V VCCGFXCORE
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+5VALW +1.8VS_AON
+1.8VGS
State BOM Structure Control Table
NVVDD
+1.0VGS
BOM Structure BTO Item BOM Structure BTO Item
@ Not stuff MIRROR@ MIRROR
FBVDDQ 15@ 15'' Stuff N18EG0@N18EG1@ GPU part
17@ 17'' stuff NOMIRROR@ 17'' stuff
7000P@ 7000P stuff NPI@ SPI VCC diode stuff
S0 O O O O O 7502M@ 7502 stuff OPT@ For NV GPU part
8111GUL@ LAN Chip 8111GUL part OPTANE@ Optane memory support part
8111H@ LAN Chip 8111H part
S3 O O O O X AG@ Anti-ghost TPM@ For support TPM sku part
2 AOAC@ AOAC support part 2
BL
S3 BL@
Battery only O O O O X CD@ Cost down part UP9632_@ UP9632 part stuff
CNVI@ CNVi support part USB@ USB2.0 port1 for USB Port
DCI@ DCI X76@ VRAM
USB2.0 port 1for Debug Reserved for G-sensor
S5 S4/AC Only O O O X X Debug@ GS@
EMC@ EMC part
EMC_8111H@ LAN 8111H EMC Part
S5 S4 EMC_NS@ EMC not stuff
Battery only O X X X X GC6@ GC6
GYSNC@ GSYNC support part
S5 S4 HDMI@ HDMI
AC & Battery X X X X X i5@i7@i9@ CPU Part
don't exist ME@ ME part(connector, hole)
M6GX6@S6GX6@ VRAM part

3 3

USB2.0 Port table USB3.0 Port table SATA Port table PCIE Port table
Port Function Port Function Port Function Port Function
1 Back USB3.0 1 Back USB3.0 0A NA 1:8 NA
2 Left USB3.0 2 Type-C Port 0B NA 9 M.2 SSD/Optane
3 Right USB3.0 3 Left USB3.0 1A M.2 SSD Gen3 10 M.2 SSD/Optane
4 Type-C Port 4 Right USB3.0 1B NA 11 M.2 SSD/Optane
5 NA 5 Back USB3.0 2 NA 12 M.2 SSD/Optane
6 Camera 6 NA 3 HDD Gen3 13 WLAN Gen1
7:8 NA 4 NA 14 LAN Gen1
9 AG
5 NA 15 Reserved for Card Reader
4 4
10
Back USB3.0 7 M.2 SSD Gen3 17:20 M.2 SSD
11:13
NA
14 BT Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Notes List


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 3 of 83
A B C D E
5 4 3 2 1

+3VALW
PD Controller AG Controller RGB
RTS5457 IT8176
2.2K
UT2 U22
D D

EC_SMB_CK0
EC_SMB_DA0

+3VALW_R
Change IC NVDD controller Vcore controller
Battery BQ24780SRUYR NCP81611 MP2979A
2.2K
JBATT1 PU201 PU7501 PU2901

EC
EC_SMB_CK1
EC_SMB_DA1

C C
+1.8VS_AON +3VALW_PCH
UE1
IT8227E
2.2K 2.2K
VGA( UV1 ) PCH( UH1 )
+3VS Thermal sensor
VGA_SMB_CK2 SML1CLK Thermal sensor
VGA_SMB_DA2 SML1DATA
F75303M NCT7718W G-Sensor
+1.8VS_AON +3VS U1 (reserved) U134 LIS2DWLTR
2.2K
Dual MOS Control Dual MOS Control
US2

EC_SMB_CK2
EC_SMB_DA2

B B

SMBUS Control Table

SOURCE VGA BATT IT8226E SODIMM WLAN Thermal PCH TP Charger RGB KB USB-C HiFi Audio Anti-ghost
WiMAX Sensor Module Backlight PD

EC_SMB_CK0 IT8226E V V
EC_SMB_DA0 +3VALW X X X X X X X X X X X
+5VS +3VALW_AG

EC_SMB_CK1 IT8226E X V V X X X X X V X X X X
EC_SMB_DA1 +3VALW_R +3VALW_R +3VALW_R +3VALW_R

EC_SMB_CK2 IT8226E V X V X X V V X X X X X X
+3VS
EC_SMB_DA2 +3VS +1.8VS_AON +3VS Reserve +3VALW_PCH

PCH_SMBCLK V V
PCH X X X X X X X X X X X
PCH_SMBDATA +3VALW_PCH +3VS +3VS
PCH_RGBKB_SCL V
PCH_RGBKB_SDA X X X X X X X X X X +LDO_3V3 X X X
EC_SMB_CK0 IT8226E V
+3VALW X X X X X X X X X X X X
EC_SMB_DA0 +5VS

A A

EC SM Bus1 address EC SM Bus2 address PCH SM Bus address PCH I2C 2 Bus address
Device Address Device Address
Device Address Device Address Need to update
DDR DIMMA 1010 000X b RGB Backlight
Smart Battery 0X16 Thermal Sensor F75303M 1001_100x b
DDR DIMMB 1010 010X b
Charger 0001 0010 b VGA 0x9E (default)
TP Module Need to update
PCH Need to update
Wlan Reserved
Thermal Sensor NCT7718W 1001100xb

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank4


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 1.0

Date: Monday, February 24, 2020 Sheet 4 of 83


5 4 3 2 1
5 4 3 2 1

25 PCIE_CRX_GTX_N[0..7]

25 PCIE_CRX_GTX_P[0..7]

PCIE_CTX_C_GRX_N[0..7] 25

PCIE_CTX_C_GRX_P[0..7] 25

D D

UC1A

PCIE_CRX_GTX_P0 G13 F4 PCIE_CTX_GRX_P0 OPT@ CC153 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P0


PCIE_CRX_GTX_N0 F13 P_GFX_RXP0 P_GFX_TXP0 F2 PCIE_CTX_GRX_N0 OPT@ CC1 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N0
P_GFX_RXN0 P_GFX_TXN0
PCIE_CRX_GTX_P1 J14 F3 PCIE_CTX_GRX_P1 OPT@ CC152 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P1
PCIE_CRX_GTX_N1 H14 P_GFX_RXP1 P_GFX_TXP1 E4 PCIE_CTX_GRX_N1 OPT@ CC2 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N1
P_GFX_RXN1 P_GFX_TXN1
PCIE_CRX_GTX_P2 G15 E1 PCIE_CTX_GRX_P2 OPT@ CC19 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P2
PCIE_CRX_GTX_N2 F15 P_GFX_RXP2 P_GFX_TXP2 C1 PCIE_CTX_GRX_N2 OPT@ CC3 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N2
P_GFX_RXN2 P_GFX_TXN2
PCIE_CRX_GTX_P3 J15 D5 PCIE_CTX_GRX_P3 OPT@ CC20 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P3
PCIE_CRX_GTX_N3 K15 P_GFX_RXP3 P_GFX_TXP3 E6 PCIE_CTX_GRX_N3 OPT@ CC4 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N3
P_GFX_RXN3 P_GFX_TXN3
PCIE_CRX_GTX_P4 H16 C6 PCIE_CTX_GRX_P4 OPT@ CC151 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P4
PCIE_CRX_GTX_N4 J16 P_GFX_RXP4 P_GFX_TXP4 D6 PCIE_CTX_GRX_N4 OPT@ CC5 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N4
P_GFX_RXN4 P_GFX_TXN4
PCIE_CRX_GTX_P5 F18 B6 PCIE_CTX_GRX_P5 OPT@ CC150 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P5
PCIE_CRX_GTX_N5 G18 P_GFX_RXP5 P_GFX_TXP5 C7 PCIE_CTX_GRX_N5 OPT@ CC6 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N5
P_GFX_RXN5 P_GFX_TXN5
PCIE_CRX_GTX_P6 J18 D8 PCIE_CTX_GRX_P6 OPT@ CC149 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P6
PCIE_CRX_GTX_N6 K18 P_GFX_RXP6 P_GFX_TXP6 B8 PCIE_CTX_GRX_N6 OPT@ CC7 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N6
P_GFX_RXN6 P_GFX_TXN6
C C
PCIE_CRX_GTX_P7 H19 C8 PCIE_CTX_GRX_P7 OPT@ CC148 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_P7
PCIE_CRX_GTX_N7 G19 P_GFX_RXP7 P_GFX_TXP7 A8 PCIE_CTX_GRX_N7 OPT@ CC8 1 2 0.22U_0201_6.3V6-K PCIE_CTX_C_GRX_N7
P_GFX_RXN7 P_GFX_TXN7

PCIE_PRX_DTX_P0 G11 L3 PCIE_PTX_DRX_P0 CC157 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P0


56 PCIE_PRX_DTX_P0 PCIE_PRX_DTX_N0 P_GPP_RXP0 P_GPP_TXP0 PCIE_PTX_DRX_N0 PCIE_PTX_C_DRX_N0 PCIE_PTX_C_DRX_P0 56
F11 L1 CC158 1 2 0.1U_0201_6.3V6-K
LAN 56 PCIE_PRX_DTX_N0 P_GPP_RXN0 P_GPP_TXN0 PCIE_PTX_C_DRX_N0 56 LAN
PCIE_PRX_DTX_P1 J10 L4 PCIE_PTX_DRX_P1 CC159 1 2 0.1U_0201_6.3V6-K PCIE_PTX_C_DRX_P1
47 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 P_GPP_RXP1 P_GPP_TXP1 PCIE_PTX_DRX_N1 PCIE_PTX_C_DRX_N1 PCIE_PTX_C_DRX_P1 47
WLAN H10 L2 CC160 1 2 0.1U_0201_6.3V6-K
WLAN
47 PCIE_PRX_DTX_N1 P_GPP_RXN1 P_GPP_TXN1 PCIE_PTX_C_DRX_N1 47
SATA_PRX_DTX_P0 G8 M4 SATA_PTX_DRX_P0
48 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 P_GPP_RXP2/SATA0_RXP P_GPP_TXP2/SATA0_TXP SATA_PTX_DRX_N0 SATA_PTX_DRX_P0 48
HDD F8 M2 HDD
48 SATA_PRX_DTX_N0 P_GPP_RXN2/SATA0_RXN P_GPP_TXN2/SATA0_TXN SATA_PTX_DRX_N0 48
G6 N3
F7 P_GPP_RXP3/SATA1_RXP P_GPP_TXP3/SATA1_TXP N1
P_GPP_RXN3/SATA1_RXN P_GPP_TXN3/SATA1_TXN

PCIE_PRX_DTX_P4 M9 T2 PCIE_PTX_DRX_P4
46 PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 P_GPP_RXP4 P_GPP_TXP4 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 46
M8 T4
46 PCIE_PRX_DTX_N4 P_GPP_RXN4 P_GPP_TXN4 PCIE_PTX_DRX_N4 46
PCIE_PRX_DTX_P5 L7 R1 PCIE_PTX_DRX_P5
46 PCIE_PRX_DTX_P5 PCIE_PRX_DTX_N5 P_GPP_RXP5 P_GPP_TXP5 PCIE_PTX_DRX_N5 PCIE_PTX_DRX_P5 46
L6 R3
46 PCIE_PRX_DTX_N5 P_GPP_RXN5 P_GPP_TXN5 PCIE_PTX_DRX_N5 46
PCIE_PRX_DTX_P6 K7 P2 PCIE_PTX_DRX_P6 M.2 SSD0
M.2 SSD0 46 PCIE_PRX_DTX_P6 PCIE_PRX_DTX_N6 K8 P_GPP_RXP6 P_GPP_TXP6 P4 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 46
46 PCIE_PRX_DTX_N6 P_GPP_RXN6 P_GPP_TXN6 PCIE_PTX_DRX_N6 46
PCIE_PRX_DTX_P7 H6 N2 PCIE_PTX_DRX_P7
46 PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 P_GPP_RXP7 P_GPP_TXP7 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 46
H7 N4
46 PCIE_PRX_DTX_N7 P_GPP_RXN7 P_GPP_TXN7 PCIE_PTX_DRX_N7 46

PCIE_SATA_PRX_DTX_P8 L9 K2 PCIE_SATA_PTX_DRX_P8
46 PCIE_SATA_PRX_DTX_P8 PCIE_SATA_PRX_DTX_N8 P_GPP_RXP8/SATA2_RXP P_GPP_TXP8/SATA2_TXP PCIE_SATA_PTX_DRX_N8 PCIE_SATA_PTX_DRX_P8 46
L10 K4
46 PCIE_SATA_PRX_DTX_N8 P_GPP_RXN8/SATA2_RXN P_GPP_TXN8/SATA2_TXN PCIE_SATA_PTX_DRX_N8 46
PCIE_PRX_DTX_P9 K11 J4 PCIE_PTX_DRX_P9
B 46 PCIE_PRX_DTX_P9 PCIE_PRX_DTX_N9 P_GPP_RXP9/SATA3_RXP P_GPP_TXP9/SATA3_TXP PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9 46 B
J11 J2
46 PCIE_PRX_DTX_N9 P_GPP_RXN9/SATA3_RXN P_GPP_TXN9/SATA3_TXN PCIE_PTX_DRX_N9 46
PCIE_PRX_DTX_P10 J12 H3 PCIE_PTX_DRX_P10
46 PCIE_PRX_DTX_P10 PCIE_PRX_DTX_N10 P_GPP_RXP10 P_GPP_TXP10 PCIE_PTX_DRX_N10 PCIE_PTX_DRX_P10 46
H12 H1
46 PCIE_PRX_DTX_N10 P_GPP_RXN10 P_GPP_TXN10 PCIE_PTX_DRX_N10 46 M.2 SSD1
M.2 SSD1 PCIE_PRX_DTX_P11 J13 H4 PCIE_PTX_DRX_P11
46 PCIE_PRX_DTX_P11 PCIE_PRX_DTX_N11 P_GPP_RXP11 P_GPP_TXP11 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 46
K13 H2
46 PCIE_PRX_DTX_N11 P_GPP_RXN11 P_GPP_TXN11 PCIE_PTX_DRX_N11 46
FP6 REV0.92
PART 2/13

AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 (PCIE SATA I/F)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 5 of 83
5 4 3 2 1
5 4 3 2 1

UC1B
UC1C
17 DDRA_MA[0..13] DDRA_MA0 DDRA_DQ[0..63] 17
AK26 DDRB_DQ[0..63] 18
DDRA_MA1 MA_ADD0/RSVD DDRA_DQ0 18 DDRB_MA[0..13] DDRB_MA0
AG24 K27 AM29
DDRA_MA2 AG23 MA_ADD1/RSVD MA_DATA0/MAA_DATA8 L26 DDRA_DQ1 DDRB_MA1 AH31 MB_ADD0/RSVD C27 DDRB_DQ0
DDRA_MA3 AG26 MA_ADD2/MAB_CA0 MA_DATA1/MAA_DATA9 N26 DDRA_DQ2 DDRB_MA2 AJ30 MB_ADD1/RSVD MB_DATA0/MBA_DATA8 A28 DDRB_DQ1
DDRA_MA4 AG27 MA_ADD3/MAA_CA4 MA_DATA2/MAA_DATA13 N27 DDRA_DQ3 DDRB_MA3 AH29 MB_ADD2/MBB_CA0 MB_DATA1/MBA_DATA9 F29 DDRB_DQ2
DDRA_MA5 AF21 MA_ADD4/MAA_CA5 MA_DATA3/MAA_DATA12 G27 DDRA_DQ4 DDRB_MA4 AG32 MB_ADD3/MBA_CA4 MB_DATA2/MBA_DATA13 F31 DDRB_DQ3
DDRA_MA6 AF22 MA_ADD5/MAA_CA3 MA_DATA4/MAA_DATA11 H27 DDRA_DQ5 DDRB_MA5 AG30 MB_ADD4/MBA_CA5 MB_DATA3/MBA_DATA12 B27 DDRB_DQ4
DDRA_MA7 AF25 MA_ADD6/MAA_CA2 MA_DATA5/MAA_DATA10 M27 DDRA_DQ6 DDRB_MA6 AG31 MB_ADD5/MBA_CA3 MB_DATA4/MBA_DATA11 D27 DDRB_DQ5
DDRA_MA8 AF24 MA_ADD7/RSVD MA_DATA6/MAA_DATA15 N24 DDRA_DQ7 DDRB_MA7 AF30 MB_ADD6/MBA_CA2 MB_DATA5/MBA_DATA10 E32 DDRB_DQ6
D DDRA_MA9 AE21 MA_ADD8/RSVD MA_DATA7/MAA_DATA14 DDRB_MA8 AG29 MB_ADD7/RSVD MB_DATA6/MBA_DATA15 F30 DDRB_DQ7 D
DDRA_MA10 AL21 MA_ADD9/RSVD L23 DDRA_DQ8 DDRB_MA9 AF29 MB_ADD8/RSVD MB_DATA7/MBA_DATA14
DDRA_MA11 AF27 MA_ADD10/MAB_CS_L1 MA_DATA8/MAA_DATA0 N21 DDRA_DQ9 DDRB_MA10 AM30 MB_ADD9/RSVD H31 DDRB_DQ8
DDRA_MA12 AE23 MA_ADD11/MAA_CKE1 MA_DATA9/MAA_DATA1 T21 DDRA_DQ10 DDRB_MA11 AF31 MB_ADD10/MBB_CS_L1 MB_DATA8/MBA_DATA0 H30 DDRB_DQ9
DDRA_MA13 AM23 MA_ADD12/MAA_CKE0 MA_DATA10/MAA_DATA5 T22 DDRA_DQ11 DDRB_MA12 AE32 MB_ADD11/MBA_CKE1 MB_DATA9/MBA_DATA1 K31 DDRB_DQ10
AM21 MA_ADD13_BANK2/RSVD MA_DATA11/MAA_DATA4 M22 DDRA_DQ12 DDRB_MA13 AP30 MB_ADD12/MBA_CKE0 MB_DATA10/MBA_DATA5 L30 DDRB_DQ11
17 DDRA_MA14_WE# MA_WE_L_ADD14/MAB_CKE1 MA_DATA12/MAA_DATA7 DDRA_DQ13 MB_ADD13_BANK2/RSVD MB_DATA11/MBA_DATA4 DDRB_DQ12
AL27 L24 AP31 G30
17 DDRA_MA15_CAS# MA_CAS_L_ADD15/RSVD MA_DATA13/MAA_DATA6 DDRA_DQ14 18 DDRB_MA14_WE# MB_WE_L_ADD14/MBB_CKE1 MB_DATA12/MBA_DATA7 DDRB_DQ13
AL24 R21 AP29 H29
17 DDRA_MA16_RAS# MA_RAS_L_ADD16/MAB_CKE0 MA_DATA14/MAA_DATA2 R23 DDRA_DQ15 18 DDRB_MA15_CAS# AN29 MB_CAS_L_ADD15/RSVD MB_DATA13/MBA_DATA6 K30 DDRB_DQ14
MA_DATA15/MAA_DATA3 18 DDRB_MA16_RAS# MB_RAS_L_ADD16/MBB_CKE0 MB_DATA14/MBA_DATA2 DDRB_DQ15
K29
AL22 P24 DDRA_DQ16 MB_DATA15/MBA_DATA3
17 DDRA_BA0 MA_BANK0/MAB_CS_L0 MA_DATA16/MAA_DATA17 DDRA_DQ17 DDRB_DQ16
AK27 R26 AN31 N32
17 DDRA_BA1 MA_BANK1/MAB_CA1 MA_DATA17/MAA_DATA16 T27 DDRA_DQ18 18 DDRB_BA0 AM32 MB_BANK0/MBB_CS_L0 MB_DATA16/MBA_DATA21 N29 DDRB_DQ17
AE27 MA_DATA18/MAA_DATA21 V27 DDRA_DQ19 18 DDRB_BA1 MB_BANK1/MBB_CA1 MB_DATA17/MBA_DATA22 P30 DDRB_DQ18
17 DDRA_BG0 MA_BG0/MAA_CS_L1 MA_DATA19/MAA_DATA20 DDRA_DQ20 MB_DATA18/MBA_DATA20 DDRB_DQ19
AE26 P25 AD29 L32
17 DDRA_BG1 MA_BG1/MAA_CS_L0 MA_DATA20/MAA_DATA19 P27 DDRA_DQ21 18 DDRB_BG0 AD31 MB_BG0/MBA_CS_L1 MB_DATA19/MBA_DATA19 L31 DDRB_DQ20
MA_DATA21/MAA_DATA18 DDRA_DQ22 18 DDRB_BG1 MB_BG1/MBA_CS_L0 MB_DATA20/MBA_DATA17 DDRB_DQ21
AD22 V23 M30
17 DDRA_ACT# MA_ACT_L/RSVD MA_DATA22/MAA_DATA23 DDRA_DQ23 MB_DATA21/MBA_DATA16 DDRB_DQ22
T25 AD30 L29
L27 MA_DATA23/MAA_DATA22 18 DDRB_ACT# MB_ACT_L/RSVD MB_DATA22/MBA_DATA18 N31 DDRB_DQ23
17 DDRA_DM0 MA_DM0/MAA_DM1 DDRA_DQ24 MB_DATA23/MBA_DATA23
N23 W22 C30
17 DDRA_DM1 R27 MA_DM1/MAA_DM0 MA_DATA24/MAA_DATA30 Y23 DDRA_DQ25 18 DDRB_DM0 H32 MB_DM0/MBA_DM1 R30 DDRB_DQ24
17 DDRA_DM2 MA_DM2/MAA_DM2 MA_DATA25/MAA_DATA31 DDRA_DQ26 18 DDRB_DM1 MB_DM1/MBA_DM0 MB_DATA24/MBA_DATA30 DDRB_DQ25
Y24 AC24 M29 R32
17 DDRA_DM3 AP27 MA_DM3/MAA_DM3 MA_DATA26/MAA_DATA26 AC23 DDRA_DQ27 18 DDRB_DM2 T29 MB_DM2/MBA_DM2 MB_DATA25/MBA_DATA31 V30 DDRB_DQ26
17 DDRA_DM4 AW23 MA_DM4/MAB_DM2 MA_DATA27/MAA_DATA27 V21 DDRA_DQ28 18 DDRB_DM3 AU30 MB_DM3/MBA_DM3 MB_DATA26/MBA_DATA26 V32 DDRB_DQ27
17 DDRA_DM5 AT21 MA_DM5/MAB_DM3 MA_DATA28/MAA_DATA28 W21 DDRA_DQ29 18 DDRB_DM4 BD28 MB_DM4/MBB_DM2 MB_DATA27/MBA_DATA27 P29 DDRB_DQ28
17 DDRA_DM6 AV18 MA_DM6/MAB_DM1 MA_DATA29/MAA_DATA29 AA24 DDRA_DQ30 18 DDRB_DM5 BB23 MB_DM5/MBB_DM3 MB_DATA28/MBA_DATA28 P31 DDRB_DQ29
17 DDRA_DM7 MA_DM7/MAB_DM0 MA_DATA30/MAA_DATA24 DDRA_DQ31 18 DDRB_DM6 MB_DM6/MBB_DM1 MB_DATA29/MBA_DATA29 DDRB_DQ30
W24 AA22 BD20 U31
MA_DM8/RSVD_52 MA_DATA31/MAA_DATA25 18 DDRB_DM7 MB_DM7/MBB_DM0 MB_DATA30/MBA_DATA25 DDRB_DQ31
W31 U29
DDRA_DQS0 M25 AP26 DDRA_DQ32 MB_DM8/RSVD_57 MB_DATA31/MBA_DATA24
17 DDRA_DQS0 DDRA_DQS#0 MA_DQS_H0/MAA_DQS_H1 MA_DATA32/MAB_DATA17 DDRA_DQ33 DDRB_DQS0 DDRB_DQ32
M24 AN24 E29 AT29
17 DDRA_DQS#0 DDRA_DQS1 P22 MA_DQS_L0/MAA_DQS_L1 MA_DATA33/MAB_DATA16 AR25 DDRA_DQ34 18 DDRB_DQS0 DDRB_DQS#0 D28 MB_DQS_H0/MBA_DQS_H1 MB_DATA32/MBB_DATA16 AU32 DDRB_DQ33
17 DDRA_DQS1 DDRA_DQS#1 MA_DQS_H1/MAA_DQS_H0 MA_DATA34/MAB_DATA21 DDRA_DQ35 18 DDRB_DQS#0 DDRB_DQS1 MB_DQS_L0/MBA_DQS_L1 MB_DATA33/MBB_DATA17 DDRB_DQ34
P21 AU26 J31 AW31
17 DDRA_DQS#1 DDRA_DQS2 MA_DQS_L1/MAA_DQS_L0 MA_DATA35/MAB_DATA20 DDRA_DQ36 18 DDRB_DQS1 DDRB_DQS#1 MB_DQS_H1/MBA_DQS_H0 MB_DATA34/MBB_DATA21 DDRB_DQ35
T24 AN25 J29 AW30
17 DDRA_DQS2 DDRA_DQS#2 R24 MA_DQS_H2/MAA_DQS_H2 MA_DATA36/MAB_DATA19 AN27 DDRA_DQ37 18 DDRB_DQS#1 DDRB_DQS2 N30 MB_DQS_L1/MBA_DQS_L0 MB_DATA35/MBB_DATA20 AR30 DDRB_DQ36
17 DDRA_DQS#2 DDRA_DQS3 AA21 MA_DQS_L2/MAA_DQS_L2 MA_DATA37/MAB_DATA18 AR27 DDRA_DQ38 18 DDRB_DQS2 DDRB_DQS#2 M31 MB_DQS_H2/MBA_DQS_H2 MB_DATA36/MBB_DATA19 AT31 DDRB_DQ37
C 17 DDRA_DQS3 DDRA_DQS#3 Y21 MA_DQS_H3/MAA_DQS_H3 MA_DATA38/MAB_DATA23 AU27 DDRA_DQ39 18 DDRB_DQS#2 DDRB_DQS3 T30 MB_DQS_L2/MBA_DQS_L2 MB_DATA37/MBB_DATA18 AV30 DDRB_DQ38 C
17 DDRA_DQS#3 DDRA_DQS4 AP23 MA_DQS_L3/MAA_DQS_L3 MA_DATA39/MAB_DATA22 18 DDRB_DQS3 DDRB_DQS#3 T31 MB_DQS_H3/MBA_DQS_H3 MB_DATA38/MBB_DATA23 AW29 DDRB_DQ39
17 DDRA_DQS4 DDRA_DQS#4 MA_DQS_H4/MAB_DQS_H2 DDRA_DQ40 18 DDRB_DQS#3 DDRB_DQS4 MB_DQS_L3/MBA_DQS_L3 MB_DATA39/MBB_DATA22
AP24 AV25 AU29
17 DDRA_DQS#4 DDRA_DQS5 AW22 MA_DQS_L4/MAB_DQS_L2 MA_DATA40/MAB_DATA30 AW25 DDRA_DQ41 18 DDRB_DQS4 DDRB_DQS#4 AU31 MB_DQS_H4/MBB_DQS_H2 AY29 DDRB_DQ40
17 DDRA_DQS5 DDRA_DQS#5 MA_DQS_H5/MAB_DQS_H3 MA_DATA41/MAB_DATA31 DDRA_DQ42 18 DDRB_DQS#4 DDRB_DQS5 MB_DQS_L4/MBB_DQS_L2 MB_DATA40/MBB_DATA29 DDRB_DQ41
AV22 AV20 BA27 AY32
17 DDRA_DQS#5 DDRA_DQS6 AT20 MA_DQS_L5/MAB_DQS_L3 MA_DATA42/MAB_DATA26 AW20 DDRA_DQ43 18 DDRB_DQS5 DDRB_DQS#5 BB27 MB_DQS_H5/MBB_DQS_H3 MB_DATA41/MBB_DATA28 BC27 DDRB_DQ42
17 DDRA_DQS6 DDRA_DQS#6 MA_DQS_H6/MAB_DQS_H1 MA_DATA43/MAB_DATA27 DDRA_DQ44 18 DDRB_DQS#5 DDRB_DQS6 MB_DQS_L5/MBB_DQS_L3 MB_DATA42/MBB_DATA24 DDRB_DQ43
AR20 AV27 BC23 BB26
17 DDRA_DQS#6 DDRA_DQS7 MA_DQS_L6/MAB_DQS_L1 MA_DATA44/MAB_DATA28 DDRA_DQ45 18 DDRB_DQS6 DDRB_DQS#6 MB_DQS_H6/MBB_DQS_H1 MB_DATA43/MBB_DATA25 DDRB_DQ44
AR18 AW26 BA23 BC25
17 DDRA_DQS7 DDRA_DQS#7 AT18 MA_DQS_H7/MAB_DQS_H0 MA_DATA45/MAB_DATA29 AU21 DDRA_DQ46 18 DDRB_DQS#6 DDRB_DQS7 BC20 MB_DQS_L6/MBB_DQS_L1 MB_DATA44/MBB_DATA27 BA25 DDRB_DQ45
17 DDRA_DQS#7 MA_DQS_L7/MAB_DQS_L0 MA_DATA46/MAB_DATA24 DDRA_DQ47 18 DDRB_DQS7 DDRB_DQS#7 MB_DQS_H7/MBB_DQS_H0 MB_DATA45/MBB_DATA26 DDRB_DQ46
Y26 AW21 BA20 BB30
Y27 MA_DQS_H8/RSVD_58 MA_DATA47/MAB_DATA25 18 DDRB_DQS#7 Y32 MB_DQS_L7/MBB_DQS_L0 MB_DATA46/MBB_DATA30 BA28 DDRB_DQ47
MA_DQS_L8/RSVD_59 AT22 DDRA_DQ48 Y30 MB_DQS_H8/RSVD_61 MB_DATA47/MBB_DATA31
DDRA_CLK0 AJ25 MA_DATA48/MAB_DATA11 AP21 DDRA_DQ49 MB_DQS_L8/RSVD_60 BA24 DDRB_DQ48
17 DDRA_CLK0 DDRA_CLK0# AJ24 MA_CLK_H0/MAA_CKT MA_DATA49/MAB_DATA10 AN19 DDRA_DQ50 DDRB_CLK0 AJ31 MB_DATA48/MBB_DATA11 BC24 DDRB_DQ49
17 DDRA_CLK0# DDRA_CLK1 MA_CLK_L0/MAA_CKC MA_DATA50/MAB_DATA14 DDRA_DQ51 18 DDRB_CLK0 DDRB_CLK0# MB_CLK_H0/MBA_CKT MB_DATA49/MBB_DATA10 DDRB_DQ50
AJ22 AN18 AK30 BC22
17 DDRA_CLK1 DDRA_CLK1# AJ21 MA_CLK_H1/MAB_CKT MA_DATA51/MAB_DATA15 AU23 DDRA_DQ52 18 DDRB_CLK0# DDRB_CLK1 AK32 MB_CLK_L0/MBA_CKC MB_DATA50/MBB_DATA14 BA22 DDRB_DQ51
17 DDRA_CLK1# MA_CLK_L1/MAB_CKC MA_DATA52/MAB_DATA12 DDRA_DQ53 18 DDRB_CLK1 DDRB_CLK1# MB_CLK_H1/MBB_CKT MB_DATA51/MBB_DATA15 DDRB_DQ52
AR22 AL31 BB25
MA_DATA53/MAB_DATA13 DDRA_DQ54 18 DDRB_CLK1# MB_CLK_L1/MBB_CKC MB_DATA52/MBB_DATA12 DDRB_DQ53
AN20 BD25
MA_DATA54/MAB_DATA9 AP19 DDRA_DQ55 MB_DATA53/MBB_DATA13 BB22 DDRB_DQ54
MA_DATA55/MAB_DATA8 MB_DATA54/MBB_DATA9 BD22 DDRB_DQ55
AT19 DDRA_DQ56 MB_DATA55/MBB_DATA8
DDRA_CS0# AL25 MA_DATA56/MAB_DATA6 AW18 DDRA_DQ57 BA21 DDRB_DQ56
17 DDRA_CS0# DDRA_CS1# MA_CS_L0/MAB_CA2 MA_DATA57/MAB_DATA7 DDRA_DQ58 MB_DATA56/MBB_DATA4 DDRB_DQ57
AM26 AU16 AN30 BC21
17 DDRA_CS1# MA_CS_L1/MAB_CA5 MA_DATA58/MAB_DATA2 DDRA_DQ59 18 DDRB_CS0# MB_CS_L0/MBB_CA2 MB_DATA57/MBB_DATA5 DDRB_DQ58
AW16 AR31 BC18
MA_DATA59/MAB_DATA3 DDRA_DQ60 18 DDRB_CS1# MB_CS_L1/MBB_CA5 MB_DATA58/MBB_DATA2 DDRB_DQ59
AW19 BB18
MA_DATA60/MAB_DATA4 AU19 DDRA_DQ61 MB_DATA59/MBB_DATA3 BB20 DDRB_DQ60
MA_DATA61/MAB_DATA5 AP16 DDRA_DQ62 MB_DATA60/MBB_DATA6 BB21 DDRB_DQ61
MA_DATA62/MAB_DATA1 AT16 DDRA_DQ63 MB_DATA61/MBB_DATA7 BB19 DDRB_DQ62
DDRA_CKE0 AD24 MA_DATA63/MAB_DATA0 MB_DATA62/MBB_DATA1 BA18 DDRB_DQ63
17 DDRA_CKE0 DDRA_CKE1 MA_CKE0/MAA_CA1 MB_DATA63/MBB_DATA0
AD25 W27 AC31
17 DDRA_CKE1 MA_CKE1/MAA_CA0 MA_CHECK0/RSVD_54 W25 18 DDRB_CKE0 AC29 MB_CKE0/MBA_CA1 W30
MA_CHECK1/RSVD_53 18 DDRB_CKE1 MB_CKE1/MBA_CA0 MB_CHECK0/RSVD_56
AC26 W29
MA_CHECK2/RSVD_68 AC27 MB_CHECK1/RSVD_55 AA30
DDRA_ODT0 AM24 MA_CHECK3/RSVD_69 V26 MB_CHECK2/RSVD_65 AB29
17 DDRA_ODT0 DDRA_ODT1 MA_ODT0/MAB_CA3 MA_CHECK4/RSVD_49 MB_CHECK3/RSVD_67
B AM27 V24 AP32 V29 B
17 DDRA_ODT1 MA_ODT1/MAB_CA4 MA_CHECK5/RSVD_48 AA27 18 DDRB_ODT0 AR29 MB_ODT0/MBB_CA3 MB_CHECK4/RSVD_50 V31
MA_CHECK6/RSVD_63 AA25 18 DDRB_ODT1 MB_ODT1/MBB_CA4 MB_CHECK5/RSVD_51 AA29
MA_CHECK7/RSVD_62 MB_CHECK6/RSVD_64 AA31
DDRA_ALERT# AE24 +1.2V MB_CHECK7/RSVD_66
17 DDRA_ALERT# MA_ALERT_L/TEST31A AK24 AE30
DDRA_EVENT# MA_PAROUT/RSVD DDRA_PARITY 17 18 DDRB_ALERT# MB_ALERT_L/TEST31B
AK23 AM31
17 DDRA_EVENT# DDRA_DRAMRST# MA_EVENT_L MB_PAROUT/RSVD DDRB_PARITY 18
17 DDRA_DRAMRST# AD27 AN21 18 DDRB_EVENT# AL30
MA_RESET_L FP6 REV0.92 M_DDR4 AN22 AC32 MB_EVENT_L FP6 REV0.92
PART 1/13 M_LPDDR4 18 DDRB_DRAMRST# MB_RESET_L PART 9/13

AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140
@ @
+1.2V

1
RD37 RD38
1K_0402_1% 1K_0402_1%
2

@ @

DDRA_ALERT#

DDRB_ALERT#
A A

Security Classification LC Future Center Secret Data Title


Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 (MEM)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 6 of 83
5 4 3 2 1
5 4 3 2 1

+1.8VS +1.8VS
UC1D

2
APU_EDP_TX0+ D11 A22 DP_ENBKL PD FOR CUSTOMER
39 APU_EDP_TX0+ APU_EDP_TX0- B11 DP0_TXP0 DP_BLON D23 DP_ENVDD PU FOR INTERNAL
RC52 RC49
+1.8VALW 39 APU_EDP_TX0- DP0_TXN0 DP_DIGON C23 DP_EDP_PWM 39.2_0402_1% @ 1K_0402_5%
APU_EDP_TX1+ C11 DP_VARY_BL @
39 APU_EDP_TX1+ APU_EDP_TX1- DP0_TXP1 APU_EDP_AUX APU_EDP_HPD
A11 D12 RC53 1 2 100K_0402_5%

APU_TEST31
39 APU_EDP_TX1- APU_EDP_AUX 39

1
DP0_TXN1 DP0_AUXP
1

B12 APU_EDP_AUX# APU_TEST31 DP_STEREOSYNC


RC50
eDP APU_EDP_TX2+ D10 DP0_AUXN C12 APU_EDP_HPD APU_EDP_AUX# 39 eDP M_TEST CONNECTION TBD
39 APU_EDP_TX2+ DP0_TXP2 DP0_HPD APU_EDP_HPD 39

2
APU_EDP_TX2- B10 +1.8VS
1/20W_4.7K_5%_0201 39 APU_EDP_TX2- DP0_TXN2 J20 RC54 RC51
APU_EDP_TX3+ D9 DP1_AUXP K20
HDMI 39.2_0402_1% 1K_0402_5%
2

APU_RST# 39 APU_EDP_TX3+ APU_EDP_TX3- DP0_TXP3 DP1_AUXN


B9 L21 @
39 APU_EDP_TX3- DP0_TXN3 DP1_HPD RPC7

1
D APU_TEST16 D
PLACE CC30 CAPS CLOSE TO APU,CRB reserve 27pf G23 L19 4 5
H23 DP1_TXP0 DP2_AUXP M19 APU_TEST15 3 6
1 DP1_TXN0 DP2_AUXN M20
Type C APU_TEST17 2 7
CC30 F22 DP2_HPD APU_TEST14 1 8
56P_0201_50V8-J G22 DP1_TXP1 M14 Checklist requir PD, PU NC, Confirm? 07/27
2 DP1_TXN1 DP3_AUXP L14
@
HDMI G21 DP3_AUXN L16
10K_0804_8P4R_5%
10/16 david Modify
DP1_TXP2 DP3_HPD @
H21
DP1_TXN2 B23 DP_STEREOSYNC
F20 DP_STEREOSYNC
+1.8VS +1.8VALW G20 DP1_TXP3
DP1_TXN3 To EDP panel +3VS
1

1
RC55 PU FOR INTERNAL

RC416 1/20W_4.7K_5%_0201 PD FOR CUSTOMER +3VALW_APU RC56


300_0402_5% 4.7K_0402_5%
@
2

2
APU_PWROK RC147
10K_0402_5%
PCH_EDP_PWM 39
PLACE CC31 CAPS CLOSE TO APU,CRB reserve 27pf
1 BB6 TEST4 1 @ TC4

1
TEST4

3
BD5 TEST5 1 @ TC5 QC1B
CC31 TEST5

D2
56P_0201_50V8-J AG12 5
2 @ TEST6 G2
G25 APU_TEST14

S2
TEST14

6
K25 APU_TEST15
APU_TEST15
QC1A
TEST15 F25 APU_TEST16

D1

4
TEST16 F26 APU_TEST17
APU_TEST17 DP_EDP_PWM 2 PJT7838_SOT363-6
TEST17 G1
+3VS_APU H26 APU_TEST31 1 @ TC7

S1
TEST31

1
RC58

1
AK9 PJT7838_SOT363-6
RPC8 1 @ TC8 100K_0402_5%
8 1 APU_PROCHOT#_R TEST41
7 2 APU_SID APU_TDI AP3 AK21 TEST470 1 @ TC9

2
6 3 APU_SIC APU_TDO AU1 TDI ANALOGIO_0 AG21 TEST471 1 @ TC10
C 5 4 ALERT# APU_TCK AR2 TDO ANALOGIO_1 C
APU_TMS AU3 TCK
1/16W_1K_5%_8P4R_0804 APU_TRST# AR4 TMS
APU_DBREQ# AT2 TRST_L
DBREQ_L +0.75VS

APU_RST# AW3 P3 SMU_ZVDDP RC60 1 2 196_0402_1%


APU_PWROK AW4 RESET_L SMU_ZVDD
73 APU_PWROK PWROK ADD level shift to mux by midq 09/19
RC62 1 2@ 0_0402_5% APU_SIC B22
+3VS_APU 28,52,59,60 EC_SMB_CK2 2@ 0_0402_5% APU_SID SIC
28,52,59,60 EC_SMB_DA2 RC63 1 D22
ALERT# C22 SID AK7 VDDP_S5_SENSE 1 @ TC25
APU_THERMTRIP# AN9 ALERT_L VDDP_S5_SENSE AK12 APU_VDDP_RUN_FB_H 1 @ TC11
25,52 APU_THERMTRIP# THERMTRIP_L VDDP_SENSE
RC66 1 2@ 0_0402_5% APU_PROCHOT#_R B25 J23 VDDCR_SOC_VCC_SENSE +3VS
RC67 1 2 1K_0402_1% APU_THERMTRIP#52 APU_PROCHOT# PROCHOT_L VDDCR_SOC_SENSE K22 VDDCR_VCC_SENSE VDDCR_SOC_VCC_SENSE 73 UR8
VDDCR_SENSE VDDCR_VCC_SENSE 73
J21 1 5
RC68 1 2@ 0_0402_5% APU_SVC_RA D25 VDDIO_MEM_S3_SENSE OE Vcc
73 APU_SVC SVC0
RC69 1 2@ 0_0402_5% APU_SVD_RA C25 J22 VDDCR_VSS_SENSE 2
73 APU_SVD SVD0 VSS_SENSE_A VDDCR_VSS_SENSE 73 IN_A
RC70 1 2 0_0402_5% APU_SVT_RA A25 FP6 REV0.92 AJ12 VSS_SENSEB 1 @ TC12
73 APU_SVT SVT0 PART 3/13 VSS_SENSE_B 3 4
GND OUT_Y
APU_SVC APU_SVD APU_SVT AMD-RENOIR-FP6_BGA1140
27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

27P_25V_J_NPO_0201

@ M74VHC1GT125DF2G_SC70-5
1 1 1
CC34 CC35 CC36
@

2 2 2
DP_ENVDD RC72 1 2 0_0402_5%
PCH_EDP_ENVDD 39
@

1
RC71
100K_0402_5%

2
B B

ADD level shift to mux by midq 09/19


+3VS
New HDT conn +1.8VALW UR7
1 5
JHDT1 +1.8VALW +1.8VALW OE Vcc
1 2
1 2 RPC9 IN_A
2 3 APU_TCK 8 1 3 4
3 GND OUT_Y
2

4 APU_TMS 7 2 RC74
4 5 APU_TDI 6 3 1K_0402_5%
5 6 APU_TDO 1 HDT@ 2 APU_DBREQ# 5 4 HDT@ M74VHC1GT125DF2G_SC70-5
6 7 APU_PWROK RC78
7 8 APU_RST# 33_0402_5% 1/16W_1K_5%_8P4R_0804
1

8 9 APU_DBREQ#_R
9 HDT@
10 APU_TRST#_R RC79 1 HDT@ 2 33_0402_5% APU_TRST#
13 10 11
GND1 11 1
14 12 CC38 DP_ENBKL RC81 1 2 0_0402_5%
GND2 12 0.01U_6.3V_K_X7R_0201 PCH_EDP_ENBKL 39
HIGHS_FC1AF121-1151H HDT@ @

1
2
ME@
RC80
100K_0402_5%

2
A A

Security Classification
Classification LC Future Center Secret Data Title
Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 (DP/JTAG/SIV2/MISC)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 7 of 83
5 4 3 2 1
5 4 3 2 1

Mirror code: Platform allows RSMRST# = 0 to SPI tri-state


add reserved QC11,RC3268 For mirror 07/31 +1.8VALW +3VALW_APU

1
RC3 1 2@ 0_0402_5% RC6 PCIE_WAKE#_RA RC5 1 2@ 0_0402_5%
1 PCIE_WAKE# 47,52,56

1
10K_0402_5%
RC4 CC21 @ DC2
10K_0402_5% 10U 6.3V M X5R 0402 SYS_RESET# 1 2 SYS_PWRGD_R
2

2
RB751V-40_SOD323-2

2
RSMRST#_R RC8 1 2@ 0_0402_5% SYS_PWRGD_R @
52 EC_RSMRST# 52 EC_SYS_PWRGD 1
1
1 CC23
CC22 CC24 0.1U_0201_6.3V6-K
+3VL 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K 2
2
2

1
需需需需 RC3268
@ 10K_0402_5% RC9 1 2@ 0_0402_5% PCIE_RST0#_R
28,46,47,55,56 PLT_RST#
D D

6
QC11A D

1
2 2
G RC10
2N7002KDWH_SOT363-6 100K_0402_5% CC25 ADD TYPE-C HPD/PCH_FB_GC6_EN 2019 0910
S @ 2200P_25V_K_X7R_0201

1
3
QC11B D 1
@ ADD F2_KET

2
5
G
2N7002KDWH_SOT363-6
S UC1E

4
AM3
@ SFH_IPIO271 AT4
SFH_IPIO272 AM1
SFH_IPIO273 AJ8
SFH_IPIO274 AW7
SFH_IPIO39 AU2
PCIE_RST0#_R AP6 SFH_IPIO41
PCIE_RST1#_R AT13 PCIE_RST0_L/EGPIO26 AP14 BOARD_ID0
RSMRST#_R AR8 PCIE_RST1_L/EGPIO27 I2C0_SCL/EGPIO145 AN14 BOARD_ID1
RSMRST_L I2C0_SDA/EGPIO146
PBTN_OUT# RC11 1 2@ 0_0402_5% PWRBTN#_R AT12 AP2 BOARD_ID2
52 PBTN_OUT# SYS_PWRGD_R PWR_BTN_L/AGPIO0 I2C1_SCL/EGPIO147 VGA_ALERT#_PCH
AW2 AN3
SYS_RESET# AL2 PWR_GOOD I2C1_SDA/EGPIO148
14 SYS_RESET# PCIE_WAKE#_RA SYS_RESET_L/AGPIO1 PCH_SMBCLK
AW12 AN12
WAKE_L/AGPIO2 I2C2_SCL/EGPIO113/SMBUS0_I2C_SCL AP12 PCH_SMBDATA
PM_SLP_S3# RC14 1 2@ 0_0402_5% PM_SLP_S3#_R AT11 I2C2_SDA/EGPIO114/SMBUS0_I2C_SDA
52 PM_SLP_S3# PM_SLP_S5# PM_SLP_S5#_R SLP_S3_L TP_I2C3_SCL_R
RC15 1 2@ 0_0402_5% AV11 AM9
14,52 PM_SLP_S5# SLP_S5_L I2C3_SCL/AGPIO19/SMBUS1_I2C_SCL AM10 TP_I2C3_SDA_R TP_I2C3_SCL_R 14,55,69
AW13 I2C3_SDA/AGPIO20/SMBUS1_I2C_SDA TP_I2C3_SDA_R 14,55,69 Touch Pad
S0A3_GPIO/AGPIO10 D24
AC_PRESENT BA8 SFH1_SCL B24
52 AC_PRESENT PXS_PWREN_R AC_PRES/AGPIO23 SFH1_SDA
RH934 1 2 0_0201_5% AV6
PM_SLP_S3# 28,62 PXS_PWREN LLB_L/AGPIO12
CC146 @1 2 2200P_25V_K_X7R_0201 @
PM_SLP_S5# CC147 @1 2 2200P_25V_K_X7R_0201 BB7 LAN_PWR_ON#
BOARD_ID3 AW8 AGPIO3 BA6 SSD_SATA_PCIE_DET1# LAN_PWR_ON# 56
EGPIO42 AGPIO4/SATAE_IFDET SSD_SATA_PCIE_DET1# 46
AK10 SATA_DEVSLP0
AGPIO5/DEVSLP0 SATA_DEVSLP0 46
BC6 OD,Pull high 3VALW?
AGPIO6/DEVSLP1 AW15 PCH_TP_INT#
SATA_ACT_L/AGPIO130 PCH_TP_INT# 55
删删DMIC AG6 AU4 PCH_TP_INT1#
ACP_WOV_CLK AGPIO9 APU_SSD_RST# PCH_TP_INT1# 55
AG7 AP7
@ 1 AJ6 ACP_WOV_MIC0_MIC1_DATA AGPIO40 AV13 PXS_RST#_R RH315 1 2@ 0_0201_5%APU_SSD_RST# 46
ACP_WOV_MIC2_MIC3_DATA AGPIO69 EC_SMI# PXS_RST# 28
TC17 BB12 +3VS_APU
C HDA_BITCLK AGPIO86/SPI_CLK2 EC_SMI# 52 C
AN6
RC19 1 2 0_0402_5% HDA_SDIN0_R AL6 AZ_BITCLK/TDM_BCLK_MIC
58 HDA_SDIN0 HDA_SDIN1 AZ_SDIN0/CODEC_GPI INTRUDER_ALERT EC_SMI#
TC1 @ 1 AM7 AU7 RC20 2 @ 1 20M_0402_5% VCCRTC RC21 1 2 2.2K_0402_5%
TC2 @ 1 HDA_SDIN2 AJ9 AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT AR11
HDA_RST# AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK/ACP_WOV_MIC4_MIC5_DATA SPKR/AGPIO91 AW11 PCH_BEEP 58 PXS_PWREN
AM6 BLINK RC3277 1 2 10K_0402_5%
HDA_SYNC AN8 AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC BLINK/AGPIO11
HDA_SDOUT AK6 AZ_SYNC/TDM_FRM_MIC AV15 PCH_FB_GC6_EN
AZ_SDOUT/TDM_FRM_PLAYBACK GENINT1_L/AGPIO89 PCH_GPU_EVENT# PCH_FB_GC6_EN 28
AU14 +3VALW_APU
GENINT2_L/AGPIO90 PCH_GPU_EVENT# 28
AM4
AL3 SW_MCLK/TDM_BCLK_BT
RH931 1 2 0_0201_5% AM2 SW_DATA0/TDM_DOUT_BT AT10 RPC3
53 F2_KEY TYPE-C_DP_HPD AGPIO7/FCH_ACP_I2S_SDIN_BT FANIN0/AGPIO84 VGA_PWRGD
PXS_PWREN 25,28 TP_I2C3_SDA_R
AL4 FP6 REV0.92 AU10 RH935 1 2 0_0201_5% 1 4
44 TYPE-C_DP_HPD AGPIO8/FCH_ACP_I2S_LRCLK_BT PART 4/13 FANOUT0/AGPIO85 TP_I2C3_SCL_R 2 3

AMD-RENOIR-FP6_BGA1140 2.2K_0404_4P2R_5%
@
+3VALW_APU
RPC4
PBTN_OUT# 1 8
PCIE_WAKE#_RA 2 7
AC_PRESENT 3 6
PXS_PWREN_R 4 5
+1.8VS_AON
RPC5 10K_0804_8P4R_5%
TC3 @ 1 HDA_RST_AUDIO# 1 8 HDA_RST#
2 7 HDA_SYNC Blink RC24 1 @ 2 10K_0402_5%
58 HDA_SYNC_AUDIO HDA_BITCLK PM_SLP_S3#_R
3 6 RC25 1 @ 2 2.2K_0402_5%
58 HDA_BITCLK_AUDIO HDA_SDOUT PM_SLP_S5#_R
4 5 RC26 1 @ 2 2.2K_0402_5%
58 HDA_SDOUT_AUDIO

2
APU_SSD_RST# RC27 1 @ 2 10K_0402_5%
1/16W_33_5%_8P4R_0804 PCH_TP_INT1# RC3276 1 2 10K_0402_5%

3 1 VGA_ALERT#_PCH SATA_DEVSLP0 RC415 1 2 10K_0402_5%

2
28 VGA_ALERT#

1K_0402_5%

1K_0402_5%

1K_0402_5%
RC29

RC30

RC31
QH22 PCH_TP_INT# RC28 1 @ 2 10K_0201_5%
LSI1012XT1G_SC-89-3 RSMRST#_R RC32 1 @ 2 100K_0402_5%
1

1
@ SYS_PWRGD_R RC33 1 2 100K_0402_5%
@ @ @
PCIE_RST1#_R RC34 1 @ 2 10K_0201_5%

DIMM1, DIMM2

B B
+1.8VS +3VALW_APU

RPH7
2N7002KDWH 1 4
Vth= min 1V, max 2.5V +3VS
ESD 2KV
2 3

2.2K_0404_4P2R_5%
2

RC35 RC36 RC37 RC41


10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%

N18PG62@
1

For EMI HDA_BITCLK


BOARD_ID0 @ @ @
1
BOARD_ID1 PCH_SMBCLK RH929 1 2@ 0_0201_5%
BOARD_ID2 SMB_CLK_S3 17,18
CC27
BOARD_ID3 56P_50V_J_NPO_0201 PCH_SMBDATA RH930 1 2@ 0_0201_5%
2 SMB_DATA_S3 17,18
EMC_NS@

Close to PCH
2

RC42 RC43 RC44 RC48


10K_0201_5% 10K_0201_5% 10K_0201_5% 10K_0201_5%

N18PG61@
1

A A

Function EGPIO145 EGPIO146 EGPIO147 EGPIO42

Y550-15-N18P G61 0 0 0 0
Y550-15-N18P G62 0 0 0 1
Security Classification LC Future Center Secret Data Title
Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 AZ/I2C/ACPI/GPIO
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 8 of 83
5 4 3 2 1
5 4 3 2 1

+3VS_APU LPCCLK0 PCH_SPI_CLK


RPC11
1 8 SSD_CLKREQ1#

2
2 7 WLAN_CLKREQ# RC82 1 2 33_0402_5% LPC_RST#_R
SSD_CLKREQ# 14,52 APU_LPC_RST#
3 6 RC83
4 5 1 0_0201_5% RC90
CC41 EMC_NS@ 10_0402_5%
10K_0804_8P4R_5% 150P_25V_J_NPO_0402 EMC_NS@

1
+3VS_APU
2
RPC58 1 1
1 4 GPU_CLKREQ# CC42 CC43
2 3 LAN_CLKREQ# 22P_0201_25V8 10P_0201_25V8G
EMC_NS@ EMC_NS@
10K_0404_4P2R_5% 2 2
EMC EMC
D D
UC1F

+3VS_APU +3VS_APU SSD_CLKREQ1# AR13


46 SSD_CLKREQ1# WLAN_CLKREQ# CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92
AP10
47 WLAN_CLKREQ# SSD_CLKREQ# CLK_REQ1_L/AGPIO115
AR15
46 SSD_CLKREQ# LCD_OD# CLK_REQ2_L/AGPIO116
RH925 1 2@ 0_0201_5% AT14
41 LCD_OD# CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131
AN11
39 EDP_SW
1

GPU_CLKREQ# AN13 CLK_REQ4_L/OSCIN/EGPIO132


25 GPU_CLKREQ# LAN_CLKREQ# CLK_REQ5_L/EGPIO120
@ @ AN15
56 LAN_CLKREQ# CLK_REQ6_L/EGPIO121
RH924 RH926
10K_0201_5% 10K_0201_5% AW14
EGPIO70 BB13 LPCPD# LPCPD# 14
2

CLK_PCIE_SSD1 RC84 1 2@ 0_0402_5% CLK_PCIE_SSD1_R AF11 LPC_PD_L/AGPIO21 BA16 LAD0 RC85 1 2 10_0402_5%
46 CLK_PCIE_SSD1 CLK_PCIE_SSD1# GPP_CLK0P LAD0/ESPI1_DATA0/EGPIO104 LPC_AD0 52
RC86 1 2@ 0_0402_5% CLK_PCIE_SSD1#_R AF12 BA15 LAD1 RC87 1 2 10_0402_5% +3VS_APU
LCD_OD# EDP_SW PCIE CLK0 SSD1 46 CLK_PCIE_SSD1# GPP_CLK0N LAD1/ESPI1_DATA1/EGPIO105 BC13 LAD2 RC88 1 2 10_0402_5%
LPC_AD1 52
LPC_AD2 52
1

CLK_PCIE_WLAN RC89 1 2@ 0_0402_5% CLK_PCIE_WLAN_R AG4 LAD2/ESPI1_DATA2/EGPIO106 BB14 LAD3 RC91 1 2 10_0402_5%
47 CLK_PCIE_WLAN GPP_CLK1P LAD3/ESPI1_DATA3/EGPIO107 LPC_AD3 52
CLK_PCIE_WLAN# RC92 1 2@ 0_0402_5% CLK_PCIE_WLAN#_R AG2 BB15 LPCCLK0RC93 2 1 3.3_0402_1% LPC_FRAME# RC94 1 @ 2 10K_0201_5%
PCIE CLK1 WLAN 47 CLK_PCIE_WLAN# GPP_CLK1N LPCCLK0/EGPIO74 BD13 1 2
CLK_PCI_EC 52
RH923 RH927 RC57 @ 0_0201_5%
CLK_PCIE_SSD LPC_CLKRUN_L/AGPIO88 LPC_CLKRUN# 14
10K_0201_5% 10K_0201_5% RC417 1 2@ 0_0402_5% CLK_PCIE_SSD_R AG3 BA12 PCH_WLAN_OFF# KBRST# RC96 1 2 10K_0201_5%
46 CLK_PCIE_SSD CLK_PCIE_SSD# GPP_CLK2P LPCCLK1/EGPIO75 PCH_WLAN_OFF# 47
RC418 1 2@ 0_0402_5% CLK_PCIE_SSD#_R AG1 BC15 10/16 david Modify
PCIE CLK2 SSD0 46 CLK_PCIE_SSD# SERIRQ 14,52
2

GPP_CLK2N SERIRQ/AGPIO87 BA13 LDRQ0# RC3272 1 2 10K_0201_5%


LFRAME_L/EGPIO109 LPC_FRAME# 52
AF2
AF4 GPP_CLK3P BC12 LPC_RST#_R
PCIE CLK3 Card Reader GPP_CLK3N LPC_RST_L/AGPIO32 AU12 RC32711 @ 2 1/16W_0_5%_0402
AGPIO68 EC_SCI# RTS5457_SM_INT 43,52
AH2 AP4 7/18 Connect to PD
GPP_CLK4P LPC_PME_L/AGPIO22 EC_SCI# 52
AH4
GPP_CLK4N
CLK_PCIE_GPU RC419 1 2@ 0_0402_5% CLK_PCIE_GPU_R AJ2
25 CLK_PCIE_GPU CLK_PCIE_GPU# GPP_CLK5P
RC420 1 2@ 0_0402_5% CLK_PCIE_GPU#_R AJ4 BA11 +3VALW_APU
PCIE CLK5 dGPU 25 CLK_PCIE_GPU# GPP_CLK5N SPI_ROM_REQ/EGPIO67 BB11
CLK_PCIE_LAN RC421 1 2@ 0_0402_5% CLK_PCIE_LAN_R AF8 SPI_ROM_GNT/EGPIO76 EC_SCI# RC100 1 @ 2 10K_0201_5%
56 CLK_PCIE_LAN CLK_PCIE_LAN# GPP_CLK6P/WIFIBT_CLKP
PCIE CLK5 LAN RC422 1 2@ 0_0402_5% CLK_PCIE_LAN#_R AF9 AT15 KBRST# KBRST# 52
56 CLK_PCIE_LAN# GPP_CLK6N/WIFIBT_CLKN ESPI_RESET_L/KBRST_L/AGPIO129 BC11
Follow CRB 0Ω resistor pull down RC101 1 2@ 0_0201_5% LDRQ0# LDRQ0# 14
TC16 @ 1 48M_OSC AK1 ESPI_ALERT_L/LDRQ0_L/EGPIO108
RC99 1 2 0_0201_5% XGBECLK0 X48M_OSC BC10 SPI_CLK RC102 1 2@ 0_0201_5% PCH_SPI_CLKM
C SPI_CLK/ESPI_CLK BA10 C
RC98 1 2 0_0201_5% XGBECLK1 SPI_D1 RC103 1 2 0_0201_5% SPI_SO_C
X48M_X1 SPI_DI/ESPI_DATA BB8 SPI_D0 SPI_SI_C SPI_SO_C 52,55
BB3 RC104 1 2 0_0201_5% SPI_SI_C 52,55
X48M_X1 SPI_DO BA9 SPI_D2 RC105 1 2@ 0_0201_5% PCH_SPI_D2
SPI_WP_L/ESPI_DAT2 BC8 SPI_D3 RC106 1 2@ 0_0201_5% PCH_SPI_D3
SPI_HOLD_L/ESPI_DAT3 BD11 SPI_CS1# RC107 1 2@ 0_0201_5% SPI_CS1#_R
X48M_X2 BA5 SPI_CS1_L BC9 AGPIO30
X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30 BB10 RC3275 1 TPM@ 2 0_0201_5%
SPI_CS3_L/AGPIO31 BD8 SPI_CS2# TPM_SPI_IRQ# 55
SPI_TPM_CS_L/AGPIO29 SPI_CS2# 55 +3VS_APU

XGBECLK0 AG10
XGBECLK1 AG9 RSVD_71

1 RC108 2

1 RC109 2

1 RC112 2
RSVD_70

1K_0402_1%

1K_0402_1%

1K_0402_1%
AW10
47 SUSCLK RTCCLK

X32K_X1 AY1 BA17 APU_UART0_RXD


X32K_X1 EGPIO141/UART0_RXD BC16 APU_UART0_TXD @ @ @
EGPIO143/UART0_TXD BD15 PCH_BT_OFF#
EGPIO142/UART0_RTS_L/UART1_RXD BC17 PCH_BT_OFF# 47
RH933 1 2 0_0201_5%
RC113 X32K_X2 AY4 EGPIO140/UART0_CTS_L/UART1_TXD BB16 PCH_SPI_PIRQ# PCH_FNLK 52,55
1 2 X32K_X2 AGPIO144/SHUTDOWN_L/UART0_INTR
20M_0402_5% FP6 REV0.92
YC1 PART 5/13
1 2 ADD QC7 For Mirror required 09/27
AMD-RENOIR-FP6_BGA1140
32.768KHZ_12.5PF_202740-PG14 @
+3VALW_APU
1 1

48MHz/10pF Crystal X48M_X1


CC44
9P_50V_B_NPO_0402
CC45
8P_50V_B_NPO_0402 Modify QC7 to SB00000ZI00 0805

2
2 2
X48M_X2

PCH_SPI_CLKM 3 1 SPI_CLK_PCH_C
B SPI_CLK_PCH_C 14,52,55 B
RC115 1 2 1M_0402_5%
Kevin H: change YC1 PN change to SJ10000MQ00,manual modify PN to SJ10000MQ00
YC2 QC7
LSI1012XT1G_SC-89-3
1 4 +1.8V_SPI +1.8VALW RC3270 1 2 0_0402_5%
OSC1 NC2 UC3
SPI_CS1#_R +1.8V_SPI
0.085 A
2 3 1 8 RC118 2 @1 0_0402_5% @
NC1 OSC2 /CS VCC
PCH_SPI_D1 2 7 PCH_SPI_D3
1 1 DO /RESET 1
48MHZ 10PF +-10PPM 7V48000023
CC46 CC47 PCH_SPI_D2 3 6 PCH_SPI_CLK CC48 RTS5457_SM_INT RC114 1 @ 2 10K_0201_5%
4.7P_50V_C_NPO_0402 4.7P_50V_C_NPO_0402 /WP CLK 0.1U_0201_6.3V6-K
2 2 4 5 PCH_SPI_D0 2 AGPIO30 RC3273 1 @ 2 10K_0201_5%
Need change to ±10ppm GND DI

W25Q128JWSIQ_SO8
16MB(128Mb)
+1.8V_SPI

RC119 1 2 10K_0402_5% SPI_CS1#_R SPI_CLK_PCH_C RC159 1 2@ 0_0201_5% PCH_SPI_CLK


RC120 1 2 10K_0402_5% PCH_SPI_D1
RC121 1 @ 2 10K_0402_5% PCH_SPI_D2
RC122 1 @ 2 10K_0402_5% PCH_SPI_D3 SPI_CS1#_R RC162 1 2@ 0_0201_5% EC_SPI_CS1#_R
EC_SPI_CS1#_R 52

SPI_SI_C RC163 1 2@ 0_0201_5% PCH_SPI_D0

SPI_SO_C RC166 1 2@ 0_0201_5% PCH_SPI_D1

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 CLK/LPC/SD/EMMC/UART
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 9 of 83
5 4 3 2 1
5 4 3 2 1

UC1G

N7 P8
R7 AGPIO256/WIFIBT_BT_DATA EGPIO267/RFIC_SPI_CLK R9
N6 AGPIO257/WIFIBT_BT_VALID EGPIO268/RFIC_SPI_SS R6
T6 AGPIO258/WIFIBT_BT_SYNC AGPIO269/RFIC_SPI_DATA
AGPIO259/WIFIBT_BT_CLK

D R10 P9 D
T12 AGPIO260/WIFIBT_QSPI_DATA0
AGPIO270/WIFIBT_RFIC_WAKEUP T9
P12 AGPIO261/WIFIBT_QSPI_DATA1 EGPIO271/WIFIBT_BUCKEN T8
P11 AGPIO262/WIFIBT_QSPI_DATA2 EGPIO266/WIFIBT_FLOW
T11 AGPIO263/WIFIBT_QSPI_DATA3
P6 AGPIO264/WIFIBT_QSPI_CLK
AGPIO265/WIFIBT_QSPI_SS V7
WIFIBT_DATA_RXP V6
WIFIBT_DATA_RXN
V9
WIFIBT_DATA_TXP V10
WIFIBT_DATA_TXN
FP6 REV0.92
PART 12/13

AMD-RENOIR-FP6_BGA1140
@

UC1H

USB20_P0 AC6 AA1 TYPE-C_USB3_TX_P0


45 USB20_P0 USB20_N0 USBC0_DP/USB0_DP USBC0_TX1P/USB0_TXP/DP2_TXP2 TYPE-C_USB3_TX_N0 TYPE-C_USB3_TX_P0 44
AC7 AA3
USB-C 45 USB20_N0 USBC0_DN/USB0_DN USBC0_TX1N/USB0_TXN/DP2_TXN2 TYPE-C_USB3_TX_N0 44
USB20_P1 AA8 AA2 TYPE-C_USB3_RX_P0 TYPE-C USB (3.0)
49 USB20_P1 USB20_N1 USB1_DP USBC0_RX1P/USB0_RXP/DP2_TXP3 TYPE-C_USB3_RX_N0 TYPE-C_USB3_RX_P0 44
AA9 AA4
LEFT USB3.0(AOU) 49 USB20_N1 USB1_DN USBC0_RX1N/USB0_RXN/DP2_TXN3 TYPE-C_USB3_RX_N0 44
USB20_P2 Y10 AC2
41 USB20_P2 USB20_N2 USB2_DP USBC0_TX2P/DP2_TXP1
Y9 AC4
Camera 41 USB20_N2 USB2_DN USBC0_TX2N/DP2_TXN1
USB20_P3 Y7 AC1 Leakage USB3.0 Port for Right USB Port
54 USB20_P3 USB20_N3 USB3_DP USBC0_RX2P/DP2_TXP0
Y6 AC3
RGB KB 54 USB20_N3 USB3_DN USBC0_RX2N/DP2_TXN0
AE1 USB30_TX_P1
USB1_TXP USB30_TX_N1 USB30_TX_P1 49
AE3
USB20_P4 USB1_TXN USB30_TX_N1 49
AC9
38 USB20_P4 USB20_N4 USBC4_DP/USB4_DP USB30_RX_P1
AC10 AD8
Back USB (2.0) 38 USB20_N4 USBC4_DN/USB4_DN USB1_RXP AD9 USB30_RX_N1 USB30_RX_P1 49 LEFT USB (3.0)
C USB20_P5 AA11 USB1_RXN USB30_RX_N1 49 MB(AOU) C
55 USB20_P5 USB20_N5 USB5_DP
AA12
Right USB (2.0) 55 USB20_N5 USB5_DN
USB20_P6 W8
47 USB20_P6 USB20_N6 USB6_DP USB30_ATX_HRX_P4
W9 V3
BT 47 USB20_N6 USB6_DN USBC4_TX1P/USB4_TXP/DP3_TXP2 V1 USB30_ATX_HRX_N4 USB30_ATX_HRX_P4 38
USB20_P7 USBC4_TX1N/USB4_TXN/DP3_TXN2 USB30_ATX_HRX_N4 38
W11
53 USB20_P7 USB20_N7 USB7_DP USB30_ARX_HTX_P4
W12 U4
Anti-Ghost 53 USB20_N7 USB7_DN USBC4_RX1P/USB4_RXP/DP3_TXP3 U2 USB30_ARX_HTX_N4 USB30_ARX_HTX_P4 38 Back USB (3.0)
+1.8VALW USBC4_RX1N/USB4_RXN/DP3_TXN3 USB30_ARX_HTX_N4 38
RPC57
1 4 USBC_I2C_SCL AL9 W2
2 3 USBC_I2C_SCL USBC4_TX2P/DP3_TXP1 W4
USBC_I2C_SDA AL8 USBC4_TX2N/DP3_TXN1
4.7K_0404_4P2R_5% USBC_I2C_SDA W1
USBC4_RX2P/DP3_TXP0 W3
HDMI_HPD AE9 USBC4_RX2N/DP3_TXN0
42 HDMI_HPD USB_OC1# USB_OC0_L/AGPIO16 USB30_TX_P5
AE10 AD2
55 USB_OC1# USB_OC2# USB_OC1_L/AGPIO17 USB5_TXP USB30_TX_N5 USB30_TX_P5 55
AE6 AD4
49 USB_OC2# USB_OC3# USB_OC2_L/AGPIO18 USB5_TXN USB30_TX_N5 55
AE7
38,50 USB_OC3# USB_OC3_L/AGPIO24 USB30_RX_P5
AD12
USB5_RXP AD11 USB30_RX_N5 USB30_RX_P5 55 Right USB (3.0)
USB5_RXN USB30_RX_N5 55

UPdate 20190910 FP6 REV0.92


PART 10/13

AMD-RENOIR-FP6_BGA1140
@

+3VALW_APU

RPC59
USB_OC2# 1 8
USB_OC3# 2 7
3 6
USB_OC1# 4 5

10K_0804_8P4R_5%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 USB/WIFI


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 1.0

Date: Monday, February 24, 2020 Sheet 10 of 83


5 4 3 2 1
5 4 3 2 1

D D

UC1I

D21 A18
A20 CAM0_CSI2_CLOCKP CAM0_CLK
CAM0_CSI2_CLOCKN C18
D18 CAM0_I2C_SCL B17
B18 CAM0_CSI2_DATAP0 CAM0_I2C_SDA
C C
CAM0_CSI2_DATAN0 D17
C19 CAM0_SHUTDOWN
D20 CAM0_CSI2_DATAP1
CAM0_CSI2_DATAN1
C21
B21 CAM0_CSI2_DATAP2
CAM0_CSI2_DATAN2
C20
B20 CAM0_CSI2_DATAP3
CAM0_CSI2_DATAN3
C15 A13
A15 CAM1_CSI2_CLOCKP CAM1_CLK
CAM1_CSI2_CLOCKN B13
D16 CAM1_I2C_SCL D13
B16 CAM1_CSI2_DATAP0 CAM1_I2C_SDA
CAM1_CSI2_DATAN0 C14
D15 CAM1_SHUTDOWN
B15 CAM1_CSI2_DATAP1 C16
CAM1_CSI2_DATAN1 FP6 REV0.92 CAM_PRIV_LED C13
PART 13/13 CAM_IR_ILLU

AMD-RENOIR-FP6_BGA1140
@

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 CAM


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 11 of 83
5 4 3 2 1
5 4 3 2 1

+VDDCR_VDD
+VDDCR_SOC +VDDCR_VDD
UC1J
15A N16 G7 58A
N18 VDDCR_SOC_1 VDDCR_1 G10
VDDCR_SOC_2 VDDCR_2

180P_50V_J_NPO_0402
N20 G12
VDDCR_SOC_3 VDDCR_3

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
P17 G14
P19 VDDCR_SOC_4 VDDCR_4 H8
VDDCR_SOC_5 VDDCR_5 1 1 1 1 1

CC60

CC165

CC166

CC167
R18 H11
VDDCR_SOC_6 VDDCR_6

1U_0201_6.3V6-M
R20 H15 CC169
T19 VDDCR_SOC_7 VDDCR_7 K6 @ @ @
U18 VDDCR_SOC_8 VDDCR_8 K12 2 2 2 2 2
@
D U20 VDDCR_SOC_9 VDDCR_9 K14 D
V19 VDDCR_SOC_10 VDDCR_10 L8
W18 VDDCR_SOC_11 VDDCR_11 M7
W20 VDDCR_SOC_12 VDDCR_12 M10
Y19 VDDCR_SOC_13 VDDCR_13 N14
VDDCR_SOC_14 VDDCR_14 P7
VDDCR_15 P10
+1.2V VDDCR_16 P13
VDDCR_17 P15
6A AC20 VDDCR_18 R8
AC28 VDDIO_MEM_S3_1 VDDCR_19 R14
AD23 VDDIO_MEM_S3_2 VDDCR_20 R16
AD26 VDDIO_MEM_S3_3 VDDCR_21 T7 +VDDCR_SOC
AD28 VDDIO_MEM_S3_4 VDDCR_22 T10
AD32 VDDIO_MEM_S3_5 VDDCR_23 T13
+3VS_APU AE20 VDDIO_MEM_S3_6 VDDCR_24 T15

22UC_6.3VC_MC_X5RC_0603
+3VS VDDIO_MEM_S3_7 VDDCR_25

180P_50V_J_NPO_0402
AE22 T17
VDDIO_MEM_S3_8 VDDCR_26

0.1U_0201_6.3V6-K
AE25 U14
VDDIO_MEM_S3_9 VDDCR_27

22UC_6.3VC_MC_X5RC_0603
AE28 U16 1 1 1
VDDIO_MEM_S3_10 VDDCR_28

CC77

CC168
RC125 1 2@ 0_0402_5%1 1 1 1 AF23 V13
VDDIO_MEM_S3_11 VDDCR_29

1U_0201_6.3V6-M
CC141
AF26 V15 CC76

CC66
VDDIO_MEM_S3_12 VDDCR_30

1U_0201_6.3V6-M

1U_0201_6.3V6-M
CC67 CC68 AF28 V17 @
22UC_6.3VC_MC_X5RC_0603

AF32 VDDIO_MEM_S3_13 VDDCR_31 W7 2 2 2


2 2 2 2 AG20 VDDIO_MEM_S3_14 VDDCR_32 W10
AG22 VDDIO_MEM_S3_15 VDDCR_33 W14
+1.8VS BO BU AG25 VDDIO_MEM_S3_16 VDDCR_34 W16
AG28 VDDIO_MEM_S3_17 VDDCR_35 Y8
1A AJ20 VDDIO_MEM_S3_18 VDDCR_36 Y13
1 1 1 VDDIO_MEM_S3_19 VDDCR_37
AJ23 Y15
CC78

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC79 CC80 AJ26 VDDIO_MEM_S3_20 VDDCR_38 Y17


AJ28 VDDIO_MEM_S3_21 VDDCR_39 AA7
2 2 2 AJ32 VDDIO_MEM_S3_22 VDDCR_40 AA10
+1.8VS +1.8VALW AK22 VDDIO_MEM_S3_23 VDDCR_41 AA14
22UC_6.3VC_MC_X5RC_0603

BO BU AK25 VDDIO_MEM_S3_24 VDDCR_42 AA16


AK28 VDDIO_MEM_S3_25 VDDCR_43 AA18
+1.8VALW AL23 VDDIO_MEM_S3_26 VDDCR_44 AB13

2
AL26 VDDIO_MEM_S3_27 VDDCR_45 AB15
RC126 RC127 AL28 VDDIO_MEM_S3_28 VDDCR_46 AB17 +1.2V
1 1 VDDIO_MEM_S3_29 VDDCR_47
1 0_0402_5% 0_0402_5% AL32 AB19
1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC82 CC83 AM22 VDDIO_MEM_S3_30 VDDCR_48 AC14


CC81

@ +VDD_AUD_ALW AM25 VDDIO_MEM_S3_31 VDDCR_49 AC16

1
2 2 VDDIO_MEM_S3_32 VDDCR_50

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

180P_50V_J_NPO_0402
AM28 AC18

22UC_6.3VC_MC_X5RC_0603
2 @ VDDIO_MEM_S3_33 VDDCR_51

0.22U_0201_6.3V6-K
AN28 AD7
22UC_6.3VC_MC_X5RC_0603

BO BU AN32 VDDIO_MEM_S3_34 VDDCR_52 AD10


1 1 1 VDDIO_MEM_S3_35 VDDCR_53 1 1 1 1 1 1 1 1 1 1 1 1

CC88

CC89

CC90

CC91

CC93

CC95

CC161

CC162

CC163

CC98
AP28 AD13

CC84

CC85

1U_0201_6.3V6-M
VDDIO_MEM_S3_36 VDDCR_54

1U_0201_6.3V6-M

1U_0201_6.3V6-M
C +3VALW_APU AR32 AD15 C
CC86 CC96 CC97
VDDIO_MEM_S3_37 VDDCR_55 AD17
2 2 2 AC21 VDDCR_56 AD19 2 2 2 2 2 2 2 2 2 2 2 2
1 1 VDDIO_VPH_1 VDDCR_57
1 AD21 AE8
1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC100 CC101 BO BU VDDIO_VPH_2 VDDCR_58 AE14


0.2A
CC99

AP9 VDDCR_59 AE16


2 2 VDDIO_AUDIO VDDCR_60 AE18
2 0.25A AL18 VDDCR_61 AF7
22UC_6.3VC_MC_X5RC_0603

BO BU AM17 VDD_33_1 VDDCR_62 AF10


VDD_33_2 VDDCR_63 AF13
+0.75VALW 2.5A AL20 VDDCR_64 AF15
ALL BU(on bottom side under SOC)
AM19 VDD_18_1 VDDCR_65 AF17
VDD_18_2 VDDCR_66 AF19
1 1 1 1A AL19 VDDCR_67 AG14
1
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC103 CC104 CC105 AM18 VDD_18_S5_1 VDDCR_68 AG16


CC102

VDD_18_S5_2 VDDCR_69 AG18


2 2 2 0.25A AL17 VDDCR_70 AH13 +1.2V
2 AM16 VDD_33_S5_1 VDDCR_71 AH15
VDD_33_S5_2 VDDCR_72 AH17
BO BU
2A AL11 VDDCR_73 AH19
22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

+0.75VS AL12 VDDP_S5_1 VDDCR_74 AJ7


VDDP_S5_2 VDDCR_75

180P_50V_J_NPO_0402

180P_50V_J_NPO_0402
AM12 AJ10
VDDP_S5_3 VDDCR_76

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K
180P_50V_J_NPO_0402

AJ14
2A M15 VDDCR_77 AJ16
1 1 1 1 1 1 1 1 1 1 1 VDDP_1 VDDCR_78 1 1 1 1 1 1

CC117

CC118

CC119

CC120

CC121

CC122
M16 AJ18
CC106

CC107

CC116
1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

1U_0201_6.3V6-M

CC108 CC109 CC110 CC111 CC112 CC113 CC114 CC115 M18 VDDP_2 VDDCR_79 AK13
VDDP_3 VDDCR_80 AK15
2 2 2 2 2 2 2 2 2 2 2 VDDCR_81 AK17 2 2 2 2 2 2
VDDCR_82 AK19
AJ11 VDDCR_83
BO(Bottom side outside SOC) BU VDDBT_RTC_G FP6 REV0.92
PART 6/13

VCCRTC +RTCBATT_APU AMD-RENOIR-FP6_BGA1140


Decoupling between processor and DIMMs
Across vddio and vss split
1 2 0.1A @
RC128 1K_0402_5%
0.22U_0201_6.3V6-K

1 1 +1.2V
CC124
1U_0201_6.3V6-M

CC123

2 2

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
1

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.22U_0201_6.3V6-K

0.1U_0201_6.3V6-K

0.1U_0201_6.3V6-K
B RC130 1 1 1 1 1 1 1 1 1 1 B

CC125

CC164

CC127

CC128

CC129

CC130

CC131

CC132

CC133

CC134
BU 470_0603_5%
@
12

D QC4 2 2 2 2 2 2 2 2 2 2
2 EC_RTCRST#_ON
EC_RTCRST#_ON 52
G
2

S L2N7002KWT1G_SOT323-3 RC131 @ @ @ @ @ @ @ @ @ @
3

@ 10K_0402_5%
@
Reserved for debug
1

A A

Security Classification
Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 POWER


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y550 1.0

Date: Monday, February 24, 2020 Sheet 12 of 83


5 4 3 2 1
5 4 3 2 1

D D

UC1K UC1L UC1M

AM20 K28 AR14 BD19 V5 AE13


A3 VSS_310 VSS_60 K32 AR16 VSS_246 VSS_305 BD21 V8 VSS_122 VSS_184 AE15
A5 VSS_1 VSS_61 L5 AR19 VSS_247 VSS_306 BD23 V11 VSS_123 VSS_185 AE17
A7 VSS_2 VSS_62 L13 AR21 VSS_248 VSS_307 BD26 V14 VSS_124 VSS_186 AE19
A10 VSS_3 VSS_63 L15 AR26 VSS_249 VSS_308 BD30 V16 VSS_125 VSS_187 AF1
A12 VSS_4 VSS_64 L18 AR28 VSS_250 VSS_309 V18 VSS_126 VSS_188 AF3
A14 VSS_5 VSS_65 L20 AT23 VSS_251 V20 VSS_127 VSS_189 AF5
A16 VSS_6 VSS_66 L25 AU5 VSS_252 V22 VSS_128 VSS_190 AF14
A19 VSS_7 VSS_67 L28 AU8 VSS_253 V25 VSS_129 VSS_191 AF16
A21 VSS_8 VSS_68 M1 AU11 VSS_254 V28 VSS_130 VSS_192 AF18
A23 VSS_9 VSS_69 M3 AU13 VSS_255 W5 VSS_131 VSS_193 AF20
A26 VSS_10 VSS_70 M5 AU15 VSS_256 W13 VSS_132 VSS_194 AG5
A30 VSS_11 VSS_71 M21 AU18 VSS_257 AV8 W15 VSS_133 VSS_195 AG8
C3 VSS_12 VSS_72 M23 AU20 VSS_258 RSVD_46 BD18 W17 VSS_134 VSS_196 AG11
C10 VSS_13 VSS_73 M26 AU22 VSS_259 RSVD_47 AV3 W19 VSS_135 VSS_197 AG13
C32 VSS_14 VSS_74 M28 AU25 VSS_260 RSVD_45 AU6 W23 VSS_136 VSS_198 AG15
E7 VSS_15 VSS_75 M32 AU28 VSS_261 RSVD_44 AR6 W26 VSS_137 VSS_199 AG17
E8 VSS_16 VSS_76 N5 AV1 VSS_262 RSVD_43 AR3 W28 VSS_138 VSS_200 AG19
E10 VSS_17 VSS_77 N8 AV5 VSS_263 RSVD_42 AP1 W32 VSS_139 VSS_201 AH14
E11 VSS_18 VSS_78 N11 AV7 VSS_264 RSVD_41 AN16 Y1 VSS_140 VSS_202 AH16
E12 VSS_19 VSS_79 N13 AV10 VSS_265 RSVD_40 AN4 Y3 VSS_141 VSS_203 AH18
E13 VSS_20 VSS_80 N15 AV12 VSS_266 RSVD_39 AN2 Y5 VSS_142 VSS_204 AH20
E14 VSS_21 VSS_81 N17 AV14 VSS_267 RSVD_38 AM14 Y11 VSS_143 VSS_205 AJ1
C C
E15 VSS_22 VSS_82 N22 AV16 VSS_268 RSVD_37 AM13 Y14 VSS_144 VSS_206 AJ3
E16 VSS_23 VSS_83 N25 AV19 VSS_269 RSVD_36 AL29 Y16 VSS_145 VSS_207 AJ5
E18 VSS_24 VSS_84 N28 AV21 VSS_270 RSVD_35 AL15 Y18 VSS_146 VSS_208 AJ13
E19 VSS_25 VSS_85 P1 AV23 VSS_271 RSVD_34 AL14 Y20 VSS_147 VSS_209 AJ15
E20 VSS_26 VSS_86 P5 AV26 VSS_272 RSVD_33 AL13 Y22 VSS_148 VSS_210 AJ17
E21 VSS_27 VSS_87 P14 AV28 VSS_273 RSVD_32 AK3 Y25 VSS_149 VSS_211 AJ19
E22 VSS_28 VSS_88 P16 AV32 VSS_274 RSVD_31 AJ29 Y28 VSS_150 VSS_212 AK5
E23 VSS_29 VSS_89 P18 AW5 VSS_275 RSVD_30 AJ27 AA5 VSS_151 VSS_213 AK8
E25 VSS_30 VSS_90 P20 AW28 VSS_276 RSVD_29 AF6 AA13 VSS_152 VSS_214 AK11
E26 VSS_31 VSS_91 P23 AY6 VSS_277 RSVD_28 AE12 AA15 VSS_153 VSS_215 AK14
E27 VSS_32 VSS_92 P26 AY7 VSS_278 RSVD_27 AD6 AA17 VSS_154 VSS_216 AK16
F5 VSS_33 VSS_93 P28 AY8 VSS_279 RSVD_26 AD3 AA19 VSS_155 VSS_217 AK18
F19 VSS_34 VSS_94 P32 AY10 VSS_280 RSVD_25 AC30 AA23 VSS_156 VSS_218 AK20
F21 VSS_35 VSS_95 R5 AY11 VSS_281 RSVD_24 AC12 AA26 VSS_157 VSS_219 AL1
F23 VSS_36 VSS_96 R11 AY12 VSS_282 RSVD_23 AB31 AA28 VSS_158 VSS_220 AL5
F28 VSS_37 VSS_97 R13 AY13 VSS_283 RSVD_22 AA20 AA32 VSS_159 VSS_221 AL7
G1 VSS_38 VSS_98 R15 AY14 VSS_284 RSVD_21 AA6 AB2 VSS_160 VSS_222 AL10
G3 VSS_39 VSS_99 R17 AY15 VSS_285 RSVD_20 Y12 AB4 VSS_161 VSS_223 AL16
G5 VSS_40 VSS_100 R19 AY16 VSS_286 RSVD_19 W6 AB14 VSS_162 VSS_224 AM5
G16 VSS_41 VSS_101 R22 AY18 VSS_287 RSVD_18 V12 AB16 VSS_163 VSS_225 AM8
G26 VSS_42 VSS_102 R25 AY19 VSS_288 RSVD_17 R12 AB18 VSS_164 VSS_226 AM11
G28 VSS_43 VSS_103 R28 AY20 VSS_289 RSVD_16 N19 AB20 VSS_165 VSS_227 AM15
G32 VSS_44 VSS_104 T1 AY21 VSS_290 RSVD_15 N12 AC5 VSS_166 VSS_228 AN1
H5 VSS_45 VSS_105 T3 AY22 VSS_291 RSVD_14 N10 AC8 VSS_167 VSS_229 AN5
H13 VSS_46 VSS_106 T5 AY23 VSS_292 RSVD_13 N9 AC11 VSS_168 VSS_230 AN7
H18 VSS_47 VSS_107 T14 AY25 VSS_293 RSVD_12 M13 AC13 VSS_169 VSS_231 AN10
H20 VSS_48 VSS_108 T16 AY26 VSS_294 RSVD_11 M12 AC15 VSS_170 VSS_232 AN23
H22 VSS_49 VSS_109 T18 AY27 VSS_295 RSVD_10 M11 AC17 VSS_171 VSS_233 AN26
H25 VSS_50 VSS_110 T20 BB1 VSS_296 RSVD_9 M6 AC19 VSS_172 VSS_234 AP5
H28 VSS_51 VSS_111 T23 BB32 VSS_297 RSVD_8 L12 AC22 VSS_173 VSS_235 AP8
J19 VSS_52 VSS_112 T26 BD3 VSS_298 RSVD_7 K19 AC25 VSS_174 VSS_236 AP13
K1 VSS_53 VSS_113 T28 BD7 VSS_299 RSVD_6 F16 AD1 VSS_175 VSS_237 AP15
K3 VSS_54 VSS_114 T32 BD10 VSS_300 RSVD_5 F14 AD5 VSS_176 VSS_238 AP18
K5 VSS_55 VSS_115 U13 BD12 VSS_301 RSVD_4 F12 AD14 VSS_177 VSS_239 AP20
K16 VSS_56 VSS_116 U15 BD14 VSS_302 RSVD_3 F10 AD16 VSS_178 VSS_240 AP25
K21 VSS_57 VSS_117 U17 BD16 VSS_303 RSVD_2 C26 AD18 VSS_179 VSS_241 AR1
K26 VSS_58 VSS_118 U19 VSS_304 RSVD_1 AD20 VSS_180 VSS_242 AR5
B VSS_59 VSS_119 V2 AE5 VSS_181 VSS_243 AR7 B
VSS_120 V4 FP6 REV0.92 AE11 VSS_182 VSS_244 AR12
FP6 REV0.92 VSS_121 PART 11/13 VSS_183 VSS_245
PART 7/13 FP6 REV0.92
AMD-RENOIR-FP6_BGA1140 AMD-RENOIR-FP6_BGA1140 PART 8/13
@ @ AMD-RENOIR-FP6_BGA1140
@

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 GND


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 13 of 83
5 4 3 2 1
5 4 3 2 1

+1.8VS +1.8VALW +3VALW_APU

1
RC132 RC133 RC134
10K_0402_5% 10K_0402_5% 10K_0402_5%
@

2
D D
SPI_CLK_PCH_C
9,52,55 SPI_CLK_PCH_C 8 SYS_RESET#

1
RC135 RC136
2K_0402_5% 2K_0402_5%
@ @

2
STRAP PINS SYS_RESET#
1:USE 48MHZ CRYSTAL CLOCK AND
GENERATE BOTH INTERNAL AND EXTERNAL CLOCKS(DEFAULT)
0:USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK AND
PCH_SPI_CLK GENERATE INTERNAL CLOCKS ONLY
C C

1:NORMAL RESET MODE(DEFAULT)


SYS_RESET# 0:SHORT RESET MODE

LPC ROM EMULATOR HEADER

+3VALW_APU +3VS_APU

PIN4 should be removed as a Key


2

RC138 RC139
0_0402_5% 0_0402_5%
DAISY CHAIN ROUTING FOR LPC SIGNALS
1

B B
@ @

APU_LPC_RST# RC140 1 2@ 0_0201_5%


9,52 APU_LPC_RST# LPC_RST#_H 1 @ IT1 IT2 @ 1 RC141 1 @ 2 0_0201_5% PM_SLP_S5#
PM_SLP_S5# 8,52
LPCRUNPWR 1 @ IT3

RC142 1 2@ 0_0201_5% I2C3_SCL_LPC 1 @ IT5 IT4 @ 1 I2C3_SDA_LPC RC143 1 2@ 0_0201_5%


8,55,69 TP_I2C3_SCL_R TP_I2C3_SDA_R 8,55,69
1 @ IT7 IT6 @ 1 SERIRQ
SERIRQ 9,52
IT8 @ 1 LDRQ0#
LDRQ0# 9
2 2
CC142 CC143
0.1U_6.3V_K_X5R_0201 0.1U_6.3V_K_X5R_0201
LPC@ 1 1 LPC@

CC142 CC143 should be put on APU side to reduce stub when MP

+3VS_APU

LPC@
RC144 1 2 10K_0201_5% LPCPD# LPCPD# 9

RC145 1 @ 2 10K_0201_5% LPC_CLKRUN#


LPC_CLKRUN# 9

RC146 2 1 100K_0201_5% APU_LPC_RST#


A A
CC138 1 @ 2 150P_0402_50V8-J

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 FP5 Straps


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 14 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 15 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 16 of 83
5 4 3 2 1
5 4 3 2 1

DDR4 SO-DIMM A +1.2V

+1.2V +1.2V

1K_0402_5%
RD5
+1.2V +1.2V JDDRL1B

2
JDDRL1A DDRA_MA3 131 132 DDRA_MA2
6 DDRA_MA3 DDRA_MA1 A3 A2 DDRA_EVENT# DDRA_MA2 6 DDRA_EVENT#
133 134
6 DDRA_MA1 A1 EVENT_n/NF DDRA_EVENT# 6
135 136
1 2 DDRA_CLK0 137 VDD_9 VDD_10 138 DDRA_CLK1
DDRA_DQ12 VSS_1 VSS_2 DDRA_DQ13 6 DDRA_CLK0 DDRA_CLK0# CK0_t CK1_t/NF DDRA_CLK1# DDRA_CLK1 6
3 4 139 140
6 DDRA_DQ12 DQ5 DQ4 DDRA_DQ13 6 6 DDRA_CLK0# CK0_c CK1_c/NF DDRA_CLK1# 6
5 6 141 142
DDRA_DQ8 7 VSS_3 VSS_4 8 DDRA_DQ9 DDRA_PARITY 143 VDD_11 VDD_12 144 DDRA_MA0
6 DDRA_DQ8 DQ1 DQ0 DDRA_DQ9 6 6 DDRA_PARITY Parity A0 DDRA_MA0 6
9 10
DDRA_DQS#1 11 VSS_5 VSS_6 12
6 DDRA_DQS#1 DDRA_DQS1 DQS0_C DM0_n/DBl0_n DDRA_DM1 6 DDRA_BA1 DDRA_MA10
13 14 145 146
6 DDRA_DQS1 DQS0_t VSS_7 DDRA_DQ11 6 DDRA_BA1 BA1 A10/AP DDRA_MA10 6
15 16 147 148
DDRA_DQ10 VSS_8 DQ6 DDRA_DQ11 6 DDRA_CS0# VDD_13 VDD_14 DDRA_BA0
D 17 18 149 150 D
6 DDRA_DQ10 DQ7 VSS_9 DDRA_DQ15 6 DDRA_CS0# DDRA_MA14_WE# CS0_n BA0 DDRA_MA16_RAS# DDRA_BA0 6
19 20 151 152
DDRA_DQ14 VSS_10 DQ2 DDRA_DQ15 6 6 DDRA_MA14_WE# A14/WE_n A16/RAS_n DDRA_MA16_RAS# 6
21 22 153 154
6 DDRA_DQ14 DQ3 VSS_11 DDRA_DQ0 DDRA_ODT0 VDD_15 VDD_16 DDRA_MA15_CAS#
23 24 155 156
DDRA_DQ5 VSS_12 DQ12 DDRA_DQ0 6 6 DDRA_ODT0 DDRA_CS1# ODT0 A15/CAS_n DDRA_MA13 DDRA_MA15_CAS# 6
25 26 157 158
6 DDRA_DQ5 DQ13 VSS_13 DDRA_DQ1 6 DDRA_CS1# CS1_n A13 DDRA_MA13 6
27 28 159 160
DDRA_DQ4 VSS_14 DQ8 DDRA_DQ1 6 DDRA_ODT1 VDD_17 VDD_18
29 30 161 162
6 DDRA_DQ4 DQ9 VSS_15 DDRA_DQS#0 6 DDRA_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMA
31 32 163 164
VSS_16 DQS1_c DDRA_DQS0 DDRA_DQS#0 6 VDD_19 VREFCA DDRA_SA2
33 34 165 166
6 DDRA_DM0 DM1_n/DBl_n DQS1_t DDRA_DQS0 6 C1/CS3_n/NC SA2
35 36 167 168
DDRA_DQ2 37 VSS_17 VSS_18 38 DDRA_DQ7 DDRA_DQ36 169 VSS_53 VSS_54 170 DDRA_DQ37
6 DDRA_DQ2 DQ15 DQ14 DDRA_DQ7 6 6 DDRA_DQ36 DQ37 DQ36 DDRA_DQ37 6 1 1
39 40 171 172 CD2 CD3
DDRA_DQ6 41 VSS_19 VSS_20 42 DDRA_DQ3 DDRA_DQ33 173 VSS_55 VSS_56 174 DDRA_DQ32
6 DDRA_DQ6 DQ10 DQ11 DDRA_DQ3 6 6 DDRA_DQ33 DQ33 DQ32 DDRA_DQ32 6
43 44 175 176 1000P_25V_K_X7R_0201 0.1U_6.3V_K_X5R_0201
DDRA_DQ20 45 VSS_21 VSS_22 46 DDRA_DQ17 DDRA_DQS#4 177 VSS_57 VSS_58 178 2 2
6 DDRA_DQ20 DQ21 DQ20 DDRA_DQ17 6 6 DDRA_DQS#4 DDRA_DQS4 DQS4_c DM4_n/DBl4_n DDRA_DM4 6
47 48 179 180
DDRA_DQ16 VSS_23 VSS_24 DDRA_DQ21 6 DDRA_DQS4 DQS4_t VSS_59 DDRA_DQ35
49 50 181 182
6 DDRA_DQ16 DQ17 DQ16 DDRA_DQ21 6 DDRA_DQ34 VSS_60 DQ39 DDRA_DQ35 6
51 52 183 184
DDRA_DQS#2 VSS_25 VSS_26 6 DDRA_DQ34 DQ38 VSS_61 DDRA_DQ38
53 54 DDRA_DM2 6
185 186
6 DDRA_DQS#2 DDRA_DQS2 DQS2_c DM2_n/DBl2_n DDRA_DQ39 VSS_62 DQ35 DDRA_DQ38 6
55 56 187 188
6 DDRA_DQS2 DQS2_t VSS_27 DDRA_DQ18 6 DDRA_DQ39 DQ34 VSS_63 DDRA_DQ41
57 58 189 190
DDRA_DQ23 VSS_28 DQ22 DDRA_DQ18 6 DDRA_DQ40 VSS_64 DQ45 DDRA_DQ41 6
59 60 191 192
6 DDRA_DQ23 DQ23 VSS_29 DDRA_DQ19 6 DDRA_DQ40 DQ44 VSS_65 DDRA_DQ44
61 62 193 194
DDRA_DQ22 VSS_30 DQ18 DDRA_DQ19 6 DDRA_DQ45 VSS_66 DQ41 DDRA_DQ44 6
63 64 195 196
6 DDRA_DQ22 DQ19 VSS_31 DDRA_DQ24 6 DDRA_DQ45 DQ40 VSS_67 DDRA_DQS#5
65 66 197 198
DDRA_DQ29 VSS_32 DQ28 DDRA_DQ24 6 VSS_68 DQS5_c DDRA_DQS5 DDRA_DQS#5 6
67 68 6 DDRA_DM5
199 200
6 DDRA_DQ29 DQ29 VSS_33 DDRA_DQ25 DM5_n/DBl5_n DQS5_t DDRA_DQS5 6
69 70 201 202
DDRA_DQ28 VSS_34 DQ24 DDRA_DQ25 6 DDRA_DQ43 VSS_69 VSS_70 DDRA_DQ46
71 72 203 204
6 DDRA_DQ28 DQ25 VSS_35 DDRA_DQS#3 6 DDRA_DQ43 DQ46 DQ47 DDRA_DQ46 6
73 74 205 206
VSS_36 DQS3_c DDRA_DQS3 DDRA_DQS#3 6 DDRA_DQ47 VSS_71 VSS_72 DDRA_DQ42
6 DDRA_DM3
75 76 207 208
DM3_n/DBl3_n DQS3_t DDRA_DQS3 6 6 DDRA_DQ47 DQ42 DQ43 DDRA_DQ42 6
77 78 209 210
DDRA_DQ31 79 VSS_37 VSS_38 80 DDRA_DQ27 DDRA_DQ53 211 VSS_73 VSS_74 212 DDRA_DQ52
6 DDRA_DQ31 DQ30 DQ31 DDRA_DQ27 6 6 DDRA_DQ53 DQ52 DQ53 DDRA_DQ52 6
81 82 213 214
DDRA_DQ30 83 VSS_39 VSS_40 84 DDRA_DQ26 DDRA_DQ49 215 VSS_75 VSS_76 216 DDRA_DQ48
6 DDRA_DQ30 DQ26 DQ27 DDRA_DQ26 6 6 DDRA_DQ49 DQ49 DQ48 DDRA_DQ48 6
85 86 217 218
87 VSS_41 VSS_42 88 DDRA_DQS#6 219 VSS_77 VSS_78 220
CB5/NC CB4/NC 6 DDRA_DQS#6 DDRA_DQS6 DQS6_c DM6_n/DBl6_n DDRA_DM6 6
89 90 221 222
VSS_43 VSS_44 6 DDRA_DQS6 DQS6_t VSS_79 DDRA_DQ50
91 92 223 224
CB1/NC CB0/NC DDRA_DQ55 VSS_80 DQ54 DDRA_DQ50 6
93 94 225 226
VSS_45 VSS_46 6 DDRA_DQ55 DQ55 VSS_81 DDRA_DQ54
95 96 227 228
DQS8_c DM8_n/DBl_n/NC DDRA_DQ51 VSS_82 DQ50 DDRA_DQ54 6
97 98 229 230
DQS8_t VSS_47 6 DDRA_DQ51 DQ51 VSS_83 DDRA_DQ56
99 100 231 232
VSS_48 CB6/NC DDRA_DQ60 VSS_84 DQ60 DDRA_DQ56 6
101 102 233 234
C CB2/NC VSS_49 6 DDRA_DQ60 DQ61 VSS_85 DDRA_DQ61 C
103 104 235 236
VSS_50 CB7/NC DDRA_DQ57 VSS_86 DQ57 DDRA_DQ61 6
105 106 237 238
CB3/NC VSS_51 DDRA_DRAMRST#_R 6 DDRA_DQ57 DQ56 VSS_87 DDRA_DQS#7
107 108 RD35 1 2 33_0402_5% 239 240
DDRA_CKE0 VSS_52 RESET_n DDRA_CKE1 DDRA_DRAMRST# 6 VSS_88 DQS7_c DDRA_DQS7 DDRA_DQS#7 6
6 DDRA_CKE0 109 110 6 DDRA_DM7 241 242
CKE0 CKE1 DDRA_CKE1 6 DM7_n/DBl7_n DQS7_t DDRA_DQS7 6
111 112 243 244
DDRA_BG1 113 VDD_1 VDD_2 114 DDRA_ACT# DDRA_DQ63 245 VSS_89 VSS_90 246 DDRA_DQ59
6 DDRA_BG1 DDRA_BG0 BG1 ACT_n DDRA_ALERT# DDRA_ACT# 6 6 DDRA_DQ63 DQ62 DQ63 DDRA_DQ59 6
6 DDRA_BG0
115 116 247 248
BG0 ALERT_n DDRA_ALERT# 6 DDRA_DQ58 VSS_91 VSS_92 DDRA_DQ62
117 118 249 250
DDRA_MA12 VDD_3 VDD_4 DDRA_MA11 6 DDRA_DQ58 DQ58 DQ59 DDRA_DQ62 6
6 DDRA_MA12 119 120 251 252
DDRA_MA9 A12 A11 DDRA_MA7 DDRA_MA11 6 SMB_CLK_S3 VSS_93 VSS_94 SMB_DATA_S3
6 DDRA_MA9 121 122 1 8,18 SMB_CLK_S3 253 254
A9 A7 DDRA_MA7 6 RD18 1 DDRA_VDDSPD SCL SDA DDRA_SA0 SMB_DATA_S3 8,18
123 124 2 255 256
DDRA_MA8 VDD_5 VDD_6 DDRA_MA5 +3VS VDDSPD SA0
125 126 CD69 0_0402_5% 257 258
6 DDRA_MA8 DDRA_MA6 A8 A5 DDRA_MA4 DDRA_MA5 6 VPP_1 VTT DDRA_SA1 +0.6VS
127 128 0.1U_0402_10V7K @ 1 1 259 260
6 DDRA_MA6 A6 A4 DDRA_MA4 6 2 VPP_2 SA1
129 130
VDD_7 VDD_8 @
CD27 CD28 261 262
2.2U_0603_6.3V6K .1U_0402_10V6-K GND_1 GND_2
Layout Note: 2 2 ARGOS_D4AR0-26005-1P40
Place near DIMM ARGOS_D4AR0-26005-1P40 @
@

RD20 1 2
+2.5V
0_0402_5%
+1.2V @

+3VS +3VS +3VS V1.0


1
1

RD22 RD24 RD26 RD1


1K_0402_1%
0_0402_5% 0_0402_5% 0_0402_5%
2

@ @ @ +VREF_CA_DIMMA
2

DDRA_SA0 DDRA_SA1 DDRA_SA2


0.1U_6.3V_K_X5R_0201

1
RD3
1K_0402_1% CD21
1

RD23 RD25 RD27 2


@ 0_0402_5% @ 0_0402_5% @ 0_0402_5%
2

B B
Note:
VREF trace width:20 mils at least
Spacing:20mils to other signal/planes
Place near DIMM scoket
SPD Address = 0H Layout Note:
Place near DIMM
+2.5V

+1.2V 1 1 1 1 1 1

1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

180P_25V_J_NPO_0201

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201
CD1 CD95 CD96 CD125 CD126
CD4
1 1 1 1 1 1 1 1 1 1 RF@ RF@
2 2 2 2 2 2
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201

CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 CD123 CD124
CD@ CD@
CD@ RF@ RF@
2 2 2 2 2 2 2 2 2 2

+1.2V +0.6VS

1 1

4.7U_6.3V_M_X5R_0402

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201
1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD127 CD128
1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
CD14 CD15 CD16 CD17 CD18 CD19 CD20 CD129 CD122 CD22 CD23 CD24 CD25 CD26
100U_6.3V_M_X5R_1206_H1.6

100U_6.3V_M_X5R_1206_H1.6

EMC@ EMC@ EMC@ @ @ RF@ RF@


@ 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2019/07/02 Deciphered Date 2020/02/24 DDRVI SO-DIMM A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 17 of 83
5 4 3 2 1
5 4 3 2 1

DDR4 SO-DIMM B
+1.2V +1.2V
+1.2V
JDDRH1A
+1.2V +1.2V

1K_0402_5%
RD34
JDDRH1B
1 2
DDRB_DQ0 3 VSS_1 VSS_2 4 DDRB_DQ4
6 DDRB_DQ0 DQ5 DQ4 DDRB_DQ4 6
5 6

2
DDRB_DQ5 7 VSS_3 VSS_4 8 DDRB_DQ1 DDRB_MA3 131 132 DDRB_MA2
6 DDRB_DQ5 DQ1 DQ0 DDRB_DQ1 6 6 DDRB_MA3 DDRB_MA1 A3 A2 DDRB_EVENT# DDRB_MA2 6 DDRB_EVENT#
9 10 133 134
DDRB_DQS#0 VSS_5 VSS_6 6 DDRB_MA1 A1 EVENT_n/NF DDRB_EVENT# 6
11 12 135 136
6 DDRB_DQS#0 DDRB_DQS0 DQS0_C DM0_n/DBI0_n DDRB_DM0 6 DDRB_CLK0 VDD_9 VDD_10 DDRB_CLK1
D 13 14 137 138 D
6 DDRB_DQS0 DQS0_t VSS_7 DDRB_DQ6 6 DDRB_CLK0 DDRB_CLK0# CK0_t CK1_t/NF DDRB_CLK1# DDRB_CLK1 6
15 16 139 140
DDRB_DQ7 VSS_8 DQ6 DDRB_DQ6 6 6 DDRB_CLK0# CK0_c CK1_c/NF DDRB_CLK1# 6
17 18 141 142
6 DDRB_DQ7 DQ7 VSS_9 DDRB_DQ3 DDRB_PARITY VDD_11 VDD_12 DDRB_MA0
19 20 143 144
DDRB_DQ2 VSS_10 DQ2 DDRB_DQ3 6 6 DDRB_PARITY Parity A0 DDRB_MA0 6
21 22
6 DDRB_DQ2 DQ3 VSS_11 DDRB_DQ8
23 24
DDRB_DQ13 VSS_12 DQ12 DDRB_DQ8 6 DDRB_BA1 DDRB_MA10
25 26 6 DDRB_BA1 145 146
6 DDRB_DQ13 DQ13 VSS_13 DDRB_DQ9 BA1 A10/AP DDRB_MA10 6
27 28 147 148
DDRB_DQ12 VSS_14 DQ8 DDRB_DQ9 6 DDRB_CS0# VDD_13 VDD_14 DDRB_BA0
29 30 149 150
6 DDRB_DQ12 DQ9 VSS_15 DDRB_DQS#1 6 DDRB_CS0# DDRB_MA14_WE# CS0_n BA0 DDRB_MA16_RAS# DDRB_BA0 6
31 32 151 152
VSS_16 DQS1_c DDRB_DQS1 DDRB_DQS#1 6 6 DDRB_MA14_WE# WE_n/A14 RAS_n/A16 DDRB_MA16_RAS# 6
6 DDRB_DM1
33 34 153 154
DM1_n/DBl1_n DQS1_t DDRB_DQS1 6 DDRB_ODT0 VDD_15 VDD_16 DDRB_MA15_CAS#
35 36 155 156
DDRB_DQ11 VSS_17 VSS_18 DDRB_DQ10 6 DDRB_ODT0 DDRB_CS1# ODT0 CAS_n/A15 DDRB_MA13 DDRB_MA15_CAS# 6
37 38 6 DDRB_CS1# 157 158
6 DDRB_DQ11 DQ15 DQ14 DDRB_DQ10 6 CS1_n A13 DDRB_MA13 6
39 40 159 160
DDRB_DQ14 41 VSS_19 VSS_20 42 DDRB_DQ15 DDRB_ODT1 161 VDD_17 VDD_18 162
6 DDRB_DQ14 DQ10 DQ11 DDRB_DQ15 6 6 DDRB_ODT1 ODT1 C0/CS2_n/NC +VREF_CA_DIMMB
43 44 163 164
DDRB_DQ19 45 VSS_21 VSS_22 46 DDRB_DQ22 165 VDD_19 VREFCA 166 DDRB_SA2
6 DDRB_DQ19 DQ21 DQ20 DDRB_DQ22 6 C1/CS3_n/NC RFU/SA2
47 48 167 168
DDRB_DQ20 49 VSS_23 VSS_24 50 DDRB_DQ21 DDRB_DQ32 169 VSS_53 VSS_54 170 DDRB_DQ33
6 DDRB_DQ20 DQ17 DQ16 DDRB_DQ21 6 6 DDRB_DQ32 DQ37 DQ36 DDRB_DQ33 6
51 52 171 172 1 1
DDRB_DQS#2 53 VSS_25 VSS_26 54 DDRB_DQ37 173 VSS_55 VSS_56 174 DDRB_DQ36 CD30 CD130
6 DDRB_DQS#2 DDRB_DQS2 DQS2_c DM2_n/DBl2_n DDRB_DM2 6 6 DDRB_DQ37 DQ33 DQ32 DDRB_DQ36 6
55 56 175 176
6 DDRB_DQS2 DQS2_t VSS_27 DDRB_DQ17 DDRB_DQS#4 VSS_57 VSS_58
57 58 177 178 DDRB_DM4 6 1000P_25V_K_X7R_0201 0.1U_6.3V_K_X5R_0201
DDRB_DQ23 VSS_28 DQ22 DDRB_DQ17 6 6 DDRB_DQS#4 DDRB_DQS4 DQS4_c DM4_n/DBl4_n 2 2
59 60 179 180
6 DDRB_DQ23 DQ23 VSS_29 DDRB_DQ16 6 DDRB_DQS4 DQS4_t VSS_59 DDRB_DQ39
61 62 181 182
DDRB_DQ18 VSS_30 DQ18 DDRB_DQ16 6 DDRB_DQ35 VSS_60 DQ39 DDRB_DQ39 6
63 64 183 184
6 DDRB_DQ18 DQ19 VSS_31 DDRB_DQ24 6 DDRB_DQ35 DQ38 VSS_61 DDRB_DQ34
65 66 185 186
DDRB_DQ25 VSS_32 DQ28 DDRB_DQ24 6 DDRB_DQ38 VSS_62 DQ35 DDRB_DQ34 6
67 68 187 188
6 DDRB_DQ25 DQ29 VSS_33 DDRB_DQ29 6 DDRB_DQ38 DQ34 VSS_63 DDRB_DQ46
69 70 189 190
DDRB_DQ28 VSS_34 DQ24 DDRB_DQ29 6 DDRB_DQ41 VSS_64 DQ45 DDRB_DQ46 6
71 72 191 192
6 DDRB_DQ28 DQ25 VSS_35 DDRB_DQS#3 6 DDRB_DQ41 DQ44 VSS_65 DDRB_DQ40
73 74 193 194
VSS_36 DQS3_c DDRB_DQS3 DDRB_DQS#3 6 DDRB_DQ47 VSS_66 DQ41 DDRB_DQ40 6
6 DDRB_DM3 75 76 195 196
DM3_n/DBl3_n DQS3_t DDRB_DQS3 6 6 DDRB_DQ47 DQ40 VSS_67 DDRB_DQS#5
77 78 197 198
DDRB_DQ31 VSS_37 VSS_38 DDRB_DQ27 VSS_68 DQS5_c DDRB_DQS5 DDRB_DQS#5 6
79 80 6 DDRB_DM5
199 200
6 DDRB_DQ31 DQ30 DQ31 DDRB_DQ27 6 DM5_n/DBl5_n DQS5_t DDRB_DQS5 6
81 82 201 202
DDRB_DQ26 83 VSS_39 VSS_40 84 DDRB_DQ30 DDRB_DQ45 203 VSS_69 VSS_70 204 DDRB_DQ44
6 DDRB_DQ26 DQ26 DQ27 DDRB_DQ30 6 6 DDRB_DQ45 DQ46 DQ47 DDRB_DQ44 6
85 86 205 206
87 VSS_41 VSS_42 88 DDRB_DQ42 207 VSS_71 VSS_72 208 DDRB_DQ43
CB5/NC CB4/NC 6 DDRB_DQ42 DQ42 DQ43 DDRB_DQ43 6
89 90 209 210
91 VSS_43 VSS_44 92 DDRB_DQ53 211 VSS_73 VSS_74 212 DDRB_DQ49
CB1/NC CB0/NC 6 DDRB_DQ53 DQ52 DQ53 DDRB_DQ49 6
93 94 213 214
95 VSS_45 VSS_46 96 DDRB_DQ48 215 VSS_75 VSS_76 216 DDRB_DQ52
DQS8_c DM8_n/DBI_n/NC 6 DDRB_DQ48 DQ49 DQ48 DDRB_DQ52 6
97 98 217 218
C
99 DQS8_t VSS_47 100 DDRB_DQS#6 219 VSS_77 VSS_78 220 C
VSS_48 CB6/NC 6 DDRB_DQS#6 DDRB_DQS6 DQS6_c DM6_n/DBl6_n DDRB_DM6 6
101 102 221 222
CB2/NC VSS_49 6 DDRB_DQS6 DQS6_t VSS_79 DDRB_DQ55
103 104 223 224
VSS_50 CB7/NC DDRB_DQ50 VSS_80 DQ54 DDRB_DQ55 6
105 106 225 226
CB3/NC VSS_51 DDRB_DRAMRST#_R 6 DDRB_DQ50 DQ55 VSS_81 DDRB_DQ54
107 108 RD36 1 2 33_0402_5% 227 228
DDRB_CKE0 VSS_52 RESET_n DDRB_CKE1 DDRB_DRAMRST# 6 DDRB_DQ51 VSS_82 DQ50 DDRB_DQ54 6
109 110 229 230
6 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 6 6 DDRB_DQ51 DQ51 VSS_83 DDRB_DQ61
111 112 231 232
DDRB_BG1 VDD_1 VDD_2 DDRB_ACT# DDRB_DQ57 VSS_84 DQ60 DDRB_DQ61 6
113 114 233 234
6 DDRB_BG1 DDRB_BG0 BG1 ACT_n DDRB_ALERT# DDRB_ACT# 6 6 DDRB_DQ57 DQ61 VSS_85 DDRB_DQ62
115 116 235 236
6 DDRB_BG0 BG0 ALERT_n DDRB_ALERT# 6 DDRB_DQ56 VSS_86 DQ57 DDRB_DQ62 6
117 118 1 237 238
DDRB_MA12 VDD_3 VDD_4 DDRB_MA11 6 DDRB_DQ56 DQ56 VSS_87 DDRB_DQS#7
119 120 239 240
6 DDRB_MA12 DDRB_MA9 A12 A11 DDRB_MA7 DDRB_MA11 6 VSS_88 DQS7_c DDRB_DQS7 DDRB_DQS#7 6
121 122 CD70 241 242
6 DDRB_MA9 A9 A7 DDRB_MA7 6 6 DDRB_DM7 DM7_n/DBl7_n DQS7_t DDRB_DQS7 6
123 124 0.1U_0402_10V7K 243 244
DDRB_MA8 125 VDD_5 VDD_6 126 DDRB_MA5 2 DDRB_DQ60 245 VSS_89 VSS_90 246 DDRB_DQ63
6 DDRB_MA8 DDRB_MA6 A8 A5 DDRB_MA4 DDRB_MA5 6 @ 6 DDRB_DQ60 DQ62 DQ63 DDRB_DQ63 6
127 128 247 248
6 DDRB_MA6 A6 A4 DDRB_MA4 6 DDRB_DQ59 VSS_91 VSS_92 DDRB_DQ58
129 130 249 250
VDD_7 VDD_8 6 DDRB_DQ59 DQ58 DQ59 DDRB_DQ58 6
251 252
SMB_CLK_S3 253 VSS_93 VSS_94 254 SMB_DATA_S3
RD19 1 8,17 2 SMB_CLK_S3 DDRB_VDDSPD SCL SDA DDRB_SA0 SMB_DATA_S3 8,17
255 256
+3VS VDDSPD SA0
0_0402_5% 1 1 257 258 +0.6VS
ARGOS_D4AS0-26005-1P40 @ CD53 259 VPP_1 Vtt 260 DDRB_SA1
ME@ 2.2U_0603_6.3V6K CD54 VPP_2 SA1
.1U_0402_10V6-K 261 262
2 2 GND_1 GND_2
+3VS +3VS +3VS
+1.2V ARGOS_D4AS0-26005-1P40
ME@
1

RD28 RD33
1

RD30
0_0402_5% @ 0_0402_5% RD21 1 2
0_0402_5% RD11 +2.5V
@ @ 1K_0402_1% 0_0402_5%
@
2

+VREF_CA_DIMMB
DDRB_SA0 DDRB_SA1 DDRB_SA2
2

0.1U_6.3V_K_X5R_0201
1

1
RD31
RD29 RD32 RD13 CD47
@ @ 0_0402_5% @ 1K_0402_1%
0_0402_5% 0_0402_5%
2
2

B B

SPD Address = 2H CAD Note:


Trace width= 20 mil, Spcing=20 mils
+2.5V

+1.2V 1 1 1 1 1 1

1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

180P_25V_J_NPO_0201

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201
CD131 CD132 CD133 CD135 CD136
CD134
1 1 1 1 1 1 1 1 1 1 RF@ RF@
2 2 2 2 2 2
10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

10U_6.3V_M_X5R_0402

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201

CD137 CD138 CD139 CD140 CD141 CD142 CD143 CD144 CD145 CD146
CD@ CD@
CD@ RF@ RF@
2 2 2 2 2 2 2 2 2 2

+1.2V +0.6VS

1 1

4.7U_6.3V_M_X5R_0402

6.8P_25V_C_NPO_0201

8.2P_50V_C_COG_0201
1 1 1 1 1 1 1 1 1 1 1 1 1 1 CD147 CD148
1U_6.3V_K_X5R_0201
0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
CD149 CD150 CD151 CD152 CD153 CD154 CD155 CD156 CD157 CD158 CD159 CD160 CD161 CD162
100U_6.3V_M_X5R_1206_H1.6

100U_6.3V_M_X5R_1206_H1.6

EMC@ EMC@ EMC@ @ @ RF@ RF@


@ 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2019/07/02 Deciphered Date 2020/02/24 DDRVI SO-DIMM B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 18 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 19 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 20 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 21 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 22 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Y550 1.0

Date: Monday, February 24, 2020 Sheet 23 of 83


5 4 3 2 1
5 4 3 2 1

STRAP2 STRAP1 STRAP0 RAMCFG[4:0] H=High: Tied to 1.8V


N17P-G1 GPIO M=Middle: Tied to 0.9V
L L L 00000
L=Low: Tied to 0V
GPIO I/O ACTIVE Function Description I/O Termination L H L 00010

GPIO0 OUT - PWM Output to control NVVDD L H H 00011

GPIO1 OUT - FB Enable for GC6 2.1 H H L 00110

GPIO2 IN - GPU wake signal for GC6 2.1 H H H 00111


D D

GPIO3 OUT - PWM Output to control the SRAM power supply


ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0] 1:ENABLE 0:DISABLE
GPIO4 OUT - GPU power sequencing for GC6 2.1 --- 1V8_MAIN_EN
L L L 1111 DEFAULT SOR0/1/2/3 ENABLE
GPIO5 IN N/A Active low Frame Lock
L L H 1110
GPIO6 OUT - Phase Shedding, NVVDD_PSI
L H L 1101
GPIO7 OUT N/A Panel Backlight enable
L H H 1100
GPIO8 OUT - Memory voltage Control
H L L 1011
GPIO9 I/O - Active Low Thermal Alert
H L H 1010
GPIO10 OUT - Memory VREF Control (100K pull Down)
H H L 1001
GPIO11 OUT - Panel Power enable
H H H 1000
GPIO12 IN - AC power detect or power supply overdraw input (10K pull High)
L L M 0111
GPIO13 OUT N/A LCD Panel Backlight Enable
L M L 0110
GPIO14 IN N/A Hot Plug Detect for IFPA
L M H 0101
C GPIO15 IN N/A Hot Plug Detect for IFPB C

L H M 0100
GPIO16 OUT - System side PCIe reset monitor
H L M 0011
GPIO17 IN N/A Hot Plug Detect for IFPD
H M L 0010
GPIO18 IN N/A Hot Plug Detect for IFPE
H M H 0001
GPIO19 OUT N/A 3D Vision L/R Signal
H H M 0000
GPIO20 N/A GC5_MODE

GPIO21 I/O N/A UNUSED


1:SMB_ALT_ADDR ENABLE
STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
GPIO22 I/O N/A UNUSED 0:SMB_ALT_ADDR DISABLE
M H H 1 1 1 1
GPIO23 OUT - GPU PCIe self-reset control 1:DEVID_SEL REBRAND
M H L 1 1 1 0 0:DEVID_SEL ORIGNAL
GPIO24 IN N/A Hot Plug Detect for IFPF
M L H 1 1 0 1 1:PCIE_CFG LOW POWER
GPIO25 N/A UNUSED
0:PCIE_CFG HIGH POWER
M L L 1 1 0 0
GPIO26 N/A UNUSED
1:VGA_DEVICE ENABLE
L H M 1 0 1 1
GPIO27 IN N/A Hot Plug Detect for IFPC 0:VGA_DEVICE DISABLE
B B
L M H 1 0 1 0

L M L 1 0 0 1

L L M 1 0 0 0

H H H 0 1 1 1
N17P-G1 Power Sequence
H H L 0 1 1 0

H L H 0 1 0 1

H L L 0 1 0 0

+1.8VS_AON NVVDDS/+1.0VGS L H H 0 0 1 1

+1.8VGS L H L 0 0 1 0
NVVDD
NVVDD L L H 0 0 0 1 DEFAULT

NVVDDS/+1.0VGS L L L 0 0 0 0

FBVDDQ

A A
1. All power rail ramp up time should be larger than 40us 1. NVVDDS/PEX_DVDD must ramp down before NVVDD, all
and is recommended to be less than 2ms. other power rails can ramp down together with NVVDD.
2. T (from 1V8_MAIN_EN to PEX_DVDD/NVVDD_Pgood) 2. All 3.3V devices that connect to the GPU must be
must NOT exceed 4ms. ramp down before 1V8_AON; GPU can NOT have any 3.3V
leakage path after 1V8_AON and 1.8V_MAIN power down.
3. All 3.3V devices that connect to the GPU must be
powered after 1V8_AON; GPU can NOT have any 3.3V 3. The previous power rail must ramp down to 10% before
leakage path before 1V8_AON present. the next power rail can start ramping down.
Security Classification LC Future Center Secret Data Title
4. The previous power rail must ramp up to 90% before
the next power rail can start ramping up.
Issued Date 2019/07/02 Deciphered Date 2020/02/24 VGA Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 24 of 83
5 4 3 2 1
5 4 3 2 1

PEX_DVDD Decouling
UV1A 3A
+1.0VGS
1/17 FBA
2000mA MLCC N18 N17 location
Under GPU(below 150mils)
Near GPU Mid way
PEX_DVDD_1
AG21
1.0uF 12/6 4

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AG22 1 1

33P_0402_50V8J

33P_0402_50V8J
PEX_DVDD_2 AG24 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Under
PEX_DVDD_3 4.7uF 3 0

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AH25
PEX_WAKE# PEX_DVDD_4

@
TV12 1 AJ11 AG19
PEX_WAKE* PEX_CVDD_1 AH21 2 2

RF_NS@

RF_NS@
OPT@

OPT@

OPT@

OPT@

OPT@
OPT@
PLT_RST_VGA# AJ12 PEX_CVDD_2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4.7uF 0 2

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

CD85

CD86
28 PLT_RST_VGA# CLK_REQ_GPU# PEX_RST*

CV2

CV3

CV4

CV5

CV536

CV537
AK12

CV548

CV549

CV550

CV553

CV551

CV552

CV555

CV554
CV1448

CV1449

CV1450

CV1451

CV1452

CV1453
PEX_CLKREQ* 10uF 3 0 Near
CLK_PCIE_GPU AL13
9 CLK_PCIE_GPU
9 CLK_PCIE_GPU#
CLK_PCIE_GPU# AK13 PEX_REFCLK
PEX_REFCLK* 22uF 2 0
D 5 PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
CV12 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P0
PCIE_CRX_C_GTX_N0
AK14
PEX_TX0 10uF 0 1 D
5 PCIE_CRX_GTX_N0 CV13 1 2 0.22U_0201_6.3V6-K OPT@ AJ14
PEX_TX0* Midway
5 PCIE_CTX_C_GRX_P0
PCIE_CTX_C_GRX_P0 AN12 22uF 0 1
PCIE_CTX_C_GRX_N0 AM12 PEX_RX0
5 PCIE_CTX_C_GRX_N0 PEX_RX0*
PCIE_CRX_GTX_P1 CV17 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P1 AH14
5 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_N1 CV19 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N1 AG14 PEX_TX1 PEX_HVDD Decouling
5 PCIE_CRX_GTX_N1

5 PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_P1
PCIE_CTX_C_GRX_N1
AN14
PEX_TX1*

PEX_RX1
PEX_HVDD_1
PEX_HVDD_2
AG13
AG15
Near GPU +1.8VS_VGA
1A
AM14 AG16
5 PCIE_CTX_C_GRX_N1 PEX_RX1* PEX_HVDD_3 AG18 Under GPU(below 150mils)
MLCC N18 N17 location
PCIE_CRX_GTX_P2 CV22 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P2 AK15 PEX_HVDD_4 AG25 Near GPU Mid way
5
5
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N2 CV23 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N2 AJ15 PEX_TX2
PEX_TX2*
PEX_HVDD_5
PEX_HVDD_6
AH15 1.0uF 13/6 4

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AH18
PCIE_CTX_C_GRX_P2 AP14 PEX_HVDD_7 AH26 Under
5 PCIE_CTX_C_GRX_P2 PEX_RX2 PEX_HVDD_8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4.7uF 3 0

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PCIE_CTX_C_GRX_N2

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
5 PCIE_CTX_C_GRX_N2 AP15 AH27
PEX_RX2* PEX_HVDD_9 AJ27
PCIE_CRX_GTX_P3 PCIE_CRX_C_GTX_P3 PEX_HVDD_10 4.7uF

@
CV24 1 2 0.22U_0201_6.3V6-K AL16 AK27

@
OPT@

OPT@

OPT@

OPT@

OPT@
OPT@

OPT@

OPT@

OPT@
5
5
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N3 CV25 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N3 AK16 PEX_TX3 PEX_HVDD_11 AL27 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 2
PEX_TX3* PEX_HVDD_12

CV522

CV523

CV524

CV525

CV526

CV527

CV528
AM28 Near
10uF 3 0

OPT@

OPT@

OPT@

OPT@

OPT@
CV532

CV533

CV534

CV302

CV535
CV1445

CV1446

CV1447

CV1444

CV1443

CV1442

CV1441

CV1381

CV1492

CV1493
PCIE_CTX_C_GRX_P3 AN15 PEX_HVDD_13 AN28
5 PCIE_CTX_C_GRX_P3 PCIE_CTX_C_GRX_N3 PEX_RX3 PEX_HVDD_14
AM15
5 PCIE_CTX_C_GRX_N3 PEX_RX3* OPT@
22uF 2 0
PCIE_CRX_GTX_P4 CV26 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P4 AK17
5
5
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N4 CV27 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_N4 AJ17 PEX_TX4 10uF 0 2
PEX_TX4*
Midway
5 PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_P4
PCIE_CTX_C_GRX_N4
AN17
PEX_RX4
22uF 0 1
5 PCIE_CTX_C_GRX_N4
AM17
PEX_RX4*
PCIE_CRX_GTX_P5 CV28 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P5 AH17
5 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_N5 PCIE_CRX_C_GTX_N5 PEX_TX5
5 PCIE_CRX_GTX_N5 CV29 1 2 0.22U_0201_6.3V6-K OPT@ AG17
PEX_TX5*
PCIE_CTX_C_GRX_P5 AP17
5 PCIE_CTX_C_GRX_P5 PCIE_CTX_C_GRX_N5 PEX_RX5
5 PCIE_CTX_C_GRX_N5 AP18
PEX_RX5*
PCIE_CRX_GTX_P6 CV30 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P6 AK18
5 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_N6 PCIE_CRX_C_GTX_N6 PEX_TX6
5 PCIE_CRX_GTX_N6 CV34 1 2 0.22U_0201_6.3V6-K OPT@ AJ18
PEX_TX6*
PCIE_CTX_C_GRX_P6 AN18
5 PCIE_CTX_C_GRX_P6 PEX_RX6 MAX:250mA
5 PCIE_CTX_C_GRX_N6
PCIE_CTX_C_GRX_N6 AM18
PEX_RX6*
MAX:100mA
PCIE_CRX_GTX_P7 CV35 1 2 0.22U_0201_6.3V6-K OPT@ PCIE_CRX_C_GTX_P7 AL19 +1.8VS_VGA +1.8VS_VGA
5 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_N7 PCIE_CRX_C_GTX_N7 PEX_TX7 CORE_PLLVDD
5 PCIE_CRX_GTX_N7 CV36 1 2 0.22U_0201_6.3V6-K OPT@ AK19 Near GPU CORE_PLLVDD
PEX_TX7* @
PCIE_CTX_C_GRX_P7 AN20 AH12 PEX_PLL_HVDD RV7 1 2 0_0402_5% UV1Q
5 PCIE_CTX_C_GRX_P7 PEX_RX7 PEX_PLL_HVDD

1U_6.3V_M_X5R_0201
PCIE_CTX_C_GRX_N7 AM20 11/17 XTAL_PLL
5 PCIE_CTX_C_GRX_N7 PEX_RX7* Place Under GPU/1 cap per pin +1.8VS_AON
1 1 2
AK20 CORE_PLLVDD AD8
LV1
XSN_PLLVDD

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
AJ20 PEX_TX8 HCB1608KF-300T60_2P H26
PEX_TX8* AE8 GPCPLL_AVDD
OPT@

OPT@
C 1 1 1 1 1 1 SP_PLLVDD C

22U_0805_6.3V6M

1U_6.3V_M_X5R_0201
2

4.7U_0603_6.3V6K
AP20 30ohms (ESR=0.01) Bead

2
PEX_RX8 AD7

CV31
AP21
PEX_RX8* P/N;SM01000M300 VID_PLLVDD

OPT@

OPT@

OPT@

OPT@
RV211
AH20 N18 change 2 2 2 2 2 2 10K_0402_5%
PEX_TX9

CV16

CV32

CV33

CV37
AG20 @

OPT@

OPT@
PEX_TX9*

CV11

CV15

1
AN21
AM21 PEX_RX9 XTALSSIN H1 J4 XTALOUT
PEX_RX9* EXT_REFCLK_FL XTAL_OUTBUFF
AK21
PEX_PLL_HVDD/Q Decouling Value
AJ21 PEX_TX10 XTAL_IN H3 H2 XTAL_OUT
XTAL_IN XTAL_OUT

1
PEX_TX10*
MLCC N18 N17 location Place near GPU
AN23 N18P-FCBGA960_BGA960 RV46
AM23 PEX_RX10 @ RV209 100K_0402_5%
PEX_RX10* CV31 1uf 0.1uf Near 1
10M_0402_5%
2 OPT@
AL22

2
AK22 PEX_TX11 OPT@
Change PEG from X16 to X8 2019/08/08 PEX_TX11* RV14
10K_0402_5%
AP23 OPT@ YV1
AP24 PEX_RX11
PEX_RX11*

1
AK23
Core_PLLVDD Decouling Value XTAL_IN 1 4
PEX_TX12 OSC1 GND2
AJ23
PEX_TX12* 2 3 XTAL_OUT
AN24 MLCC N18 N17 location GND1 OSC2
AM24 PEX_RX12
1 1
PEX_RX12* CV16 1uf 0.1uf Under CV262
27MHZ_10PF_7V27000050
OPT@ CV263
AH23
AG23 PEX_TX13 10P_0402_50V8J 10P_0402_50V8J
2 2
PEX_TX13* CV32 1uf 0.1uf Under OPT@ OPT@
AN26
AM26 PEX_RX13
PEX_RX13*
AK24 CV33 1uf 0.1uf Under
AJ24 PEX_TX14
PEX_TX14*
Change CV262&CV263 from 12P to 8P
AP26
AP27 PEX_RX14 CV37 1uf 0.1uf Under SIT 0129SF
PEX_RX14*
AL25
AK25 PEX_TX15
PEX_TX15*
AN27
AM27 PEX_RX15
PEX_RX15* AP29 PEX_TERMP 1 2
PEX_TERMP RV34
2.49K_0402_1%
N18P-FCBGA960_BGA960 OPT@
B @ B

1 2 +1.8VS_VGA
OVERT#_NVEN 28
RV1207
0_0402_5%
@

1 2

2
WRST# 52
RV20
0_0402_5% For SWG mode RV1243
5.6K_0402_1%
RV29
10K_0402_5%
@

+1.8VS_AON

@
1 2
APU_THERMTRIP# 7,52 OPT@
RV1

1
+1.8VS_AON
1

0_0402_5% 1
For UMA mode 1
@

8,28 VGA_PWRGD 2
@

RV2
CV1 RV8

choose one 10K_0402_5%


0_0402_5% 1
@

1U_6.3V_K_X5R_0201
CV66
3

D 2

2
.1U_0402_10V6-K
2

5 QV1B LBSS138LT1G

@
G LBSS138DW1T1G_SOT363-6 Vds=50V 2
@

S Id=200mA
4

10K_0402_5%
Rdson=Max10ohm
6

1
Vgs= +-20V
28 OVERT# OVERT# 2 QV1A Vgs(th)=0.5V--1V

OPT@
RV31
G LBSS138DW1T1G_SOT363-6

2
@

S
1

1 3 CLK_REQ_GPU#
9 GPU_CLKREQ#
1

D
@

PLT_RST_VGA#
1
1 2 2 QV2
CV20 QV5
RV3 G LBSS139WT1G_SC70-3
A LSI1012XT1G_SC-89-3 A
@

0_0402_5% S 1U_6.3V_K_X5R_0201
OPT@
3

2
@

Vgs(th)≤0.9V
@

1
CV21
1U_6.3V_K_X5R_0201
2

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_(1/6):PEG I/F


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y550 1.0

Date: Monday, February 24, 2020 Sheet 25 of 83


5 4 3 2 1
5 4 3 2 1

Ref NV DG-08780-001
If an IFP link is unused, in general it should be left unconnected.
This includes Main and Aux links.
IFPxy_RSET and IFPxy_PLLVDD (xy=AB,CD,EF)
can be left unconnected if neither of IFPx /IFPy is in use

UV1K
5/17 IFPAB

DVI DP

SL/DL

TXC/TXC AN6 GPU_SNK0_DP3N UV1N


2 1 IFPAB_RSET TXC/TXC IFPA_L3* GPU_SNK0_DP3P GPU_SNK0_DP3N 44
AJ8 AM6 8/17 IFPE
IFPAB_RSET IFPA_L3 GPU_SNK0_DP3P 44
RV68 1K_0402_1% @
AN3 GPU_SNK0_DP2N 2 1 IFPEF_RSET AD6
OPT@ TXD0/0 IFPA_L2* GPU_SNK0_DP2P GPU_SNK0_DP2N 44 IFPE_RSET
D CORE_PLLVDD AP3 RV1140 1K_0402_1% D
TXD0/0 IFPA_L2 GPU_SNK0_DP2P 44
@ HDMI DP
RV69 1 2 0_0603_5% +IFPAB_PLLVDD AH8 AM5 GPU_SNK0_DP1N CORE_PLLVDD
IFPAB_PLLVDD
TXD1/1
IFPA_L1* AN5 GPU_SNK0_DP1P GPU_SNK0_DP1N
GPU_SNK0_DP1P
44
44
for Type-C DP AB4
IFPA_L1 RV11241 +IFPEF_PLLVDD
2 1/10W_0_+-5%_0603 AB8 IFPE_AUX_SDA* AB3
1 TXD1/1 IFPE_PLLVDD IFPE_AUX_SCL
@

1U_6.3V_M_X5R_0201
OPT@ CV7 AK6 GPU_SNK0_DP0N
IFPA_L0* AL6 GPU_SNK0_DP0P GPU_SNK0_DP0N 44 AC5
1U_6.3V_K_X5R_0201 TXD2/2 IFPA_L0 GPU_SNK0_DP0P 44 TXC IFPE_L3* AC4
2 TXD2/2 1 TXC IFPE_L3

@
TXD0
AC3
AH6 GPU_SNK0_AUX_DN IFPE_L2* AC2
IFPA_AUX_SDA* GPU_SNK0_AUX_DP GPU_SNK0_AUX_DN 44 TXD0 IFPE_L2
AJ6 2

CV461
IFPA_AUX_SCL GPU_SNK0_AUX_DP 44 AC1
TXD1 IFPE_L1* AD1
TXD1 IFPE_L1
+1.0VGS TXC AH9 AD3
TXC IFPB_L3* TXD2 IFPE_L0*
AJ9 TXD2
AD2
RV72 1 OPT@ 2 1/10W_0_+-5%_0603 +IFPAB_IOVDD AG8 IFPB_L3 +1.0VGS IFPE_L0
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

IFP_IOVDD_5 AP5 GPU_SNK0_AUX_DP RV15 1 OPT@ 2 100K_0402_5%


1U_6.3V_K_X5R_0201

TXD0/3 IFPB_L2*
AG9 AP6
4.7U_0603_6.3V6K

IFP_IOVDD_6 TXD0/3 IFPB_L2 +IFPF_IOVDD


1 1 1 1 1 RV337 1 OPT@ 2 1/10W_0_+-5%_0603 AC7
GPU_SNK0_AUX_DN RV1292 1 OPT@ 2 100K_0402_5% AC8 IFP_IOVDD_1
@ AL7 IFP_IOVDD_2

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
TXD1/4 IFPB_L1*
OPT@

OPT@

OPT@

TXD1/4
AM7

1U_6.3V_K_X5R_0201
2 2 2 2 2 IFPB_L1 N18P-FCBGA960_BGA960
CV69

CV70

CV71
CV1175

AM8

4.7U_0603_6.3V6K
1 1 1 1 1
OPT@
CV445

IFPB_L0* @
AN8
TXD2/5 IFPB_L0
TXD2/5 @

OPT@

OPT@
2 2 2 2 2

CV463

CV462

CV446
CV1176
AL8
IFPB_AUX_SDA*

OPT@
CV460
AK8
IFPB_AUX_SCL
OPT@
near GPU under GPU
IFPAB
N18P-FCBGA960_BGA960 near GPU under GPU
@

C C

Decouling Value
MLCC N18 N17 location
CV7 1uf 0.1uf Under UV1L
7/17 IFPD

CV222 1uf 0.1uf Under


HDMI DP

CV461 1uf 0.1uf Under AK2 GPU_EDP_AUX#


IFPD_AUX_SDA* AK3 GPU_EDP_AUX GPU_EDP_AUX# 39
IFPD_AUX_SCL GPU_EDP_AUX 39
CV70 1uf 0.1uf Under
AK5 GPU_EDP_TX3-
UV1M IFPD TXC IFPD_L3* AK4 GPU_EDP_TX3+ GPU_EDP_TX3- 39
6/17 IFPC CV71 1uf 0.1uf Under TXC IFPD_L3 GPU_EDP_TX3+ 39
AL4 GPU_EDP_TX2-
2 1 IFPCD_RSET AF8 TXD0 IFPD_L2* AL3 GPU_EDP_TX2+ GPU_EDP_TX2- 39
IFPCD_RSET TXD0 IFPD_L2 GPU_EDP_TX2+ 39
RV73 OPT@ 1K_0402_1%
CV223 1uf 0.1uf Under GPU_EDP_TX1-
AM4
HDMI DP TXD1 IFPD_L1* GPU_EDP_TX1+ GPU_EDP_TX1- 39
AM3
TXD1 IFPD_L1 GPU_EDP_TX1+ 39
AG2 1uf 0.1uf Under
IFPC_AUX_SDA* AG3 HDMI1_DAT 42 CV68 AM2 GPU_EDP_TX0-
CORE_PLLVDD IFPC_AUX_SCL HDMI1_CLK 42 TXD2 IFPD_L0* AM1 GPU_EDP_TX0+ GPU_EDP_TX0- 39
TXD2 IFPD_L0 GPU_EDP_TX0+ 39
HDMI1_TXC- CV462 1uf 0.1uf Under
AG4
1 2 1/10W_0_+-5%_0603 +IFPCD_PLLVDD AF7 TXC IFPC_L3* AG5 HDMI1_TXC+ HDMI1_TXC- 42
LV4
IFPCD_PLLVDD TXC IFPC_L3 HDMI1_TXC+ 42 HDMI CLK CV484 1uf 0.1uf Under
OPT@
AH4 HDMI1_TX0-
1 TXD0 IFPC_L2* HDMI1_TX0+ HDMI1_TX0- 42
OPT@ AH3 HDMI D0
TXD0 IFPC_L2 HDMI1_TX0+ 42 GPU_EDP_AUX#
CV222 For HDMI RV1293 1 OPT@ 2 100K_0402_5%
1U_6.3V_M_X5R_0201 IFPC TXD1 IFPC_L1*
AJ2 HDMI1_TX1-
HDMI1_TX1+ HDMI1_TX1- 42
N18P-FCBGA960_BGA960
GPU_EDP_AUX
2 AJ3 RV1294 1 OPT@ 2 100K_0402_5%
TXD1 IFPC_L1 HDMI1_TX1+ 42 HDMI D1 @
AJ1 HDMI1_TX2-
TXD2 IFPC_L0* HDMI1_TX2+ HDMI1_TX2- 42
+1.0VGS AK1
TXD2 IFPC_L0 HDMI1_TX2+ 42 HDMI D2
LV5 1 OPT@ 2 1/10W_0_+-5%_0603 +IFPC_IOVDD AF6
IFP_IOVDD_3
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

B B
1U_6.3V_K_X5R_0201

AG6
4.7U_0603_6.3V6K

IFP_IOVDD_4
1 1 1 1 1
OPT@

OPT@

OPT@

2 2 2 2 2 N18P-FCBGA960_BGA960
CV459

CV223

CV68
OPT@
CV227

CV1174

ADD HDMI Port @


@

Change HDMI PORT to IFPC follow Y550 wei 7/30

near GPU under GPU

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_(3/6):VRAM I/F


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y550 1.0

Date: Monday, February 24, 2020 Sheet 26 of 83


5 4 3 2 1
5 4 3 2 1

UV1C
3/17 FBB
UV1B
2/17 FBA
33,34 FBB_D[0..63]
+FB_PLLAVDD
FBB_D0 G9
31,32 FBA_D[0..63] FBB_D1 FBB_D0 FBB_CMD[0..33] 33,34
E9
D FBA_D0 L28 K27 FBB_D2 G8 FBB_D1 D13 FBB_CMD0 D

1U_6.3V_M_X5R_0201
FBA_D1 M29 FBA_D0 FB_REFPLL_AVDD FBB_D3 F9 FBB_D2 FBB_CMD0 E14 FBB_CMD1
FBA_D2 L29 FBA_D1 FBB_D4 F11 FBB_D3 FBB_CMD1 F14 FBB_CMD2
FBA_D3 FBA_D2 1 FBB_D5 FBB_D4 FBB_CMD2 FBB_CMD3
M28 G11 A12
FBA_D4 N31 FBA_D3 FBB_D6 F12 FBB_D5 FBB_CMD3 B12 FBB_CMD4
FBA_D5 FBA_D4 FBB_D7 FBB_D6 FBB_CMD4 FBB_CMD5

OPT@
P29 G12 C14
FBA_D6 R29 FBA_D5 2 FBB_D8 G6 FBB_D7 FBB_CMD5 B14 FBB_CMD6
FBA_D6 FBB_D8 FBB_CMD6

CV64
FBA_D7 P28 Under GPU FBB_D9 F5 G15 FBB_CMD7
FBA_D8 J28 FBA_D7 FBB_D10 E6 FBB_D9 FBB_CMD7 F15 FBB_CMD8
FBA_D9 FBA_D8 FBA_CMD[0..33] 31,32 FBB_D11 FBB_D10 FBB_CMD8 FBB_CMD9
H29 F6 E15
FBA_D10 J29 FBA_D9 U30 FBA_CMD0 FBB_D12 F4 FBB_D11 FBB_CMD9 D15 FBB_CMD10
FBA_D11 H28 FBA_D10 FBA_CMD0 T31 FBA_CMD1 FBB_D13 G4 FBB_D12 FBB_CMD10 A14 FBB_CMD11
FBA_D12 G29 FBA_D11 FBA_CMD1 U29 FBA_CMD2 FBB_D14 E2 FBB_D13 FBB_CMD11 D14 FBB_CMD12
FBA_D13 E31 FBA_D12 FBA_CMD2 R34 FBA_CMD3 FBB_D15 F3 FBB_D14 FBB_CMD12 A15 FBB_CMD13
FBA_D14 E32 FBA_D13 FBA_CMD3 R33 FBA_CMD4 FBB_D16 C2 FBB_D15 FBB_CMD13 B15 FBB_CMD14
FBA_D15 F30 FBA_D14 FBA_CMD4 U32 FBA_CMD5 FBB_D17 D4 FBB_D16 FBB_CMD14 C17 FBB_CMD15
FBA_D16 C34 FBA_D15 FBA_CMD5 U33 FBA_CMD6 FBB_D18 D3 FBB_D17 FBB_CMD15 D18 FBB_CMD16
FBA_D17 D32 FBA_D16 FBA_CMD6 U28 FBA_CMD7 FBB_D19 C1 FBB_D18 FBB_CMD16 E18 FBB_CMD17
FBA_D18 B33 FBA_D17 FBA_CMD7 V28 FBA_CMD8 GDDR6 CMD Mapping FBB_D20 B3 FBB_D19 FBB_CMD17 F18 FBB_CMD18
x16 Mode
FBA_D19 C33 FBA_D18 FBA_CMD8 V29 FBA_CMD9 FBB_D21 C4 FBB_D20 FBB_CMD18 A20 FBB_CMD19
Lower 0..31 Upper 32..63
FBA_D20 F33 FBA_D19 FBA_CMD9 V30 FBA_CMD10 FBB_D22 B5 FBB_D21 FBB_CMD19 B20 FBB_CMD20
DRAM1 DRAM2
FBA_D21 F32 FBA_D20 FBA_CMD10 U34 FBA_CMD11 FBB_D23 C5 FBB_D22 FBB_CMD20 C18 FBB_CMD21
CHA-Byte 0,1 CHA-Byte 4,5
FBA_D22 H33 FBA_D21 FBA_CMD11 U31 FBA_CMD12 FBB_D24 A11 FBB_D23 FBB_CMD21 B18 FBB_CMD22
FBA_D23 H32 FBA_D22 FBA_CMD12 V34 FBA_CMD13 FBB_D25 C11 FBB_D24 FBB_CMD22 G18 FBB_CMD23
CA0_A CMD0 CMD20
FBA_D24 P34 FBA_D23 FBA_CMD13 V33 FBA_CMD14 FBB_D26 D11 FBB_D25 FBB_CMD23 G17 FBB_CMD24
CA1_A CMD9 CMD28
FBA_D25 P32 FBA_D24 FBA_CMD14 Y32 FBA_CMD15 FBB_D27 B11 FBB_D26 FBB_CMD24 F17 FBB_CMD25
CA2_A CMD8 CMD21
FBA_D26 P31 FBA_D25 FBA_CMD15 AA31 FBA_CMD16 FBB_D28 D8 FBB_D27 FBB_CMD25 D16 FBB_CMD26
CA3_A CMD32 CMD29
FBA_D27 P33 FBA_D26 FBA_CMD16 AA29 FBA_CMD17 FBB_D29 A8 FBB_D28 FBB_CMD26 A18 FBB_CMD27
CA4_A CMD7 CMD23
FBA_D28 L31 FBA_D27 FBA_CMD17 AA28 FBA_CMD18 FBB_D30 C8 FBB_D29 FBB_CMD27 D17 FBB_CMD28
CA5_A CMD11 CMD27
FBA_D29 L34 FBA_D28 FBA_CMD18 AC34 FBA_CMD19 FBB_D31 B8 FBB_D30 FBB_CMD28 A17 FBB_CMD29
CA6_A CMD15 CMD30
FBA_D30 L32 FBA_D29 FBA_CMD19 AC33 FBA_CMD20 FBB_D32 F24 FBB_D31 FBB_CMD29 B17 FBB_CMD30
CA7_A CMD14 CMD31
FBA_D31 L33 FBA_D30 FBA_CMD20 AA32 FBA_CMD21 FBB_D33 G23 FBB_D32 FBB_CMD30 E17 FBB_CMD31
CA8_A CMD3 CMD19
FBA_D32 AG28 FBA_D31 FBA_CMD21 AA33 FBA_CMD22 FBB_D34 E24 FBB_D33 FBB_CMD31 G14 FBB_CMD32
CA9_A CMD1 CMD17
FBA_D33 AF29 FBA_D32 FBA_CMD22 Y28 FBA_CMD23 FBB_D35 G24 FBB_D34 FBB_CMD32 G20 FBB_CMD33
CABI_A CMD6 CMD22
FBA_D34 AG29 FBA_D33 FBA_CMD23 Y29 FBA_CMD24 FBB_D36 D21 FBB_D35 FBB_CMD33 C12 FBB_DEBUG0 1 @ 2
CKE_A CMD10 CMD26 FBVDDQ
FBA_D35 AF28 FBA_D34 FBA_CMD24 W31 FBA_CMD25 FBB_D37 E21 FBB_D36 FBB_CMD34 C20 RV121
FBA_D36 AD30 FBA_D35 FBA_CMD25 Y30 FBA_CMD26 FBB_D38 G21 FBB_D37 FBB_CMD35 60.4_0402_1%
CHB-Byte 2,3 CHB-Byte 6,7
FBA_D37 AD29 FBA_D36 FBA_CMD26 AA34 FBA_CMD27 FBB_D39 F21 FBB_D38 FBB_DEBUG1 1 @ 2
CA0_B CMD4 CMD16
FBA_D38 AC29 FBA_D37 FBA_CMD27 Y31 FBA_CMD28 CA1_B CMD12 CMD25
FBB_D40 G27 FBB_D39 RV122 1.55V
C
FBA_D39 AD28 FBA_D38 FBA_CMD28 Y34 FBA_CMD29 FBB_D41 D27 FBB_D40 60.4_0402_1% C
CA2_B CMD5 CMD24
FBA_D40 AJ29 FBA_D39 FBA_CMD29 Y33 FBA_CMD30 FBB_D42 G26 FBB_D41 D12
CA3_B CMD13 CMD33
FBA_D41 AK29 FBA_D40 FBA_CMD30 V31 FBA_CMD31 FBB_D43 E27 FBB_D42 FBB_CLK0 E12 FBB_CLK0 33
CA4_B CMD7 CMD23
FBA_D42 AJ30 FBA_D41 FBA_CMD31 R28 FBA_CMD32 FBB_D44 E29 FBB_D43 FBB_CLK0* E20 FBB_CLK0# 33
CA5_B CMD11 CMD27
FBA_D43 AK28 FBA_D42 FBA_CMD32 AC28 FBA_CMD33 FBB_D45 F29 FBB_D44 FBB_CLK1 F20 FBB_CLK1 34
CA6_B CMD15 CMD30
FBA_D44 AM29 FBA_D43 FBA_CMD33 R32 FBA_DEBUG0 1 2 FBB_D46 E30 FBB_D45 FBB_CLK1* FBB_CLK1# 34
@ FBVDDQ 1.55V CA7_B CMD14 CMD31
FBA_D45 AM31 FBA_D44 FBA_CMD34 AC32 RV119 FBB_D47 D30 FBB_D46
CA8_B CMD3 CMD19
FBA_D46 FBA_D45 FBA_CMD35 FBA_DEBUG1 FBB_D48 FBB_D47
AN29 60.4_0402_1% CA9_B CMD1 CMD17 A32
FBA_D47 AM30 FBA_D46 1 @ 2 FBB_D49 C31 FBB_D48
CABI_B CMD6 CMD22
FBA_D48 AN31 FBA_D47 RV120 FBB_D50 C32 FBB_D49 F8 FBB_WCK01
CKE_B CMD10 CMD26
FBA_D49 AN32 FBA_D48 60.4_0402_1% FBB_D51 B32 FBB_D50 FBB_WCK01 E8 FBB_WCK01_N FBB_WCK01 33
FBA_D50 AP30 FBA_D49 FBB_D52 D29 FBB_D51 FBB_WCK01* A5 FBB_WCK23 FBB_WCK01_N 33
RESET* CMD2 CMD18
FBA_D51 AP32 FBA_D50 R30 FBA_CLK0 FBB_D53 A29 FBB_D52 FBB_WCK23 A6 FBB_WCK23_N FBB_WCK23 33
FBA_D52 AM33 FBA_D51 FBA_CLK0 R31 FBA_CLK0# FBA_CLK0 31 FBB_D54 C29 FBB_D53 FBB_WCK23* D24 FBB_WCK45 FBB_WCK23_N 33
FBA_D53 AL31 FBA_D52 FBA_CLK0* AB31 FBA_CLK1 FBA_CLK0# 31 FBB_D55 B29 FBB_D54 FBB_WCK45 D25 FBB_WCK45_N FBB_WCK45 34
FBA_D54 AK33 FBA_D53 FBA_CLK1 AC31 FBA_CLK1# FBA_CLK1 32 FBB_D56 B21 FBB_D55 FBB_WCK45* B27 FBB_WCK67 FBB_WCK45_N 34
FBA_D55 AK32 FBA_D54 FBA_CLK1* FBA_CLK1# 32 FBB_D57 C23 FBB_D56 FBB_WCK67 C27 FBB_WCK67_N FBB_WCK67 34
FBA_D56 AD34 FBA_D55 FBB_D58 A21 FBB_D57 FBB_WCK67* FBB_WCK67_N 34
FBA_D57 AD32 FBA_D56 FBB_D59 C21 FBB_D58
FBA_D58 AC30 FBA_D57 FBB_D60 B24 FBB_D59
FBA_D59 AD33 FBA_D58 FBB_D61 C24 FBB_D60
FBA_D60 AF31 FBA_D59 FBB_D62 B26 FBB_D61 D6 FBB_WCKB01
FBA_D61 AG34 FBA_D60 FBB_D63 C26 FBB_D62 FBB_WCKB01 D7 FBB_WCKB01_N FBB_WCKB01 33
FBA_D62 AG32 FBA_D61 FBB_D63 FBB_WCKB01* C6 FBB_WCKB23 FBB_WCKB01_N 33
FBA_D63 AG33 FBA_D62 FBB_WCKB23 B6 FBB_WCKB23_N FBB_WCKB23 33
FBA_D63 K31 FBA_WCK01 FBB_DBI0# E11 FBB_WCKB23* F26 FBB_WCKB45 FBB_WCKB23_N 33
FBA_WCK01 L30 FBA_WCK01_N FBA_WCK01 31 33 FBB_DBI0# FBB_DBI1# E3 FBB_DQM0 FBB_WCKB45 E26 FBB_WCKB45_N FBB_WCKB45 34
FBA_DBI0# P30 FBA_WCK01* H34 FBA_WCK23 FBA_WCK01_N 31 33 FBB_DBI1# FBB_DBI2# A3 FBB_DQM1 FBB_WCKB45* A26 FBB_WCKB67 FBB_WCKB45_N 34
31 FBA_DBI0# FBA_DBI1# F31 FBA_DQM0 FBA_WCK23 J34 FBA_WCK23_N FBA_WCK23 31 33 FBB_DBI2# FBB_DBI3# C9 FBB_DQM2 FBB_WCKB67 A27 FBB_WCKB67_N FBB_WCKB67 34
31 FBA_DBI1# FBA_DBI2# F34 FBA_DQM1 FBA_WCK23* AG30 FBA_WCK45 FBA_WCK23_N 31 33 FBB_DBI3# FBB_DBI4# F23 FBB_DQM3 FBB_WCKB67* FBB_WCKB67_N 34
31 FBA_DBI2# FBA_DBI3# M32 FBA_DQM2 FBA_WCK45 AG31 FBA_WCK45_N FBA_WCK45 32 34 FBB_DBI4# FBB_DBI5# F27 FBB_DQM4
31 FBA_DBI3# FBA_DBI4# AD31 FBA_DQM3 FBA_WCK45* AJ34 FBA_WCK67 FBA_WCK45_N 32 34 FBB_DBI5# FBB_DBI6# C30 FBB_DQM5
32 FBA_DBI4# FBA_DBI5# AL29 FBA_DQM4 FBA_WCK67 AK34 FBA_WCK67_N FBA_WCK67 32 34 FBB_DBI6# FBB_DBI7# A24 FBB_DQM6
32 FBA_DBI5# FBA_DBI6# AM32 FBA_DQM5 FBA_WCK67* FBA_WCK67_N 32 34 FBB_DBI7# FBB_DQM7
32 FBA_DBI6# FBA_DBI7# AF34 FBA_DQM6 +FB_PLLAVDD
32 FBA_DBI7# FBA_DQM7 FBB_EDC0 D10
33 FBB_EDC0 FBB_EDC1 D5 FBB_DQS_WP0
FBA_EDC0 M31 33 FBB_EDC1 FBB_EDC2 C3 FBB_DQS_WP1
31 FBA_EDC0 FBA_EDC1 G31 FBA_DQS_WP0 J30 FBA_WCKB01 33 FBB_EDC2 FBB_EDC3 B9 FBB_DQS_WP2 H17 +FB_PLLAVDD
31 FBA_EDC1 FBA_EDC2 E33 FBA_DQS_WP1 FBA_WCKB01 J31 FBA_WCKB01_N FBA_WCKB01 31 33 FBB_EDC3 FBB_EDC4 E23 FBB_DQS_WP3 FBB_PLL_AVDD

1U_6.3V_M_X5R_0201
B 31 FBA_EDC2 FBA_EDC3 M33 FBA_DQS_WP2 FBA_WCKB01* J32 FBA_WCKB23 FBA_WCKB01_N 31 34 FBB_EDC4 FBB_EDC5 E28 FBB_DQS_WP4 B
31 FBA_EDC3 FBA_EDC4 AE31 FBA_DQS_WP3 FBA_WCKB23 J33 FBA_WCKB23_N FBA_WCKB23 31 34 FBB_EDC5 FBB_EDC6 B30 FBB_DQS_WP5
32 FBA_EDC4 FBA_EDC5 AK30 FBA_DQS_WP4 FBA_WCKB23* AH31 FBA_WCKB45 FBA_WCKB23_N 31 34 FBB_EDC6 FBB_EDC7 A23 FBB_DQS_WP6 1
32 FBA_EDC5 FBA_EDC6 AN33 FBA_DQS_WP5 FBA_WCKB45 AJ31 FBA_WCKB45_N FBA_WCKB45 32 34 FBB_EDC7 FBB_DQS_WP7
32 FBA_EDC6 FBA_EDC7 AF33 FBA_DQS_WP6 FBA_WCKB45* AJ32 FBA_WCKB67 FBA_WCKB45_N 32

OPT@
32 FBA_EDC7 FBA_DQS_WP7 FBA_WCKB67 AJ33 FBA_WCKB67_N FBA_WCKB67 32
FBA_WCKB67* FBA_WCKB67_N 32 2

CV1161
N18P-FCBGA960_BGA960
@

Under GPU

+FB_PLLAVDD

U27
FBA_PLL_AVDD
1U_6.3V_M_X5R_0201

1 FBVDDQ FBVDDQ
H31
FB_VREF
OPT@

2
2

1
OPT@ N18P-FCBGA960_BGA960 CKE_A CKE_A
CV1160

1
RC702 @ RV1286 RV1287 RV1288 RV1289
CV1522 1/20W_49.9_1%_0201 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%
3.9P_50V_B_NPO_0402 OPT@ OPT@ OPT@ OPT@
2
1

2
FBA_CMD7 FBB_CMD7
Under GPU FBA_CMD33 FBB_CMD33

FBA_CMD2 FBB_CMD2
FBA_CMD18 FBB_CMD18
+FB_PLLAVDD

A A
30ohms (ESR=0.01) Bead

1
P/N;SM01000M300 RESET RV76 RV80 RESET RV87 RV88
N18 change
22U_0603_6.3V6-M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

+1.8VS_VGA +FB_PLLAVDD 1 1 1 10K_0402_1% 10K_0402_1% 10K_0402_1% 10K_0402_1%


2 OPT@ OPT@ OPT@ OPT@

2
+FB_PLLAVDD
2 2 2
1 2
OPT@

OPT@

OPT@
CV475

CV474

CV562

LV7
HCB1608KF-300T60_2P
OPT@ Title
Security Classification LC Future Center Secret Data
Place close to BGA Near GPU Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_(3/6):VRAM I/F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y550 1.0

Date: Monday, February 24, 2020 Sheet 27 of 83


5 4 3 2 1
5 4 3 2 1

+1.8VS_AON

2
UV1P RV197 RV1202 RV199
12/17 MISC2 +1.8VS_AON +1.8VS_AON 100K_0402_5% 10K_0402_1% 100K_0402_5%
@ @ @ 1:ENABLE 0:DISABLE
SOR0 DISABLE

1
SOR1/2/3 ENABLE

2
H6 ROM_CS# ROM_SI
ROM_CS* RV1105 GPU ROM_SO ROM_SI ROM_SCLK SOR_EXPOSED[3:0]
ROM_SI 1 1 ROM_SO
H5 10K_0402_5% CV465 CV464
ROM_SI H7 ROM_SO OPT@ 10U 6.3V M X5R 0402 .1U_0402_10V6-K
STRAP0 J2 ROM_SO H4 ROM_SCLK OPT@ ROM_SCLK N17P L L H 1110
@ OPT@

1
STRAP1 J7 STRAP0 ROM_SCLK UV3 2 2
STRAP2 J6 STRAP1 ROM_CS# RV1102 2 OPT@ 1 33_0402_5% ROM_CS#_R 1 8
STRAP3 J5 STRAP2 ROM_SO RV1101 2 1@ 0_0402_5% ROM_SO_R 2 CS# VCC 7 N18P L L L ENABLE

2
@ STRAP4 J3 STRAP3 3 DO HOLD# 6 ROM_SCLK_R RV1103 2 OPT@ 1 33_0402_5% ROM_SCLK
STRAP5 RV17 1 MULTI_STRAP
2 0_0402_5% J1 STRAP4 4 WP# CLK 5 ROM_SI_R RV1104 2 OPT@ 1 33_0402_5% ROM_SI RV200 RV1203 RV202
STRAP5 GND DI 100K_0402_5% 10K_0402_1% 100K_0402_5%
1

W25Q80EWSNIG_SO8 OPT@ OPT@ OPT@


RV16

1
40.2K_0402_1% E1
@ BUFRST*

1
NV RVL
2

RV203
N18P-FCBGA960_BGA960 10K_0402_5%
@ @ SPI ROM need doublecheck

2
change to SA00009RB00_0928SF
D D

+1.8VS_AON

+1.8VS_AON
I2CB_SCL RV22 1 OPT@ 2 2.2K_0402_5%
+1.8VS_AON I2CB_SDA RV25 1 OPT@ 2 2.2K_0402_5%

2
1V8_MAIN_EN RV27 2 OPT@ 1 10K_0402_5%
RV1201 1 2 0_0402_5%
RV187 RV188 RV189

+1.8VS_AON NVVDD_PSI RV28 1 @ 2 10K_0402_5%


100K_0402_5%
X76@
100K_0402_5%
X76@
100K_0402_5%
X76@
VRAMCFG

1
1 VGA_ALERT# RV23 1 OPT@ 2
OPT@
10K_0402_5% GPU VRAM FB Memory (GDDR6) RAMCFG[4:0] STRAP2 STRAP1 STRAP0
UV1O
CV1185 VGA_AC_DET_R
10/17 MISC1 RV26 1 OPT@ 2 100K_0402_5% STRAP2
2

1U_0402_6.3V6K
2 ADC_MUX_SEL Samsung 8Gb K4Z80325BC-HC14 0(0x0000) L L L
RV214 RV3811 OPT@ 2 10K_0402_5% STRAP1 4GB
100K_0402_5%
T4 VGA_SMB_CK2 STRAP0
OPT@
I2CS_SCL VGA_SMB_DA2 Micron 8Gb MT61K256M32JE-14:A 1(0x0001) L L H
AG10 T3 Internal Thermal Sensor
1

TS_AVDD I2CS_SDA

2
OVERT# M1 R2 I2CC_SCL
25 OVERT# OVERT I2CC_SCL I2CC_SDA MEM_VREF
R3 RV32 2 OPT@ 1 100K_0402_5% RV192 RV193 RV194
TV5 @ 1 AP9 I2CC_SDA 100K_0402_5% 100K_0402_5% 100K_0402_5%
TS_VREF R7 I2CB_SCL NB_FGC6 RV7582 OPT@ 1 10K_0402_5% X76@ X76@ X76@
K4 I2CB_SCL R6 I2CB_SDA

1
THERMDN I2CB_SDA GPU_EDP_ENBKL RV1305 1 OPT@ 2 100K_0201_5%
K3
THERMDP GPU_EDP_PWM RV1306 1 OPT@ 2 100K_0201_5%
P6 NVVDD_PWM_VID
GPIO0 M3 FB_GC6_EN NVVDD_PWM_VID 79 GPU_EDP_ENVDD RV1307 1 OPT@ 2 10K_0201_5%
TV1 @ 1 AM10 GPIO1 L6 GPU_EVENT#
TV2 @ 1 AP11 JTAG_TCK GPIO2 P5 删删GPU_MUX_CNTL
TV3 @ 1 AM11 JTAG_TMS GPIO3 P7 1V8_MAIN_EN
RV37 TV4 @ 1 AP12 JTAG_TDI GPIO4 L7 GPU_FRAME_LOCK# GPU_FRAME_LOCK# 41
OPT@1 2 10K_0402_5% JTAG_TRST AN11 JTAG_TDO GPIO5 M7 NVVDD_PSI_GPU RV107 1 2 0_0402_5%
NVJTAG_SEL AK11 JTAG_TRST* GPIO6 N8 GPU_EDP_PWM NVVDD_PSI 79
RV24 1 2 10K_0402_5% @
NVJTAG_SEL GPIO7 L3 VRAM_VDDQ_ADJ GPU_EDP_PWM 39
OPT@
GPIO8 M2 VGA_ALERT# VRAM_VDDQ_ADJ 76
@
RV1228 1 2 0_0402_5% ADC_IN_P_GPU AN9 GPIO9 L1 MEM_VREF
80 ADC_IN_P ADC_IN GPIO10 MEM_VREF 31,33
@ M5 GPU_EDP_ENVDD
2 0_0402_5% ADC_IN_N_GPU AM9 GPIO11 N3 VGA_AC_DET_R GPU_EDP_ENVDD 39
RV1229 1 +1.8VS_AON
80 ADC_IN_N ADC_IN* GPIO12 M4 删删iGPU_EDP_ENBKL
GPIO13 N4 IFPA_HPD VGA_DEVICE
GPIO14 P2 IFPA_HPD 44
GPIO15 R8
GPIO16 M6 GPU_EDP_HPD STRAP5 STRAP4 STRAP3 SMB_ALT_ADDR DEVID_SEL PCIE_CFG VGA_DEVICE
GPU_EDP_HPD 39 1

2
GPIO17 R1 IFPE_HPD PAD @ TV16 port swap, HDMI change to C port
GPIO18 P3 del E-port HPD GPIO +1.8VS_AON
RV19 RV21 RV74 L L H 0 0 0 1
GPIO19 P4 NB_FGC6 yong 07/12 100K_0402_5% 100K_0402_5% 100K_0402_5%
GPIO20 P1 GPU_EDP_ENBKL OPT@ @ @
GPIO21 P8 ADC_MUX_SEL_R GPU_EDP_ENBKL 39 VRAM_VDDQ_ADJ 2
RV1239 1 2@ 0_0402_5% @ 1 10K_0402_5%
ADC_MUX_SEL 80

1
GPIO22 T8 GPU_PEX_RST_HOLD#_R @ 1 RV41
GPIO23 L2 PAD 1: SMB_ALT_ADDR ENABLE
TV14 STRAP5
GPIO24 R4 FBVDDQ_PSI @ 1 OPT@2 1 10K_0402_5%
GPIO25 R5 GPIO26_FP_FUSE PAD 0: SMB_ALT_ADDR DISABLE
TV15 RV43 STRAP4
GPIO26 U3 IFPC_HPD GPIO26_FP_FUSE 29
GPIO27 IFPC_HPD 42 STRAP3 1: DEVID_SEL REBRAND
N18P-FCBGA960_BGA960
@ VGA_ALERT# 8 0: DEVID_SEL ORIGNAL

2
@
VGA_ALERT# 2 1 RV78 RV75 RV77 1: PCIE_CFG LOW POWER
DV6 RB751V-40_SOD323-2 100K_0402_5% 100K_0402_5% 100K_0402_5%
@ OPT@ OPT@ 0: PCIE_CFG HIGH POWER
VGA_AC_DET_R OPT@2 1
VGA_AC_DET 52

1
DV1 RB751V-40_SOD323-2
1: VGA_DEVICE ENABLE
0: VGA_DEVICE DISABLE

+1.8VS_AON
+1.8VS_AON +3VS
C C

+3VS
2
2

RV1208 +3VALW RV12


RV1209 2.2K_0402_5% RV1212 RV1213 10K_0402_5% RV51 1 2 0_0402_5%
PCH_FB_GC6_EN 8
2.2K_0402_5% OPT@ 2.2K_0402_5% 2.2K_0402_5% OPT@ OPT@
5

OPT@ OPT@ OPT@


1

RV57
G2
1

10K_0402_5%
I2CC_SCL FB_GC6_EN_R
4
S2 D2
3
NVDD_SCL 79
OPT@
DG Power on/off sequence discharger circuit
1

QV35B D
PJT7838_SOT363-6 5 QV7B @
DV10 +1.8VS_VGA +3VS
OPT@ G LBSS138DW1T1G_SOT363-6 OVERT#_NVEN 1 2
2 1 S OPT@ 25 OVERT#_NVEN
4

RV1211
2

RB751V-40_SOD323-2
0_0402_5%

1
6

@ D
G1

FB_GC6_EN 2 RV13 RV334


QV7A
I2CC_SDA 1 6 OPT@ 0_0402_5% 10K_0402_1%
G LBSS138DW1T1G_SOT363-6
S1 D1 NVDD_SDA 79 DV9 @
OPT@
1

S
1

Vgs(th)≤1.0V

2
RV313 PXS_PWREN RV2201 2 0_0402_5% 3
QV35A 8,62 PXS_PWREN 1 OPT@
10K_0402_5% OPT@
PJT7838_SOT363-6 1V8_MAIN_EN_R 2 NVVDD_EN 29,79
OPT@
OPT@
2

1
2 1 BAT54AW_SOT323-3
RV335
RV1210 RV55 1 @ 2 0_0402_5%
1 @ 2 0_0402_5% 100K_0402_1%
0_0402_5%
RV333 @
@

2
+1.8VS_AON +3VS
+1.8VS_AON

PLT_RST_VGA#

1
2
2

PXS_PWREN 1 2 RV331
For Optimus Power OFF OPT@
2

RV89 8.2K_0402_1%
RV1241 RV1138 RV1240
RV1136 DV8 10K_0402_5% OPT@
10K_0402_5% 0_0402_5% 0_0402_5% RB751V-40_SOD323-2
+1.8VS_AON 10K_0402_5% @
@ OPT@ OPT@

2
@ 1V8_MAIN_EN_R RV11351 2 0_0402_5%
DV7

1
1

OPT@
1

1V8_MAIN_EN RV1134 1 @ 2 0_0402_5%2


For GC6 Power OFF 1 RV982 1
NVVDD_PWRGD 3 1V0_MAIN_EN 30
OPT@ 0_0402_5%
For Power ON 79 NVVDD_PWRGD

1
2

+1.8VS_AON
+1.8VS_AON +3VS
RV5 RV6 1 OPT@ 2 BAT54AW_SOT323-3
+3VS RV4 RV330
2.2K_0402_5% 2.2K_0402_5% OPT@
5

10K_0402_5% 10K_0402_1% +3VS


OPT@ OPT@
2

OPT@
1

2
G2
1

OPT@
VGA_SMB_CK2 4 3 RV319 RV59
1

EC_SMB_CK2 7,52,59,60

2
S2 D2 10K_0402_5% 0_0402_5% +3VALW RV1129
OPT@ RV320
10K_0402_5%
1

QV3B 10K_0402_5% OPT@


2

OPT@
PJT7838_SOT363-6
2

2
OPT@ RV1132
2

1
10K_0402_5%
2 @ 1 OPT@ 1V8_MAIN_EN_R
GPU_EVENT# 3 1 GPU_EVENT#_R RV3181 2 0_0402_5%
2

1V8_MAIN_EN_R 29
RV1238 PCH_GPU_EVENT# 8
OPT@
0_0402_5%
G1

3
D
VGA_SMB_DA2 1 6 QV8 5 QV32B
S1 D1 EC_SMB_DA2 7,52,59,60 LSI1012XT1G_SC-89-3
For GC6 20180827 ref Y540 change0927SF G LBSS138DW1T1G_SOT363-6
Vgs(th)≤1.0V Vgs(th)≤0.9V S OPT@

4
QV3A PU AT EC SIDE, +3VS AND 4.7K
PJT7838_SOT363-6

6
OPT@ RV3171 @ 2 0_0402_5% D
1V8_MAIN_EN 2 QV32A
2 @ 1 G LBSS138DW1T1G_SOT363-6
B RV1235 UV12 OPT@ B
S

1
0_0402_5% FB_GC6_EN_R RV110 1 OPT@ 2 0_0402_5% 1 4 FBVDDQ_PWR_EN
1.0VGS_PG 1 2 0_0402_5% 2 IN B OUT Y FBVDDQ_PWR_EN 30,76
RV325 RV1133
IN A 10K_0402_5%
NVVDD_PWRGD 1 2 3 5 RV1218 1 OPT@ 2 0_0402_5% @
GND Vcc +3VS
RV1123 10K_0402_5%

0.1U_0402_25V6

2
@
MC74VHC1G32DFT2G_SC70-5 1
follow 330G-ICH NV review result SF0926
1

@ CV1189
CV458

.1U_0402_10V6-K
2

2 OPT@

+3VS

1V8_MAIN_EN 1
RV1231 @ 2 0_0402_5% 1V8_MAIN_EN_R
1

RV38
0_0402_5%
OPT@
2

+3VS

1 +1.8VS_AON

CV58
2

.1U_0402_10V6-K
2

2 BAT54AW RV104
OPT@ VF=0.32V @ IF=1mA 10K_0402_5%
RV50
DV3 OPT@
10K_0402_5%
OPT@ RV49 2 1 0_0402_5% 2
1
5

76 FBVDDQ_PWROK 1
UV2 OPT@
1

PLT_RST# 1 VGA_PWRGD 8,25


RV64 2 1 0_0402_5% 3
P

8,46,47,55,56 PLT_RST# B VGA_RST# PLT_RST_VGA# 77 1.0VGS_PG


4 RV44 1 OPT@ 2 0_0402_5% OPT@
2 Y PLT_RST_VGA# 25
G

8 PXS_RST# A BAT54AW_SOT323-3
MC74VHC1G09DFT2G_SC70-5 OPT@
3

OPT@
1

1
CC171 RV324
1000P_0402_50V7K RV217 100K_0402_5%
100K_0402_5% OPT@
2 OPT@
OPT@
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_(4/6):GPIO


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y550 1.0

Date: Monday, February 24, 2020 Sheet 28 of 83


5 4 3 2 1
5 4 3 2 1

1.8V Total 1A (AON+MAIN)


5A Peak 8A 0.5A +1.8VS_AON
FBVDDQ
Cost down list: UV1H UV1I
1U 4Pcs for N18P reserve 0928sf 14/17 FBVDDQ 17/17 1V8_AON
+1.8VS_AON

Partition A Under GPU(below 150mils) AA27


AA30 FBVDDQ_01
under GPU near GPU

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
AB27 FBVDDQ_02 J8

CV99
CV112

CV113

CV100

CV101

CV102

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
AB33 FBVDDQ_03 1V8_AON_1 K8
1 1 1 1 1 1 1 1 1 1 1 1 FBVDDQ_04 1V8_AON_2
AC27 1 1 1 1 1 1 1 1 2 1 1 1 1

1U_0603_10V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AD27 FBVDDQ_05 AG12
FBVDDQ_06 FP_FUSE_SRC

OPT@

OPT@

OPT@
@ @ OPT@ @ @ @ AE27
OPT@
CV114

CV103

2 2 2 2 2 2 2 2 2 2 2 2 FBVDDQ_07

OPT@

OPT@
AF27
FBVDDQ_08 2 2 2 2 2 2 2 2 1 2 2 @ 2 @ 2
CV104

CV105

CV106

CV115
AG27

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
@
FBVDDQ_09

CV205

CV206
@ @ B13 @ @

CV203

CV207

CV211

CV204

CV208

CV213
CV1475

CV1476

CV1477

CV1478

CV1479
D D
B16 FBVDDQ_10
B19 FBVDDQ_11
E13 FBVDDQ_12
E16 FBVDDQ_13
Partition B Under GPU(below 150mils) FBVDDQ_14
E19
H10 FBVDDQ_15
1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201

1U_6.3V_M_X5R_0201
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
H11 FBVDDQ_16

CV1486

CV1487

CV1488

CV1489

CV1490

CV1491
H12 FBVDDQ_17
1 1 1 1 1 1 1 1 1 1 1 1 FBVDDQ_18
H13 N18P-FCBGA960_BGA960
H14 FBVDDQ_19
FBVDDQ_20 @ 1.8VS_AON Decouling Value
OPT@

OPT@

OPT@

OPT@ @ @ @ OPT@ @ @ H15


CV873

CV862

2 2 2 2 2 2 2 2 2 2 2 2 H16 FBVDDQ_21
FBVDDQ_22
CV863

CV864

CV868

CV865

H18
@ @ H19 FBVDDQ_23 FP_FUSE_GPU MLCC N18 N17 location
H20 FBVDDQ_24
H21 FBVDDQ_25 1 CV205 1uf 0.1uf Under

1
H22 FBVDDQ_26
FBVDDQ FBVDDQ_27 RV1200 CV1104
H23
1/16W_2.21K_1%_0402
H24 FBVDDQ_28
FBVDDQ_29 OPT@
2.2U_0402_6.3V6M
OPT@ 2 CV206 1uf 0.1uf Under
Under GPU(below 150mils) H8
H9 FBVDDQ_30

2
FBVDDQ_31
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
2 2 2 2 L27
M27 FBVDDQ_32 CV1475 @ @ Under
N27 FBVDDQ_33
P27 FBVDDQ_34
1 1 1 1 R27 FBVDDQ_35
OPT@

OPT@

OPT@
@
T27 FBVDDQ_36 CV1476 @ @ Under
CALIBRATION PIN N17P N18P
CV94

CV86

CV87

CV88
T30 FBVDDQ_37
T33 FBVDDQ_38
FBVDDQ V27 FBVDDQ_39
Near GPU W27 FBVDDQ_40 FB_CAL_x_PD_VDDQ 40.2Ohm 40.2Ohm
W30 FBVDDQ_41 RV94 40.2ohm 60.4ohm
W33 FBVDDQ_42
Near GPU FBVDDQ_43 FB_CAL_x_PU_GND 40.2Ohm 40.2Ohm
Y27
FBVDDQ_44
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
10U_0603_6.3V6M

10U_0603_6.3V6M

2 2 1 1 1 1 1
1 1 FB_CAL_xTERM_GND 60.4Ohm 40.2Ohm only for N18P
33P_0402_50V8J

33P_0402_50V8J

OPT@

1 1 2 OPT@ 2 CD@2 2 2 +1.8VS_AON


OPT@
RF_NS@

RF_NS@

CV90

CV91

CV97

CV92

CV93
OPT@

2 2 CD@
CV95

CV89

OPT@ F1 FBVDDQ_SENSE_GPU RV90 1 OPT@ 2 0_0402_5%


CD89

CD90

FBVDDQ_SENSE FBVDDQ_VCC_SENSE 76
UV11
C FBVDDQ_SENSE_GND_GPU FP_FUSE_GPU C
F2 RV91 1 @ 2 0_0402_5% CV1103 1 2 OPT@ A2 A1
PROBE_FB_GND 2.2U_0402_6.3V6M VIN Vout
J27 FBCAL_VDDQ 1 2 B1 B2 GPIO26_FP_FUSE
FB_CAL_PD_VDDQ FBVDDQ GND ON GPIO26_FP_FUSE 28
RV92 40.2_0402_1% OPT@
H27 FBCAL_GND 1 2
FB_CAL_PU_GND

1
RV93 40.2_0402_1% OPT@ AP22913CN4-7_X1-WLB0909-4
H25 FBCAL_TERM 1 2 OPT@ RV1198
FB_CAL_TERM_GND RV94 40.2_0402_1% OPT@ 10K_0402_5%
OPT@
Place near balls

2
N18P-FCBGA960_BGA960
@

FBVDDQ

FBVDDQ_VCC_SENSE @
RV310 1 2 2_0402_5%

PLACE MIDWAY BETWEEN FBA AND FBB

UV1J
4/17 NC

AC6 AK9
AD4 NC_1 NC_20 AL10
AD5 NC_2 NC_21 AL11
AE3 NC_3 NC_22 AL9
AE4 NC_4 NC_23 AN2
AF1 NC_5 NC_24 AP8
+1.8VS_VGA AF2 NC_6 NC_25 C15
AF3 NC_7 NC_26 D19
B B
AF4 NC_8 NC_27 D20
AF5 NC_9 NC_28 D23
AG1 NC_10 NC_29 D26
AG26 NC_11 NC_30 L8
AG7 NC_12 NC_31 M8
AH11 NC_13 NC_32 V32
AJ26 NC_14 NC_33 U2
AJ28 NC_15RSVD_GNDS_SENSE U1
AJ4 NC_16RSVD_VDDS_SENSE
AJ5 NC_17
AK26 NC_18
AG26,AJ28 NC pin, NC_19
only for under GPU 1.8VS_VGA layout trace

2A
AON7408L
Vds=30V
+1.8VS_AON +1.8VS_VGA
Ids=15A
V20B+ QV16 Rdson=28mohm@Vgs=4.66V
=20mohm@Vgs=6V N18P-FCBGA960_BGA960
AON7380_DFN8-5
=18mohm@Vgs>10V @
Vgs=+-20V
2

RV42 1
2 Vgsth=1~3V
47K_0402_5% 5 3
OPT@
1

+5VALW
2 1 1 CV74
4

OPT@ CV73 RV85


CV72 10U_0603_6.3V6M
Vg=16.4V@AC 0.01U_0402_25V7K 47_0603_5%
OPT@
1

Vg=7.38V@Battery 0.1U_0402_25V6 OPT@


RV86 1@ 2@ 2
2

47K_0402_5% 1 2
OPT@ RV83
1K_0402_5% 2
2

D OPT@
1

+1.8VGS_PWR_EN# 5 RV47 CV75 D


G 210K_0402_1% 0.1U_0402_25V6 +1.8VGS_PWR_EN# 2
1
LBSS138DW1T1G_SOT363-6

S QV9B OPT@ OPT@ G QV20


4
LBSS138DW1T1G_SOT363-6

OPT@ 2N7002KW_SOT323-3
2
6

@ D S OPT@
RV1285
3

A RV58 2 1 0_0402_5% 2 1 0_0402_5% 2 QV9A A


28 1V8_MAIN_EN_R
G OPT@
S
0.1U_0402_25V6

1
1

2
PD3 0_0402_5%
CV38

@ RV84 +1.8V_MAIN discharger circuit


3 PR4 1 @ 2 100K_0402_5%
RV1284 @
1 1
2 @ 1 0_0402_5%
2

28,79 NVVDD_EN 0_0402_5%


2 PR5 1 @ 2

LBAT54SWT1G_SOT323-3
@
Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_(5/6):PWR


Reserve PD3/PR4/PR5/CV38 for NV sequence requirement THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 29 of 83
5 4 3 2 1
5 4 3 2 1

BOTH GP107 AND N18P-G5 NEED


NC AF30,AF32,AK31,AM34,E34,H30,M30,M34, NVVDD
A30,A9,B2,B23,D22,D28,D9,E4 NVVDD

UV1D UV1F NVVDD NVVDD UV1E

AG11
15/17 GND_1/2

GND_001 GND_071
AL18
16/17 GND_2/2 UV1G
13/17 NVVDD
9/17 XVDD
NVVDD
UNDER GPU NEAR GPU
A2 AL2 G25 P18 AA12 P12

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
CONFIGURABLE
GND_002 GND_072 GND_141 GND_190 VDD_01 VDD_51

33P_0402_50V8J

33P_0402_50V8J
1 1 1 1 1 1 1 1

330U_B2_2.5VM_R9M
A30 AL20 G28 P20 AA14 P14 POWER 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A33 GND_003 GND_073 AL21 G3 GND_142 GND_191 P22 AA16 VDD_02 VDD_52 P16 CHANNELS

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
GND_004 GND_074 GND_143 GND_192 VDD_03 VDD_53 +
A9 AL23 G30 P24 AA19 P19 U4
GND_005 GND_075 GND_144 GND_193 VDD_04 VDD_54 XVDD_01

RF_NS@

RF_NS@
OPT@

OPT@

OPT@

OPT@

OPT@
AA11 AL24 G32 R12 AA21 P21 U5 2 2 2 2 2 2 2
AA13 GND_006 GND_076 AL26 G33 GND_145 GND_194 R14 AA23 VDD_05 VDD_55 P23 XVDD_02 U6 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CV137

CV134

CV149

CV1148

CV1149
2

CV139

CV140

CV141

CV142

CV143

CV144

CV145

CV146

CV1114

CV1115

CV1116

CV1118

CV1117

CV1119
GND_007 GND_077 GND_146 GND_195 VDD_06 VDD_56 XVDD_03

CD94

CD93
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
AA15 AL28 G5 R16 AB11 R11 U7

CD@

CD@

CD@

CD@

CV1422
AA17 GND_008 GND_078 AL30 G7 GND_147 GND_196 R19 AB13 VDD_07 VDD_57 R13 XVDD_04 U8
D
AA18 GND_009 GND_079 AL32 H30 GND_148 GND_197 R21 AB15 VDD_08 VDD_58 R15 XVDD_05 V1 D
GND_010 GND_080 GND_149 GND_198 VDD_09 VDD_59 XVDD_06

@
AA20 AL33 K2 R23 AB17 R17 V2
AA22 GND_011 GND_081 AL5 K28 GND_150 GND_199 T11 AB18 VDD_10 VDD_60 R18 XVDD_07 V3
AA24 GND_012 GND_082 AM13 K30 GND_151 GND_200 T13 AB20 VDD_11 VDD_61 R20 XVDD_08 V4
AB12 GND_013 GND_083 AM16 K32 GND_152 GND_201 T15 AB22 VDD_12 VDD_62 R22 XVDD_09
AB14 GND_014 GND_084 AM19 K33 GND_153 GND_202 T17 AB24 VDD_13 VDD_63 R24
AB16 GND_015 GND_085 AM22 K5 GND_154 GND_203 T18 AC12 VDD_14 VDD_64 T12 V5
AB19 GND_016 GND_086 AM25 K7 GND_155 GND_204 T2 AC14 VDD_15 VDD_65 T14 XVDD_10 V6
GND_017 GND_087 GND_156 GND_205 VDD_16 VDD_66 XVDD_11

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
AB2 AM34 L12 T20 AC16 T16 V7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AB21 GND_018 GND_088 AN1 L14 GND_157 GND_206 T22 AC19 VDD_17 VDD_67 T19 XVDD_12 V8

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K

1U_0201_6.3V6K
AB23 GND_019 GND_089 AN10 L16 GND_158 GND_207 T24 AC21 VDD_18 VDD_68 T21 XVDD_13 W2
AB28 GND_020 GND_090 AN13 L19 GND_159 GND_208 T28 AC23 VDD_19 VDD_69 T23 XVDD_14 W3

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CD@

CD@

CD@
AB30 GND_021 GND_091 AN16 L21 GND_160 GND_209 T32 AD11 VDD_20 VDD_70 U11 XVDD_15 W4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

CV1150

CV1153

CV1151

CV1152

CV1155

CV1154

CV1156

CV1158

CV1157

CV1159
CV1508

CV1509

CV1510

CV1511

CV1512

CV1513

CV1514

CV1515

CV1516

CV1517

CV1518

CV1519
GND_022 GND_092 GND_161 GND_210 VDD_21 VDD_71 XVDD_16

@
AB32 AN19 L23 T5 AD13 U13 W5
AB5 GND_023 GND_093 AN22 M11 GND_162 GND_211 T7 AD15 VDD_22 VDD_72 U15 XVDD_17 W7
AB7 GND_024 GND_094 AN25 M13 GND_163 GND_212 U12 AD17 VDD_23 VDD_73 U17 XVDD_18
AC11 GND_025 GND_095 AN30 M15 GND_164 GND_213 U14 AD18 VDD_24 VDD_74 U18
AC13 GND_026 GND_096 AN34 M17 GND_165 GND_214 U16 AD20 VDD_25 VDD_75 U20 W8
AC15 GND_027 GND_097 AN4 M18 GND_166 GND_215 U19 AD22 VDD_26 VDD_76 U22 XVDD_19 Y1
AC17 GND_028 GND_098 AN7 M20 GND_167 GND_216 U21 AD24 VDD_27 VDD_77 U24 XVDD_20 Y2
AC18 GND_029 GND_099 AP2 M22 GND_168 GND_217 U23 L11 VDD_28 VDD_78 V11 XVDD_21 Y3
AC20 GND_030 GND_100 AP33 Y23 GND_169 GND_218 V12 L13 VDD_29 VDD_79 V13 XVDD_22 Y4
AC22 GND_031 GND_101 B1 M24 GND_239 GND_219 V14 L15 VDD_30 VDD_80 V15 XVDD_23 Y5
AC24 GND_032 GND_102 B10 M30 GND_170 GND_220 V16 L17 VDD_31 VDD_81 V17 XVDD_24 Y6
AD12 GND_033 GND_103 B2 M34 GND_171 GND_221 V19 L18 VDD_32 VDD_82 V18 XVDD_25 Y7
GND_034 GND_104 GND_172 GND_222 VDD_33 VDD_83 XVDD_26

10U_0603_6.3V6M

10U_0603_6.3V6M
AD14 B22 N12 V21 L20 V20 Y8

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
GND_035 GND_105 GND_173 GND_223 VDD_34 VDD_84 XVDD_27 2 2 1 1 1 1 1 1 1 1
AD16 B23 N14 V23 L22 V22
AD19 GND_036 GND_106 B25 N16 GND_174 GND_224 W11 L24 VDD_35 VDD_85 V24
AD21 GND_037 GND_107 B28 N19 GND_175 GND_225 W13 M12 VDD_36 VDD_86 W12 AA1
AD23 GND_038 GND_108 B31 N2 GND_176 GND_226 W15 M14 VDD_37 VDD_87 W14 XVDD_28 AA2 1 1 2 2 2 2 2 2 2 2

OPT@

OPT@
AE2 GND_039 GND_109 B34 N21 GND_177 GND_227 W17 M16 VDD_38 VDD_88 W16 XVDD_29 AA3

OPT@

OPT@

OPT@

OPT@

OPT@
CV433

CV434

CV435

CV436

CV437

CV1120

CV1121

CV1122
CD@

CD@

CD@
CV428

CV429
AE28 GND_040 GND_110 B4 N23 GND_178 GND_228 W18 M19 VDD_39 VDD_89 W19 XVDD_30 AA4
AE30 GND_041 GND_111 B7 N28 GND_179 GND_229 W20 M21 VDD_40 VDD_90 W21 XVDD_31 AA5
AE32 GND_042 GND_112 C10 N30 GND_180 GND_230 W22 M23 VDD_41 VDD_91 W23 XVDD_32 AA6
AE33 GND_043 GND_113 C13 N32 GND_181 GND_231 W24 N11 VDD_42 VDD_92 Y11 XVDD_33 AA7
AE5 GND_044 GND_114 C19 N33 GND_182 GND_232 W28 N13 VDD_43 VDD_93 Y13 XVDD_34 AA8
AE7 GND_045 GND_115 C22 N5 GND_183 GND_233 Y12 N15 VDD_44 VDD_94 Y15 XVDD_35
C AF30 GND_046 GND_116 C25 N7 GND_184 GND_234 Y14 N17 VDD_45 VDD_95 Y17 C
AF32 GND_047 GND_117 C28 P11 GND_185 GND_235 Y16 N18 VDD_46 VDD_96 Y18
AH10 GND_048 GND_118 C7 P13 GND_186 GND_236 Y19 N20 VDD_47 VDD_97 Y20
AH13 GND_049 GND_119 D2 P15 GND_187 GND_237 Y21 N22 VDD_48 VDD_98 Y22

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
GND_050 GND_120 GND_188 GND_238 VDD_49 VDD_99 1 1 1 1 1 1 1 1 1 1 1 1 1
AH16 D22 P17 N24 Y24
AH19 GND_051 GND_121 D28 GND_189 VDD_50 VDD_100
AH2 GND_052 GND_122 D31 C16
AH22 GND_053 GND_123 D33 GND_OPT_1 W32 N18P-FCBGA960_BGA960 2 2 2 2 2 2 2 2 2 2 2 2 2
AH24 GND_054 GND_124 D9 GND_OPT_2

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV1123

CV1124

CV1125

CV1126

CV1127

CV1128

CV1129

CV1130

CV1131

CV1132

CV1133

CV1134

CV1135
CD@

CD@

CD@

CD@
GND_055 GND_125 @
AH28 E10
AH29 GND_056 GND_126 E22 Optional CMD GNDs (2)
AH30 GND_057 GND_127 E25 NC for 4-Lyr cards
AH32 GND_058 GND_128 E34
AH33 GND_059 GND_129 E4 N18P-FCBGA960_BGA960
AH5 GND_060 GND_130 E5
GND_061 GND_131 @
AH7 E7
AJ7 GND_062 GND_132 F28
AK10 GND_063 GND_133 F7
AK31 GND_064 GND_134 G10

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
GND_065 GND_135 1 1 1 1 1 1 1 1 1 1 1
AK7 G13
AL12 GND_066 GND_136 G16
AL14 GND_067 GND_137 G19
AL15 GND_068 GND_138 G2 2 2 2 2 2 2 2 2 2 2 2
AL17 GND_069 GND_139 G22

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV1136

CV1137

CV1138

CV1139

CV1140

CV1141

CV1142

CV1143

CV1144

CV1145

CV1146
CD@

CD@

CD@

CD@

CD@
GND_070 GND_140 trace width: 16mils
differential voltage sensing.
N18P-FCBGA960_BGA960
differential signal routing.
L4 NVVDD_VDD_SENSE NVVDD_VDD_SENSE 79
@ VDD_SENSE

L5 NVVDD_VSS_SENSE NVVDD_VSS_SENSE 79
GND_SENSE

N18P-FCBGA960_BGA960
@

B B

Add RV332 for NVVDDS discharge Hai Y520 SVT


Change NVVDDS & +1.0VGS discharge circuit
HLZ SIV 0725

NVVDD +1.0VGS Change QV6/RV48/QV4/RV62 from REV@ to ns Hai Y520 SVT


FBVDDQ
1

+5VALW
15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

15_0805_1%

RV61
2 RV332 1

RV45 1

2 RV326 1

2 RV327 1

RV63 1

2 RV328 1

2 RV329 1

470_0603_5%
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

+5VALW RV48
2

47K_0402_5%
@
2

2
1

D QV6B
RV60
5
47K_0402_5% 2N7002KDWH_SOT363-6
G
1

OPT@
@
D

S
2

4
6

D QV6A
2 2
G G 2
28,76 FBVDDQ_PWR_EN 2N7002KDWH_SOT363-6
G
LBSS139WT1G_SC70-3

A A
S

QV11 QV29 QV12


S
1

D
1

AO3402_SOT-23-3 AO3402_SOT-23-3
3

3
OPT@

2
28,77 1V0_MAIN_EN
G OPT@ OPT@
S
3

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_(6/6):PWR,VSS


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y550 1.0

Date: Monday, February 24, 2020 Sheet 30 of 83


5 4 3 2 1
5 4 3 2 1

UV4D
?
? UV4C
COMMON ?
?
FBVDDQ COMMON

27,32 FBA_CMD[0..33]
A11 A1 UV4B FBA_CMD13 H3 K1 +FBA_VREFC
A13 VSS_1 VDD_1 A14 UV4A FBA_CMD15 G11 CA0_A VREFC
A2 VSS_2 VDD_2 E10 FBA_CMD0 G4 CA1_A
NORMAL
A4 VSS_3 VDD_3 E5 FBA_CMD9 H12 CA2_A
VSS_4 VDD_4 27 FBA_D[0..15] NORMAL 27 FBA_D[16..31] CA3_A
B1 H13 x16 x8 FBA_CMD11 H5
B14 VSS_5 VDD_5 H2 FBA_D3 G2 FBA_D29 N2 FBA_CMD12 H10 CA4_A
C10 VSS_6 VDD_6 L13 FBA_D4 B3 DQ7_A FBA_D28 P3 DQ6_B FBA_CMD3 J12 CA5_A
C12 VSS_7 VDD_7 L2 FBA_D7 F2 DQ2_A FBA_D31 M2 DQ4_B FBA_CMD4 J11 CA6_A
D VSS_8 VDD_8 FBA_D5 DQ6_A BYTE3 FBA_D30 DQ7_B FBA_CMD6 CA7_A D
C3 P10 E3 P2 J4
C5 VSS_9 VDD_9 P5 FBA_D2 B4 DQ4_A FBA_D25 U3 DQ5_B FBA_CMD5 J3 CA8_A
VSS_10 VDD_10 BYTE0 FBA_D0 DQ0_A FBA_D24 DQ2_B FBA_CMD8 CA9_A
D1 V1 B2 V3 J5
D12 VSS_11 VDD_11 V14 FBA_D6 E2 DQ3_A FBA_D26 U4 DQ1_B FBA_CMD7 G10 CABI_n_A
D14 VSS_12 VDD_12 FBA_D1 A3 DQ5_A FBA_D27 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBA_EDC0 C2 FBA_EDC3 T2 TCK
VSS_15 FBVDDQ 27 FBA_EDC0 FBA_DBI0# EDC0_A 27 FBA_EDC3 FBA_DBI3# EDC0_B
E4 D2 R2 F10
VSS_16 27 FBA_DBI0# DBI0_n_A 27 FBA_DBI3# DBI0_n_B TDI
F1 N10
F12 VSS_17 FBA_WCK01 D4 FBA_WCKB23 R4 TDO
VSS_18 27 FBA_WCK01 FBA_WCK01_N WCK_t_A 27 FBA_WCKB23 FBA_WCKB23_N NC3
F14 B10 D5 R5 F5
VSS_19 VDDQ_1 27 FBA_WCK01_N WCK_c_A 27 FBA_WCKB23_N NC4 FBA_CMD10 TMS
F3 B5 L3
G1 VSS_20 VDDQ_2 C1 FBA_D19 P13 FBA_CMD1 M11 CA0_B
G12 VSS_21 VDDQ_3 C11 FBA_D17 U13 DQ13_B FBA_CMD32 M4 CA1_B
x16 x8
G14 VSS_22 VDDQ_4 C14 FBA_D10 B11 FBA_D20 M13 DQ11_B FBA_CMD14 L12 CA2_B
VSS_23 VDDQ_5 FBA_D11 DQ8_A
NC BYTE2 FBA_D21 DQ15_B FBA_CMD11 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBA_D15 E13 DQ15_A FBA_D16 U12 DQ14_B FBA_CMD12 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBA_D12 F13 DQ13_A FBA_D23 P12 DQ10_B FBA_CMD3 K12 CA5_B
VSS_26 VDDQ_8 BYTE1 FBA_D13 DQ14_A NC
FBA_D18 DQ12_B FBA_CMD4 CA6_B
L11 F11 E12 NC V12 K11
L4 VSS_27 VDDQ_9 F4 FBA_D8 B12 DQ12_A FBA_D22 U11 DQ9_B FBA_CMD6 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBA_D9 B13 DQ10_A DQ8_B FBA_CMD5 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBA_D14 A12 DQ11_A FBA_EDC2 T13 FBA_CMD8 K5 CA9_B J14FBA_ZQ_1_A RV1290 1 OPT@ 2 121_0402_1%
NC
VSS_30 VDDQ_12 DQ9_A 27 FBA_EDC2 FBA_DBI2# EDC1_B FBA_CMD7 CABI_n_B ZQ_A
M14 J13 R13 M10
VSS_31 VDDQ_13 FBA_EDC1 27 FBA_DBI2# DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBA_ZQ_1_B RV1122 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 27 FBA_EDC1 FBA_DBI1# EDC1_A FBA_WCK23 ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 27 FBA_DBI1# DBI1_n_A NC 27 FBA_WCK23 FBA_WCK23_N WCK_t_B
N12 K2 R10
VSS_34 VDDQ_16 FBA_WCKB01 27 FBA_WCK23_N WCK_c_B
N14 L1 D11 NC
VSS_35 VDDQ_17 27 FBA_WCKB01 FBA_WCKB01_N D10 NC1
N3 L14 NC
VSS_36 VDDQ_18 27 FBA_WCKB01_N NC2 FBA_CMD2
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBA_CLK0# K10
VSS_41 VDDQ_23 27 FBA_CLK0# CK_c
R3 T11 FBA_CLK0 J10
VSS_42 VDDQ_24 27 FBA_CLK0 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
T5 VSS_45 VDDQ_27 U5 NC6
C C
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
VPP_1 @
A5
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1 1 1 1
V5
VPP_4
@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV588

CV589

CV590

CV591

CV592

CV1523

CV1524

CV1525
MT61K256M32JE-14-A_FBGA180
2 2 2 2 2 2 2 2
@

FBVDDQ

1
RV97
549_0402_1%
@

2
FBVDDQ FBVDDQ 1 @ 2 +FBA_VREFC
+FBA_VREFC 32
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM RV1291 16 mil

1
931_0402_1% 1
RV99 CV1521
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1K_0402_1% 820P_0402_25V7

1
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 OPT@ @
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

2
CD@
@

@
2 QV48
CV587

CV576

CV577

CV578

CV582

CV579

CV580

CV581

CV585

CV583

CV584

CV586
28 MEM_VREF
2

B 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 B
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

LSI1012XT1G_SC-89-3
CV234

CV235

CV236

CV237

CV238

CV563

@
CV178

CV220

CV221

CV228

CV490

CV491

3
Vgs(th)≤0.9V VREFC IS NOT USED IN
x16 CONFIGURATION
FBVDDQ FBVDDQ
1K OHM PULL-DOWN IS
CLOSE TO DRAM CLOSE TO DRAM IN PLACE OF THE 1.33K
FOR RV99
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CD@
CV564

CV565

CV566

CV567

CV571

CV568

CV569

CV570

CV575

CV572

CV573

CV574

CV492

CV493

CV494

CV239

CV240

CV241

CV242

CV243

CV244

CV245

CV246

CV247

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_GDDR6_A_[31_0]


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 31 of 83
5 4 3 2 1
5 4 3 2 1

UV5D
?
? UV5C
COMMON ?
?
FBVDDQ COMMON
UV5A
27,31 FBA_CMD[0..33]
UV5B
A11 A1 FBA_CMD29 H3 K1 +FBA_VREFC
VSS_1 VDD_1 27 FBA_D[32..47] NORMAL CA0_A VREFC +FBA_VREFC 31
A13 A14 NORMAL FBA_CMD31 G11
A2 VSS_2 VDD_2 E10 FBA_D40 G2 FBA_CMD16 G4 CA1_A
VSS_3 VDD_3 DQ7_A 27 FBA_D[48..63] CA2_A 1
A4 E5 FBA_D44 B3 x16 x8 FBA_CMD25 H12 CV172
B1 VSS_4 VDD_4 H13 FBA_D41 F2 DQ2_A FBA_D52 N2 FBA_CMD22 H5 CA3_A 820P_0402_25V7
B14 VSS_5 VDD_5 H2 FBA_D46 E3 DQ6_A FBA_D53 P3 DQ6_B FBA_CMD21 H10 CA4_A
VSS_6 VDD_6 BYTE5 FBA_D42 DQ4_A FBA_D54 DQ4_B FBA_CMD24 CA5_A 2
@
C10 L13 B4 M2 J12
C12 VSS_7 VDD_7 L2 FBA_D47 B2 DQ0_A FBA_D55 P2 DQ7_B FBA_CMD23 J11 CA6_A
D VSS_8 VDD_8 FBA_D43 DQ3_A BYTE6 FBA_D49 DQ5_B FBA_CMD26 CA7_A D
C3 P10 E2 U3 J4
C5 VSS_9 VDD_9 P5 FBA_D45 A3 DQ5_A FBA_D51 V3 DQ2_B FBA_CMD17 J3 CA8_A
D1 VSS_10 VDD_10 V1 DQ1_A FBA_D50 U4 DQ1_B FBA_CMD30 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBA_EDC5 C2 FBA_D48 U2 DQ0_B FBA_CMD33 G10 CABI_n_A
VSS_12 VDD_12 27 FBA_EDC5 FBA_DBI5# EDC0_A DQ3_B CKE_n_A
D14 D2
VSS_13 27 FBA_DBI5# DBI0_n_A FBA_EDC6
D3 T2 N5
VSS_14 FBA_WCKB45 27 FBA_EDC6 FBA_DBI6# EDC0_B TCK
E11 D4 R2
VSS_15 FBVDDQ 27 FBA_WCKB45 FBA_WCKB45_N WCK_t_A 27 FBA_DBI6# DBI0_n_B
E4 D5 F10
VSS_16 27 FBA_WCKB45_N WCK_c_A FBA_WCK67 TDI
F1 R4 N10
VSS_17 27 FBA_WCK67 FBA_WCK67_N NC3 TDO
F12 R5
VSS_18 27 FBA_WCK67_N NC4
F14 B10 x16 x8 F5
F3 VSS_19 VDDQ_1 B5 FBA_D34 B11 FBA_D58 P13 FBA_CMD27 L3 TMS
NC
G1 VSS_20 VDDQ_2 C1 FBA_D38 G13 DQ8_A FBA_D60 U13 DQ13_B FBA_CMD28 M11 CA0_B
NC
G12 VSS_21 VDDQ_3 C11 FBA_D36 E13 DQ15_A FBA_D56 M13 DQ11_B FBA_CMD19 M4 CA1_B
VSS_22 VDDQ_4 BYTE4 FBA_D37 DQ13_A
NC
FBA_D57 DQ15_B FBA_CMD20 CA2_B
G14 C14 F13 NC BYTE7 N13 L12
G3 VSS_23 VDDQ_5 C4 FBA_D39 E12 DQ14_A FBA_D61 U12 DQ14_B FBA_CMD22 L5 CA3_B
NC
H11 VSS_24 VDDQ_6 E1 FBA_D32 B12 DQ12_A FBA_D59 P12 DQ10_B FBA_CMD21 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBA_D33 B13 DQ10_A FBA_D62 V12 DQ12_B FBA_CMD24 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBA_D35 A12 DQ11_A FBA_D63 U11 DQ9_B FBA_CMD23 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBA_CMD26 K4 CA7_B
M1 VSS_28 VDDQ_10 H1 FBA_EDC4 C13 FBA_EDC7 T13 FBA_CMD17 K3 CA8_B
GND
VSS_29 VDDQ_11 27 FBA_EDC4 FBA_DBI4# EDC1_A 27 FBA_EDC7 FBA_DBI7# EDC1_B FBA_CMD30 CA9_B
M12 H14 D13 R13 K5 J14FBA_ZQ_2_A RV1177 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 27 FBA_DBI4# DBI1_n_A NC 27 FBA_DBI7# DBI1_n_B FBA_CMD33 CABI_n_B ZQ_A
M14 J13 M10
M3 VSS_31 VDDQ_13 J2 FBA_WCK45 D11 FBA_WCKB67 R11 CKE_n_B K14FBA_ZQ_2_B RV1178 1 OPT@ 2 121_0402_1%
NC
VSS_32 VDDQ_14 27 FBA_WCK45 FBA_WCK45_N NC1 27 FBA_WCKB67 FBA_WCKB67_N R10 WCK_t_B ZQ_B
N1 K13 D10 NC
VSS_33 VDDQ_15 27 FBA_WCK45_N NC2 27 FBA_WCKB67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180 FBA_CMD18 J1
VSS_37 VDDQ_19 @ RESET_n
P4 N4 @
R1 VSS_38 VDDQ_20 P1
R12 VSS_39 VDDQ_21 P14
R14 VSS_40 VDDQ_22 T1 FBA_CLK1# K10 CK_c
R3
T10
T12
T3
VSS_41
VSS_42
VSS_43
VSS_44
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
T11
T14
T4
U10
follow CRB bit swap 27
27
FBA_CLK1#
FBA_CLK1
FBA_CLK1 J10
CK_t
NC5
G5

M5
T5 VSS_45 VDDQ_27 U5 NC6
C C
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
VPP_1 @
A5
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1 1 1 1
V5
VPP_4
@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV596

CV597

CV598

CV599

CV600

CV1526

CV1527

CV1528
MT61K256M32JE-14-A_FBGA180
2 2 2 2 2 2 2 2
@

FBVDDQ FBVDDQ
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

@
CD@
CV636

CV623

CV624

CV625

CV628

CV627

CV626

CV629

CV632

CV630

CV631

CV635
2

B 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 B
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV617

CV620

CV616

CV619

CV618

CV621

CV633

CV634

CV611

CV610

CV609

CV608

FBVDDQ FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV622

CV601

CV602

CV603

CV607

CV604

CV605

CV606

CV614

CV612

CV613

CV615

CV595

CV638

CV637

CV639

CV642

CV641

CV640

CV643

CV593

CV645

CV644

CV594

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_GDDR6_A_[63_32]


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 32 of 83
5 4 3 2 1
5 4 3 2 1

UV6D
?
? UV6C
COMMON ?
?
FBVDDQ COMMON

27,34 FBB_CMD[0..33]
A11 A1 UV6B FBB_CMD13 H3 K1 +FBB_VREFC
A13 VSS_1 VDD_1 A14 UV6A FBB_CMD15 G11 CA0_A VREFC
A2 VSS_2 VDD_2 E10 NORMAL FBB_CMD0 G4 CA1_A
A4 VSS_3 VDD_3 E5 FBB_CMD9 H12 CA2_A
VSS_4 VDD_4 27 FBB_D[0..15] NORMAL 27 FBB_D[16..31] CA3_A
B1 H13 x16 x8 FBB_CMD11 H5
B14 VSS_5 VDD_5 H2 FBB_D7 G2 FBB_D28 N2 FBB_CMD12 H10 CA4_A
C10 VSS_6 VDD_6 L13 FBB_D1 B3 DQ7_A FBB_D30 P3 DQ6_B FBB_CMD3 J12 CA5_A
D
C12 VSS_7 VDD_7 L2 FBB_D5 F2 DQ2_A FBB_D29 M2 DQ4_B FBB_CMD4 J11 CA6_A D
VSS_8 VDD_8 FBB_D6 DQ6_A BYTE3 FBB_D31 DQ7_B FBB_CMD6 CA7_A
C3 P10 BYTE0 E3 P2 J4
C5 VSS_9 VDD_9 P5 FBB_D2 B4 DQ4_A FBB_D24 U3 DQ5_B FBB_CMD5 J3 CA8_A
D1 VSS_10 VDD_10 V1 FBB_D0 B2 DQ0_A FBB_D25 V3 DQ2_B FBB_CMD8 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBB_D4 E2 DQ3_A FBB_D26 U4 DQ1_B FBB_CMD7 G10 CABI_n_A
D14 VSS_12 VDD_12 FBB_D3 A3 DQ5_A FBB_D27 U2 DQ0_B CKE_n_A
D3 VSS_13 DQ1_A DQ3_B N5
E11 VSS_14 FBB_EDC0 C2 FBB_EDC3 T2 TCK
VSS_15 FBVDDQ 27 FBB_EDC0 FBB_DBI0# EDC0_A 27 FBB_EDC3 FBB_DBI3# EDC0_B
E4 D2 R2 F10
VSS_16 27 FBB_DBI0# DBI0_n_A 27 FBB_DBI3# DBI0_n_B TDI
F1 N10
F12 VSS_17 FBB_WCK01 D4 FBB_WCKB23 R4 TDO
VSS_18 27 FBB_WCK01 FBB_WCK01_N WCK_t_A 27 FBB_WCKB23 FBB_WCKB23_N NC3
F14 B10 D5 R5 F5
VSS_19 VDDQ_1 27 FBB_WCK01_N WCK_c_A 27 FBB_WCKB23_N NC4 FBB_CMD10 TMS
F3 B5 L3
G1 VSS_20 VDDQ_2 C1 FBB_D20 P13 FBB_CMD1 M11 CA0_B
G12 VSS_21 VDDQ_3 C11 FBB_D17 U13 DQ13_B FBB_CMD32 M4 CA1_B
x16 x8
G14 VSS_22 VDDQ_4 C14 FBB_D10 B11 FBB_D22 M13 DQ11_B FBB_CMD14 L12 CA2_B
VSS_23 VDDQ_5 FBB_D15 DQ8_A
NC BYTE2 FBB_D21 DQ15_B FBB_CMD11 CA3_B
G3 C4 G13 NC N13 L5
H11 VSS_24 VDDQ_6 E1 FBB_D8 E13 DQ15_A FBB_D19 U12 DQ14_B FBB_CMD12 L10 CA4_B
VSS_25 VDDQ_7 BYTE1 FBB_D13 DQ13_A
NC
FBB_D23 DQ10_B FBB_CMD3 CA5_B
H4 E14 F13 NC P12 K12
L11 VSS_26 VDDQ_8 F11 FBB_D12 E12 DQ14_A FBB_D16 V12 DQ12_B FBB_CMD4 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 FBB_D9 B12 DQ12_A FBB_D18 U11 DQ9_B FBB_CMD6 K4 CA7_B
NC
M1 VSS_28 VDDQ_10 H1 FBB_D14 B13 DQ10_A DQ8_B FBB_CMD5 K3 CA8_B
NC
M12 VSS_29 VDDQ_11 H14 FBB_D11 A12 DQ11_A FBB_EDC2 T13 FBB_CMD8 K5 CA9_B J14FBB_ZQ_1_A RV1179 1 OPT@ 2 121_0402_1%
NC
VSS_30 VDDQ_12 DQ9_A 27 FBB_EDC2 FBB_DBI2# EDC1_B FBB_CMD7 CABI_n_B ZQ_A
M14 J13 R13 M10
VSS_31 VDDQ_13 FBB_EDC1 27 FBB_DBI2# DBI1_n_B CKE_n_B
M3 J2 C13 GND K14FBB_ZQ_1_B RV1180 1 OPT@ 2 121_0402_1%
VSS_32 VDDQ_14 27 FBB_EDC1 FBB_DBI1# EDC1_A FBB_WCK23 ZQ_B
N1 K13 D13 R11
VSS_33 VDDQ_15 27 FBB_DBI1# DBI1_n_A NC 27 FBB_WCK23 FBB_WCK23_N WCK_t_B
N12 K2 R10
VSS_34 VDDQ_16 FBB_WCKB01 27 FBB_WCK23_N WCK_c_B
N14 L1 D11 NC
VSS_35 VDDQ_17 27 FBB_WCKB01 FBB_WCKB01_N D10 NC1
N3 L14 NC
VSS_36 VDDQ_18 27 FBB_WCKB01_N NC2 FBB_CMD2
P11 N11 J1
VSS_37 VDDQ_19 RESET_n
P4 N4 MT61K256M32JE-14-A_FBGA180
R1 VSS_38 VDDQ_20 P1 MT61K256M32JE-14-A_FBGA180
VSS_39 VDDQ_21 @
R12 P14 @
R14 VSS_40 VDDQ_22 T1 FBB_CLK0# K10
VSS_41 VDDQ_23 27 FBB_CLK0# CK_c
R3 T11 FBB_CLK0 J10
VSS_42 VDDQ_24 27 FBB_CLK0 CK_t
T10 T14 G5
T12 VSS_43 VDDQ_25 T4 NC5
T3 VSS_44 VDDQ_26 U10 M5
C C
T5 VSS_45 VDDQ_27 U5 NC6
U1 VSS_46 VDDQ_28
U14
V11
V13
V2
VSS_47
VSS_48
VSS_49
VSS_50 +1.8VS_AON +1.8VS_AON
follow CRB bit swap
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
VPP_1 @
A5
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1 1 1 1
V5
VPP_4
@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV649

CV650

CV652

CV651

CV653

CV1529

CV1530

CV1531
2 2 2 2 2 2 2 2
MT61K256M32JE-14-A_FBGA180
@

FBVDDQ

1
RV1181
549_0402_1%
@

2
FBVDDQ FBVDDQ 1 2 +FBB_VREFC
+FBB_VREFC 34
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM RV1182 16 mil

1
931_0402_1% 1
@ RV1183 CV675
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
1K_0402_1% 820P_0402_25V7

1
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 OPT@ @
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

2
B B
@

@
2 QV33
CD@

CD@
CV690

CV678

CV677

CV679

CV683

CV680

CV681

CV682

CV687

CV685

CV684

CV689
28 MEM_VREF
2

1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

LSI1012XT1G_SC-89-3
CV669

CV672

CV670

CV673

CV671

CV674

@
CV688

CV686

CV663

CV664

CV661

CV662

3
Vgs(th)≤0.9V VREFC IS NOT USED IN
x16 CONFIGURATION
FBVDDQ FBVDDQ
1K OHM PULL-DOWN IS
CLOSE TO DRAM CLOSE TO DRAM IN PLACE OF THE 1.33K
FOR RV1183
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV676

CV654

CV655

CV656

CV660

CV658

CV657

CV659

CV668

CV665

CV666

CV648

CV691

CV692

CV693

CV697

CV694

CV695

CV696

CV646

CV698

CV699

CV647
CV1520

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_GDDR6_B_[31_0]


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 33 of 83
5 4 3 2 1
5 4 3 2 1

UV7D
?
? UV7C
COMMON ?
?
FBVDDQ COMMON
UV7A
27,33 FBB_CMD[0..33]
UV7B
A11 A1 FBB_CMD29 H3 K1 +FBB_VREFC
VSS_1 VDD_1 27 FBB_D[32..47] NORMAL CA0_A VREFC +FBB_VREFC 33
A13 A14 NORMAL FBB_CMD31 G11
A2 VSS_2 VDD_2 E10 FBB_D43 G2 FBB_CMD16 G4 CA1_A
VSS_3 VDD_3 DQ7_A 27 FBB_D[48..63] CA2_A 1
A4 E5 FBB_D41 B3 x16 x8 FBB_CMD25 H12 CV743
B1 VSS_4 VDD_4 H13 FBB_D46 F2 DQ2_A FBB_D50 N2 FBB_CMD22 H5 CA3_A 820P_0402_25V7
B14 VSS_5 VDD_5 H2 FBB_D45 E3 DQ6_A FBB_D55 P3 DQ6_B FBB_CMD21 H10 CA4_A
VSS_6 VDD_6 BYTE5 FBB_D42 DQ4_A FBB_D54 DQ4_B FBB_CMD24 CA5_A 2
@
C10 L13 B4 M2 J12
D
C12 VSS_7 VDD_7 L2 FBB_D47 B2 DQ0_A FBB_D53 P2 DQ7_B FBB_CMD23 J11 CA6_A D
VSS_8 VDD_8 FBB_D44 DQ3_A BYTE6 FBB_D51 DQ5_B FBB_CMD26 CA7_A
C3 P10 E2 U3 J4
C5 VSS_9 VDD_9 P5 FBB_D40 A3 DQ5_A FBB_D49 V3 DQ2_B FBB_CMD17 J3 CA8_A
D1 VSS_10 VDD_10 V1 DQ1_A FBB_D52 U4 DQ1_B FBB_CMD30 J5 CA9_A
D12 VSS_11 VDD_11 V14 FBB_EDC5 C2 FBB_D48 U2 DQ0_B FBB_CMD33 G10 CABI_n_A
VSS_12 VDD_12 27 FBB_EDC5 FBB_DBI5# EDC0_A DQ3_B CKE_n_A
D14 D2
VSS_13 27 FBB_DBI5# DBI0_n_A FBB_EDC6
D3 T2 N5
VSS_14 FBB_WCKB45 27 FBB_EDC6 FBB_DBI6# EDC0_B TCK
E11 D4 R2
VSS_15 FBVDDQ 27 FBB_WCKB45 FBB_WCKB45_N WCK_t_A 27 FBB_DBI6# DBI0_n_B
E4 D5 F10
VSS_16 27 FBB_WCKB45_N WCK_c_A FBB_WCK67 TDI
F1 R4 N10
VSS_17 27 FBB_WCK67 FBB_WCK67_N NC3 TDO
F12 R5
VSS_18 27 FBB_WCK67_N NC4
F14 B10 x16 x8 F5
F3 VSS_19 VDDQ_1 B5 FBB_D34 B11 FBB_D60 P13 FBB_CMD27 L3 TMS
NC
G1 VSS_20 VDDQ_2 C1 FBB_D38 G13 DQ8_A FBB_D57 U13 DQ13_B FBB_CMD28 M11 CA0_B
NC
G12 VSS_21 VDDQ_3 C11 FBB_D35 E13 DQ15_A FBB_D61 M13 DQ11_B FBB_CMD19 M4 CA1_B
NC
G14 VSS_22 VDDQ_4 C14 FBB_D33 F13 DQ13_A FBB_D58 N13 DQ15_B FBB_CMD20 L12 CA2_B
VSS_23 VDDQ_5 BYTE4 FBB_D37 DQ14_A NC BYTE7 FBB_D56 DQ14_B FBB_CMD22 CA3_B
G3 C4 E12 NC U12 L5
H11 VSS_24 VDDQ_6 E1 FBB_D32 B12 DQ12_A FBB_D63 P12 DQ10_B FBB_CMD21 L10 CA4_B
NC
H4 VSS_25 VDDQ_7 E14 FBB_D39 B13 DQ10_A FBB_D59 V12 DQ12_B FBB_CMD24 K12 CA5_B
NC
L11 VSS_26 VDDQ_8 F11 FBB_D36 A12 DQ11_A FBB_D62 U11 DQ9_B FBB_CMD23 K11 CA6_B
NC
L4 VSS_27 VDDQ_9 F4 DQ9_A DQ8_B FBB_CMD26 K4 CA7_B
M1 VSS_28 VDDQ_10 H1 FBB_EDC4 C13 FBB_EDC7 T13 FBB_CMD17 K3 CA8_B
GND
VSS_29 VDDQ_11 27 FBB_EDC4 FBB_DBI4# EDC1_A 27 FBB_EDC7 FBB_DBI7# EDC1_B FBB_CMD30 CA9_B
M12 H14 D13 R13 K5 J14FBB_ZQ_2_A RV1184 1 OPT@ 2 121_0402_1%
VSS_30 VDDQ_12 27 FBB_DBI4# DBI1_n_A NC 27 FBB_DBI7# DBI1_n_B FBB_CMD33 CABI_n_B ZQ_A
M14 J13 M10
M3 VSS_31 VDDQ_13 J2 FBB_WCK45 D11 FBB_WCKB67 R11 CKE_n_B K14FBB_ZQ_2_B RV1185 1 OPT@ 2 121_0402_1%
NC
VSS_32 VDDQ_14 27 FBB_WCK45 FBB_WCK45_N NC1 27 FBB_WCKB67 FBB_WCKB67_N R10 WCK_t_B ZQ_B
N1 K13 D10 NC
VSS_33 VDDQ_15 27 FBB_WCK45_N NC2 27 FBB_WCKB67_N WCK_c_B
N12 K2
N14 VSS_34 VDDQ_16 L1
N3 VSS_35 VDDQ_17 L14 MT61K256M32JE-14-A_FBGA180
P11 VSS_36 VDDQ_18 N11 MT61K256M32JE-14-A_FBGA180 FBB_CMD18 J1
VSS_37 VDDQ_19 @ RESET_n
P4 N4 @
R1 VSS_38 VDDQ_20 P1
R12 VSS_39 VDDQ_21 P14
R14 VSS_40 VDDQ_22 T1 FBB_CLK1# K10 CK_c
R3
T10
T12
T3
VSS_41
VSS_42
VSS_43
VSS_44
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26
T11
T14
T4
U10
follow CRB bit swap 27
27
FBB_CLK1#
FBB_CLK1
FBB_CLK1 J10
CK_t
NC5
G5

M5
C C
T5 VSS_45 VDDQ_27 U5 NC6
U1 VSS_46 VDDQ_28
U14 VSS_47
V11 VSS_48
V13 VSS_49
V2 VSS_50 +1.8VS_AON +1.8VS_AON
V4 VSS_51
VSS_52 CLOSE TO DRAM
MT61K256M32JE-14-A_FBGA180
A10
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
VPP_1 @
A5
4.7U_0603_6.3V6K

VPP_2 V10
VPP_3 1 1 1 1 1 1 1 1
V5
VPP_4
@

@
OPT@

OPT@

OPT@

OPT@

OPT@
CV747

CV749

CV748

CV750

CV751

CV1532

CV1533

CV1534
2 2 2 2 2 2 2 2
MT61K256M32JE-14-A_FBGA180
@

FBVDDQ FBVDDQ
AROUND DRAM CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201
2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
1

B B
@

@
CD@
CV733

CV720

CV721

CV722

CV725

CV723

CV724

CV726

CV730

CV727

CV728

CV732
2

1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CV714

CV717

CV713

CV715

CV716

CV718

CV729

CV731

CV708

CV707

CV706

CV705

FBVDDQ FBVDDQ
CLOSE TO DRAM CLOSE TO DRAM
1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1U_6.3V_K_X5R_0201

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@

@
OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@

OPT@
CD@
CV719

CV752

CV753

CV700

CV704

CV701

CV702

CV703

CV711

CV709

CV710

CV712

CV746

CV736

CV734

CV735

CV739

CV738

CV737

CV740

CV744

CV742

CV741

CV745

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 N18P_GDDR6_B_[63_32]


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 34 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Y550 1.0

Date: Monday, February 24, 2020 Sheet 35 of 83


5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Y550 1.0

Date: Monday, February 24, 2020 Sheet 36 of 83


5 4 3 2 1
5 4 3 2 1

USB Redriver移移移移
D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 DDI Redriver PS8330


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 37 of 83
5 4 3 2 1
5 4 3 2 1

+3V_HUB +3V_HUB
+DVDD12_HUB +AVDD12_HUB
LI97 LI98

0.1U_6.3V_K_X5R_0201
USB_HUB_1V2_SW 1 2 USB_HUB_1V2_FB 1 2
1

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
10U_0603_6.3V6M

10U_0603_6.3V6M
2.2UH_EP-22AM05B02_2A_20% HCB1608KF-181T20_2P

CI119
1 1 1 1 1 1 1 1 1 1 1 1 1
2

CI106

CI107

CI108

CI109

CI110

CI111

CI112

CI113

CI114

CI115

CI116

CI117

CI118
+3V_HUB
2 2 2 2 2 2 2 2 2 2 2 2 2

U136

0.1U_6.3V_K_X5R_0201
8
1

VCC
SPI_HUB_CS# RI324 1 2 10K_0402_5%
D SPI_HUB_CLK SPI_HUB_CS# SPI_HUB_MISO D
6 1 RI325 1 2 10K_0402_5%

CI120
SPI_HUB_MOSI 5 CLK CS# 3 SPI_HUB_WP# SPI_HUB_WP# RI326 1 2 10K_0402_5%
SPI_HUB_MISO 2 DI WP# 7 SPI_HUB_HD# SPI_HUB_MOSI RI327 1 2 10K_0402_5% 2
DO HOLD# SPI_HUB_CLK RI328 1 2 10K_0402_5%

GND
SPI_HUB_HD# RI329 1 2 10K_0402_5%

+3V_HUB W25X05CLSNIG_SO8

4
+AVDD12_HUB +DVDD12_HUB

+3V_HUB

12
45

29

37
27
1
7
UI132 +USB_VCCD +USB_VCCD
RI331 1 2 10K_0402_5% USB_OC3#_R

AVDD12
VP12_P3
VP12_P2
VP12_P0

DVDD12

DVDD33
V33

1/16W 5.1K +-5% 0402


10K_0402_5%
USB20_HUB_D_P3 3 41 USB20_P4
50 USB20_HUB_D_P3 USB20_HUB_D_N3 DP_P3 DP_P0 USB20_N4 USB20_P4 10
4 42

RI332

RI333
50 USB20_HUB_D_N3 USB30_HUB_D_TX_N3 DM_P3 DM_P0 USB20_N4 10
5 43 CI128 1 2 0.1U_6.3V_K_X5R_0201
50 USB30_HUB_D_TX_N3 USB30_HUB_D_TX_P3 TXN1_P3 TXN1_P0 USB30_ARX_HTX_N4 10
6 44 CI129 1 2 0.1U_6.3V_K_X5R_0201
50 USB30_HUB_D_TX_P3 USB30_ARX_HTX_P4 10

2
USB30_HUB_D_RX_N3 8 TXP1_P3 TXP1_P0 46 CI126 1 2 0.1U_6.3V_K_X5R_0201
50 USB30_HUB_D_RX_N3 USB30_HUB_D_RX_P3 RXN1_P3 RXN1_P0 USB30_ATX_HRX_N4 10 USB_HUB_RESET# USB_HUB_VBUSIN
9 47 CI127 1 2 0.1U_6.3V_K_X5R_0201
50 USB30_HUB_D_RX_P3 RXP1_P3 RXP1_P0 USB30_ATX_HRX_P4 10
USB30_HUB_D_TX_N2 10 31 SPI_HUB_MOSI
51 USB30_HUB_D_TX_N2 GL3523

1/16W_39K_1%_0402
TXN1_P2 P_SPI_DO

1
USB30_HUB_D_TX_P2 11 32 SPI_HUB_CLK
1

1U_0402_6.3V6K
51 USB30_HUB_D_TX_P2 TXP1_P2 P_SPI_CK

1
USB30_HUB_D_RX_N2 13 33 SPI_HUB_MISO
QFN-48

10K_0402_5%
51 USB30_HUB_D_RX_N2 USB30_HUB_D_RX_P2 RXN1_P2 P_SPI_DI SPI_HUB_CS#
14 34

RI334

CI121
51 USB30_HUB_D_RX_P2 USB20_HUB_D_P2 RXP1_P2 P_SPI_CZ
15

RI335
51 USB20_HUB_D_P2 USB20_HUB_D_N2 DP_P2 2
51 USB20_HUB_D_N2
16

2
DM_P2 35 USB_HUB_PGANG RI336 1 2 100K_0402_5%

2
18 PGANG 28 USB_HUB_RTERM RI337 1 2 20K_0402_1%
19 PWREN3J RTERM 30 USB_HUB_RESET#
RI338 1 @ 2 0_0402_5% USB_OC3#_R 20 OVCUR3J RESETJ 39 USB_HUB_X1
10,50 USB_OC3# 21 OVCUR2J X1 38 USB_HUB_X2
C C
PWREN2J X2
USB_HUB_1V2_FB 22 23
USB_HUB_1V2_SW 24 FB VSSP 49
SW GND

AVDD33_1
AVDD33_2
AVDD33_3
AVDD33

VDDP
USB_HUB_X2

VBUS
V5
GL3523-ONY10_QFN48_6X6 USB_HUB_X1
RI340 1 2 1M_0402_5%

48
40
2
17

25
26
36
+3V_HUB

1
RI341
0_0402_5%

USB_HUB_VBUSIN
YI1
+5VALW_HUB

2
1 4

0.1U_6.3V_K_X5R_0201
OSC1 GND2

10U_0603_6.3V6M
22U_0603_6.3V6-M
USB_HUB_X2_R

CC156
1 1 1 2 3
GND1 OSC2

CI123

CI124
2 2 2 25MHZ_10PF_7V25000014

USB_HUB_X2_R

USB_HUB_X1

1 1
B B
C3 C4
12P_0402_50V8 18P_0402_50V8
2 2

MAX 0.2A
+5VALW +5VALW_HUB

RX38
+5VALW 1 2

0_0603_5%

LP2301ALT1G_SOT23-3
+5VALW
3
S

QX37 1
1

RX40
100K_0201_5%
G
2

RX41
@
0_0402_5%
2

1 2
@
@
1

D 1
2 QX38
52 USB_HUB_RST_EN G L2N7002KWT1G_SOT323-3 CX29
0.1U_6.3V_K_X5R_0201
1

S 2
@
3

RX42
@
100K_0201_5%
2

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 USB3.0 Back Hub


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Wednesday, February 26, 2020 Sheet 38 of 83
5 4 3 2 1
5 4 3 2 1

SA000060U00, S IC PS8331BQFN60GTR-A2 QFN 60P DP SWITCH symbol & footprint apply


UR2
VDD33 +3VS

APU_EDP_TX0+ CR9 1 2 0.1u_0201_10V6K IN1D0P IN1D1N 5 50 MUX_PD


7 APU_EDP_TX0+ IN1_D1n PD
VDD33 21 49 RR46 1 2 1/10W_0_+-5%_0603
APU_EDP_TX0- CR10 1 2 0.1u_0201_10V6K IN1D0N IN2AUX 30 VDD33_1 VDD33_4 47
7 APU_EDP_TX0- IN2_PEQ IN2_AUXp CEXT MUX_EDP_TX0+
51 46
APU_EDP_TX1+ CR15 1 2 0.1u_0201_10V6K IN1D1P 57 IN2_PEQ/SCL_CTL OUT_D0p 45 MUX_EDP_TX0-
7 APU_EDP_TX1+ GND_5 OUT_D0n 1
44 EDP_HPD
APU_EDP_TX1- CR12 1 2 0.1u_0201_10V6K IN1D1N @ OUT_HPD 42 MUX_EDP_TX1- CR33
D 7 APU_EDP_TX1- IN1_HPD OUT_D1n 2.2U_0402_6.3V6M D
RR23 1 2 0_0201_5% 3 41
APU_EDP_TX2+ 7 APU_EDP_HPD IN1_HPD GND_4 2
CR18 1 2 0.1u_0201_10V6K IN1D2P IN1D1P 4
7 APU_EDP_TX2+ IN1_D1p
APU_EDP_TX2- CR19 1 2 0.1u_0201_10V6K IN1D2N IN1D2P 6 40 MUX_EDP_TX2+
7 APU_EDP_TX2- IN1_D2p OUT_D2p MUX_EDP_TX2-
IN1D2N 7 39
APU_EDP_TX3+ CR16 1 2 0.1u_0201_10V6K IN1D3P IN1D3P 9 IN1_D2n OUT_D2n 37 MUX_EDP_TX3+ VDD33
7 APU_EDP_TX3+ IN1_D3p OUT_D3p MUX_EDP_TX3-
IN1D3N 10 36
APU_EDP_TX3- CR17 1 2 0.1u_0201_10V6K IN1D3N IN2D0N 12 IN1_D3n OUT_D3n 35 VDD33
7 APU_EDP_TX3- IN2_HPD IN2_D0n VDD33_3 MUX_REXT
13 34 RR27 1 21/20W_4.99K_+-1%_0201
IN2D1N 15 IN2_HPD REXT 32 MUX_EDP_AUX
IN2_D1n OUT_AUXp_SCL 2
APU_EDP_AUX CR11 1 2 0.1u_0201_10V6K IN1AUX IN2D2P 16 31 MUX_EDP_AUX#
7 APU_EDP_AUX IN2_D2p OUT_AUXn_SDA CR32
APU_EDP_AUX# CR13 1 2 0.1u_0201_10V6K IN1AUX# 27 IN1AUX# 0.1u_0201_10V6K
7 APU_EDP_AUX# IN1_AUXn 1
24 26 VDD33
25 IN2_SDA VDD33_2 29 IN2AUX#
IN2_SCL IN2_AUXn 28 IN1AUX
22 IN1_AUXp
23 IN1_SDA
IN1_SCL 48 CA_DET RR43 1 2 1M_0402_5%
CA_DET 38 PC0
GPU_EDP_TX0+ CR20 1 2 0.1u_0201_10V6K IN2D0P IN1D0N 2 PC0
26 GPU_EDP_TX0+ VDD33 IN1_D0n MUX_EDP_TX1+
43
GPU_EDP_TX0- CR21 1 2 0.1u_0201_10V6K IN2D0N IN1D0P 1 OUT_D1p 33
26 GPU_EDP_TX0- IN1_D0p GND_3
VDD33 60
GPU_EDP_TX1+ CR22 1 2 0.1u_0201_10V6K IN2D1P VDD33_5
26 GPU_EDP_TX1+ MUX_EDP_TX0+
56 PI0

CR30

CR35

CR31

CR34

0.1u_0201_10V6K
MUX_EDP_TX0+ 41

0.01U_0201_10V6K

0.01U_0201_10V6K
GPU_EDP_TX1- CR23 1 2 0.1u_0201_10V6K IN2D1N IN2D2N 17 PI0 55 PC1

0.1u_0201_10V6K
26 GPU_EDP_TX1- IN2_D2n PC1 EDP_MUX_SW MUX_EDP_TX0-
2 1 1 2 IN2D3N 20 54
GPU_EDP_TX2+ IN2_D3n SW I2C_CTL_EN MUX_EDP_TX0- 41
CR24 1 2 0.1u_0201_10V6K IN2D2P 53
26 GPU_EDP_TX2+ IN1_AEQ# I2C_CTL_EN MUX_EDP_TX1+
59 8
GPU_EDP_TX2- IN2_AEQ# IN1_AEQ# GND_1 MUX_EDP_TX1+ 41
CR25 1 2 0.1u_0201_10V6K IN2D2N 58
26 GPU_EDP_TX2- 1 2 2 1 IN2_AEQ# MUX_EDP_TX1-
11 IN2D0P
GPU_EDP_TX3+ IN2_D0p MUX_EDP_TX1- 41
CR26 1 2 0.1u_0201_10V6K IN2D3P 19 IN2D3P
26 GPU_EDP_TX3+ IN2_D3p IN1_PEQ MUX_EDP_TX2+
IN2D1P 14 52
GPU_EDP_TX3- IN2_D1p IN1_PEQ/SDA_CTL MUX_EDP_TX2+ 41
CR27 1 2 0.1u_0201_10V6K IN2D3N Place near to PIN 60,21,49,26 18 61
26 GPU_EDP_TX3- GND_2 GND_6 MUX_EDP_TX2-
MUX_EDP_TX2- 41
C MUX_EDP_TX3+ C
GPU_EDP_AUX MUX_EDP_TX3+ 41
CR29 1 2 0.1u_0201_10V6K IN2AUX PS8331BQFN60GTR-A1_QFN60_5X9
26 GPU_EDP_AUX MUX_EDP_TX3-
GPU_EDP_AUX# CR28 MUX_EDP_TX3- 41
1 2 0.1u_0201_10V6K IN2AUX#
26 GPU_EDP_AUX# MUX_EDP_AUX#
MUX_EDP_AUX# 41
MUX_EDP_AUX
MUX_EDP_AUX 41
MUX_EDP_AUX# RR45 1 2 100K_0201_5%
VDD33
+1.8VS_AON MUX_EDP_AUX RR47 1 2 100K_0201_5%
IN1_AEQ# RR37 1 @ 21/20W_4.7K_5%_0201 VDD33

1
IN2_AEQ# RR36 1 @ 21/20W_4.7K_5%_0201
+5VS VDD33
RR42
10K_0201_5% IN2AUX# RR51 1 @ 2 100K_0201_5% VDD33

1 IN2AUX RR52 1 @ 2 100K_0201_5%

2
CR36
1U_0402_10V6K GPU_EDP_HPD
2 28 GPU_EDP_HPD VDD33
UR3
16 QR5822
Vcc 4 MMBT3904WH_SOT323-3
1A MUX_EDP_ENBKL 52

1
2 7 C
7 PCH_EDP_ENBKL GPU_EDP_ENBKL_B 1B1 2A MUX_EDP_ENVDD 41 IN2_HPD
3 9 2 RR48 1 2 100K_0201_5% RR49 1 2 0_0201_5% RR21
1B2 3A MUX_INVT_PWM 41 10K_0201_5%
5 12 B
7 PCH_EDP_ENVDD GPU_EDP_ENVDD_B 6 2B1 4A E
1

3
2B2

2
11 15 1 1
7 PCH_EDP_PWM

2
GPU_EDP_PWM_B 10 3B1 OE 1 EDP_MUX_SW CR39 RR50 CR38 MUX_PD
14 3B2 S 470P_25V_K_X7R_0201 CR37
4B1 100K_0201_5%
13 8 L: B1 2 EMC_NS@ 220P_25V_K_X7R_0201 220P_25V_K_X7R_0201
4B2 GND

1
17 H:B2 2 2 @

1
T-PAD RR22

1
CBT3257ABQ_DHVQFN16_2P5X3P5 1/20W_499_+-1%_0201 D QR5821
2 EDP_HPD
B MUX@ EDP_HPD 41 B
G

2
1 S

3
L2N7002KWT1G_SOT323-3
CR8
1U_6.3V_M_X5R_0201
2
+3VS
+3VS
UR4
1 5 for DDS
OE Vcc 08/06
GPU_EDP_PWM 2
28 GPU_EDP_PWM IN_A
2

3 4 GPU_EDP_PWM_B RR25
GND OUT_Y
4.7K_0402_5%
+3VALW @
M74VHC1GT125DF2G_SC70-5
1

EDP_MUX_SW
1

RR26
+3VS 10K_0201_5% VDD33 VDD33 VDD33 VDD33 VDD33 VDD33
UR5

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
for DDS @
3

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
1 5 08/06

RR40

RR38

RR28

RR30

RR32

RR34
2

OE Vcc

1
QR28B
D2

1
GPU_EDP_ENBKL 2 5 PJT7838_SOT363-6
28 GPU_EDP_ENBKL IN_A G2 @ @ @
3 4 GPU_EDP_ENBKL_B @ @ @
S2

GND OUT_Y

2
@
4

2
6

M74VHC1GT125DF2G_SC70-5 PI0 I2C_CTL_EN PC0 PC1 IN2_PEQ IN1_PEQ


QR28A

RR39

RR31

RR33
D1

1/20W_4.7K_5%_0201
EDP_SW 2

RR41

RR29

RR35
9 EDP_SW G1 PJT7838_SOT363-6

1
1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201

1/20W_4.7K_5%_0201
+3VS
S1

0_0201_5%
for DDS @ @ @ @ @
UR6 08/06 @
A A
1

1 5 Vgs(th)≤1.0V

2
OE Vcc
GPU_EDP_ENVDD 2
28 GPU_EDP_ENVDD IN_A
3 4 GPU_EDP_ENVDD_B
GND OUT_Y
RR24 1 2 0_0201_5%
M74VHC1GT125DF2G_SC70-5

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 EDP MUX


EDP_SW :Port switching control configuration; Internal pull down
at ~150KΩ, 3.3V I/O. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
L: Input Port1 is selected (default) C 1.0
H: Input Port2 is selected DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 39 of 83
5 4 3 2 1
A B C D E

1 1

2 删删DDS线线 2

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 DC V TO VS INTERFACE


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 1.0

Date: Monday, February 24, 2020 Sheet 40 of 83


A B C D E
5 4 3 2 1

LCD POWER CIRCUIT

+LCD_VDD +3VS

UG9
W=60mils 1 2 0_0603_5% 1 5
W=60mils V20B+ +LED_VDD
RG3
OUT IN FG3

4.7U_0603_6.3V6K

0.1u_0201_10V6K
2 2A 80 mil 2A 80 mil
GND 1 2
1 1
2 1 3 4
OCB EN
CG7

CG8
RG6 1 1
0_0402_5% 3A_32V_0497003PKRHF CG14 CG15 +5VALW
2 2 SY6288C20AAC_SOT23-5 4.7U_0805_25V6K 0.1U_0402_25V6 +5VALW
@
CD@ EMC@
2 2

1
RG67
D 470_0603_5% RG70 D
EMI Request
470_0603_5%

2
MUX_EDP_ENVDD LOGO_LED1_PWM_CONN
39 MUX_EDP_ENVDD @

2
YLOGO_LED_PWM_CONN
QG7 1 @

1
QG8 1

100K_0402_5%

.1U_0402_10V6-K
1 @ D
52 LOGO_LED1_PWM RG68 1 2 0_0402_5% 2 @ D

RG1

CG22
G 52 YLOGO_LED_PWM RG71 1 2 0_0402_5% 2
S G

2
2 2@ S

2
RG69 3 PJA138K_SOT23-3 PJA138K_SOT23-3
100K_0402_5% RG72 3
100K_0402_5%
modify by david 04/26

1
modify by david 04/26

1
need confirm LOGO ID
yong 07/23

EDP_HPD MUX_INVT_PWM LOGO_LED1_PWM_CONN YLOGO_LED_PWM_CONN


EMI request
1

1
RG5 RG2

1
100K_0201_5% 100K_0201_5% 1 DG6 1 DG7
EMC@ AZ5725-01F.R7GR_DFN1006P2X2 EMC@ AZ5725-01F.R7GR_DFN1006P2X2
CG101 EMC@ CG102 EMC@
2

0.1U_25V_K_X5R_0402 0.1U_25V_K_X5R_0402
2 2

2
2

2
C C

EMI request
BKOFF# MUX_INVT_PWM JEDP1
2A 80 mil 1
+LED_VDD 1
2
3 2
1 1 3
4
CG12 CG13 MUX_INVT_PWM 5 4
470P_25V_K_X7R_0201 470P_25V_K_X7R_0201 39 MUX_INVT_PWM BKOFF# 6 5
2 2 52 BKOFF# EDP_HPD 7 6
EMC_NS@ EMC_NS@
39 EDP_HPD 8 7
+LCD_VDD 1A Inrush 2A 8
9
10 9
11 10
MUX_EDP_AUX# CG21 1 2 0.1u_0201_10V6K EDP_AUX# 12 11
39 MUX_EDP_AUX# MUX_EDP_AUX EDP_AUX 12
select for LOGO_led PWR CG20 1 2 0.1u_0201_10V6K 13
39 MUX_EDP_AUX 14 13
06/12 yong
DMIC_DATA_R_CONN MUX_EDP_TX0+ CG19 1 2 0.1u_0201_10V6K EDP_TX0+ 15 14
+5VALW_LOGO 39 MUX_EDP_TX0+ MUX_EDP_TX0- EDP_TX0- 15
CG16 1 2 0.1u_0201_10V6K 16
1 2 0_0402_5% 39 MUX_EDP_TX0- 17 16
+5VS RG46 @
DMIC_CLK_R_CONN MUX_EDP_TX1+ CG18 1 2 0.1u_0201_10V6K EDP_TX1+ 18 17
1 39 MUX_EDP_TX1+ MUX_EDP_TX1- EDP_TX1- 18
CG17 1 2 0.1u_0201_10V6K 19
1 2 0_0402_5% Logo_led_Power 39 MUX_EDP_TX1- 20 19
CG28 +3VALW RG47 @
10P_50V_D_NPO_0201 MUX_EDP_TX2+ CG26 1 2 0.1u_0201_10V6K EDP_TX2+ 21 20
1 39 MUX_EDP_TX2+ MUX_EDP_TX2- CG27 EDP_TX2- 21
2 EMC_NS@ RG48 1 2 0_0603_5% 1 2 0.1u_0201_10V6K 22
+5VALW 39 MUX_EDP_TX2- 22
CG11 23
100P_50V_J_NPO_0201 MUX_EDP_TX3+ CG25 1 2 0.1u_0201_10V6K EDP_TX3+ 24 23
2 EMC_NS@ 39 MUX_EDP_TX3+ MUX_EDP_TX3- CG24 1 2 0.1u_0201_10V6K EDP_TX3- 25 24
39 MUX_EDP_TX3- 26 25
27 26
+3VS +3VS_DMIC +3VS_CMOS GSYNC# 28 27
29 28
+3VS_DMIC 30 29
LCD_OD# 31 30
1 2 0_0603_5% 9 LCD_OD# 32 31
RG81
RG106 1 2 0_0603_5% +3VS_DMIC 33 32
RG82 1 2@ 0_0402_5% DMIC_DATA_R_CONN 34 33
58 DMIC_DATA_R DMIC_CLK_R_CONN 34
2 RG83 1 2@ 0_0402_5% 35
58 DMIC_CLK_R 36 35
CG23
0.047U_0402_16V7K 37 36
CD@ RG51 1 @ 2 0_0402_5% USB20_N2_R 38 37
1 10 USB20_N2 1 2 0_0402_5% USB20_P2_R 39 38
RG52 @
+1.8VS_AON 10 USB20_P2 +3VS_CMOS 40 39
+3VS_CMOS 0.5A 40
41
YLOGO_LED_PWM_CONN RG77 1 2@ 0_0402_5% 42 41
LOGO_LED1_PWM_CONN RG78 1 2@ 0_0402_5% 43 42 46
2

RG65 44 43 GND2 45
B 10K_0402_5% +5VALW_LOGO 44 GND1 B
+3VALW CVILUX_CF69442D0R0-05-NH
ME@
1
2

RG66
GPU_FRAME_LOCK# 28
+LCD_VDD 10K_0402_5%
GSYNC@
3

For EMI
1

QG47B
D2
1

5 PJT7838_SOT363-6
RG64 G2 GSYNC@ EXC24CH900U_4P
USB20_N2 4 3 USB20_N2_R
S2

10K_0402_5% 4 3
GSYNC@
2

USB20_P2 1 2 USB20_P2_R
QG47A 1 2
D1

GSYNC# 2 PJT7838_SOT363-6 LG1


G1 EMC@
S1

GSYNC@
1

Vgs(th)≤1.0V

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 eDP/ CMOS/Touch screen


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 1.0

Date: Wednesday, February 26, 2020 Sheet 41 of 83


5 4 3 2 1
5 4 3 2 1

+1.8VS_AON

1
RG60
10K_0402_5%
@ update by bing
RG31 1 2 0_0402_5% HDMI1_TX0-_R

2
20180316
EMC_NS@
HDMI1_TX0- CG33 1 2 0.1u_0201_10V6K HDMI1_TX0-_C LG3 1 2 IFPC_HPD
26 HDMI1_TX0- 1 2 28 IFPC_HPD

HDMI D0 HDMI1_TX0+ CG32 1 2 0.1u_0201_10V6K HDMI1_TX0+_C


26 HDMI1_TX0+ 4 3 QG4
4 3 MMBT3904WH_SOT323-3

1
EXC24CH500U_4P
@ C
RG38 1 2 0_0402_5% HDMI1_TX0+_R 2 RG58 1 2 100K_0402_5% RG59 1 2 0_0402_5% HDMI1_HPD_CON
D D
B
E

3
1 1

1
CG29 CG30
RG57 220P_0402_50V7K 220P_0402_50V7K
@ 100K_0402_5% @
RG32 1 2 0_0402_5% HDMI1_TX1-_R 2 2

2
EMC_NS@
HDMI1_TX1- CG35 1 2 0.1u_0201_10V6K HDMI1_TX1-_C LG5 1 2
26 HDMI1_TX1- 1 2
HDMI D1 HDMI1_TX1+ HDMI1_TX1+_C
26 HDMI1_TX1+ CG34 1 2 0.1u_0201_10V6K 4 3 +3VALW_APU
4 3 V0.4
EXC24CH500U_4P
@
RG37 1 2 0_0402_5% HDMI1_TX1+_R

@
RG33 1 2 0_0402_5% HDMI1_TX2-_R

EMC_NS@ HPD

1
HDMI1_TX2- CG37 1 2 0.1u_0201_10V6K HDMI1_TX2-_C LG4 1 2
26 HDMI1_TX2- 1 2
HDMI D2 RG61

2
1M_0402_5%
HDMI1_TX2+ HDMI1_TX2+_C

G
26 HDMI1_TX2+ CG36 1 2 0.1u_0201_10V6K 4 3
4 3

3
HDMI_HPD HDMI1_HPD_CON

1
EXC24CH500U_4P
@
HDMI1_TX2+_R 10 HDMI_HPD
RG36 1 2 0_0402_5%

D
@
RG34 1 2 0_0402_5% HDMI1_CLK-_R QG6

1
PJA138K_SOT23-3
EMC_NS@ RG62
HDMI1_TXC- CG39 1 2 0.1u_0201_10V6K HDMI1_CLK-_C LG2 1 2 100K_0402_5%
26 HDMI1_TXC- 1 2

2
HDMI1_TXC+ CG38 1 2 0.1u_0201_10V6K HDMI1_CLK+_C 4 3
HDMI CLK 26 HDMI1_TXC+ 4 3
EXC24CH500U_4P
@
RG35 1 2 0_0402_5% HDMI1_CLK+_R V0.4
C C

HDMI1_TX0+_C RG15 1 2 499_0402_1% HDMI1_TX0+_B RG23 1 2 0_0402_5%

HDMI1_TX0-_C RG16 1 2 499_0402_1% HDMI1_TX0-_B RG24 1 2 0_0402_5%

HDMI1_TX1+_C RG17 1 2 499_0402_1% HDMI1_TX1+_B RG25 1 2 0_0402_5%

HDMI1_TX1-_C RG18 1 2 499_0402_1% HDMI1_TX1-_B RG26 1 2 0_0402_5%

HDMI1_TX2+_C RG19 1 2 499_0402_1% HDMI1_TX2+_B RG27 1 2 0_0402_5%

HDMI1_TX2-_C RG20 1 2 499_0402_1% HDMI1_TX2-_B RG63 1 2 0_0402_5%

HDMI1_CLK+_C RG21 1 2 499_0402_1% HDMI1_CLK+_B RG29 1 2 0_0402_5%

HDMI1_CLK-_C RG22 1 2 499_0402_1% HDMI1_CLK-_B RG30 1 2 0_0402_5%

V1.0

+5VS +5VS_HDMI1_F +5VS_HDMI1


1

D QG1 QG5
+3VS 2 LP2301ALT1G_SOT23-3
G 2N7002KW_SOT323-3 FG2
1 3 1 2

S
S
3

1.1A_8V_1206L110THYR
RG4 1 @ 2

G
2
100K_0402_5%
62 SUSP
B B

2
DG1 @ RG43 RG45 @
HDMI1_HPD_CON 1 1 10 9 HDMI1_HPD_CON 0_0805_5%
0_0805_5% 1
CG31
HDMI1_DAT_CON 2 2 9 8 HDMI1_DAT_CON DG4 DG5 .1U_0402_10V6-K

1
RB751V-40_SOD323-2 RB751V-40_SOD323-2
HDMI1_CLK_CON 4 4 HDMI1_CLK_CON 2
7 7 V1.0
+5VS_HDMI1 5 5 6 6 +5VS_HDMI1

1
3 3 NV suggestion
RG53 RG54
8 2.2K_0402_5% 2.2K_0402_5%

2
AZ1045-04F_DFN2510P10E-10-9 JHDMI1
HDMI1_HPD_CON 19
EMC_NS@ Hot_Plug_Detect
18
17 +5V_Power
+1.8VS_VGA +1.8VS_AON +1.8VS_VGA +1.8VS_AON HDMI1_DAT_CON 16 DDC/CEC_GND
DG2 HDMI1_CLK_CON 15 SDA
HDMI1_TX0-_R 1 1 HDMI1_TX0-_R SCL
10 9 14
13 Utility 20
CEC GND1
2

HDMI1_TX0+_R 2 2 9 8 HDMI1_TX0+_R HDMI1_CLK-_R RG14 1 2 1/16W_6.8_5%_0402 HDMI1_CLK-_CON 12


RG41 RG42 RG39 RG40 11 TDMS_Clock- 21
HDMI1_CLK-_R 4 4 HDMI1_CLK-_R HDMI1_CLK+_R HDMI1_CLK+_CON TDMS_Clock_Shield GND2
7 7 @ 0_0402_5% 0_0402_5% @ 0_0402_5% 0_0402_5% RG13 1 2 1/16W_6.8_5%_0402 10
HDMI1_TX0-_R RG8 1 2 1/16W_6.8_5%_0402 HDMI1_TX0-_CON 9 TDMS_Clock+ 22
HDMI1_CLK+_R 5 5 HDMI1_CLK+_R TDMS_Data0- GND3
6 6 8
1

HDMI1_TX0+_R RG7 1 2 1/16W_6.8_5%_0402 HDMI1_TX0+_CON 7 TDMS_Data0_Shield 23


3 3 AUX V1.0 V1.0 HDMI1_TX1-_R RG10 1 2 1/16W_6.8_5%_0402 HDMI1_TX1-_CON 6
5
TDMS_Data0+
TDMS_Data1-
GND4

8 HDMI1_TX1+_R RG9 1 2 1/16W_6.8_5%_0402 HDMI1_TX1+_CON 4 TDMS_Data1_Shield


TDMS_Data1+
1

NV suggestion HDMI1_TX2-_R RG12 1 2 1/16W_6.8_5%_0402 HDMI1_TX2-_CON 3


RG56 RG55 2 TDMS_Data2-
AZ1045-04F_DFN2510P10E-10-9 10K_0402_5% 10K_0402_5% HDMI1_TX2+_R RG11 1 2 1/16W_6.8_5%_0402 HDMI1_TX2+_CON 1 TDMS_Data2_Shield
For EMC TDMS_Data2+
2

EMC_NS@
ALLTO_C128AU-K1939-L
G1

HDMI1_DAT_CON ME@
6 1
D1 S1 HDMI1_DAT 26
A DG3 A
HDMI1_TX1-_R 1 1 10 9 HDMI1_TX1-_R PJT7838_SOT363-6
QG3A
HDMI1_TX1+_R 2 2 9 8 HDMI1_TX1+_R
5

HDMI1_TX2-_R 4 4 7 7 HDMI1_TX2-_R
G2

HDMI1_TX2+_R 5 5 6 6 HDMI1_TX2+_R HDMI1_CLK_CON 3 4


D2 S2 HDMI1_CLK 26
3 3
Vgs(th)≤1V PJT7838_SOT363-6
8 QG3B
For EMC Security Classification LC Future Center Secret Data Title

AZ1045-04F_DFN2510P10E-10-9 Issued Date 2019/07/02 Deciphered Date 2020/02/24 HDMI_CONN


EMC_NS@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y540 1.0

Date: Monday, February 24, 2020 Sheet 42 of 83


5 4 3 2 1
4 3 2 1

+3VALW
+VBUS_P0 +5VALW +LDO_3V3

2
RT11
0_0402_5%

1
RA=RT42

1
RT45 RT41 RT42@
@
200K_0402_1% 590K_0402_1% 0_0402_5%

2
D D

2
G
VMON LOC_PWR_MON

1 6 SM_CK

S
52,53,54,60 EC_SMB_CK0

D
1

5
RB=RT47

G
VMON: RT40 RT46 QT1A
Used to monitor VBUS voltage. 10K_0402_1% 10K_0402_1% RT47 2N7002KDWH_SOT363-6
Divide the VBUS voltage down to ADC full-scale input of 1.2V. 10K_0402_1% EC @
SM_SDA
Then connect the divided voltage to this pin. 4 3

S
52,53,54,60 EC_SMB_DA0

D
QT1B 2N7002KDWH
2N7002KDWH_SOT363-6 Vth= min 1V, max 2.5V
@ ESD 2KV

@
RT10 1 2 0_0402_5%

+5VALW
+VCON_IN +VCON_IN @
500mA 100mA 100mA RT9 1 2 0_0402_5%
10U_0805_10V6K

.1U_0402_10V6-K

+5VALW +5V_IN
1 2
CT102

CT101

RT48@ 2 1 0_0603_5% +VCON_IN

2 1 R103 1 2 0_0603_5%

+5V_IN
1
CT1
place close to pin13 10U_0603_10V6K
C 2 C

1 3
D

VDS=-20 1 1

4.7U_10V_K_X5R_0402
QT2
VGS=+-8V

CT2
AO3413_SOT23-3 CT3
G
2

SB93413000J Id=3A 10U_0603_10V6K


2 2
Vth=-1v

I2C1_IRQ# +LDO_3V3
RT55 2 1 47K_0402_5% 1
CT4 for redriver pin control mode used
4.7U_0402_6.3V6M This pin can be fonfigured as digital GPIO via F/W
2 in some applications
06/13 yong

13

21

15
UT2 RT14 1 2 0_0402_5%
PS8747_FLIP_C1 44

LDO_3V3
VCON_IN

5V_IN
for redriver pin control mode used RT16 1 2@ 0_0402_5% 7 11 PS8747_FLIP_C1_R EMC@
44 PS8747_USB_MODE_C1 AUX_N/MGPIO5 BB_DM/MGPIO1 VBUS_DSCHG
RT15 1 2@ 0_0402_5% 6 10 CT5 1 2 220P_0402_50V7-J
06/13 yong 44 PS8747_DP_MODE_C1 AUX_P/MGPIO4 BB_DP/MGPIO0 VBUS_DSCHG 45
9 14 USBC_CC2_CONN
SBU2/MGPIO7 CC2 USBC_CC1_CONN USBC_CC2_CONN 45
8 12
SBU1/MGPIO6 CC1 USBC_CC1_CONN 45
CT6 1 2 220P_0402_50V7-J

EMC@
22 1 INT#_TYPEC_R RT58 1 2 0_0402_5% RTS5457_SM_INT
45 VBUS_EN
I2C1_IRQ#
I2C_EN/GPIO10 RTS5457T-GR SM_INT/GPIO4
SM_SDA_R SM_SDA
RTS5457_SM_INT 9,52
5 24 RT215 1 2 0_0402_5%
I2C_INT/GPIO9 SM_SDA/GPIO6
REPETER_SDA RT17 1 @ 2 0_0402_5% 23 3 SM_CK_R RT216 1 2 0_0402_5% SM_CK
44 REPETER_SDA I2C_SDA/GPIO8 SM_SCL/GPIO5
REPETER_SCL RT18 1 @ 2 0_0402_5% 4
44 REPETER_SCL I2C_SCL/GPIO7
20 RT59 1 2 6.2K_0402_1%
REXT
LOC_PWR_MON 19 16
@ RT60 for dead battery
RT60 1 2 0_0402_5%
B LOC_PWR_MON DB_CFG Stuff: disable B

45 TYPE_C_OCP#
18
IMON_MGPIO8 HPD/GPIO3
2 TYPE-C_DP_RE_HPD
TYPE-C_DP_RE_HPD 44 unStuff: Enable
VMON 17 25
VMON_MGPIO9 E-PAD
+3VALW

RTS5457T-GR_QFN24_4X4

INT#_TYPEC_R 1 2 RT978 4.7K_0402_5%

SM_CK 1 @ 2 RT977 4.7K_0402_5%

SM_SDA 1 @ 2 RT979 4.7K_0402_5%

+LDO_3V3

I2C1_IRQ# 1 2 RT980 4.7K_0402_5%

REPETER_SDA 1 @ 2 RT981 4.7K_0402_5%

REPETER_SCL 1 @ 2 RT982 4.7K_0402_5%

RTS5457_SM_INT 1 @ 2 RT983 4.7K_0402_5%

Modify by Yong@05/14

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2019/07/02 Deciphered Date 2020/02/24 USB TYPE-C Controller
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 43 of 83
4 3 2 1
5 4 3 2 1

+3VS +3VALW

@ +3VS_RE1
RR20 1 2 0_0603_5%

RR1 1 2 1/2W_0.01_+-1%_0603_50PPM/C

@
1 1 1 1
CR3 CR4 CR2 CR1
D D

10U 6.3V M X5R 0402

10U 6.3V M X5R 0402

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
@
2 2 2 2

20
28

17
6
UR1
CR43 1 2 0.1U_6.3V_K_X5R_0201 TYPE-C_DP_RE_TXP0 9

VDD_DCI
VDD33_1
VDD33_2
VDD33_3
26 GPU_SNK0_DP0P TYPE-C_DP_RE_TXN0 ML0P
CR44 1 2 0.1U_6.3V_K_X5R_0201 10
26 GPU_SNK0_DP0N TYPE-C_DP_RE_TXP3 ML0N
CR46 1 2 0.1U_6.3V_K_X5R_0201 18
26 GPU_SNK0_DP3P TYPE-C_DP_RE_TXN3 ML3P
CR45 1 2 0.1U_6.3V_K_X5R_0201 19
26 GPU_SNK0_DP3N ML3N +3VS_RE1
PS8747_SSDE1 11 30
PS8747_CDE1 SSDE/DCI_DATA RX1P TYPEC_RXP1 45
14 31 TYPEC_RXN1 45
CDE/DCI_CLK RX1N 40
USB30_RX_P0_MUX RX2P TYPEC_RXP2 45
CR54 1 2 0.33U_25V_K_X5R_0201 5 39 TYPEC_RXN2 45
10 TYPE-C_USB3_RX_P0 CR53 1 2 0.33U_25V_K_X5R_0201 USB30_RX_N0_MUX 4 SSRXP RX2N RR18 2 1 1/20W_4.7K_5%_0201 PS8747_DP_MODE_C1
10 TYPE-C_USB3_RX_N0 CR51 1 2 0.22U_6.3V_K_X5R_0201 USB30_TX_P0_MUX 8 SSRXN
10 TYPE-C_USB3_TX_P0 CR52 1 2 0.22U_6.3V_K_X5R_0201 USB30_TX_N0_MUX 7 SSTXP
10 TYPE-C_USB3_TX_N0 SSTXN 33 RR19 2 1 1/20W_4.7K_5%_0201 PS8747_FLIP_C1
TX1P TYPEC_TXP1 45
10/16 david Modify 34
TYPE-C_DP_RE_TXP2 TX1N TYPEC_TXN1 45
CR50 1 2 0.1U_6.3V_K_X5R_0201 15 37
26 GPU_SNK0_DP2P TYPE-C_DP_RE_TXN2 ML2P TX2P TYPEC_TXP2 45 PS8747_USB_MODE_C1
CR49 1 2 0.1U_6.3V_K_X5R_0201 16 36 RR11 2 1
26 GPU_SNK0_DP2N TYPE-C_DP_RE_TXP1 ML2N TX2N TYPEC_TXN2 45
CR47 1 2 0.1U_6.3V_K_X5R_0201 12 1/20W_4.7K_5%_0201
26 GPU_SNK0_DP1P TYPE-C_DP_RE_TXN1 ML1P
CR48 1 2 0.1U_6.3V_K_X5R_0201 13
26 GPU_SNK0_DP1N ML1N pin control mode, connect to PDC
CR41 1 2 0.1U_6.3V_K_X5R_0201 GPU_DDI2_M_AUXP 24 follow yoga740 change to stuff
26 GPU_SNK0_AUX_DP CR42 1 2 0.1U_6.3V_K_X5R_0201 GPU_DDI2_M_AUXN 25 AUXP 1 internally PD 150K 07/01 YONG
26 GPU_SNK0_AUX_DN AUXN CEXT 23 PS8747_DP_MODE_C1
PS8747_I2C_CTRL1 CE_DP PS8747_USB_MODE_C1 PS8747_DP_MODE_C1 43
29 35
PS8747_ADDR1 I2C_EN CE_USB PS8747_FLIP_C1 PS8747_USB_MODE_C1 43
3 38
DCICFG/ADDR FLIP USBC_DPAUX1_CONN PS8747_FLIP_C1 43
C 27 C
SBU1 USBC_DPAUX1_CONN 45
RR4 1 @ 20_0201_5% PS8747_SCL1 21 26 USBC_DPAUX2_CONN
43 REPETER_SCL DPEQ/CSCL SBU2 USBC_DPAUX2_CONN 45
RR3 1 @ 20_0201_5% PS8747_SDA1 22 32 TYPE-C_DP_RE_HPD
43 REPETER_SDA CEQ/CSDA IN_HPD TYPE-C_DP_RE_HPD 43

EPAD
2
REXT

1
1

41
RR2 PS8747BQFN40GTR-B1_QFN40_6X4
4.99K_0402_1% CR5
2.2U_0402_6.3V6M
2
2

+1.8VS_AON

HPD

1
RR57
10K_0402_5%

2
IFPA_HPD
28 IFPA_HPD
to NV GPU
QR8
+3VS_RE1 MMBT3904WH_SOT323-3

1
C
2 @ 1 PS8747_SCL1 RR13 1 2 1/20W_4.7K_5%_0201 2 RR56 1 2 100K_0402_5% RR53 1 2 0_0402_5% TYPE-C_DP_RE_HPD
RR5 1/20W_4.7K_5%_0201 B
E

1
2 1 PS8747_SDA1 RR14 1 2 1/20W_4.7K_5%_0201

1
RR6 1/20W_4.7K_5%_0201 RR55 1
100K_0402_5% CR40 RR54
2 @ 1 PS8747_I2C_CTRL1 RR15 1 2 1/20W_4.7K_5%_0201 220P_0402_50V7K 100K_0402_5%
RR7 1/20W_4.7K_5%_0201

2
2

2
Automatic DCI mode ent 2 1 PS8747_ADDR1 RR12 2 1 1/20W_4.7K_5%_0201
ering enabled @ @
B B
RR8 1/20W_4.7K_5%_0201

2 @ 1 PS8747_SSDE1
RR9 1/20W_4.7K_5%_0201
to APU TYPE-C_DP_HPD RR58 1 2 0_0402_5% TYPE-C_DP_RE_HPD
PS8747_CDE1 8 TYPE-C_DP_HPD
2 @ 1
RR10 1/20W_4.7K_5%_0201

+3VS

RR16 1 2 100K_0201_5% GPU_DDI2_M_AUXN


Setting:
1. PS8747_I2C_CTRL=L, I2C disable RR17 1 2 100K_0201_5% GPU_DDI2_M_AUXP
2. PS8747_SCL/DPEQ=L, DP Receiver equalization Compensation for channel loss up to 7dB
3. PS8747_SDA/CEQ=L, USB Type-C connector facing RX channel receiver equalization setting Compensation
4.ADDR/DCICFG=M, Automatic DCI mode entering enabled for channel loss up to 7dB
5. CDE/DCICLK=L,When NO DCI mode-->USB Type-C connector facing TX channel De-emphasis setting -3.5dB Output De-emphasis(default)
6. SSDE/DCIDAT=L,When NO DCI mode-->USB HOST facing TX channel De-emphasis setting -3.5dB Output De-emphasis(default)

100P 25V J NPO 0201

100P 25V J NPO 0201


1 1
@ @

2 2

CR7

CR6
A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 DDI Redriver PS8330


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 44 of 83
5 4 3 2 1
4 3 2 1

RT63 1 @ 2 0_0402_5%

LT6 TYPE-C_USB20_P0_C
USB20_N0 4 3 TYPE-C_USB20_N0_C TYPE-C_USB20_N0_C
10 USB20_N0 4 3

USB20_P0 1 2 TYPE-C_USB20_P0_C
10 USB20_P0 1 2

GND4
GND3
GND2
GND1
EXC24CH900U_4P

AZ5425-01F_DFN1006P2E2

AZ5425-01F_DFN1006P2E2
2

2
EMC@ DT18 DT22
JUSBC1

2
RT81 1 @ 2 0_0402_5%

GND8
GND7
GND6
GND5
B12 A1
GND4 GND1
TYPE-C_RX1_P_C B11 A2 TYPE-C_TX1_P_C
SSRXp1 SSTXp1

1
@
RT84 1 2 0_0402_5% TYPE-C_RX1_N_C B10 A3 TYPE-C_TX1_N_C EMC_NS@ EMC_NS@

1
SSRXn1 SSTXn1
B9 A4
+VBUS_P0 Vbus4 Vbus1 +VBUS_P0
LT1 @ USBC_DPAUX2_CONN B8 A5 USBC_CC1_CONN
TYPEC_TXN1 TYPE-C_TX1_N_R TYPE-C_TX1_N_C 44 USBC_DPAUX2_CONN SBU2 CC1 USBC_CC1_CONN 43
CT30 1 2 0.22U_25V_K_X5R_0402 1 2
44 TYPEC_TXN1 1 2 TYPE-C_USB20_N0_C TYPE-C_USB20_P0_C
B7 A6
Dn2 Dp1
TYPEC_TXP1 CT31 1 2 0.22U_25V_K_X5R_0402 TYPE-C_TX1_P_R 4 3 TYPE-C_TX1_P_C TYPE-C_USB20_P0_C B6 A7 TYPE-C_USB20_N0_C
44 TYPEC_TXP1 4 3 Dp2 Dn1 USBC_DPAUX1_CONN USBC_DPAUX2_CONN
EXC24CH500U_4P USBC_CC2_CONN B5 A8 USBC_DPAUX1_CONN
43 USBC_CC2_CONN CC2 SBU1 USBC_DPAUX1_CONN 44

1
B4 A9
@ +VBUS_P0 Vbus3 Vbus2 +VBUS_P0 R2 R1
RT86 1 2 0_0402_5% TYPE-C_TX2_N_C B3 A10 TYPE-C_RX2_N_C 2M_0402_5% 2M_0402_5%
SSTXn2 SSRXn2
D D
TYPE-C_TX2_P_C B2 A11 TYPE-C_RX2_P_C

2
SSTXp2 SSRXp2
@ B1 A12

GND10
GND3 GND2

GND9
RT89 1 2 0_0402_5%

DT21
USBC_DPAUX1_CONN 9 10 1 1 USBC_DPAUX1_CONN

GND5
GND6
LT22 EMC_NS@ HIGHSTAR-UB11249-B200W-1H
TYPEC_TXP2 CT33 1 2 0.22U_25V_K_X5R_0402 TYPE-C_TX2_P_R 1 2 TYPE-C_TX2_P_C USBC_DPAUX2_CONN 8 9 2 2 USBC_DPAUX2_CONN
44 TYPEC_TXP2 1 2
USBC_CC1_CONN 7 7 4 4 USBC_CC1_CONN
TYPEC_TXN2 CT32 1 2 0.22U_25V_K_X5R_0402 TYPE-C_TX2_N_R 4 3 TYPE-C_TX2_N_C
44 TYPEC_TXN2 4 3 USBC_CC2_CONN USBC_CC2_CONN
6 6 5 5
EXC24CH500U_4P
3 3

@ 8
RT91 1 2 0_0402_5%
AZ1045-04F_DFN2510P10E-10-9
EMC_NS@

@
RT92 1 2 0_0402_5%

DT19
TYPE-C_RX2_P_C 10 1 TYPE-C_RX2_P_C
NC1 Line-1
LT13 TYPE-C_RX2_N_C TYPE-C_RX2_N_C
9 2
TYPEC_RXN1 CT27 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX1_N 1 2 TYPE-C_RX1_N_C NC2 Line-2
44 TYPEC_RXN1 1 2 TYPE-C_TX2_P_C TYPE-C_TX2_P_C
7 4
NC3 Line-3
TYPEC_RXP1 CT26 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX1_P 4 3 TYPE-C_RX1_P_C TYPE-C_TX2_N_C 6 5 TYPE-C_TX2_N_C
44 TYPEC_RXP1 4 3 NC4 Line-4
3
EXC24CH500U_4P GND1
EMC_NS@ 8
GND2
@ AZ1143-04F-R7G_DFN2510P10E10
RT98 1 2 0_0402_5% EMC_NS@

@
RT100 1 2 0_0402_5%
DT20
TYPE-C_TX1_N_C 10 1 TYPE-C_TX1_N_C
LT21 NC1 Line-1
EMC_NS@ TYPE-C_TX1_P_C 9 2 TYPE-C_TX1_P_C
TYPEC_RXP2 CT28 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX2_P 1 2 TYPE-C_RX2_P_C NC2 Line-2
44 TYPEC_RXP2 1 2 TYPE-C_RX1_N_C TYPE-C_RX1_N_C
7 4
NC3 Line-3
TYPEC_RXN2 CT29 1 2 0.33U_10V_K_X5R_0402 TYPE-C_RX2_N 4 3 TYPE-C_RX2_N_C TYPE-C_RX1_P_C 6 5 TYPE-C_RX1_P_C
44 TYPEC_RXN2 4 3 NC4 Line-4
EXC24CH500U_4P 3
GND1
8
@ GND2
RT101 1 2 0_0402_5% AZ1143-04F-R7G_DFN2510P10E10
EMC_NS@

modify by grace 12/31 V0.4

C C

是是需是是? +VBUS_P0 +VBUS_P0


1

AZ5725-01F.R7GR_DFN1006P2X2
RT171

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K

0.47U_0402_25V6K
10U_0805_25V6K
High enable discharge @ 470_0603_5%

1
Low disable discharge 1 1 1 1 1

CT11

CT9

CT8

CT7
CT10
1
2

EMC_NS@

DT1
RT2
1

0_0402_5% QT3 D 2 2 2 2 2
VBUS_DSCHG 1 2 2
43 VBUS_DSCHG

2
@ G @
update by bing 0523

2
2

S 2N7002KW_SOT323-3
3

RT3
@ 100K_0402_5%
1

+LDO_3V3
3A
+5VALW +VBUS_P0
2

UT1
RT12
5 1 10K_0402_5%
IN OUT
B B
2
1

GND
VBUS_EN 4 3 TYPE_C_OCP#
43 VBUS_EN TYPE_C_OCP# 43
2

EN FLAG
Active high RT13 G517G1TO1U_TSOT-23-5
100K_0402_5%
1

+5VALW
Place close to UT1.5
CT12 1 yong 07/01
22U_0603_6.3V6-M

22U_0603_6.3V6-M

1 1
150U_B2_6.3VM_R35M

@ 2 2
2
CT13

CT14

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2019/07/02 Deciphered Date 2020/02/24 USB TYPE-C Port
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 45 of 83
4 3 2 1
A B C D E

+3.3V_NGFF1 +3.3V_NGFF1

1
M.2 SSD1(SATA/PCIE) 2
C1
0.1U_6.3V_K_X5R_0201 PR8117
10K_0402_5%

5
U134

2
+3VS +3.3V_NGFF1

VCC
PLT_RST# 1
8,28,47,55,56 PLT_RST# IN1 SSD_RST#
@ 2A OUT
4
RF9 1 2 0_0805_5% APU_SSD_RST# 2

GND
8 APU_SSD_RST# IN2

CF37
22U_0603_6.3V6-M
1 1 1

1
CF38
4.7U_0402_6.3V6M
@ CF39 1 MC74VHC1G08DFT2G_SC70-5

3
.1U_0402_10V6-K CC170 PR8118
@ 1000P_0402_50V7K 10K_0402_5%
2 2 2
2

NGFF1

2
JSSD1 +3.3V_NGFF1

1 2
3 GND_1 3.3V_1 4
1 PCIE_PRX_DTX_N11 5 GND_2 3.3V_2 6 1
5 PCIE_PRX_DTX_N11 PCIE_PRX_DTX_P11 PERN3 N/C_2 2
7 8 CF40
5 PCIE_PRX_DTX_P11 PERP3 N/C_3
9 10 .1U_0402_10V6-K
PCIE_PTX_DRX_N11 CF17 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N11_C 11 GND_3 DAS/DSS# 12
5 PCIE_PTX_DRX_N11 PCIE_PTX_DRX_P11 PCIE_PTX_DRX_P11_C PETN3 3.3V_3 1
CF18 2 1 0.22U_0201_6.3V6-K 13 14
5 PCIE_PTX_DRX_P11 PETP3 3.3V_4 +3.3V_NGFF1
15 16
PCIE_PRX_DTX_N10 17 GND_4 3.3V_5 18
5 PCIE_PRX_DTX_N10 PCIE_PRX_DTX_P10 PERN2 3.3V_6
19 20
5 PCIE_PRX_DTX_P10 PERP2 N/C_4
21 22
PCIE_PTX_DRX_N10 CF19 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N10_C 23 GND_5 N/C_5 24
5 PCIE_PTX_DRX_N10 PETN2 N/C_6

1
PCIE_PTX_DRX_P10 CF21 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P10_C 25 26
5 PCIE_PTX_DRX_P10 PETP2 N/C_7
27 28 RF10
PCIE_PRX_DTX_N9 29 GND_6 N/C_8 30 10K_0201_5%
5 PCIE_PRX_DTX_N9 PCIE_PRX_DTX_P9 PERN1 N/C_9
31 32
5 PCIE_PRX_DTX_P9 PERP1 N/C_10
33 34
D1

2
PCIE_PTX_DRX_N9 CF20 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N9_C 35 GND_7 N/C_11 36
5 PCIE_PTX_DRX_N9 PCIE_PTX_DRX_P9 PCIE_PTX_DRX_P9_C PETN1 N/C_12 SATA_DEVSLP0
CF14 2 1 0.22U_0201_6.3V6-K 37 38 2 1
5 PCIE_PTX_DRX_P9 PETP1 DEVSLP SATA_DEVSLP0 8
39 40
PCIE_SATA_PRX_DTX_P8 41 GND_8 N/C_13 42
5 PCIE_SATA_PRX_DTX_P8 PCIE_SATA_PRX_DTX_N8 PERN0/SATA-B+ N/C_14 RB521CM-30T2R_VMN2M-2
43 44
5 PCIE_SATA_PRX_DTX_N8 PERP0/SATA-B- N/C_15

1
45 46 @
PCIE_SATA_PTX_DRX_N8 CF15 2 1 0.22U_0201_6.3V6-K PCIE_SATA_PTX_DRX_N8_C 47 GND_9 N/C_16 48 RF12
5 PCIE_SATA_PTX_DRX_N8 PCIE_SATA_PTX_DRX_P8 PCIE_SATA_PTX_DRX_P8_C PETN0/SATA-A- N/C_17 SSD_RST#
CF16 2 1 0.22U_0201_6.3V6-K 49 50 10K_0201_5%
5 PCIE_SATA_PTX_DRX_P8 PETP0/SATA-A+ PERST# SSD_CLKREQ1#
51 52
CLK_PCIE_SSD1# GND_10 CLKREQ# SSD_CLKREQ1# 9
53 54 1 1
9 CLK_PCIE_SSD1#

2
CLK_PCIE_SSD1 55 REFCLKN PEWAKE# 56 @ CF41
9 CLK_PCIE_SSD1 REFCLKP N/C_18
57 58 TPF2 1000P_0402_50V7K
+3.3V_NGFF1 GND_11 N/C_19

1
59 NC 60 NC 2
RF13 61 NC 62 NC RF22 1 @ 2 SUSCLK_R
10K_0201_5% 63 NC 64 NC
@ 65 NC 66 NC 0_0201_5%
67 68 SUSCLK_SSD1 +3.3V_NGFF1 SUSCLK是是需需是是?

2
PEDET1 69 N/C_1 SUSCLK 70
71 PEDET 3.3V_7 72
73 GND_12 3.3V_8 74
75 GND_13 3.3V_9

0.1u_0201_10V6K

CF143
22U_0603_6.3V6-M
GND_14 1 1 1

0.01U_0201_10V6K
CF42
PEDET (PE_DTCT) RF14 77 76

CF36
PEG1 PEG2

@
10K_0201_5%
SATA Device GND @ 2 2 2
PCIe Device Open ARGOS_NASM0-S6701-TS40

2
ME@
SSD_DET#
0 - SATA
1 - PCIE

+3VALW_APU

2
2 RF18 2
10K_0402_5%

1
PEDET1 RF15 1 2@ 0_0402_5%
SSD_SATA_PCIE_DET1# 8

M.2 SSD0(PCIE)
+3VS +3.3V_NGFF

@ 2A
RF1 1 2 0_0805_5%
CF24
22U_0603_6.3V6-M

1 1 1
CF25
4.7U_0402_6.3V6M

@ CF26
.1U_0402_10V6-K
@
2 2 2

JSSD0
NGFF
76 +3.3V_NGFF
GND15
1 2
3 GND1 3.3V_1 4
PCIE_PRX_DTX_N4 5 GND2 3.3V_2 6
5 PCIE_PRX_DTX_N4 PCIE_PRX_DTX_P4 PERn3 N/C_2 2
7 8 CF23
3 5 PCIE_PRX_DTX_P4 PERp3 N/C_3 3
9 10 .1U_0402_10V6-K
PCIE_PTX_DRX_N4 CF12 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N4_C 11 GND3 DAS/DSS#(I/O)/LED1#(I)(0/3.3V) 12
5 PCIE_PTX_DRX_N4 PCIE_PTX_DRX_P4 PCIE_PTX_DRX_P4_C PETn3 3.3V_3 1
CF13 2 1 0.22U_0201_6.3V6-K 13 14
5 PCIE_PTX_DRX_P4 PETp3 3.3V_4 +3.3V_NGFF
15 16
PCIE_PRX_DTX_N5 17 GND4 3.3V_5 18
5 PCIE_PRX_DTX_N5 PCIE_PRX_DTX_P5 PERn2 3.3V_6
19 20
5 PCIE_PRX_DTX_P5 PERp2 N/C_4
21 22
PCIE_PTX_DRX_N5 CF10 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N5_C 23 GND5 N/C_5 24
5 PCIE_PTX_DRX_N5 PETn2 N/C_6
1

PCIE_PTX_DRX_P5 CF11 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_P5_C 25 26


5 PCIE_PTX_DRX_P5 PETp2 N/C_7
27 28 RF2
PCIE_PRX_DTX_N6 29 GND6 N/C_8 30 10K_0201_5%
5 PCIE_PRX_DTX_N6 PCIE_PRX_DTX_P6 PERn1 N/C_9
31 32
5 PCIE_PRX_DTX_P6 PERp1 N/C_10
33 34
2

PCIE_PTX_DRX_N6 CF8 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N6_C 35 GND7 N/C_11 36


5 PCIE_PTX_DRX_N6 PCIE_PTX_DRX_P6 PCIE_PTX_DRX_P6_C PETn1 N/C_12
CF9 2 1 0.22U_0201_6.3V6-K 37 38
5 PCIE_PTX_DRX_P6 PETp1 DEVSLP(O)
39 40
PCIEPRX_DTX_P7 41 GND8 N/C_13 42
5 PCIE_PRX_DTX_P7 PCIE_PRX_DTX_N7 PERn0/SATA-B+ N/C_14
43 44
5 PCIE_PRX_DTX_N7 PERp0/SATA-B- N/C_15
1

45 46
PCIE_PTX_DRX_N7 CF1 2 1 0.22U_0201_6.3V6-K PCIE_PTX_DRX_N7_C 47 GND9 N/C_16 48 RF4
5 PCIE_PTX_DRX_N7 PCIE_PTX_DRX_P7 PCIE_PTX_DRX_P7_C PETn0/SATA-A- N/C_17 SSD_RST#
CF7 2 1 0.22U_0201_6.3V6-K 49 50 10K_0201_5% @
5 PCIE_PTX_DRX_P7 PETp0/SATA-A+ PERST#(O)(0/3.3V) or N/C SSD_CLKREQ#
51 52
GND10 CLKREQ#(I/O)(0/3.3V) or N/C SSD_CLKREQ# 9
53 54 1 1
9 CLK_PCIE_SSD#
2

CLK_PCIE_SSD 55 REFCLKn PEWAKE#(I/O)(0/3.3V) or N/C 56 @ CF29


9 CLK_PCIE_SSD REFCLKp N/C_18
57 58 TPF1 1000P_0402_50V7K
+3.3V_NGFF GND11 N/C_19
1

2
RF6 RF23 1 @ 2 SUSCLK_R
SUSCLK_R 47
10K_0201_5%
67 68 +3.3V_NGFF 0_0201_5%
PEDET 69 N/C_1 SUSCLK(32kHz)(O)(0/3.3) 70
2

71 PEDET(NC-PCIe/GND-SATA) 3.3V_7 72
@ GND12 3.3V_8
73 74
GND13 3.3V_9
0.1u_0201_10V6K

CF27
22U_0603_6.3V6-M

75 1 1 1
GND14
0.01U_0201_10V6K

77
1

GND16
CF28

Only support PCIE SSD


CF22
@

RF7
10K_0201_5% ARGOS_NASM0-S6705-TSH4 2 2 2
@
2

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 NGFF WLAN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 46 of 83
A B C D E
5 4 3 2 1

+3VS_WLAN

Mini-Express Card(WLAN/WiMAX)

10U_0603_6.3V6M
0.1u_0201_10V6K

4.7U_0603_6.3V6K
1U_0402_10V6K
1 1 2 1

CN1

CN2

CN3

CN4
@ @

2@ 2@ 1 2
JWLAN1

1 2
USB20_P6 3 GND1 3.3VAUX1 4
D 10 USB20_P6 USB20_N6 5 USB_D+ 3.3VAUX2 6 1 D
@ TN13
10 USB20_N6 7 USB_D- LED1# 8
9 GND2 PCM_CLK/I2S_SCK 10
11 SDIO_CLK PCM_SYNC/I2S_WS 12
13 SDIO_CMD PCM_IN/I2S_SD_IN 14
15 SDIO_DATA0 PCM_OUT/I2S_SD_OUT 16 1 @ TN14
17 SDIO_DATA1 LED#2 18
19 SDIO_DATA2 GND11 20
21 SDIO_DATA3 UART_WAKE# 22
23 SDIO_WAKE# UART_RXD
SDIO_RESET#

KEY E
25 PIN24~PIN31 NC PIN 24
need confirm BOM structure 27
29
26
28
yong 06/25 31 30

33 32
35 GND3 UART_TXD 34
+3VS +3VS_WLAN 5 PCIE_PTX_C_DRX_P1 37 PETP0 UART_CTS 36
5 PCIE_PTX_C_DRX_N1 39 PETN0 UART_RTS 38 EC_TX_RSVD 1 2 0_0402_5% EC_TX
RN5 @
GND4 VENDOR_DEFINED1 EC_RX_RSVD EC_RX
WLAN 41 40 RN6 1 @ 2 0_0402_5%

2
5 PCIE_PRX_DTX_P1 43 PERP0 VENDOR_DEFINED2 42
5 PCIE_PRX_DTX_N1

2
QN2 RN13 45 PERN0 VENDOR_DEFINED3 44

G
47 GND5 COEX3 46 EC_TX 50,52
@ 10K_0402_5%
9 CLK_PCIE_WLAN 49 REFCLKP0 COEX2 48 EC_RX 50,52
9 CLK_PCIE_WLAN# 51 REFCLKN0 COEX1 50 SUSCLK_R

1
3 1 WLAN_CLKREQ_Q# 53 GND6 SUSCLK 52 PLT_RST# +3VS_WLAN
9 WLAN_CLKREQ# CLKREQ0# PERST0# BT_OFF# PCH_BT_OFF# PLT_RST# 8,28,46,55,56

D
RN21 1 @ 2 0_0402_5% 55 54 RN8 1 2 1K_0402_5%
8,52,56 PCIE_WAKE# PEWAKE0# W_DISABLE2# WLAN_OFF# PCH_WLAN_OFF# PCH_BT_OFF# 9
L2N7002KWT1G_SOT323-3 RN22 1 @ 2 0_0402_5% 57 56 RN9 1 2 0_0402_5%
52,56 LAN_WAKE# GND7 W_DISABLE1# PCH_WLAN_OFF# 9

10K_0201_5% RN25

RN26
@ @

1
59 58 EC_RX

1
RN14 1 2 0_0402_5% 61 RSRVD/PETP1 I2C_DATA 60 EC_TX

10K_0201_5%
63 RSRVD/PETN1 I2C_CLK 62 delete CLK 20190910
65 GND8 ALERT# 64
67 RSRVD/PERP1 RSRVD 66
If support AOAC, stuff RN14;

2
69 RERVD/PERN1 UIM_SWP/PERST1# 68 +3VS_WLAN
if not support AOAC, NC RN14.

2
71 GND9 UIM_POWER_SNK/CLKREQ1# 70
73 RSRVD/REFCLKP1 UIM_POWER_SRC/GPIO1/PEWAKE1# 72 RN10 PCH_BT_OFF#
75 RSRVD/REFCLKN1 3.3VAUX3 74 100K_0402_5% PLT_RST# PCH_WLAN_OFF#
GND10 3.3VAUX4
77 76 1

2
GND15 GND14 CN7
1000P_0402_50V7K

ARGOS_NASE0-S6701-TS40 2
@
C
ME@ C

0.1u_0201_10V6K
1U_0402_10V6K
1 1

CN5

CN6
2@ 2@

+3VS +3VS_WLAN

JN9 Need short


1 2
1 2 JUMP_43X79
@
+3VALW
JN10Don't short
1 2
+3VALW 1 2 JUMP_43X79
@
+3VS

UN1
RN19 1
5 1 1 2
IN OUT C2
0.01_0603_1% U135
2 0.1U_6.3V_K_X5R_0201
GND @ 2 5 1
3V_WLAN_EN 1 @ Vcc OE

CN20
0.01U_0402_25V7K
4 3
52 3V_WLAN_EN EN OCB 2 SUSCLK
IN_A SUSCLK 9
SY6288C20AAC_SOT23-5 2@ SUSCLK_R 4 3
46 SUSCLK_R OUT_Y GND
@
M74VHC1GT125DF2G_SC70-5
@

RN27 1 @ 2 0_0402_5%

B B

A A

Title
<Title>

Size Document Number Rev


D <Doc> 1.0

Date: Monday, February 24, 2020 Sheet 47 of 83


5 4 3 2 1
A B C D E F G H

SATA HDD Conn.


+5VS

JHDD1
@

22U_10V_M_X5R_0603

22U_10V_M_X5R_0603
0.1U_6.3V_K_X5R_0201

33P_50V_J_NPO_0201

33P_50V_J_NPO_0201
RF8 1 2 0_0805_5% 1

10U_0805_10V6K

10U_0805_10V6K
1 1 1 1 1 1 1 +5VS 1
2

CF30

CF31

CF32

CF33

CF34

CF35
1 1
CF6 3 2
@ @ @ 4 3
2 2 2 2 2 2 2 SATA_PRX_C_DTX_P0_CON 5 4
RF@ RF@ SATA_PRX_C_DTX_N0_CON 6 5
7 6
SATA_PTX_C_DRX_N0_CON 8 7 12
SATA_PTX_C_DRX_P0_CON 9 8 GND2
10 9 11
10 GND1

HIGHS_FC5AF101-2931H
ME@

SATA HDD Redriver(NEW ADD 20190614 ) +3VS


+3VS_SATA

R109 1 2 0_0402_5%

2
+3VS_SATA 2

+3VS_SATA

2
RF20
1/20W_4.7K_5%_0201

U133
Close APU

1
7 10
EN VDD1 20
SATA_PTX_DRX_P0 CF147 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_P0 1 VDD2
5 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 SATA_PTX_C_DRX_N0 A_INP
CF148 1 2 0.01U_6.3V_K_X7R_0201 2 6 REXT RF21 1 2 4.99K_0402_1%
5 SATA_PTX_DRX_N0 A_INN REXT 16 DEW
SATA_PRX_DTX_P0 CF149 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_P0 5 DEW
5 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 CF150 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_N0 4 B_OUTP 9 A_DE
5 SATA_PRX_DTX_N0 B_OUTN A_DE 8 B_DE
A_EQ1 17 B_DE
A_EQ2 18 A_EQ1 15 SATA_PTX_U_DRX_P0 CF151 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_P0_CON
B_EQ1 19 A_EQ2 A_OUTP 14 SATA_PTX_U_DRX_N0 CF152 1 2 0.01U_6.3V_K_X7R_0201 SATA_PTX_C_DRX_N0_CON
B_EQ2 13 B_EQ1 A_OUTN
B_EQ2 11 SATA_PRX_U_DTX_P0 CF153 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_P0_CON
3 B_INP 12 SATA_PRX_U_DTX_N0 CF154 1 2 0.01U_6.3V_K_X7R_0201 SATA_PRX_C_DTX_N0_CON
21 GND1 B_INN
EPAD
PS8527C_TQFN20_4X4

3 3
+3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA +3VS_SATA

+3VS_SATA
2

2
R41 R43 R47 R54 R57 R79 R36
1/20W_4.7K_5%_0201 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201
1

1
A_EQ1 A_EQ2 B_EQ1 B_EQ2 A_DE B_DE DEW
1 1 1
2

2
CF144 CF145 CF146
R44 R45 R46 R60 R78 R80 R81 0.01U_25V_K_X5R_0201 0.1U_25V_K_X5R_0201 0.1U_25V_K_X5R_0201
@ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201 @ 1/20W_4.7K_5%_0201
2 2 2
1

1
Close to pin 10. Close to pin 20.

Equalization level setting for Channel x(x=A/B), De-emphasis level setting for Channel x(x=A/B), De-emphasis widith adjustment,
internally tied to VDD/2 internally tied to VDD/2 internally pulled down
[x_EQ2, x_EQ1] == [x_DE] == [DEW] ==
L/M: for channel loss up to 2.4dB M: -3.5dB (default) M: for SATA3(default)
L/L: for channel loss up to 7.4dB L: 0dB L: for SATA3
L/H: for channel loss up to 14.4dB H: -6dB H: for SATA2
M/M: for channel loss up to 12.2dB (default)
4 M/L: for channel loss up to 9.4dB 4
M/H: for channel loss up to 13.3dB
H/M: for channel loss up to 6.2dB
H/L: for channel loss up to 11.2dB
H/H: for channel loss up to 5dB

Security Classification LC Future Center Secret Data Title


Follow Vendor suggest Issued Date 2019/07/02 Deciphered Date 2020/02/24 HDD/XBOX CONN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540 1.0

Date: Monday, February 24, 2020 Sheet 48 of 83


A B C D E F G H
A B C D E

+USB_VCCA

CI5 1 2 220U_B2_6.3VM_R35M

+
CI6 1 2
1 1
@ 1U_0603_25V6M

CI7 1 2
@ 470P_0402_50V7K

JUSB2
1
USB20_N1_B RI7 1 @ 2 0_0402_5% USB20_N1_R 2 VBUS
USB20_P1_B RI6 1 @ 2 0_0402_5% USB20_P1_R 3 D-
4 D+
USB30_RX_N1 CI130 1 USB30_RX_C_N1 RI8
20.33U_25V_K_X5R_0201 1 2@ 0_0402_5% USB30_RX_R_N1 5 GND1
10 USB30_RX_N1 USB30_RX_P1 CI131 1 USB30_RX_C_P1 RI9 USB30_RX_R_P1 SSRX-
20.33U_25V_K_X5R_0201 1 2@ 0_0402_5% 6 10
10 USB30_RX_P1 SSRX+ GND3
7 11
USB30_TX_N1 CI9 1 USB30_TX_C_N1 RI5
20.22U_6.3V_K_X5R_0201 1 2@ 0_0402_5% USB30_TX_R_N1 8 GND2 GND4 12
10 USB30_TX_N1 USB30_TX_P1 USB30_TX_C_P1 RI4 USB30_TX_R_P1 SSTX- GND5
CI8 1 20.22U_6.3V_K_X5R_0201 1 2@ 0_0402_5% 9 13
10 USB30_TX_P1 SSTX+ GND6

ALLTO_C107MJ-10939-L
need follow Y540 modify bom structure ME@
yong 07/31

USB20_P1_R
+USB_VCCA
USB20_N1_R
3

2 2
1

DI63
AZC199-02S.R7G_SOT23-3 DI11
1

EMC@ AZ5725-01F.R7GR_DFN1006P2X2
EMC@

USB charger
2

2.5A
2

+5VALW
1

UI3

CI12 2 1 .1U_0402_16V7K 1 16 ILIM_HI RI31 1 2 20K_0402_1%


@ IN ILIM_HI
USB20_N1 2 15 ILIM_LO RI32 1 @ 2 20K_0402_1%
10 USB20_N1 DM_OUT ILIM_LO
USB20_P1 3 14
10 USB20_P1 DP_OUT GND
ILIM_SEL 4 13 USB_OC2#
ILIM_SEL FAULT USB_OC2# 10
5 12 +USB_VCCA
52 USB_CHG_EN EN OUT
DI12
USB30_RX_R_N1 10 1 USB30_RX_R_N1 CHG_MOD1 6 11 USB20_N1_B
NC1 Line-1 52 CHG_MOD1 CLT1 DM_IN
USB30_RX_R_P1 9 2 USB30_RX_R_P1 CHG_MOD2 7 10 USB20_P1_B
NC2 Line-2 CLT2 DP_IN

E_PAD
USB30_TX_R_N1 7 4 USB30_TX_R_N1 CHG_MOD3 8 9 STATUS#
NC3 Line-3 52 CHG_MOD3 CLT3 STATUS STATUS# 52
USB30_TX_R_P1 6 5 USB30_TX_R_P1
NC4 Line-4 SN1702001RTER_WQFN16_3X3

17
3
GND1
8
GND2
AZ1143-04F-R7G_DFN2510P10E10
3 EMC@ 3
+5VALW

For EMC +5VALW

RPI3
ILIM_SEL 1 4 STATUS# RI36 2 1 10K_0402_5%
CHG_MOD2 2 3
LI9 for placement optimization
EXC24CH900U_4P 10K_0404_4P2R_5% [close to EC side]
USB30_RX_C_P1 4 3 USB30_RX_R_P1
4 3
ILIM_SEL RI34 2 @ 1 10K_0402_5%
USB30_RX_C_N1 1 2 USB30_RX_R_N1
1 2 CHG_MOD2 RI35 2 @ 1 10K_0402_5%
@ CLT1 CLT2 CLT3 ILIM_SEL MOD
USB_CHG_EN RI33 2 1 10K_0402_5%
LI10
EXC24CH900U_4P 0 0 0 X DCH OUT held low
USB30_TX_C_P1 4 3 USB30_TX_R_P1
4 3

USB30_TX_C_N1 1 2 USB30_TX_R_N1 * 1 1 1 1 CDP Data Connected and Port Power Mgt. Function Active
1
@
2
* 1 1 1 0 SDP2 Data Connected

LI11
EXC24CH900U_4P
* 1 1 0 X SDP1 Data Connected
USB20_P1_B 4 3 USB20_P1_R
4 3
* 0 1 0 X SDP1 Data Connected
USB20_N1_B 1 2 USB20_N1_R
1 2
EMC@ 1 0 0 X DCP_Short Device Forced to stay in DCP BC 1.2 charging mode

For EMC 1 0 1 X DCP_Divider Device Forced to stay in DCP Divider 1 Charging Mode
4 4

* 0 1 1 X DCP_Auto Data Disconnected and Port Power Mgt. Function Active

0 0 1 X DCP_Auto Data Disconnected and Power Wake Function Active

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 USB2.0/USB3.0 PORT (LEFT)


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 49 of 83
A B C D E
5 4 3 2 1

+USB_VCCD

CI2 1 2 220U_6.3V_M

+
USB3.1 PORT x2
CI3 1 2
@ 1U_0603_25V6M
+5VALW +USB_VCCD
CI4 1 2
Low Active 2.2A
@ 470P_0402_50V7K UI125
5 1
IN OUT
D D
JUSB1 2 2
USB30_HUB_D_TX_P3 CI10 1 USB30_TX_C_P3
2 0.1U_6.3V_K_X5R_0201 RI10 1 2@ 0_0402_5% USB30_TX_R_P3 9 CI32 GND
38 USB30_HUB_D_TX_P3 StdA_SSTX+ USB_OC3#
1 1U_0402_16V6K 4 3
USB30_HUB_D_TX_N3 CI11 1 USB30_TX_C_N3
2 0.1U_6.3V_K_X5R_0201 RI11 1 2@ 0_0402_5% USB30_TX_R_N3 8 VBUS ENB OCB USB_OC3# 10,38
38 USB30_HUB_D_TX_N3 USBP3+_S USBP3+_S_R StdA_SSTX- 1
RI2 1 @ 2 0_0402_5% 3 SY6288D20AAC_SOT23-5 1
UARTA_P80_EN 7 D+ CI31
USBP3-_S RI3 1 @ 2 0_0402_5% USBP3-_S_R 2 GND_DRAIN 10 1000P_0402_50V7K
USB30_HUB_D_RX_P3 RI13 1 2@ 0_0402_5% USB30_RX_R_P3 6 D- GND_2 11 @
38 USB30_HUB_D_RX_P3 StdA_SSRX+ GND_3 2
4 12
USB30_HUB_D_RX_N3 RI12 1 2@ 0_0402_5% USB30_RX_R_N3 5 GND_1 GND_4 13 USB_ON#
38 USB30_HUB_D_RX_N3 StdA_SSRX- GND_5 52 USB_ON#
ALLTO_C190DU-10939-L
ME@

1
RI26 RI27

2 Debug@
100K_0402_5%
USB@

0_0402_5%
1

For USB Debug Function

C C

DI24
USB30_RX_R_N3 10 1 USB30_RX_R_N3 USBP3+_S_R +USB_VCCD
NC1 Line-1
USB30_RX_R_P3 9 2 USB30_RX_R_P3 USBP3-_S_R
NC2 Line-2
UI129
3

USB30_TX_R_N3 7 4 USB30_TX_R_N3
NC3 Line-3

1
USB30_TX_R_P3 6 5 USB30_TX_R_P3

1
NC4 Line-4 DI62 DI65 RI24 2 Debug@ 1 0_0402_5% EC_TX_C 1 10 RI37 2 Debug@ 1 0_0402_5%
47,52 EC_TX 1D+ VCC +3VALW
3 AZC199-02S.R7G_SOT23-3 AZ5725-01F.R7GR_DFN1006P2X2
GND1 EMC@ EMC@ RI25 2 Debug@ 1 0_0402_5% EC_RX_C 2 9 USB_UART_SEL
47,52 EC_RX 1D- S
8
GND2 USB20_HUB_D_P3 USBP3+_S

2
3 8
38 USB20_HUB_D_P3 2D+ D+
AZ1143-04F-R7G_DFN2510P10E10 NCY3958Y

2
USB20_HUB_D_N3 4 7 USBP3-_S
EMC@ 38 USB20_HUB_D_N3 2D- D-
5 6
1

GND1 OE#
11
GND2
for EMC

LI15 NCT3958Y_DFN10_3X3
EXC24CH900U_4P Debug@
USB30_HUB_D_RX_N3 4 3 USB30_RX_R_N3
4 3

USB30_HUB_D_RX_P3 1 2 USB30_RX_R_P3
1 2
EMC_NS@
USB20_HUB_D_P3 2 USB@ 1 USBP3+_S
LI16 RI28 0_0402_5%
EXC24CH900U_4P
USB30_TX_C_N3 4 3 USB30_TX_R_N3 USB20_HUB_D_N3 2 USB@ 1 USBP3-_S
B 4 3 RI29 0_0402_5% B
USBDEBUG Kernel debug
USB30_TX_C_P3 1 2 USB30_TX_R_P3
1 2 Set input Set input
EMC_NS@
Set output Low ENABLE
LI8
EXC24CH900U_4P
USBP3-_S 4 3 USBP3-_S_R +3VALW
4 3

USBP3+_S 1 2 USBP3+_S_R
1 2 UARTA_P80_EN POST 80

1
for EMC EMC@
Set input DISABLE RI30
Debug@ 10K_0402_5%
Set output Low ENABLE

2
USB_UART_SEL

1
D
UARTA_P80_EN 2
OE# S FUNCTION G L2N7002KWT1G_SOT323-3
QI13
H X DISABLE S Debug@

3
L L D(+/-) to 1D(+/-)

L H D(+/-) to 2D(+/-)

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 USB2.0


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 50 of 83
5 4 3 2 1
5 4 3 2 1

+USB_VCCD

CI341 2
@ 1U_0603_25V6M

CI351 2
@ 470P_0402_50V7K
D D

JUSB3
USB30_HUB_D_TX_P2 CI36 1 USB30_HUB_D_TX_C_P2
2 0.1U_6.3V_K_X5R_0201 RI43 1 2@ 0_0402_5% USB30_HUB_D_TX_R_P2 9
38 USB30_HUB_D_TX_P2 StdA_SSTX+
1
USB30_HUB_D_TX_N2 CI37 1 USB30_HUB_D_TX_C_N2
2 0.1U_6.3V_K_X5R_0201 RI45 1 2@ 0_0402_5% USB30_HUB_D_TX_R_N2 8 VBUS
38 USB30_HUB_D_TX_N2 USB20_HUB_D_P2 StdA_SSTX-
RI46 1 @ 2 0_0402_5% USB20_HUB_D_P2_R 3
38 USB20_HUB_D_P2 D+
7
USB20_HUB_D_N2 RI47 1 @ 2 0_0402_5% USB20_HUB_D_N2_R 2 GND_DRAIN 10
38 USB20_HUB_D_N2 USB30_HUB_D_RX_P2 D- GND_2
RI48 1 2@ 0_0402_5% USB30_HUB_D_RX_R_P2 6 11
38 USB30_HUB_D_RX_P2 StdA_SSRX+ GND_3
4 12
USB30_HUB_D_RX_N2 RI49 1 2@ 0_0402_5% USB30_HUB_D_RX_R_N2 5 GND_1 GND_4 13
38 USB30_HUB_D_RX_N2 StdA_SSRX- GND_5
ALLTO_C190DU-10939-L
ME@

C C

DI4 USB20_HUB_D_P2_R
USB30_HUB_D_RX_R_N2 10 1 USB30_HUB_D_RX_R_N2
NC1 Line-1 USB20_HUB_D_N2_R
USB30_HUB_D_RX_R_P2 9 2 USB30_HUB_D_RX_R_P2
NC2 Line-2

2
USB30_HUB_D_TX_R_N2 7 4 USB30_HUB_D_TX_R_N2
NC3 Line-3
USB30_HUB_D_TX_R_P2 6 5 USB30_HUB_D_TX_R_P2 DI3
NC4 Line-4 AZC199-02S.R7G_SOT23-3
3 EMC@
GND1
8
GND2
AZ1143-04F-R7G_DFN2510P10E10
EMC@
1

for EMC

LI93
EXC24CH900U_4P
USB30_HUB_D_RX_N2 4 3 USB30_HUB_D_RX_R_N2
4 3

USB30_HUB_D_RX_P2 1 2 USB30_HUB_D_RX_R_P2
1 2
EMC_NS@

LI94
B EXC24CH900U_4P B
USB30_HUB_D_TX_C_N2 4 3 USB30_HUB_D_TX_R_N2
4 3

USB30_HUB_D_TX_C_P2 1 2 USB30_HUB_D_TX_R_P2
1 2
EMC_NS@

EMC@
USB20_HUB_D_P2 1 2 USB20_HUB_D_P2_R
1 2

USB20_HUB_D_N2 4 3 USB20_HUB_D_N2_R
4 3
EXC24CH900U_4P
for EMC LI95

10/16 david Modify

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 USB2.0


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 51 of 83
5 4 3 2 1
5 4 3 2 1

@
For EMI +VFSPI RE1 1 2 0_0603_5% +3VL 0.5A

+1.8VALW RE3 1 2 0_0603_5%


+3VALW
@
2 @ 1 RE2 CLK_PCI_EC
+3VALW_R +3VALW_R +3VALW_EC
10_0402_5% RE97 2 @1 0_0402_5%
1 @
For SPI ROM Mirror +3VALW_R All capacitors close to EC RE4 1 2 0_0603_5%
CE2
10P_0402_50V8J 1 1
2 @ CE4

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K

.1U_0402_10V6-K
+VFSPI 1 1 1 1 1 1 .1U_0402_10V6-K CE5
EMC_NS@ 220P_0402_50V7K 2 1 CE24 LPC_FRAME# Close EC +3VS CE6 CE7 CE8 CE9 CE10 CE11 1000P_0402_50V7K
+3VALW_EC RE6 1 2 0_0603_5% 2 EC_AGND 2 +3VS
D LPC_AD3 D
EMC_NS@ 220P_0402_50V7K 2 1 CE25 CE3 CD@ @ @
APU_LPC_RST# 1 2 VCOREVCC 2 2 2 2 2 2
EMC_NS@ 220P_0402_50V7K 2 1 CE26 LPC_AD2
1 .1U_0402_10V6-K EC_AGND
CE1 EMC_NS@ 220P_0402_50V7K 2 1 CE27 LPC_AD1
1000P_0402_50V7K RPE1
EMC_NS@ 220P_0402_50V7K 2 1 CE28 LPC_AD0 EC_FAN2_SPEED 1 4
minimum trace width 12 mil

114
121
127
106
2 EC_FAN1_SPEED 2 3

12

11

26
50
92

74
UE1
10K_0404_4P2R_5%
Reserved Cap HLZ SDV 0616

VCC

VFSPI

AVCC
VCORE

VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5
VSTBY6
EC_FAN2_PWM RE65 1 @ 2 10K_0402_5%

EC_FAN1_PWM RE11 1 @ 2 10K_0402_5%


25 WRST# PWR_LED_PWM_B
KBRST# 4 24
+3VALW_R 9 KBRST# KBRST#/GPB6 PWM0/GPA0 YLOGO_LED_PWM PWR_LED_PWM_B 55 LPC_FRAME#
SERIRQ 5 25 RE7 1 @ 2 10K_0402_5%
9,14 SERIRQ LPC_FRAME# ALERT#/SERIRQ/GPM6 PWM1/GPA1 PWR_LED_PWM_R YLOGO_LED_PWM 41
6 28
9 LPC_FRAME# LPC_AD3 ECS#/LFRAME#/GPM5 PWM2/GPA2 PWR_LED_PWM_G PWR_LED_PWM_R 55
7 29 ENBKL RE9 1 @ 2 100K_0402_5%
9 LPC_AD3 LPC_AD2 EIO3/LAD3/GPM3 PWM3/GPA3 EC_FAN2_PWM PWR_LED_PWM_G 55
DE1 1 2 @ 8 30 @
9 LPC_AD2 LPC_AD1 EIO2/LAD2/GPM2 SMCLK5/PWM4/GPA4 EC_FAN1_PWM EC_FAN2_PWM 60
9 31 RE872 2 1 0_0402_5%
9 LPC_AD1 LPC_AD0 EIO1/LAD1/GPM1 SMDAT5/PWM5/GPA5 EC_FAN1_PWM 60 LOGO_LED1_PWM 41 BEEP remove to PCH control
10 32 RE871 2 @ 1 0_0402_5%
RB751V-40_SOD323-2 9 LPC_AD0 CLK_PCI_EC EIO0/LAD0/GPM0 PWM6/SSCK/GPA6 VR_PWRGD 删删EC_EDP_PWM BEEP# 58 yong 07/08 +3VALW
13 34 VR_PWRGD 73
9 CLK_PCI_EC ESCK/LPCCLK/GPM4 PWM7/RIG1#/GPA7 CHG_MOD3
RE8 1 2 100K_0402_5% WRST# 14 120
EC_SMI# WRST# GPC4 CHG_MOD3 49
15 124 SUSP# @
8 EC_SMI# EC_RX PLTRST#/ECSMI#/GPD4 GPC6 SUSP# 55,58,62,69
1 16 RE106 2 1 0_0402_5% AGKB_INT 53
47,50 EC_RX EC_TX RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7 NTC_V1_GPU EC_0.75VALW_EN
17 66 NTC_V1_GPU 60 new add for RGB_KB RE98 1 @ 2 10K_0402_5%
CE12 47,50 EC_TX APU_LPC_RST# TXD/SOUT0/LPCPD#/GPE6 ADC0/GPI0 NTC_V2_CPU yong 07/16
22 67 NTC_V2_CPU 60 @
1U_0402_6.3V6K 9,14 APU_LPC_RST# EC_SCI# ERST#/LPCRST#/GPD2 ADC1/GPI1
23 68 RE29 2 1 0_0402_5% RE868 2 1 0_0402_5% RGB_KB_INT 54
2 9 EC_SCI# EC_RTCRST#_ON ECSCI#/GPD3 ADC2/GPI2 BATT_I PCIE_WAKE# 8,47,56
126 69
12 EC_RTCRST#_ON GA20/GPB5 ADC3/GPI3 BATT_I 67 NTC_V3_DIMM_R
70 RE870 2 @ 1 0_0402_5%
ITE-IT8227E-192/CX_ ADC4/GPI4
ADC5/DCD1#/GPI5
71
72
ADP_I
EC_SYS_PWRGD ADP_I 67
ADAPTER_ID_R RE869 2 1 0_0402_5% ADAPTER_ID
NTC_V3_DIMM
ADAPTER_ID
60
66,67

58
KSI0/STB#
LQFP128 ADC6/DSR1#/GPI6
ADC7/CTS1#/GPI7
73 PSYS
EC_SYS_PWRGD
PSYS 67
8
39 MUX_EDP_ENBKL
RE12 2 @1 0_0402_5% ENBKL

59 78 EC_TP_ON
+3VALW_R KSI1/AFD# DAC2/TACH0B/GPJ2 0.75VALW_PG EC_TP_ON 55
60 79 0.75VALW_PG 70 RE10 2 1 100K_0402_5%
61 KSI2/INIT# DAC3/TACH1B/GPJ3 80 H_PROCHOT#_EC CHANGE pin79 ME_FLASH TO 1.8 ENABLE 20190910
C C
62 KSI3/SLIN# DAC4/DCD0#/GPJ4 81 RE92 1 @ 2 0_0402_5%
KSI4 DAC5/RIG0#/GPJ5 EC_ON 60,68,70
RPE2 63
1 4 EC_SMB_CK1 EC_KSI6 64 KSI5 85 0_0402_5% 2 @1 RE102 +5VALW
EC_SMB_DA1 EC_KSI7 KSI6 PS2CLK0/TMB0/CEC/GPF0 PBTN_OUT# AGKB_PWR_EN# 53,54
2 3 65 86
KSI7 PS2DAT0/TMB1/GPF1 EC_SMB_CK0 PBTN_OUT# 8
15P_0402_50V8J

15P_0402_50V8J

1 1 36 87
69 +0.6V_ENABLE KSO0/PD0 SMCLK0/GPF2 EC_SMB_DA0 EC_SMB_CK0 43,53,54,60 USB_ON#
2.2K_0404_4P2R_5% 37 88 RE15 1 2 100K_0402_5%
55 USB_ON_DB# KSO1/PD1 SMDAT0/GPF3 EC_SMB_DA0 43,53,54,60 SYSON_VDDQ
CE113

CE112

@ @ 38 89 RE100 1 @ 2 0_0402_5% RTS5457_SM_INT 9,43 RE64 1 @ 2 100K_0402_5%


38 USB_HUB_RST_EN KSO2/PD2 PS2CLK2/GPF4 EC_0.75VALW_EN
39 90
2 2 KSO3/PD3 PS2DAT2/GPF5 EC_0.75VALW_EN 70
40 +3VALW_R
41 KSO4/PD4 96
删删TOP_SWAP_EN,PWM_OUT_EN,EC_EDP_ENVDD KSO5/PD5 GPH3/ID3 BATT_CHG_LED# STATUS# 49 USB_ON_DB#
42 97 RE43411 2 100K_0402_5%
KSO6/PD6 GPH4/ID4 BATT_LOW_LED# BATT_CHG_LED# 55 EC_1.8VALW_EN
43 98 RE43381 2 100K_0402_5%
EC_SMB_CK2 KSO7/PD7 GPH5/ID5 3V_WLAN_EN_R RE4308 2 BATT_LOW_LED# 55
44 99 @ 1 0_0402_5%
3V_WLAN_EN 47
EC_SMB_DA2 68 EC_3V/5V_USM KSO8/ACK# GPH6/ID6
45 SUSP# RE18 1 @ 2 100K_0402_5%
KSO9/BUSY EC_SPI_CS1#
15P_0402_50V8J

15P_0402_50V8J

1 1 46 101
51 KSO10/PE FSCE# 102 EC_SPI_SI change pin99 PCH_POWROK to 3V_WLAN_EN 20190910 SUSP# RE19 1 2 100K_0402_5%
55 EC_ON
SYS_LED KSO11/ERR# FMOSI EC_SPI_SO
CE30

CE117

@ @ 0_0402_5% 1 @ 2 RE96 52 103


+3VALW 53 KSO12/SLCT FMISO 105 EC_SPI_CLK SYSON RE21 1 2 100K_0402_5%
2 2 55 PWR_LED_SEL GSENSE_INT KSO13 FSCK
59 GSENSE_INT
54
BoardID_ADP_LIM
@ 55 KSO14 EC_ON_APU RE14 1 @ 2 100K_0402_5%
RPE4 RE103 1 2 0_0402_5% 56 KSO15 108 ACIN#
EC_SMB_CK0 53 FN_KEY KSO16/SMOSI/GPC3 GPB0 EC_1.8VALW_EN
2 3 60 SMB1_ALERT#
1 @ 2 0_0402_5% 57 109 NOVO# NOVO# 55 RE43391 @ 2 100K_0402_5%
1 4 EC_SMB_DA0 RE101 KSO17/SMISO/GPC5 GPB1
@
2.2K_0404_4P2R_5% ON/OFF 110 82 RE30 1 @ 2 0_0402_5% VGA_AC_DET
55 ON/OFF CHG_MOD1 PWRSW/GPB3 EGAD/GPE1 VGA_AC_DET 28
111 83 RE43091 2 0_0402_5%
CHG_MOD1 49 EC_SMB_CK1 GPB4 EGCS#/GPE2 SYSON_VDDQ EC_1.8VALW_EN 71
115 84
66,67,79 EC_SMB_CK1 EC_SMB_DA1 @ SMCLK1/GPC1 EGCLK/GPE3 SYSON_VDDQ 69
116
66,67,79 EC_SMB_DA1 SMDAT1/GPC2 EC_MUTE#
RE328 1 2 0_0402_5% 117 77 delete pin83 VCCIO_PG 20190910
7,25 APU_THERMTRIP# USB_CHG_EN SMCLK2/PECI/GPF6 TACH2B/GPJ1 EC_MUTE# 58
delete pin177 PECI 20190910 118 100 GPG2
49 USB_CHG_EN EC_SMB_CK2 SMDAT2/PECIRQT#/GPF7 SSCE0#/GPG2
94 125 ENBKL
7,28,59,60 EC_SMB_CK2 EC_SMB_DA2 CRX1/SIN1/SMCLK3/GPH1/ID1 SSCE1#/GPG0
95 119 SYSON
7,28,59,60 EC_SMB_DA2 CTX1/SOUT1/SMDAT3/GPH2/ID2 DSR0#/GPG6 LAN_WAKE# SYSON 69
122
DTR1#/SBUSY/GPG1/ID7 113 BKOFF#
CRX0/GPC0 LID_SW# BKOFF# 41 Change RE30 to 0ohm jump
123 LID_SW# 55
delete pin35 CPU_PWRGD PIN33 EC_ON_1V 20190910 EC_ON_5V 112 CTX0/TMA0/GPB2 18 PM_SLP_S3#
68 EC_ON_5V EC_ON_APU RING#/CK32KOUT/LPCRET#/GPB7 RI1#/GPD0 EC_VR_ON PM_SLP_S3# 8
107 21 @
B 62 EC_ON_APU GPE4 RI2#/GPD1 EC_FAN2_SPEED EC_VR_ON 73 ADAPTER_ID B
76 EC_FAN2_SPEED 60 RE105 1 2 0_0402_5% CE31 1 2 .1U_0402_10V6-K
+3VL TACH2A/GPJ0 PM_SLP_S5# SYSTEM_STATUS1 53
48
TACH1A/TMA1/GPD7 EC_FAN1_SPEED PM_SLP_S5# 8,14
47 EC_FAN1_SPEED 60 SYSON CE13 1 2 .1U_0402_10V6-K EMC_NS@
USB_ON# 33 TACH0A/GPD6 19 1 RE76@ 2 0_0402_5%
50 USB_ON# GINT/CTS0#/GPD5 SMCLK4/L80HLAT/BAO/GPE0 CAPS_LED# 53,55
1

P_APU_OCPL 35 20 1 RE77@ 2 0_0402_5% EC_VR_ON RE4336 1 2 100K_0402_5%


73 P_APU_OCPL RTS1#/GPE5 SMDAT4/L80LLAT/GPE7 NUM_LED# 53,55
RE108 93 3 RE873 2 @ 10_0402_5%
8 EC_RSMRST# CLKRUN#/GPH0/ID0 GPH7 PCH_FNLK 9,55
100K_0201_5% @
RE104 1 2 0_0402_5%
BATT_TEMP SYSTEM_STATUS2 53
2
66,67 BATT_TEMP
2

BoardID_ADP_LIM GPJ7
AC_PRESENT 128
8 AC_PRESENT GPJ6
1

RE34 1 2 0_0402_5% APU_PROCHOT# 7


RE109 67 VR_HOT#
100K_0201_5%
@ H_PROCHOT#_EC RE325 1 2 0_0402_5%
AVSS
VSS1

VSS2
VSS3
VSS4
VSS5

BoardID_ADP_LIM:
2

1: N18E <= 135W adapter not support


0: N18P <= 90W adapter not support EC_SMB_CK1 PAD 1 @
ITE1

1
EC request 11/12 EC_SMB_DA1 PAD 1 @ QE1 D
ITE2 1
1

27
49
91
104

75

PAD 1 @ H_PROCHOT#_EC 2 CE14


ITE3
PAD 1 @ G 47P_0402_50V8J
+3VL ITE4
PAD 1 @ @
ITE5 S 2
2N7002KW_SOT323-3

3
RE43422 1 100K_0402_5% EC_ON_5V
@
RE95 1 @ 2 100K_0402_5% EC_ON EC_KSI7 PAD 1 @ IT8227E-192CX_LQFP128_14X14 EC_AGND
EC_KSI6 ITE6
PAD 1 @
ITE7
WRST# PAD 1 @
ITE8
RE36 1 @ 2 10K_0402_5% BKOFF#
BATT_TEMP CE16 1 2 100P_0402_50V8J EMC_NS@
RE38 2 1 100K_0402_5% LID_SW# +3VL
For factory EC flash
ACIN# CE17 1 2 100P_0402_50V8J EMC_NS@

RE43401 2 100K_0402_5% EC_ON same net name with PCH ON/OFF CE18 1 2 1U_0402_6.3V6K EMC_NS@ +3VS

1
EC_SPI_CS1# RE45 1 @ 2 0_0402_5%
RE40 1 2 100K_0402_5% BKOFF# EC_SPI_CS1#_R 9 RE42
EC_SPI_SI RE47 2 1 0_0402_5% 100K_0402_5% +3VALW_R
SPI_SI_C 9,55 1
A CE19 A
EC_SPI_SO RE48 2 1 0_0402_5% NOVO# CE48 1 2 .01U_0402_16V7-K @ .1U_0402_10V6-K @
SPI_SO_C 9,55

1
ACIN# RE94 1 2 0_0402_5%
EC_SPI_CLK PM_SLP_S3# 2 ACIN 67
+3VALW_R RE49 2 1 0_0402_5% CE29 1 2 .01U_0402_16V7-K @ RE5
SPI_CLK_PCH_C 9,14,55 10K_0402_5%
PM_SLP_S5# CE135 1 2 .01U_0402_16V7-K @
GPG2 RE44 2 1 10K_0402_5%

2
MIRROR@ LAN_WAKE#
LAN_WAKE# 47,56
GPG2 RE46 2 1 10K_0402_5%
NOMIRROR@ EC_SPI_CS1# CE20 1 2 .01U_0402_16V7-K @
when mirror, GPG2 pull high EC_SPI_SI Security Classification LC Future Center Secret Data Title
CE21 1 2 .01U_0402_16V7-K @
when no mirror, GPG2 pull low EC_SPI_SO CE22 1 2 .01U_0402_16V7-K @
Issued Date 2019/07/02 Deciphered Date 2020/02/24 ITE8371LQFP
EC_SPI_CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
CE23 1 2 .01U_0402_16V7-K @ AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Monday, February 24, 2020 Sheet 52 of 83
5 4 3 2 1
5 4 3 2 1

+3VALW_AG AVCC3.3V_AG
KSI[0..7] +3VALW_AG AVCC3.3V_AG
55 KSI[0..7]
KSO[0..17] +3VALW_AG LI24 1 2 HCB1608KF-181T20
55 KSO[0..17]
AG@

0.1U_0402_10V7K

0.1U_0402_10V7K
1 1

CI13

CI14

1000P_0402_50V7K
0.1U_0402_10V7K
1 1

CI15

CI17
RI14
1.5K_0402_5% AG@ 2 AG@2
@ AG@ 2 AG@ 2 +3VALW_AG

2
USB20_P7_AGKB UI22 RI42 1 2 1/10W_0_+-5%_0603
D D
IT8176FN-56A-BX_QFN48_6X6 RI40 1 2 AG_SMCLK

17

18

32
7

8
1.5K Reserve for USB AG@ 2.2K_0402_5%
+3VALW_AG slave mode use

VCOREB2

VCOREB

VSTBY33_1
VSTBY33_2

AVCC33
DI44 AG_AGND RI41 1 2 AG_SMDAT
1 2 2.2K_0402_5%

RB751V-40_SOD323-2 RI39 1 2 AGKB_INT


AG@ 1 2.2K_0402_5%
SMCLK0/PWM0/GPA0 CAPS_LED# 52,55 +3VALW_AG
2
2 1 10K_0402_5% AG_WRST# SMDAT0/PWM1/GPA1 3 AG_SMCLK NUM_LED# 52,55
RI15
AG@ SMCLK1/PWM2/GPA2 4 AG_SMDAT
SMDAT1/PWM3/GPA3
1
CI18 PAD 1 @

0.1U_0402_10V7K

0.1U_0402_10V7K
TI8 1 1

CI19

CI20
1U_0402_6.3V6K
AG@
2
48 AG@ 2 AG@ 2
WRST#
5
PWM5/GPA5 47 SYSTEM_STATUS2 52
LI23
10 USB20_N7
USB20_N7

USB20_P7
1
1 2
2 USB20_N7_AGKB

USB20_P7_AGKB
IT8176FN-56A/BX PWM4/GPA4 LED_KB_PWM 55
+3VALW_AG

10 USB20_P7
4
4
EXC24CH900U_4P
3
3
19
20 DM
DP
QFN48
AG@
1 @ 2 0_0402_5%
RI16

2
G
RI17 1 @ 2 0_0402_5% 45
C TXD/GPA7 FN_KEY 52 C
46
RXD/GPA6 SYSTEM_STATUS1 52
KSI0 37
KSI1 38 KSI0/ADC16/STB#/GPD0 AG_SMCLK 1 6 EC_SMB_CK0

S
KSI1/ADC17/AFD#/GPD1 EC_SMB_CK0 43,52,54,60

D
KSI2 39
KSI2/ADC18/INIT#/GPD2

5
KSI3 40

G
KSI4 41 KSI3/ADC19/SLIN#/GPD3 QI20A
KSI5 42 KSI4/ADC20/GPD4 2N7002KDWH_SOT363-6
KSI6 43 KSI5/ADC21/GPD5
KSI7 44 KSI6/ADC22/GPD6 AG_SMDAT 4 3 EC_SMB_DA0

S
KSI7/ADC23/GPD7 EC_SMB_DA0 43,52,54,60

D
KSO0 9 34 KB_BL_CONFIG
KSO1 10 KSO0/PD0/GPE0 ADC0/GPC0 35 RI38 1 2 0_0402_5% QI20B 2N7002KDWH
KSO1/PD1/GPE1 ADC1/GPC1 F2_KEY 8
KSO2 11 36 2N7002KDWH_SOT363-6 Vth= min 1V, max 2.5V
KSO3 12 KSO2/PD2/GPE2 ADC2/GPC2 AGKB_INT 52 ESD 2KV
13 KSO3/PD3/GPE3
KSO4
KSO4/PD4/GPE4
SYSTEM_STATUS1 SYSTEM_STATUS2
KSO5 14
KSO6 15 KSO5/PD5/GPE5
KSO7 16 KSO6/PD6/GPE6
KSO7/PD7/GPE7 L L S5
KSO8 22
KSO9 23 KSO8/ACK#/GPF0
KSO10 24 KSO9/BUSY/GPF1
KSO10/PE/GPF2 L H S3
KSI7 PAD 1 @ KSO11 25 FW update change part number SA000081L20
ITI8 KSO11/ERR#/GPF3
KSI6 PAD 1 @ KSO12 26
ITI7 27 KSO12/SLCT/GPF4
KSO13 H L S0
KSO17 1 @ TI12 KSO14 28 KSO13/GPF5
KSO15 29 KSO14/GPF6
KSO16 30 KSO15/GPF7
KSO17 31 KSO16/SMCLK2/GPG0
KSO17/SMDAT2/GPG1

AVSS
VSS1
VSS2

PAD
B B
6
21

33

49
AG@ +3VALW

2
RI18
AG_AGND 0_0603_5%
KSI0

1
KSI1 +3VALW_AG +3VALW_AG
KSI2 RI19
KSI3 +3VALW_IN 1 2
2

KSI4 @
KSI5

10U_0603_25V6-M
RI21 0_0603_5%
KSI6 10K_0402_5% 1

2
KSI7 KB_BL_CONFIG KB Backlight RGB@ CI21
RI20
1

KB_BL_CONFIG UI23
33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

33P_0402_50V8J

1 1 1 1 1 1 1 1 AG@ 100K_0402_5%
5 1 2
CI23

CI24

CI25

CI26

CI27

CI28

CI29

CI30

L non-RGB IN OUT
@
2

1
RI22 2
AG@ 2 AG@ 2 AG@ 2 AG@ 2 AG@ 2 AG@ 2 AG@ 2 AG@ 2 GND
H RGB 10K_0402_5%
AGKB_PWR_OCB
4 3
52,54 AGKB_PWR_EN# ENB OCB
1

0.1U_0402_10V7K
1

CI22
SY6288D20AAC_SOT23-5
AG@
AG@2
A A

Security Classification LC Future Center Secret Data Title


Issued Date 2019/07/02 Deciphered Date 2020/02/24 Anti-ghost KB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Wednesday, February 26, 2020 Sheet 53 of 83
5 4 3 2 1
5 4 3 2 1

+5VS +5VS_KLED +3VALW_RGB

@ RGB@
RI72 1 2 0_0805_5% CI70 1 2 22U_10V_M_X5R_0603

+3VALW_RGB CI601 2
@ 1U_0603_25V6M

2
G
CI611 2
@ 470P_0402_50V7K
D RI96 1 RGB@ 2 4.7K_0402_5%RGB_KB_INT D
RGB_SMCLK 6 1 EC_SMB_CK0
EC_SMB_CK0 43,52,53,60

S
RI286 1 RGB@ 2 2.2K_0402_5% RGB_SMCLK

D
5
G
QI21A
RI287 1 RGB@ 2 2.2K_0402_5%RGB_SMDAT 2N7002KDWH_SOT363-6

150P_25V_J_COG_0201

150P_25V_J_COG_0201
RGB_SMDAT 3 4 EC_SMB_DA0
EC_SMB_DA0 43,52,53,60

S
D
2 2
QI21B 2N7002KDWH
2N7002KDWH_SOT363-6 Vth= min 1V, max 2.5V
1 1

CI76

CI77
ESD 2KV

@ @
RI345 1 @ 20_0201_5%

RI346 1 @ 20_0201_5%

+5VS_KLED
JRGB1
22
GND2 21
GND1 20
20 19
19 18
18 17
17 16
16 15
15 14
14 13
13 12 RGB_SMCLK
12 11 RGB_SMDAT
LI96 11 10 RGB_KB_INT
USB20_N3 1 2 USB20_N3_RGB 10 9 CODEC_I2C_SCL RGB_KB_INT 52
10 USB20_N3 1 2 9 8 CODEC_I2C_SDA CODEC_I2C_SCL 58
8 7 CODEC_I2C_SDA 58
USB20_P3 4 3 USB20_P3_RGB 7 6 USB20_N3_RGB
10 USB20_P3 4 3 6 5 USB20_P3_RGB
EXC24CH900U_4P 5 4
4 3 +3VALW_RGB
EMC_NS@ 3 2
RI79 2 @1 0_0402_5% 2 1
1
RI80 2 @1 0_0402_5% ME@
HIGHS_FC5AF201-1151H

C C

+3VALW

+3VALW_RGB
2

RI283
0_0603_5%
1

RGB@
RI284
+3VALW_IN_R 1 2
10U_0603_25V6-M

0_0603_5%
1
2

CI74
RI285
UI130 @ 100K_0402_5%
5 1 2 @
IN OUT
1

2
GND
4 3 RGBKB_PWR_OCB
52,53 AGKB_PWR_EN# ENB OCB
0.1U_0402_10V7K

1
CI75

SY6288D20AAC_SOT23-5
@
@ 2

need confirm if another GPIO


yong 07/22

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 RGB KB


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 1.0

Date: Monday, February 24, 2020 Sheet 54 of 83


5 4 3 2 1
5 4 3 2 1

DI23 AZ5725-01F.R7GR_DFN1006P2X2
ON/OFF switch +3VL +3VS
1 2 EMC@ CAPS_R_LED#
HIGHSTAR_FC8AF341-3201H 1 2 LED_KB_C
No function field

2
35 34
RI282 36 GND1 34 33 DI35 AZ5725-01F.R7GR_DFN1006P2X2
GND2 33 32 FNlock_R_LED# FNlock_LED#
100K_0402_5% RI541 2 0 +-5% 0402 1
RI95 1 2 0_0402_5% 32 31 PWR_FnLK_LED# 1 2 EMC@ NUM_R_LED# D
Charger LED +3VALW 31 30 1 2
53 LED_KB_PWM
2 QI14

1
30 29 NUM_R_LED#
DI15 @ RI291 1 2 0 +-5% 0402 G PJA138K_SOT23-3
2 LED301 29 28 NUM_LED# 52,53
NOVO# KSO17 S BL@

2
52 NOVO# 28 27 KSO16
RI344 DI102 AZ5725-01F.R7GR_DFN1006P2X2
1 NOVO_BTN# BATT_LOW_LED# 4 3 1 2 27 26 KSI1 3
RI55
52 BATT_LOW_LED# 26 25 1 2 EMC@ FNlock_R_LED#
KSI7 100K_0402_5%
ON/OFF 1 2 RI85 3 25 24 KSI6 1 2
1/16W_82_1%_0402 BL@
0_0402_5% BATT_CHG_LED# 1
RI97
24 23 KSO9 K/B Connector

1
2 1 2 23 22 KSI4
@ BAT54CW_SOT323-3 1
52 BATT_CHG_LED# CI73 22 21 KSI5
@ 1 1 21 FNlock_R_LED#
1/16W_82_1%_0402 .1U_0402_10V6-K 20 KSO0
1 2 @ +3VL 20 19 KSI2 KSI[0..7]
J2 CI71 CI72 B2972UDBS05P-000114_AMBER-WHITE @
2 19 18 KSI3 KSI[0..7] 53
220P_0402_50V7K 220P_0402_50V7K 1
2 2 18 17 KSO5 KSO[0..17] CAPS_R_LED#
SHORT PADS EMC_NS@ EMC_NS@ EMC_NS@

2
17 16 KSO1 KSO[0..17] 53
CI122
1 2 @ 16 15 KSI0 KSO16 1 1000P_0402_50V_X7R_0402 NUM_R_LED#
J3 RI111 @ TI11 1
15 14 KSO2 2
100K_0402_5% CI132
14 13 KSO4
SHORT PADS 1000P_0402_50V7K
1
13 12 KSO7 EMC_NS@CI133
12

1
11 KSO8 2 1000P_0402_50V7K +5VS 0.5A
D 11 D
ON/OFFBTN# RI119 1 2 0_0402_5% ON/OFF 10 KSO6 EMC_NS@ JKBL1
ON/OFF 52 10 9 2 1
KSO3
9 8 KSO12 LED_KB_C 2 1
@ @
8 7 KSO13 1 2 0_0603_5% LED_Power_C1 3 2
RI57
7 6 KSO14 4 3
6 5 KSO11 4
5

0.1U_0402_10V6K
4 KSO10 5

CI55
4 2 GND1
3 KSO15 08/14 add 6
BATT_LOW_LED# 3 2 CAPS_R_LED# GND2
RI290 1 2 0 +-5% 0402 +3VS
2 1 PWR_CAPS_LED CAPS_LED# 52,53 @ HIGHS_FC1AF040-1201H
BATT_CHG_LED# 1 1
ME@
JKB1

1
ON/OFFBTN# ME@ @
RI342

AZ5123-01F.R7GR_DFN1006P2X2
need confirm pin 1 470_0603_5%

1
yong 07/22

1
AZ5123-01F.R7GR_DFN1006P2X2
SW5

2
DI1 DI13 DI14 FNlock_LED#

1
1

AZ5725-01F.R7GR_DFN1006P2X2 EMC_NS@

1
QI23 D
PCH_FNLK 2
9,52 PCH_FNLK

2
G

2
2 EMC_NS@ @ S 2N7002KW_SOT323-3

3
RI343
100K_0402_5%
2

1
T4BJB16BQR_4P

change PN
6P00 EOL
only have 15

+5VALW
+5VALW

+3VS TP_PWR PWR LED

1
1
LED2 RI318
RI56 1 2 0_0402_5% CI57 @ 470_0603_5%
1U_0402_10V6K PWR_LED_PWM_B_OUT RI292 1 21/16W 1.8K +-1% 0402 3 -
2 B
PWR_LED_PWM_R_OUT
Right Side USB2.0 Port X 1 (USB/B)

2
.1U_0402_10V6-K
1 PWR_LED_PWM_G_OUT
UI1 RI293 1 21/16W 2.2K +-5% 0402 2 - + 4
+5VALW

1
16

150P_25V_J_COG_0201

150P_25V_J_COG_0201
G QI3 D 1
Vcc 4 PWR_LED_PWM_B_MUX PWR_LED_PWM_R_MUX 2 EMC_NS@

CI54

CI53
TP_I2C3_SCL 2 2 1A 7 PWR_LED_PWM_G_MUX PWR_LED_PWM_R_OUT
RI294 1 2 1/16W 1K +-1% 04021 CI103 RI53 1 2 0_0402_5%

CI52
1 1 - G
TP/B Connector 52 PWR_LED_PWM_B 3 1B1 2A 9 PWR_LED_PWM_R_MUX
R 1000P_0402_50V_X7R_0402

2
TP_I2C3_SDA TP_PWR 5 1B2 3A 12 2
S 2N7002KW_SOT323-3
52 PWR_LED_PWM_G

3
6 2B1 4A
JTP1 LED LTST-C19HEGBW-KN RED/GREEN/BLUE RI319 LI14
1

2 2 10 11 2B2 15 100K_0402_5% USB20_P5 2 1 USB20_P5_CONN


9 GND2 52 PWR_LED_PWM_R 10 3B1 OE 1 10 USB20_P5 2 1
1

GND1 14 3B2 S PWR_LED_SEL 52

1
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

DI36 DI37 8 13 4B1 8 USB20_N5 3 4 USB20_N5_CONN


TP_I2C3_SCL 7 8 4B2 GND 17 10 USB20_N5 3 4
RI295
C TP_I2C3_SDA 6 7 T-PAD C
+3VS 100K_0402_5% EXC24CH900U_4P
6
2

5 CBT3257ABQ_DHVQFN16_2P5X3P5
5 EMC_NS@
RI77 1 @ 2 0_0402_5% 4
+3VL
2

1
LID_SW# 1 @ 2 0_0402_5% 3 4 1 2 0_0402_5%
RI78 RI52
EMC_NS@ EMC_NS@ 1 20_0201_5% TP_INT# 2 3
RI61
8 PCH_TP_INT# 1 2
For EMC Status OE S
2

52 EC_TP_ON 1
10K_0201_5%

2
ME@ Blue L L
RI51

HIGHS_FC5AF081-2931H
G

@ RI50 White L H
10K_0201_5% +5VALW
1

OFF H x +5VALW
TP_INT# 1PCH_TP_INT1# USB3.1 PORT x1

1
3
PCH_TP_INT1# 8
S

1
QX36
L2N7002KWT1G_SOT323-3
+3VS RI314
+5VALW
Low Active 1.8A +USB_VCCB
470_0603_5% RI316
PWR_LED_PWM_B_OUT PWR_LED_PWM_G_OUT PWR_LED_PWM_R_OUT
@ @ 470_0603_5%
UI2

2
PWR_LED_PWM_B_OUT 5 1

2
PWR_LED_PWM_G_OUT IN OUT

1
QI1 D 2

1
PWR_LED_PWM_B_MUX 2 GND
1 QI2 D 1 2
TP_PWR PWR_LED_PWM_G_MUX 2 4 3 USB_OC1#
RPH8 G EMC_NS@ EMC_NS@ CI50
2

1
2N7002KDWH 1 4 CI104 G CI105 1U_0402_16V6K ENB OCB USB_OC1# 10
G

TP_PWR

2
Vth= min 1V, max 2.5V 2 3 1000P_0402_50V_X7R_0402
S 2N7002KW_SOT323-3 1000P_0402_50V_X7R_0402 G517E2T11U_SOT23-5 1

2
3
ESD 2KV 2 2 1
DI103 DI104 DI105 RI315 S 2N7002KW_SOT323-3 CI51

3
2.2K_0404_4P2R_5% AZ5725-01F.R7GR_DFN1006P2X2 AZ5725-01F.R7GR_DFN1006P2X2 AZ5725-01F.R7GR_DFN1006P2X2 100K_0402_5% RI317 1000P_0402_50V7K
6 1 TP_I2C3_SCL
EMC_NS@ EMC_NS@ EMC_NS@ 100K_0402_5% @
S

8,14,69 TP_I2C3_SCL_R 2
D
5

1
USB_ON_DB#

2
QH23A L2N7002KDW1T1G_SOT363-6
G

52 USB_ON_DB#

1
2

2
3 4 TP_I2C3_SDA
S

8,14,69 TP_I2C3_SDA_R
D

QH23B L2N7002KDW1T1G_SOT363-6

+1.8VALW +1.8V_TPM
system LED +3VALW

RM1
1 2 1
0.01_0603_1% CI56
+3VALW +1.8V_TPM 1U_0402_10V6K +3VALW for 15" USB board +USB_VCCB
TPM@
10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

2 2 2 2 +1.8V_TPM
2
CM2

CM1 TPM@

CM3 TPM@

CM4

UI4
1 5 JIO1
52 SYS_LED

1
PWR_LED_PWM_B 3 Y1 Vcc 1
2

1 1 1 1@ Y0 4 SYS_LED_MUX 2 1
RM13 RM6 RI321
Z 3 2
@ TPM@ @ RTPM28 stuff for NationZ 470_0603_5%
3
0_0603_5% 0_0603_5% 2 6 4
GND S SUSP# 52,58,62,69 4
5

2
B SYS_LED_MUX_CONN USB20_P5_CONN 5 B
6
1

USB20_N5_CONN 7 6
2 1 1 1 74LVC1G3157GW_SOT363-6

1
8 7
CM5 CM6 CM7 CM8 QI22 D
SYS_LED_MUX 2 USB30_RX_N5 9 8
@ TPM@ 0.1U_0201_6.3V6-K 0.1U_0201_6.3V6-K
10U_0603_6.3V6M 4.7U_0402_6.3V6MTPM@ TPM@ 10 USB30_RX_N5 USB30_RX_P5 10 9
G
1 2 2 2 10 USB30_RX_P5 11 10

2
USB30_TX_N5 12 11
1 2 S 2N7002KW_SOT323-3
10 USB30_TX_N5

3
USB30_TX_P5 13 12
CM9 CM10 S z RI322
10 USB30_TX_P5 14 13
+1.8V_TPM TPM@ @ 100K_0402_5%
SYS_LED_MUX_CONN 15 14
2
1U_0402_6.3V6K
1
10U_0603_6.3V6M H Y1 16 15
+3VALW

1
17 16
L Y0 LID_SW# 17
RM93 0_0402_5%

18
52 LID_SW#
2

NOVO_BTN# 19 18
2

RM92 RM20 20 19
+3VL 21 20
22

RM2 10K_0402_5% @
8

10K_0402_5%
TPM@ 10K_0402_5% UM1 NT_REMOTE1+ 22 21
60 NT_REMOTE1+ NT_REMOTE1- 23 22
TPM@
VSB
VHIO2

VHIO1

60 NT_REMOTE1-
1

24 23
TPM_IRQ# 24
1

RM9 2 1 0_0402_5% TPM@ 18 2


9 TPM_SPI_IRQ# PIRQ#/GPIO2 NC1 3 TPM_GP2 2 TPM@ 1 10K_0402_5% 25
TPM@ RM94
NC2 4 TPM_PIN4 +1.8V_TPM GND1
RM95 2 @ 1 0_0402_5%
TPM_MOSI PP/GPIO6 +1.8V_TPM
RM90 1 2 1/16W_10_5%_0402 21 5 26
9,52 SPI_SI_C TPM_MISOI MOSI/GPIO7 NC3 GND2
RM91 1 2 1/16W_10_5%_0402 24 9
9,52 SPI_SO_C MISO NC5 10
NC6 11 ELCO_046809624210846+
NC7 12
TPM_CS2# NC8 ME@
RM7 2 1 0_0402_5% TPM@ 20 13
9 SPI_CS2# SCS#/GPIO5 GPIO4 14
TPM_CLK NC9 +1.8V_TPM
RM89 1 2 1/16W_10_5%_0402 19 15
9,14,52 SPI_CLK_PCH_C SCLK NC10 16
NPCT750LABYX_QFN32_5X5
TPM_PLT_RST# 17 GND1 25
PLTRST# NC11 26
6 NC12 27 TPM_PIN27
RM14 1 @ 2 10K_0402_5%
GPIO3 NC13 28
TPM_PP 7 NC14 31
NC4 NC15 32
NC16
29 TPM_PIN29
1

SDA/GPIo0 30
GND2

GND3

RM11 SCL/GPIO1
0_0402_5%
@
2

23

33

TPM@
+1.8V_TPM
1

RM15
TPM@
10K_0402_5%
2

TPM_PLT_RST# +1.8V_TPM
+5VALW

A A
1

RM17 RM18
10K_0402_5% @
TPM@ 10K_0402_5%
6

TPM_PIN29 PLT_RST#
2

D RM19 2 @ 1 0_0402_5%
2 QM1A
DM3
G 2N7002KDWH_SOT363-6
TPM@ 2 1
S
3

D @
5 QM2B RB751V-40_SOD323-2
8,28,46,47,56 PLT_RST#
G 2N7002KDWH_SOT363-6 SCS00008K00
TPM@
S
4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 KBD/PWR/IO/LED/TP Conn.


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y540 1.0

Date: Wednesday, March 04, 2020 Sheet 55 of 83


5 4 3 2 1
5 4 3 2 1

+3VALW TO +3VALW_LAN
+3VALW_LAN rising time (10%~90%):
+3VALW +3VALW_LAN
0.5ms<spec<100ms
Need short +3VALW_LAN +LAN_VDDREG
@
JL1 1 2 @ width : 40 mils RL1 1 2 0_0603_5%
D 1 2 D
JUMP_43X79

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201
CL1

CL2
1 1
+3VALW

0.01U_6.3V_K_X7R_0201

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
LP2301ALT1G_SOT23-3

CL4

CL5
1 1 1 1

8111GUL@

8111GUL@
3

D
QL2 1 @

1
2 2

0.1U_6.3V_K_X5R_0201

CL6

CL7
CL9
RL2 1 1 @ @
100K_0402_5% 2 2 2 2

G
2
CL8
@ @
@

2
2 2
RL3 1 @ 2 47K_0402_5%
8 LAN_PWR_ON#

Close to Pin11 Close to Pin32 Close to Pin11 Close to Pin32

+3VALW_LAN
+3VALW_LAN +3VS

2 RL5
10K_0402_5% manual change the PN to RTL8111GUL-CG

2
@

2
RL4

G
UL1
10K_0402_5%
1

RL7 1 @ 2 0_0402_5% PCIE_WAKE#_R @ QL1


8,47,52 PCIE_WAKE#
47,52 LAN_WAKE# RL6 1 2 0_0402_5% L2N7002KWT1G_SOT323-3

1
LAN_CLKREQ#_R 1 3
LAN_CLKREQ# 9

S
@
33
+3VALW_LAN 32 GND 16 CLK_PCIE_LAN#
AVDD33_2 REFCLK_N CLK_PCIE_LAN CLK_PCIE_LAN# 9
RL8 1 RSET 2 31 15 RL18 1 2 0_0402_5%
+LAN_VDD10 RSET REFCLK_P PCIE_PTX_C_DRX_N0 CLK_PCIE_LAN 9
C 2.49K_0402_1% 30 14 C
LAN_XTALO AVDD10 HSIN PCIE_PTX_C_DRX_P0 PCIE_PTX_C_DRX_N0 5
29 13
LAN_XTALI CKXTAL2 HSIP LAN_CLKREQ#_R PCIE_PTX_C_DRX_P0 5
28 12
+3VS RL12 TPL1 @ 1 Test_Point_12MIL 27 CKXTAL1 CLKREQB 11 +3VALW_LAN
LAN_PWR_ON# 1 2 LAN_DISABLE# 26 LED0 AVDD33_1 10 LAN_MDI3-
LED1/GPO MDIN3 LAN_MDI3+ LAN_MDI3- 57
0_0402_5% TPL2 @ 1 Test_Point_12MIL 25 9
LED2 MDIP3 LAN_MDI3+ 57
1

@ +LAN_REGOUT 24 8 +LAN_VDD10
RL9 +LAN_VDDREG 23 REGOUT AVDD10_2 7 LAN_MDI2-
+LAN_VDD10 VDDREG MDIN2 LAN_MDI2+ LAN_MDI2- 57
1K_0402_1% 22 6
PCIE_WAKE#_R DVDD10 MDIP2 LAN_MDI1- LAN_MDI2+ 57
21 5
LANWAKEB MDIN1 LAN_MDI1+ LAN_MDI1- 57
ISOLATE# 20 4
LAN_MDI1+ 57
2

PLT_RST# 19 ISOLATEB MDIP1 3 +LAN_VDD10


8,28,46,47,55 PLT_RST# PCIE_PRX_C_DTX_N0 PERSTB AVDD10_1 LAN_MDI0-
CL10 1 2 0.1U_6.3V_K_X5R_0201 18 2
ISOLATE# RL10 1 @ 2 LAN_PWR_ON# 5 PCIE_PRX_DTX_N0
CL11 1 2 0.1U_6.3V_K_X5R_0201 PCIE_PRX_C_DTX_P0 17 HSON MDIN0 1 LAN_MDI0+ LAN_MDI0- 57 2018/01/24: add AZ5815-01F.R7GR for
5 PCIE_PRX_DTX_P0 HSOP MDIP0 LAN_MDI0+ 57 RTL8111H Lan Surge issue (Default reserve)
0_0402_5%
1

place close to M.2 +LAN_VDD10


RL11
15K_0402_5%
@

1
2

DL4

1
RTL8111H-CG_QFN32_4X4
AZ5815-01FPR7GR_DFN1006P2E-2
@

2
2
For RTL8111GUL(SWR mode)
For RTL8111H (LDO mode)
+LAN_VDD10
LL1 1 2 8111GUL@
2.2UH_NLC252018T-2R2J-N_5%
LAN_XTALI
+LAN_REGOUT RL13 1 2 8111H@
B B
0_0805_5%
LAN_XTALO_R 1 2 LAN_XTALO
1 1

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

1U_6.3V_M_X5R_0201

0.1U_6.3V_K_X5R_0201
RL19 1K_0402_5% 1
YL1 CL3 CL15 CL16 1 1 1 1 1 1
0.1U_6.3V_K_X5R_0201 4.7U_0402_6.3V6M 0.1U_6.3V_K_X5R_0201
2 2 8111GUL@

CL17

CL18

CL19

CL20

CL21

CL22
1 4 8111H@ 8111GUL@
OSC1 GND2 2
2 3 2 2 2 2 2 2
GND1 OSC2 @ @
1 1
CL12 25MHZ_10PF_7V25000014 CL13
15P_0402_50V8J 15P_0402_50V8J
Layout Note: LL1 must be
within 200mil to Pin24,
2 2 CL15,CL16 must be within
200mil to LL1 Close to Pin3, 8, 22, 30 Close to Pin22(Reserved)
+LAN_REGOUT: Width =60mil

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 LAN_RTL8111GUL_H


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. LAN
Date: Monday, February 24, 2020 Sheet 56 of 83
5 4 3 2 1
5 4 3 2 1

DL1/DL2 TL1

1'S PN:SC300005900 1:1 24 LAN_MDO3-


LAN_MDI3- 1 T1/B MX1+
Place Close to TL1 56 LAN_MDI3- TD1+

23 LAN_MDO3+
MX1-
LAN_MDI3+ 2
56 LAN_MDI3+ TD1-
TDCT 3 22
TCT1 T1/A MCT1
DL1
D LAN_MDI3- LAN_MDI2- D
4 3 4 21
I/O3 I/O2 TCT2 1:1 MCT2 LAN_MDO2-
T1/B
20
LAN_MDI2- 5 MX2+
56 LAN_MDI2- TD2+
5 2
VDD GND
19 LAN_MDO2+
LAN_MDI2+ 6 MX2-
LAN_MDI3+ LAN_MDI2+ 56 LAN_MDI2+ TD2-
6 1
I/O4 I/O1
AZ1215-04S.R7G_SOT23-6L-6 T1/A
EMC_8111H@ 1:1 18 LAN_MDO1-
LAN_MDI1- T1/B MX3+
7
56 LAN_MDI1- TD3+

17 LAN_MDO1+
MX3-
LAN_MDI1+ 8
56 LAN_MDI1+ TD3-
DL2 9 16
LAN_MDI1- 4 3 LAN_MDI0- TCT3 T1/A MCT3
I/O3 I/O2
10 15
TCT4 1:1 MCT4 LAN_MDO0-
T1/B
14
5 2 LAN_MDI0- 11 MX4+
VDD GND 56 LAN_MDI0- TD4+
2
LAN_MDI1+ 6 1 LAN_MDI0+ CL24 13 LAN_MDO0+
I/O4 I/O1 LAN_MDI0+ 12 MX4-
0.01U_0201_25V6-K 56 LAN_MDI0+ TD4-
AZ1215-04S.R7G_SOT23-6L-6 1
EMC@
EMC_8111H@
T1/A

BOTH_NA0069R-LF
C C

1
RL17
20_0603_5%

1
DL3

1
2
BS4200N-C-LV_SMB-F2
EMC@

2
2
1 1
CL32 CL25
68P_0402_50V8J 1000P_1206_2KV7-K
EMC@ EMC_NS@
2 2

CHASSIS1_GND

B B

RL14 1 2@ 0_0402_5%

RL15 1 2@ 0_0402_5%

RL16 1 2@ 0_0402_5%

RL24 1 2@ 0_0402_5%

JRJ45

Reserve for EMI go rural solution


CHASSIS1_GND LAN_MDO3- 8
BI_DD-
LAN_MDO3+ 7
BI_DD+
LAN_MDO1- 6
RX_DB-
LAN_MDO2- 5
BI_DC-
LAN_MDO2+ 4
BI_DC+
LAN_MDO1+ 3
RX_DB+
LAN_MDO0- 2
TX_DA-
LAN_MDO0+ 1 9
TX_DA+ GND_1
10
GND_2
ALLTOP_C10261-10839-L
ME@

A CHASSIS1_GND A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 LAN_Transformer


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 57 of 83
5 4 3 2 1
5 4 3 2 1

+1.8VS +1.8VALW +1.8VS


+1.8VALW

RA232 1 @ 2 0_0402_5%
QX33
HDA_BITCLK_AUDIO AON7380_DFN8-5
8 HDA_BITCLK_AUDIO

8 HDA_SYNC_AUDIO
HDA_SYNC_AUDIO +5VALW V20B+ 1
2
HDA_SDOUT_AUDIO 5 3

0.1U_0402_25V6
8 HDA_SDOUT_AUDIO

1
HDA_SDIN0 1
RX33 CX24

1
8 HDA_SDIN0 100K_0402_1% 0.01U_50V_K_X7R_0402

4
CX25
RX35
2

CA7
4.7U_0402_6.3V6M
1 1 1 47K_0402_5%
RX36

2
DMIC_CLK_R

CA48
0.1u_0201_10V6K

CA49
0.1u_0201_10V6K
41 DMIC_CLK_R 2 1

2
DMIC_DATA_R
41 DMIC_DATA_R 2 2 2

0.1U_0402_25V6
10K_0402_5%

3
QX34B D
EC_MUTE#

L2N7002KDW1T1G_SOT363-6
5
52 EC_MUTE#

1
D G D

CX27
52 BEEP# BEEP#

6
QX34A D S RX37

2
PCH_BEEP

L2N7002KDW1T1G_SOT363-6
52,55,62,69 SUSP# 2 430K_0402_1%
8 PCH_BEEP
G

2
S

1
+1.8V_AUDIO
DVDD DVDD_IO +5VD +5VA
Analog power for DACs, ADCs

+5VD
Note: DVDD-IO must be equal to or smaller than DVDD

0.1U_6.3V_K_X5R_0201

2.2U_0402_6.3V6M
+5VA
2 2

CA2
DVDD_IO
+3VS DVDD +1.8V_AUDIO

CA1
+1.8VALW
+1.8VS
@ @ @ 1 1
RA3 1 2 0_0402_5% RA1 1 2 0_0402_5% RA2 1 2 0_0402_5%

18

46

41

40

20
3
UA1
2.2U_0402_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201

DVDD

DVDD-IO

PVDD2

PVDD1

AVDD1

CPVDD/AVDD2
+3VALW 1 2

10U 6.3V M X5R 0402


2 1 Rev1.1 change
CA3

CA4

CA5
RA6 1 @ 2 0_0402_5% CA6 2 SPKR_MUTE#
PDB
2 1
1 2 HDA_BITCLK_AUDIO

CD@
Rev1.1 change 14
HPOUT_L 27 BCLK
HPOUT-L 15 HDA_SYNC_AUDIO
HPOUT_R 26 SYNC
HPOUT-R 47 RA7 2 @ 1 100K_0402_1%
MIC2_VREFOL JD2 +3VS
28 Rev1.1 change
MIC2-VREFO-L 48 JSENSE RA8 1 2@ 0_0402_5% PLUG_IN
Close to Pin7 MIC2_VREFOR 29 JD1
MIC2-VREFO-R
Note: need to configuration 1*JD mode by verb table
1
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
4 DMIC_DATA_C RA9 1 2@ 0_0402_5% DMIC_DATA_R
RING2_CONN 30 GPIO0/DMIC-DATA12
MIC2-L/RING2 5 DMIC_CLK RA10 1 2@ 0_0402_5% DMIC_CLK_R
RING3_CONN 31 GPIO1/DMIC-CLK
+5VS +5VA MIC2-R/SLEEVE 6 CODEC_I2C_SDA_R RA234 1 2@ 0_0402_5% CODEC_I2C_SDA
+5VD PC_BEEP I2C-DATA CODEC_I2C_SDA 54
34
@ +5VS PCBEEP 7 CODEC_I2C_SCL_R RA235 1 2@ 0_0402_5% CODEC_I2C_SCL
I2C-CLK CODEC_I2C_SCL 54
RA11 1 2 0_0402_5%
LA1 1 2 +5VA
0.1U_6.3V_K_X5R_0201

1U_0402_6.3V6K

BLM15PD600SN1D_2P EMC_NS@ 8
RA12 1 2 10K_0402_5% VDD_STB 33 NC1 DVDD
2 2 5VSTB
CA9

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_6.3V_K_X5R_0201

0.1U_6.3V_K_X5R_0201
@ 1 1 2 2 9
NC2
CA8

CA10

CA11

CA12

CA13
RA13 1 2 0_0603_5% LINE2-R 35
LINE2-R 10
1 1@ LINE2-L 36 NC3 CODEC_I2C_SDA_R RA236 1 2 2.2K_0402_5%
2 2 1 1 LINE2-L 11
NC4 CODEC_I2C_SCL_R RA237 1 2 2.2K_0402_5%
12
NC5

CA14 1 2 1U_0402_6.3V6K CBP 23 45 SPK_R+


C CBP SPK-OUT-R+ C

CBN 24 44 SPK_R-
CBN SPK-OUT-R-
43 SPK_L-
SPK-OUT-L-
42 SPK_L+
2.2U_0402_6.3V6M 2 1 CA15 MIC2-CAP 32 SPK-OUT-L+
MIC2-CAP 13
2.2U_0402_6.3V6M 2 1 CA16 VREF 38 DC DET/EAPD
EC_MUTE# RA16 1 2 0_0402_5% @ SPKR_MUTE# VREF
2.2U_0402_6.3V6M 1 2 CA17 LDO3-CAP 19 16 SDATA_IN RA14 2 1 33_0402_5% HDA_SDIN0
LDO3-CAP SDATA-IN
2.2U_0402_6.3V6M 1 2 CA18 LDO2-CAP 21 17 HDA_SDOUT_AUDIO
Rev1.1 change LDO2-CAP SDATA-OUT
2.2U_0402_6.3V6M 1 2 CA19 LDO1-CAP 39
LDO1-CAP 25 CPVEE
CPVEE

Thermal Pad
2
CA20
1U_0402_6.3V6K

AVSS1

AVSS2
1

ALC3287-CG_MQFN48_6X6

37

22

49
Note: power beep function is removed from BIOS spec
@
BEEP# RA17 1 @ 2 EC_BEEP_R CA211 2
4.7K_0402_5%
Rev1.1 change 0.1U_6.3V_K_X5R_0201

CA22
PCH_BEEP RA18 1 2 PC_BEEP1_R 1 2 PC_BEEP
4.7K_0402_5%
1

0.1U_6.3V_K_X5R_0201
RA19
10K_0402_5%
Speaker
JSPK1
@
2

SPK_R+ RA23 1 2 HCB1608KF-121T30_0603 EMC@ SPK_R+_CONN 1


RA21 1 2 0_0402_5% SPK_R- RA22 1 2 HCB1608KF-121T30_0603 EMC@ SPK_R-_CONN 2 1
EMC_NS@ SPK_L+ RA24 1 2 HCB1608KF-121T30_0603 EMC@ SPK_L+_CONN 3 2 5
SPK_L- RA25 1 2 HCB1608KF-121T30_0603 EMC@ SPK_L-_CONN 4 3 GND1 6
RA26 1 2 0_0402_5% @ 4 GND2

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201

220P_25V_K_X7R_0201
1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

1500P_25V_K_X7R_0201

220P_25V_K_X7R_0201
HDA_SYNC_AUDIO HIGHS_WS33041-S0191-HF

CA27

CA28

CA29

CA30
CA23

CA24

CA25

CA26
RA27 1 2 0_0402_5% @ ME@
HDA_SDOUT_AUDIO DMIC_CLK_R 2 2 2 2
1 1 1 1
EMC_NS@
HDA_BITCLK_AUDIO_R 1 2 HDA_BITCLK_AUDIO DMIC_DATA_R RA29 1 2 0_0402_5%
For EMC Near CODEC

EMC@

EMC@

EMC@

EMC@

CD@

CD@

CD@
RA28 1/16W_27_5%_0402 EMC_NS@ 1 1 1 1

CD@
HDA_SDIN0 2 2 2 2
100P 25V J NPO 0201

100P 25V J NPO 0201


22P_0201_258J

EMC@

EMC_NS@

1 1
22P_0201_258J

EMC_NS@

33P_50V_J_NPO_0201

33P_50V_J_NPO_0201

CA31

CA32

1 GND GNDA
EMC_NS@

CA34

EMC_NS@

EMC_NS@

1 1 1
CA33

CA35

CA36

B B
2 2
2 For EMC Near Conn.
2 2 2
Rev1.1 change

RING3_CONN
RING2_CONN
A_HP_OUTL_R
Audio Jack
A_HP_OUTR_R
PLUG_IN JHP1

RA30 0_0402_5% CA37 470P_50V_K_X7R_0201 MIC2_VREFOL RA31 2 1 2.2K_0402_5% RING2_CONN 3


2A_HP_OUTL_R_C A_HP_OUTL_R HPOUT_L A_HP_OUTL_R G/M
AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

AZ5123-01F.R7GR_DFN1006P2X2

1 @ 1 2 @ RA32 1 2 56_0402_5% 1
L
1

PLUG_IN
47P_25V_J_NPO_0201

LINE2-L CA38 1 @ 2 1U_0402_6.3V6K 5


5
EMC_NS@

1 DA7 DA3 DA4 DA5 DA6


1

1
CA39

LINE2-R CA40 1 @ 2 1U_0402_6.3V6K 6


6
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC@

CA41 HPOUT_R RA34 1 2 56_0402_5% A_HP_OUTR_R 2


2 RA35 0_0402_5% 470P_50V_K_X7R_0201 R
2A_HP_OUTR_R_C A_HP_OUTR_R MIC2_VREFOR RING3_CONN
2

1 @ 1 2 @ RA36 2 1 2.2K_0402_5% 4
M/G
2

100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201

100P 25V J NPO 0201


7

CA42

CA43

CA44

CA45
MS
1 2 1 1
RIYUE-3F137-01J02
ME@
For EMI

EMC@

EMC@
2@ 1@ 2 2
Rev1.1 change

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Codec ALC3287


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Custom
Y550 1.0

Date: Monday, February 24, 2020 Sheet 58 of 83

5 4 3 2 1
5 4 3 2 1

D D

+3VS +3VS_GS

RS1 1 @ 2 0_0402_5%
APS G-Sensor

+3VS_GS
TABLE
TABLE of G-Sersor (UGSEN1)
RS2 1 GS@ 2 10K_0402_5% GSENSE_INT P/N ADDR_SEL Address
Vendor P/N LCFC P/N
ST LIS2DWLTR SA00009AQ00
H 32h (W) & 33h (R)
Kionix KX022-1020 SA000081E00 LIS2DWLTR
+3VS_GS L 30h (W) & 31h (R)

H 3Eh (W) & 3Fh (R)


2

RS3
KX022-1020
@
L 3Ch (W) & 3Dh (R)
10K_0402_5%
1

C ADDR_SEL C
2

RS4
GS@
0_0402_5%
1

+3VS_GS

1
RS5
@ 0_0402_5%

2
US2 @
@ ADDR_SEL 1 12 EC_SMB_CK2_G RS6 1 2 0_0402_5% EC_SMB_CK2
EC_SMB_DA2 EC_SMB_DA2_G SDO/SA0 SCL/SPC EC_SMB_CK2 7,28,52,60
RS7 1 2 0_0402_5% 2 11
7,28,52,60 EC_SMB_DA2 +3VS_GS SDA/SDI/SDO NC
3 10
@ 4 VDD_IO CS 9
GSENSE_INT RS8 1 2 0_0402_5% GSENSE_INT_R 5 RES GND_2 8
52 GSENSE_INT INT1 GND_1
1 Test_Point_12MIL 6 7
TPS1 @ INT2 VDD
1 1
USED EC KSIO FOR INT, need confirm LIS2DWLTR_LGA12_2X2
1 1 SA00009AQ00 GS@ CS3 CS2
GS@ 0.1U_0402_10V7K @ 100P 25V J NPO 0201
CS1 CS4 GS@ 2 2
100P 25V J NPO 0201 0.1U_0402_10V7K
2 2 CLOSE VDD
@
CLOSE VDDIO

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 USB2.0


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 59 of 83
5 4 3 2 1
5 4 3 2 1

Fintek(1 Local+2 Remote) thermal sensor +3VS +3VS

placed near DIMM


REMOTE+/-_R, REMOTE1+/-, REMOTE2+/-:
Trace width/space:10/10 mil
Trace length:<8"

2
+3VS Near CPU FAN RS17 RS18
US1 4.7K_0402_5% 4.7K_0402_5% REMOTE1+
Near GPU&VRAM REMOTE2+
Near CPU core
@ @ 1 1

1
C C

1
1 10 EC_SMB_CK2 CS5 2 QS15 CS6 2 QS16
D VCC SCL EC_SMB_CK2 7,28,52,59 B B D
3300P_0402_50V7-K MMBT3904WH_SOT323-3 3300P_0402_50V7-K MMBT3904WH_SOT323-3
1 REMOTE1+ 2 9 EC_SMB_DA2 @ 2 E @ 2 E
EC_SMB_DA2 7,28,52,59

3
DP1 SDA REMOTE1- REMOTE2-
CS7 REMOTE1- 3 8 THEM_ALERT# RS13 1 2 0_0402_5%
.1U_0402_10V6-K DN1 ALERT# SMB1_ALERT# 52
2 THERM_L @
REMOTE2+ 4 7
@ DP2 THERM#
REMOTE2- 5 6
DN2 GND

F75303M_MSOP10

Near GPU&VRAM
Near CPU

+5VLP +5VLP +3VALW


+5VLP +3VALW

HW thermal sensor

1
2

CS12 RS29 RS36 RS19

1
0.1U_0603_25V7-M 21.5K_0402_1% 21.5K_0402_1% 13.7K_0402_1%
@ @ @ @ RS21
1

13.7K_0402_1%

2
@
US18 NTC_V1_GPU
52 NTC_V1_GPU

2
1 8 TMSNS1 RS88 1 @ 2 0_0402_5% NTC_V1_GPU
VCC TMSNS1

1
NTC_V2_CPU
52 NTC_V2_CPU
2 7 PHYST1 RS9 1 @ 2 10K_0402_5% RTS2
GND RHYST1 @ 100K_0402_1%_TSM0B104F4251RZ
3 6 TMSNS2 RS10 1 @ 2 0_0402_5% NTC_V2_CPU
OT1 TMSNS2
C C

1
4 5 PHYST2 RS11 1 @ 2 10K_0402_5%
52,68,70 EC_ON OT2 RHYST2 RTS3
G718TM1U_SOT23-8 @ 100K_0402_1%_TSM0B104F4251RZ

2
@
RS20

2
0_0402_5%
over temperature threshold:
RSET=3*RTMH

1
92+/-30C @

Hysteresis temperature threshold.


RHYST=(RSET*RTML)/(3*RTML-RSET)
56+/-30C

for layout optimized, change the EC_AGND to GND

Nuvoton(1 Local+1 Remote) thermal sensor +3VS +3VS

placed near TBD Near DIMM


+3VS +3VS

2
+3VALW
RS93 RS92
2.2K_0402_5% 2.2K_0402_5%
2

1
2
+3VS R443 R441 RS22
Near PCH

G
1

1
4.7K_0402_5% 4.7K_0402_5% 13.7K_0402_1%
@ @ @
US134
1

2
1 8 THM_SMCLK0 THM_SMCLK0 1 6 EC_SMB_CK0

S
VDD SCL EC_SMB_CK0 43,52,53,54 NTC_V3_DIMM

D
52 NTC_V3_DIMM

5
NT_REMOTE1+ 2 7 THM_SMDAT0

G
B 1 D+ SDA QS22A B
C363 NT_REMOTE1- 3 6 R442 1 2 0_0402_5% SMB1_ALERT# 2N7002KDWH_SOT363-6
D- ALERT#

1
.1U_0402_10V6-K
2 @ THM_SMDAT0 EC_SMB_DA0
@ 4 5 4 3 RTS4

S
T_CRIT# GND EC_SMB_DA0 43,52,53,54

D
@ 100K_0402_1%_TSM0B104F4251RZ
NCT7718W_MSOP8
QS22B
SMBus Address: 1001_100xb

2
2N7002KDWH_SOT363-6

2
RS23 RS12
0_0402_5% 0_0402_5%
NT_REMOTE1+ @
NT_REMOTE1- NT_REMOTE1+ 55
NT_REMOTE1- 55

1
@
Thermal Diode Near GPU FAN(DB)
NT_REMOTE1+/-: EC_AGND
Trace width/space:10/10 mil
Trace length:<8"
Address 1001_101xb FAN Conn Right
FAN Conn LEFT
+5VS
+5VS JFAN2
JFAN1
RS52 1 2 0_0603_5% +5VS_FAN1 1 RS75 1 2 0_0603_5% +5VS_FAN2 1
@ 2 1 2 1
52 EC_FAN1_SPEED 2 52 EC_FAN2_SPEED 2
1 3 1 @ 1 3 5
52 EC_FAN1_PWM 3 52 EC_FAN2_PWM 3 GND1
1 4 CS10 4 6
CS8 CS9 4 CS11 .1U_0402_10V6-K 4 GND2
A 10U_0805_10V6K .1U_0402_10V6-K 5 10U_0805_10V6K @ A
2 @ 6 GND1 2 2 HIGHS_WS32041-S0471-HF
2 GND2
ME@

HIGHS_WS33040-S0351-HF
ME@

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Thermal sensor/FAN CONN


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 60 of 83
5 4 3 2 1
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 XDP


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y540
Date: Monday, February 24, 2020 Sheet 61 of 83
5 4 3 2 1
A B C D E

+1.8VALW +1.8VS_AON

+5VALW to +5VS +1.8VALW to +1.8VS_AON


+3VALW
+5VLP +5VALW QX4
AON7380_DFN8-5
5VS_CT2 +0.6VS
1
V20B+

1000P_0402_50V7K
+5VALW 1

1
CX1 +3VS 1 2

0.1U_0402_25V6
UX2

CX5
1U_0402_16V6K RX10 RX8 5 3

1
2 1 14 100K_0402_5% @ 100K_0402_5% RX9
1 1

1
2 IN1_1 OUT1_2 13
Change net to SUSP# for PWR sequence CX10 47_0603_5% RX16 @ CX17

1
@ IN1_2 OUT1_1 .1U_0402_10V6-K 2 @ 100K_0402_1% 0.01U_50V_K_X7R_0402 RX18 1

4
3VS_CT1

CX18
SUSP# RX13 1 2 0_0402_5% 3 12 @ RX15 OPT@ OPT@ @ 1/10W_47_5%_0603 CX13

2
EN1 CT1 2 SUSP 47K_0402_5% 2 @ 10U_0603_6.3V6M
42 SUSP

2
4 11 OPT@ RX20 @

2
@ VBIAS GND D 1 2 2

2
RX14 1 2 0_0402_5% 5 10 5VS_CT2 +5VS 2 SUSP 1K_0402_5%

0.047U_0402_25V7K
+5VALW EN2 CT2 3VS_CT1 G QX18 OPT@

3
2200P_0402_25V7-K
1 V1.0 6 9 D 2N7002KW_SOT323-3 QX25B D
IN2_1 OUT2_2 +1.8VS_AON_EN#

L2N7002KDW1T1G_SOT363-6
1 7 8 SUSP# 2 S @ 5 1
1 2 52,55,58,69 SUSP# 1

3
IN2_2 OUT2_1

CX16

OPT@
CX4
CX3 1 CX9 G QX6 G

1
0.01U_50V_K_X7R_0402 15 .1U_0402_10V6-K 2N7002KW_SOT323-3

6
2 CX2 Thermal Pad @ S QX25A OPT@ S RX21
D
@

4
2 1 2

L2N7002KDW1T1G_SOT363-6
1U_0402_10V6K RX17 1 @ 2 0_0402_5% 2 430K_0402_1%
2 G2898KD1U_TDFN14P_2X3 8,28 PXS_PWREN G OPT@ OPT@

1
D
DX12

2
RX22 S +1.8VS_AON_EN# 2 QX23

1
3 1 2 0_0402_5% CX15 RX19 G L2N7002KWT1G_SOT323-3
0.1U_0402_25V6 100K_0402_5% @
1 OPT@ OPT@ @ S

3
RX23 59K_0402_1%

2
2 1 2

LBAT54SWT1G_SOT323-3OPT@
OPT@

AON6324
VDS=30V VGS=+_12V, ID=85A,
Rds=2.8mohm @ VGS=10V
APU Power control
+3VALW TO +3VALW_APU
+0.75VALW QX3 +/- 5% 2A VGS(th)=2.25V Max
+/- 2% AON6324_DFN8-5
+0.75VS
SB00000QP0J LP2301ALT1G 1P SOT-23-3 MAX 0.25A
Load MOS N MOS Id =< -1.6A, Vgs(th) Max >= 1V
1 Vds max 20V, Vgs Max ±8V,Rds(on) >= 150mohm +3VALW 3VS Modify +3VALW 0726 +3VALW_APU
2 1 1
1 5 3 CX22 @
CX23 CX21 1U_0402_6.3V6K +3VALW RX24 1 2 1/2W_0.01_+-1%_0603_50PPM/C
0.01U_6.3V_K_X7R_0201

10U_0603_6.3V6M 10U_0603_6.3V6M

1
@ 2 2
1 1
4

2 CX6 CX7 RX11


0.1U_0201_6.3V6-K 470_0603_5% LP2301ALT1G_SOT23-3
2 @ @ @ +3VL RX25 2
2 2 3 1 +3VALW_M 1 2

D
+3VALW Modify +3VL 726 QX5
V20B+

1
RX26 0_0603_5%
RX12 RX30 RX31 Change RX14 130K to 768K For QX3 GS 0819 100K_0201_5%

G
2
+0.75VS_GATE_R2 1 2 10.75VS_GATE 1 2 RX27

0.1U_6.3V_K_X5R_0201
0_0402_5%

2
0_0402_5% 0_0402_5% 768K_0402_1% 1 2 EC_ON_APU
1
1

1
1 D D
CX8 RX32 2 QX2 SUSP 2 QX32 RX28

1
0.01U_0201_25V6-K 1M_0402_5% G L2N7002KWT1G_SOT323-3 G L2N7002KWT1G_SOT323-3 0_0402_5% D 1 CX19
@ EC_ON_APU 1 2 2 QX31 2
2 52 EC_ON_APU
S S G L2N7002KWT1G_SOT323-3 CX20
2

1
@ 0.1U_6.3V_K_X5R_0201
RX29 S 2

3
100K_0201_5%
@

2
@

3 3

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 DC V TO VS INTERFACE


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
D
Y540 1.0

Date: Wednesday, February 26, 2020 Sheet 62 of 83


A B C D E
5 4 3 2 1

HDMI Logo PCB MB GPU


ZZZ1 HDMI@ ZZZ2 UV1 UV1

N18PG62@
N18PG61@

HDMI Logo PCB 1HW NM-D041 REV1.0 M/B S IC N18P-G61-MP2-A1 BGA 960P GPU 12 ! S IC N18P-G62-A1 BGA 960P GPU 12 !
RO00000040J DAZ1QE00100 SA0000AQ800 SA0000AE700

D D

CPU
UC1 R5@ UC1 R7@

S IC RYZEN 5 100-000000100 3.2G IP 12S! IC RYZEN 7 100-000000098 2.9G IP 12 !


SA0000AGQ20 SA0000AGP20

UV4 UV6 RV192 RV194


Samsung 4GB VRAM
X76S4GX4@ X76S4GX4@ X76S4GX4@ X76S4GX4@
ZZZ4 S4GX4@

S IC D6 8G/1750 K4Z80325BC-HC14 FBGA 180P 11GBPS@1.2V 12


S IC
! D6 8G/1750 K4Z80325BC-HC14 FBGA 180P 11GBPS@1.2V 12 ! 100K_0402_5% 100K_0402_5%
SA00009L430 SA00009L430 SD02810038J SD02810038J

UV5 UV7 RV193


SAMSUNG_4GB_VRAM
X7648U12002
X76S4GX4@ X76S4GX4@ X76S4GX4@

S IC D6 8G/1750 K4Z80325BC-HC14 FBGA 180P 11GBPS@1.2V 12


S IC
! D6 8G/1750 K4Z80325BC-HC14 FBGA 180P 11GBPS@1.2V 12 ! 100K_0402_5%
SA00009L430 SA00009L430 SD02810038J
C C

UV4 UV6 RV187 RV194

Micron 4GB VRAM X76M4GX4@ X76M4GX4@ X76M4GX4@ X76M4GX4@

ZZZ5 M4GX4@
S IC D6 256M32 MT61K256M32JE-14:A FBGA 180P 11GBPS@1.2VS12IC! D6 256M32 MT61K256M32JE-14:A FBGA 180P 11GBPS@1.2V 12
100K_0402_5%
! 100K_0402_5%
SA00009L530 SA00009L530 SD02810038J SD02810038J

RV193
UV5 UV7
MICRON_4GB_VRAM
X7648U12001 X76M4GX4@
X76M4GX4@ X76M4GX4@

100K_0402_5%
SD02810038J
S IC D6 256M32 MT61K256M32JE-14:A FBGA 180P 11GBPS@1.2VS12IC! D6 256M32 MT61K256M32JE-14:A FBGA 180P 11GBPS@1.2V 12 !
SA00009L530 SA00009L530

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Virtual symbol


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Thursday, February 27, 2020 Sheet 63 of 83
5 4 3 2 1
5 4 3 2 1

H1 H2 H3 H4 H5 H6 H7
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
@ @ @ @ @ @ @
1

1
D D
PAD_D2P5 PAD_D2P5 PAD_D2P5 PAD_D2P5 PAD_D2P5 PAD_D2P5 PAD_D2P5

SH9 ME@ SH13 ME@ SH16 ME@


H8 H9 H10 H11
HOLEA HOLEA HOLEA HOLEA 1 1 1
@ @ @ @ 1 1 1
1

1
SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
PAD_CT6P4B7P0D3P4 PAD_C7P0D3P3 PAD_D3P3 PAD_CT6P5D2P5 SH10 ME@ SH14 ME@

1 1 SH17 ME@
1 1
1
1

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P
H12 H13 H14 H15 H16 H17
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA SHIELDING_SUL-35A2M_9P2X3P3_1P
C
@ @ @ @ @ @ C
SH18 ME@ SH15 ME@
1

1
1 1
1 1
PAD_C8P0D3P0 PAD_C8P0D3P0 PAD_C8P0D3P0 PAD_C8P0D3P0 PAD_C8P0D3P0 PAD_C8P0D3P0

SHIELDING_SUL-35A2M_9P2X3P3_1P SHIELDING_SUL-35A2M_9P2X3P3_1P

SH12 ME@
H18
HOLEA 1
@ 1
1

SHIELDING_SUL-35A2M_9P2X3P3_1P
PAD_C7P0D2P5
SO-DIMM Shielding
H22 H23 H25 H26 NH26
B HOLEA HOLEA HOLEA HOLEA HOLEA B
@ @ @ @ @
1

CHASSIS1_GND PAD_CB6P5D2P5 PAD_CT7P0B6P2D3P2 PAD_CT6P0D2P8 pad_o2p2x2p5d2p2x2p5n


PAD_C8P0D2P5

HICT1 HICT2 HICT3


HOLEA HOLEA HOLEA
@ @ @ FD1 FD2 FD3 FD4 FD5 FD6
1

1
PAD_C2P5D2P5N PAD_C2P5D2P5N PAD_C2P5D2P5N

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2019/07/02 Deciphered Date 2020/02/24 Hole


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
B
Y550 1.0

Date: Monday, February 24, 2020 Sheet 64 of 83


5 4 3 2 1
5 4 3 2 1

B+ +5VLP/ 100mA
Richtek Silergy
Adaptor RT6585B +5VALW/14A SY8032 +1.0VGS/2A
D
EC_ON_5V EN1 Switch Mode Converter
D

ALW_PWRGD 1V0_MAIN_EN EN
230W/20V FOR SYS PGOOD FOR GPU PGOOD
Page 68
Page 78
EC_ON EN2 +3VLP/ 100mA

+3VALW/ 8A GMT
G9661 +2.5V/600mA
SYSON EN LDO
FOR DDR PGOOD

Richtek Page 69
+1.2V/10A
RT8231
Switch Mode +0.6VS/1A
SYSON S5 FOR DDR Silergy
SM_PG_CTRL S3 Page 69 PGOOD +1.8VALW/3.4A
SY8033
EC_ON_1.8V EN Converter
FOR GPU PGOOD

Silergy Page 79
TI SY8286 +1.05VALW/ 6A
C
BQ24780SRUYR Converter C

EC_ON_1V EN FOR PCH PGOOD


Battery Charger Page 71

Switch Mode
Page 59 Richtek
RT8816 FBVDDQ/ 35A
Switch Mode
VRAM_VDDQ_ADJ EN PGOOD VDDQPWROK
FOR GPU
Page 77
SMBus

Silergy
SY8286 VCCIO/ 6A
Converter
SUSP# EN FOR CPU PGOOD VCCIO_PG
Page 72

MPS VCC_CORE/86A/140A

B
MP2979 VCCGT/25A/32A B
Switch Mode
FOR CPU Core VCCSA/10A
CPUCORE_ON EN
Page 73-76 PGOOD
CPU_PWRGD

Battery ON
Li-ion NCP81611 NVVDD/90A/225A
Switch Mode
3S1P/57WH FOR GPU NVVDD
NVVDD_EN EN PGOOD NVVDD_PWRGD
Page 71

A A

Security Classification LC Future Center Secret Data Title


Issued Date 2018/08/02 Deciphered Date 2018/08/02 Power Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER. Y550
Date: Wednesday, February 26, 2020 Sheet 65 of 83
5 4 3 2 1
5 4 3 2 1

+3VL

PL201 EMC@

1
HCB2012KF-121T50_0805
1 2
VIN PR201 @
0_0603_5%
VCCRTC
JDCIN1
PL202 EMC@
PF201 RTC_VCC

2
1 HCB2012KF-121T50_0805 PR203
GND_1 PR202 PD201
2 APDIN 1 2 1 2 47K_0402_1%
POWER_1 VCCRTC_D_R 0_0603_5% VCCRTC_D
3 2 1 2 1 3
DETECT(ID) 4 12A_24V_F1206HB12V024T/M
POWER_2 @
5 @ 1
D GND_2 D

0.1U_0402_25V6
6

0.1U_0402_25V6
1000P_0402_50V7K

1000P_0402_50V7K
EMC_NS@
GND_3

EMC_NS@
RTC_VCC_R

PC201 EMC@

PC204 EMC@
7 1 2 2
GND_4 For 15"

1
PC203
PC202
PR204
HIGHS_PJSSS56-B4000-1H ADAPTER_ID 52,67 JRTC1 BAT54CW_SOT323-3
1K_0603_5%

2
ME@ 1
1 2
2 3
GND1

1
4 PC205
GND2
1U_0402_10V6K
@

2
HIGHS_WS33020-S0351-HF
ME@

ME@
ALLTO_C51126-112Z9-C
JBATT1
1
VMB BATT+
1 2 PL204 EMC@
2 3 HCB2012KF-121T50_0805
C C
3 4 1 2
4 5 EC_SMCA
5 6 EC_SMDA
6 7 PL205 EMC@
7 8 HCB2012KF-121T50_0805
8
3

1
9 PC206 1 2 PC207
9 10 1000P_0402_50V7K 0.01U_0402_25V7K
10 11 PL206 EMC@
EMC@ EMC@
2

2
11 12 HCB2012KF-121T50_0805
12 13 1 2
GND1
1

14
100_0402_1%

GND2 15
PR205

GND3
1

16
100_0402_1%

GND4
PR206

2
2

PD203 EC_SMB_CK1 52,67,72,79


AZC199-02S.R7G_SOT23-3
EMC_NS@
EC_SMB_DA1 52,67,72,79

PR207 1 2 100K_0402_1%
+3VALW

BATT_TEMP_IN 1 2
BATT_TEMP 52,67 A/D
PR208
10K_0402_5%

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-DCIN/BATT/RTC


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C Y550 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, February 26, 2020 Sheet 66 of 83
5 4 3 2 1
5 4 3 2 1

PQ101 PQ102
AONS32304_DFN8-5 AONS32314_DFN8-5
P2 V20B+
VIN 1 1 P3
2 2 PR101
5 3 3 5 1 4

2 3

EMC_NS@

EMC_NS@
0.01U_0402_25V7K

0.01U_0402_25V7K
4

4
0.01_1206_1%

1
D D

PC103

PC104
1

1
PC102
PC101 0.022U_0402_25V7K

2
470P_0402_50V7K PR102

2
4.7_0603_5% PQ103

5
AONS32314_DFN8-5

2
1 2

PC105 780s_BATDRV 4

1
PC106 0.1U_0402_25V6 PC107
0.1U_0402_25V6 0.1U_0402_25V6

BQ24780_ACN
BQ24780_ACP
2

3
2
1
1
PR103
499K_0402_1% PC108
VIN BATT+ 0.01U_0402_25V7K

2
2
780s_ACDRV_R

3
PD101
V20B+
BAT54CW_SOT323-3

0.1U_0402_25V6

10U_0805_25V6K

10U_0805_25V6K
1780s_VCC_R
1

2
EMC@

PC110

PC111
VIN
1

PC109
4.02K_0603_1%

4.02K_0603_1%

1
PR104

PR105
ACDET Threshold:min:17.878V BQ24780S_VDD
BAT Max V=17.6V

5
1/16W_43.2K_1%_0402 PR107
2

1
PR108 PR106 PC112 10_1206_5% PQ104
6.49K_0402_1% 1U_0603_25V6K AON7380_DFN8-5

ACN
ACP
C 1 2 C

2
1 2 780s_VCC 28 24 1 2

2
VCC REGN 2.2U_0603_10V6-K PC113 4
2 1 780s_ACDET 6 PC115
PC114 ACDET 0.047U_0603_16V7K
0.01U_0402_25V7K 25 780s_BS
1 2780s_BS_R
2 1
BTST PR109 PR110
BATT+

3
2
1
2.2_0603_5% 2.2UH_PCMB063T-2R2MS_8A_20% 0.01_1206_1%
780s_CMSRC 3 26 780s_HG PL101
CMSRC HIDRV 1 2 1 4
780s_ACDRV 4
ACDRV 2 3

0.1U_0402_25V6
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
27 780s_LX

5
PR111 @
PHASE

EMC@
0_0402_5% PR112

2
PC118
1 2 780s_ACOK 5 PQ105

PC116

PC117

PC139

PC140
ACOK 4.7_0805_5%
52 ACIN PU101 AONR32340C_DFN8-5
780s_SDA 11
EMC_NS@

1
52,66 EC_SMB_DA1 SDA 23 780s_LG 4

780s_SN
LODRV G
780s_SCL 12 22

S3
S2
S1
SCL GND

1
52,66 EC_SMB_CK1
PC119

3
2
1
7 29 1000P_0402_50V9-J

0.1U_0402_25V6

0.1U_0402_25V6
2
52 ADP_I IADP PAD
EMC_NS@

1
780s_BATDRV

PC120

PC121
8 18
52 BATT_I IDCHG BATDRV
9
52,72 PSYS

2
PMON 17 780s_BATSRC 1 2 780s_BATSRC_R
BATSRC PR118 10_0603_5%
20 780s_SRP 1 2 780s_SRP_R
10 SRP PR119 10_0603_5%
100P_0402_50V8J

100P_0402_50V8J

100P_0402_50V8J

52 VR_HOT#
1

1
PROCHOT#
1

PR120 13 PC123
10K_0402_1% CMPIN
0.1U_0402_25V6
V charge (MAX):17.6V

2
BATPRES#
I charge (MAX):7.2A
PC122

PC124

PC125

14

TB_STAT#
2

CMPOUT 19 780s_SRN 1 2 780s_SRN_R


FSW:800K
2

21 SRN PR121 10_0603_5%


ILIM
2

B B
PR122

780s_TB# 16

15
0_0402_5% BQ24780SRUYR_QFN28_4X4
@
+3VALW
1

1 2 780s_ILIM_R 1 2
+3VALW BATT_TEMP 52,66
PR123 PR124
1

105K_0402_1% 32.4K_0402_1%
1

PR125
PC126 100K_0402_1%
0.1U_0402_25V6
V20B+
2

IchargeLIM=8.05A
IDischargeLIM=32.2A
1

PR126

1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K

1000P_0402_25V7-K
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
750_0603_1%
2

1
PC127

PC128

PC129

PC130

PC131

PC132

PC133

PC134

PC135

PC136
2

2
ADAPTER_ID 52,66
680P_0402_50V7K

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@
AZ5123-01F.R7GR_DFN1006P2X2
1
0.1U_0402_25V6

@
1
1

1
PC137

PC138

PD102

@
A A
2

2
2

Security Classification LC Future Center Secret Data Title


Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-charger
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y550 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, February 26, 2020 Sheet 67 of 83

5 4 3 2 1
5 4 3 2 1

D D

+3VALW_VIN
PJ2001
+5VLP 2 1
+3VLP 2 1 +3VL 1A
JUMP_43X39

0.1U_0402_25V7-K

62K_0402_1%

@
+3VALW_VIN

4.7U_0603_6.3V6K
PC2001

4.7U_0603_6.3V6K
0_0603_5%
V20B+ V20B+

10K_0402_1%
1

1
PC2002

@PR2003

PC2003
2

PR2002
PJ2002
PJ2003

2
1 2
+3VALW Vout=5V+-5%

1
1 2 +5VALW_VIN 2 1

+3V5V_CS2 2

+3V5V_CS1 2
2 1
Vset=5.06V+-1.5%

PR2001
JUMP_43X79

0.1U_0402_25V6

+5V_LDO
JUMP_43X118 FSW=500KHz(RT6585:400K)

10U_0805_25V6K

10U_0805_25V6K
1

2
@

PC2004

0.1U_0402_25V6
EMC_NS@
+3VLP

PC2005

PC2006

10U_0805_25V6K

10U_0805_25V6K
1

@
PC2009
PR2004
TDC=14A OCP=20A

PC2007

PC2008

EMC_NS@
C 100K_0402_1% C

2
Vout=3.3V+-5% PU2001 OVP=Vout*113%

2
12

13
UVP=Vout*52%

5
Vset=3.3V+-1.82% RT6585CGQW_WQFN20_3X3

VIN

CS2

CS1

LDO5

LDO3
FSW=600KHz (RT6585:475K)

AON6380_DFN8-5
21

PQ2001
AONR32340C_DFN8-5

D
ALW_PWRGD 7 GND
TDC=8A OCP=14A @

PQ2002
16,69 ALW_PWRGD PGOOD PJ2006

+3VALW OVP=Vout*113% 4 +3V_UG 10 UGATE1


16 +5V_UG
PR2006 PC2011
4 2
2 1
1

UVP=Vout*52% G PC2010 PR2005 UGATE2 2.2_0603_5% 0.1U_0603_25V7K


JUMP_43X118
+5VALW
0.1U_0603_25V7K 2.2_0603_5% 17 +5V_BST 1 2 1 2 1.5UH_CMMB104T-1R5MS_16A_20%

S1
S2
S3
1.5UH_PCMB063T-1R5MS_10A_20% 1 2 1 2 +3V_BST 9 BOOT1
PL2002 PJ2005 @

3
2
1
BOOT2
PJ2004 PL2001

1
2
3
18 +5V_LX 1 2 +5VALWP 2 1
2 1 +3VALWP 1 2 +3V_LX 8 PHASE1 2 1
2 1 PHASE2
JUMP_43X118

5
15 +5V_LG

5
14A
330P_0402_50V7K

JUMP_43X118 LGATE1

2
+3V_LG 11

AONR32340C_DFN8-5

D
680K_0402_1%

SKIPSEL
1

2
LGATE2
@

AON6324_DFN8-5
14 PR2009

PQ2003
1

BYP1
220U_B2_6.3VM_R25M

PR2008

PQ2004
1/8W_2.2_5%_0805
PC2012

PR2007

PR2011
EN2

EN1
FB2

FB1
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

1 4.7_0805_5% EMC@
1

22U_0603_6.3V6-M
0.1U_0402_25V6

0.1U_0402_25V6
4 4
PC2016

PC2017
PC2014

PC2015

PC2018

PC2019

PC2020

PC2021

PC2023 @
2

1
EMC_NS@ G

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
PC2013

+
@

13K_0402_1%

20

19

2
2

1
PC2022

220U_B2_6.3VM_R25M
+

PC2024

PC2025

PC2026

PC2027

PC2028
S1
S2
S3
2

PR2010

+5V_FB
2 @ @

EC_ON_3V_R

EC_ON_5V_R

RT8249_USM
1

1
2
3

3
2
1

2
1
2

1
1
PC2030 @

30K_0402_1%
PC2029
1

1000P_0402_50V9-J 1000P_0402_50V9-J @

2
1

EMC@
PC2031

EMC_NS@
2
0.01U_0402_25V7K
2
@

+3V_FB
2

PR2014 @
0_0402_5% @
B PR2013 2 1 2 1 B
52,60 EC_ON EC_ON_5V 52
20K_0402_1%

1
1M_0402_5%
PR2015

0.1U_0402_10V7K

1M_0402_5%
1

0.1U_0402_10V7K
PR2016
@ PC2032

PR2017

1
@ PC2033
@
Vout=2V*(1+PR610/PR613) 0_0402_5%

2
PR2018 Vout=2V*(1+PR612/PR616)

2
19.6K_0402_1%

2
+3VL
2

PR2020
100K_0402_1% @
PR2012 @
1

0_0402_5%
2 1 RT8249_USM
52,60 EC_3V/5V_USM

1 2

PR2019
200_0402_1%
@

EC_3V/5V_USM H DEM L ASM defualt H


A PR2012 for RT8249C PR2019 for RT6585 A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-3/5VALW


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Size
Custom
Document Number
Y550 Rev
0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, February 26, 2020 Sheet 68 of 83
5 4 3 2 1
A B C D

Vout=1.2V±5%
Vout=0.6V±5%
V20B+ Vset=1.205V±1.74%
OCP=1.5A
TDC=10A
PJ2701
@ VTT=1/2VDDQ
+1.2V_VIN 2 1 1.5A OCP=15A
2 1
JUMP_43X79
Vref=0.75+-%(VID=H VFB=0.675)

0.1U_0402_25V6
@ OVP=(1.25~1.35)*Vref

10U_0805_25V6K

10U_0805_25V6K
1

1
PC2701
UVP=(0.7~0.8)*Vref

PC2702

PC2703
Fsw=500K

2
+1.2VP
1 1

1A

5
PC2704 PQ2701
PR2701
0.1U_25V_K_X7R_0402

D
2.2_0603_5% AONR32340C_DFN8-5
PC2705 1 2 +1.2V_BST_R 1 2
10U_0603_6.3V6M
1 2 1 2 +1.2V_UG_R 4
+0.6VSP G +1.2V

@
PR2702 0_0603_5%

S3
S2
S1
PL2701
PJ2705

3
2
1
0.68UH_PCMB063T-R68MS_16A_20%
1A +1.2V_LX 1 2 10A +1.2VP 2 1

+1.2V_BST
2 1

+1.2V_UG

+1.2V_LX
22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
JUMP_43X118

22U_0603_6.3V6-M

22U_0603_6.3V6-M
1

1
@
PC2706

PC2711
PR2703

PC2707

PC2709

PC2710

PC2712

PC2713

PC2714
PC2708
5
4.7_0805_5%
20

19

18

17

16
2

2
PQ2702 EMC_NS@
AON7380_DFN8-5
VLDOIN

UGATE

PHASE
VTT

BOOT

2
21 @ @
PAD
1 15 +1.2V_LG 4
VTTGND LGATE 1A

+1.2V_SN
2 14
VTTSNS PGND
+1.2VP +0.6VSP +0.6VS

3
2
1
PU2701 PR2704 @
3 13 +1.2V_CS 1 2 +5VALW PJ2702
GND RT8231AGQW_WQFN20_3X3 CS 300K_0402_1% PR2705 2 1
2 1

1
5.1_0603_5% PC2715

2
VTTREFP 4 12 +1.2V_VDD 1 2 1000P_0402_50V9-J
VTTREF VDD PR2706 JUMP_43X79
+3VALW EMC_NS@

2
1

PR2707 0_0402_5%
PC2716

0.01U_0402_25V7K
+1.2VP 5 11 +1.2V_VID 1 2 @
1U_0402_6.3V6K VDDQ VID

1
PGOOD

PC2717 @

PC2718
100K_0402_1%
2

1
1U_0402_6.3V6K
TON
FB

S3

S5

VDDQ_FB_R
2 2

2
1 PR2708 2
100K_0402_1% 8.1 voltage console circuit for memory OC function
6

10
+1.2V_FB

+1.2V_PG
+1.2V_TON

+5VALW
PR2709
100K_0402_1%

1
@

1
+1.2V_S3

+1.2V_S5

1 2 +3VALW PC2719 PR2710


470P_0402_50V7K 1K_0402_1%

1.3K_0402_1%
1

1
PC2721

1U_0402_16V6K
2
PR2711 1 2 499K_0402_1% PC2720

PR2712
+1.2V_VIN

2
PU2702 1U_0402_16V6K
PR2713@

2
+1.2V_FB 1 2 8 1 @
PR2714

2
@ OUT VCC
2 1 +1.2V_S3 0_0402_5% @
52 +0.6V_ENABLE

1
1M_0402_5%

7 2
0.1U_0402_10V7K

NC2 BUS_SEL
@
1

0_0402_5% @ PR2715
1

2
1.65K_0402_1%
PC2726

PR2717

3.92K_0402_1%
1 2 @ 6 3

PR2718
52,62 SUSP#
PR2716 NC1 GND
2

2
0_0402_5%
2

@ 5 4

1
SCL SDA

PR2719
UP1804AMA8_SOT23-8 @
+1.2V_S5 PR2720
52 SYSON_VDDQ 2 1
@ 1 2 TP_I2C3_SDA_R 8,14,55
1M_0402_5%
1

0_0402_5%
1

PC2727
PR2721

@ 0.1U_0402_10V7K 0_0402_5%
@ @
2

PR2722
2

+3VALW ADDR 0X62 1 2 TP_I2C3_SCL_R 8,14,55

0_0402_5%
2

+5VALW
3 3

PR2723 @
100K_0402_5%
@
1
1

PC2728
1U_0402_6.3V6K
+3VALW PU2703
2

+2.5V_POK
+2.5V
0.5A @ 10 5
PJ2703 VPP POK
@
2 1 +2.5V_VIN 7 PJ2704
2 1 VIN1 2 +2.5V_P 2 1
0.5A
4.7U_0603_6.3V6K

8 VO1 2 1
4.7U_0603_6.3V6K

JUMP_43X39 VIN2
1

3
PC2729

PC2730

VO2 JUMP_43X39
1

1
PC2731 @

22U_0603_6.3V6-M
2

6 PR2724 @

22U_0603_6.3V6-M
220P_0402_50V7K

2
VEN

1
PR2725 @ 39K_0402_1%
0_0402_5%
@ Vout=2.5V±5%

PC2732

PC2733
2

1 2
68 ALW_PWRGD

2
1 4 +2.5V_FB
NC1 ADJ Vset=2.514V±2.9%
9 11
NC2 THERMAL_PAD Ilimit=3A
1

2 1 +2.5V_EN
52 SYSON
PR2726 PR2727
18.2K_0402_1%
Vref=0.8V(+-1.5%)
0_0402_5% G9661MRE1U_TDFN10_3X3
1

@ PC2734
2

.1U_0402_10V6-K
2

4
Address 0X6A 0X68 0X66 0X64 0X62 0X60 4

TOP R (Kohm) OPEN 3.9 3 2.3 1.3 10


STATE EN1 EN2 VDDQ VTT_REFP VTT
BOT R (Kohm) 10 1.3 2.3 3 3.9 OPEN
S0 Hi Hi On On On
Bus_sel Volt
Off (% of VCC) 0% 25% 40% 60% 75% 100%
S3 Lo Hi On On (Hi-Z)
Security Classification LC Future Center Secret Data Title
S4/S5 Lo Lo Off Off Off Issued Date 2019/07/02 Deciphered Date 2019/07/02 PWR-VDDQ/VTT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
Note: S3 - sleep ; S5 - power off
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y550 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, February 26, 2020 Sheet 69 of 83
A B C D
A B C D

1 1

+3VALW

1
PR1401
10K_0402_5%

2
0.75VALW_PG_R
PR1402
0_0402_5%
1 2
+5VALW @
0.75VALW_PG 52

PJ1401
1A
PU1401 +0.75VALW
2 1 0.75VALW_VIN 5 9
2 1 4 IN1 PG 1 0.75VALW_BS 1 2
0.1U_25V_K_X7R_0402

IN2 BS
EMC_NS@

3 PC1401 PL1401 @
10U_0805_25V6K

10U_0805_25V6K
2 IN3
1

JUMP_43X39 2 0.1U_25V_K_X7R_0402 1UH_PCMB053T-1R0MS_7A_20% PJ1402


PC1402

PC1403

PC1404
IN4 0.75VALW_LX 0.75VALW_P 2
@

6 1 2 1
7 LX1 19 2 1
2

GND1 LX2

1
1

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603

22UC_6.3VC_MC_X5RC_0603
8 20 JUMP_43X79
18 GND2 LX3 PR1403 PC1405
2
GND3 1 1 1 1 2

21 4.7_0603_5% 330P_0402_50V8J

2
PR1404 @ GND4 14 0.75VALW_FB EMC_NS@

0.75V_FB_R3

PC1406

PC1407

PC1408

PC1409
FB

1
100K_0402_5%

2
1 2 0.75VLAW_ILMT 13 12 PR1405 2 2 2 2

VCCIO_SN
+3VALW
0.75VALW_EN 11 ILMT NC3 10 20K_0402_1%
EN NC1 16
+3VALW
NC2
1

@ 15

2
BYP

2
PR1406 17 0.75VALW_VCC PC1410
1M_0402_5% VCC 1500P_0402_50V7-K Vout=0.75V±37.5mV

4.7U_0603_6.3V6K
1

PR1407
EMC_NS@ Vset=0.752V±1.46%

2
PC1411 SY8286RAC_QFN20_3X3

1
1K_0402_1%

PC1412
2

4.7U_0603_6.3V6K
Vref=0.6V
2

1
2
TDC=4A
OCP=9.5A TYP=10.5A MAX 11.5A

1
ILMT=0 OCP=6.5A PR1410
78.7K_0402_1%
OVP=(1.15~1.25)*Vout
ILMT=floating OCP=9.5A
UVP=(0.6~0.7)*Vout
ILMT=1 OCP=12.5A

2
Fsw=500Khz min=425K max=575K
47,52,62,69
EC_0.75VALW_EN 1 2
PR1413
1K_0402_1%

3
52,60 EC_ON 1 2 0.75VALW_EN 3

PR1414
100K_0402_1%

0.1U_25V_K_X7R_0402
2

1K_0402_1% @
1M_0402_5%

2
PC1413

PR1416

@
PR1415

1
1

1
@

4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-VCCIO


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y550 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, February 26, 2020 Sheet 70 of 83
A B C D
A B C D

Vout=1.8V±5%
Vset=1.8V±2.3%
1 Vref=0.6V(+-1%) 1

TDC=8A
OCP=16A
OVP=(1.15~1.25)*Vout
UVP=(0.6~0.7)*Vout
+3VALW Fsw=500Khz min=425K max=575K

1
PR1301 @
10K_0402_5%
V20B+
PC1302
PJ1301 PU1301

2
0.1U_25V_K_X7R_0402
2
1.5A1 2 +1.8VALW_VIN 5 9 +1.8VALW_PG +1.8VALW 2
1 2 4 IN1 PG 1 +1.8VALW_BS 1 2
IN2 BS
EMC_NS@

3 PL1301

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
JUMP_43X79 IN3 PJ1302
1

1
2 0.68UH_PCMB063T-R68MS_16A_20%
8A
PC1303

PC1304

PC1301
IN4 +1.8VALW_LX +1.8VALW_P
@ LX1
6 1 2 1
1 2
2
7 19
2

2
GND1 LX2

1
8 20

330P_0402_50V8J

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M

22U_0603_6.3V6-M
GND2 LX3 JUMP_43X79

1
18 PR1302
GND3

1
21 4.7_0805_5% @

PC1305
PR1303 GND4 14 +1.8VALW_FB EMC_NS@

PC1309

PC1306

PC1307

PC1308

PC1310

PC1311
2
FB

2
100K_0402_5%

2
1 2 +1.8VALW_ILMT 13 12

1VALW_SN
+3VALW
1 2 +1.8VALW_EN 11 ILMT NC3 10 PR1309
EN NC1

1
+3VALW 16 30K_0402_1%

1K_0402_1%
51 EC_1.8VALW_EN
.1U_0402_10V6-K

NC2
1

PR1304 15

PR1307

1
BYP
1

1
PR1306 100K_0402_5% 1M_0402_5% 17 +1.8VALW_VCC PC1312
VCC
1

1M_0402_5% 1000P_0402_50V9-J
PC1315

PR1308

4.7U_0603_6.3V6K
@ 1 EMC_NS@

2
PC1313 SY8288RAC_QFN20_3X3

1
PC1314
2

4.7U_0603_6.3V6K
2

3 3

1
PR1311
15K_0402_1%

2
4 4

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 PWR-1.0VALW


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Y550 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Date: Wednesday, February 26, 2020 Sheet 71 of 83
A B C D
5 4 3 2 1

D D

C C

B B

A A

Security Classification LC Future Center Secret Data Title

Issued Date 2018/08/02 Deciphered Date 2018/08/02 Blank


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY LC FUTURE CENTER NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF LC FUTURE CENTER.
Y550
Date: Wednesday, February 26, 2020 Sheet 72 of 83
5 4 3 2 1
5 4 3 2 1

+APU_VDD_VIN
PL5106
HCB2012KF-121T50_0805
+5VALW 1 2
+5VALW 1 2 V20B+
PL5107

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
HCB2012KF-121T50_0805
2.2U_10V_K_X5R_0402

2
PR5101 PC5102 1 1 1
1 2 RT3667_VCC 1 2 PR5102
PU5107 change to LV3667 SA0000AHM00

EMC@

PC5103

PC5101

PC5104
10_0603_5% 2.2_0603_5%
PC5105 0.1U_25V_K_X5R_0402 from RT3667 SA0000AEP00 can not link CIS 2 2 2
2 1

28

1
PU5107 2.2_0603_5% 0.22U_25V_K_X7R_0402
1U_25V_K_X6S_0402 PQ5101

VCC
PR5108

2
2 1 PC5106 AON6982_DFN8-7
PR5109 1M FOR 4S battery, PR5107 300K_0402_1%
PC5111 4 2 1 1 2 1
RT3667_PWM1 BOOT
3S battery need change to 787K PWM1
50 2 1 8
VCC 3 VDD_UG1
PL5101
1 2 RT3667_DVD 46 51 RT3667_PWM2 RT3667_PWM1 5 UGATE
V20B+ 1M_0402_1% DVD PWM2 PWM 2 VDD_PH1 7 VDD_PH1
0.15UH_PCME064T-R15MS0R665 36A_20%
1 2
VDDCR_VDD:TDC=58A PK=96A
PR5109
PWM3
52 RT3667_PWM3 1 2 1
EN
PHASE
VDD_LG1
+VDDCR_VDD
@ 7 6 @ @

EMC_NS@
RT3667_PWM4

2
1 6 LGATE
PR5103 1/16W_40.2_1%_0402 100K_0402_1% PR5110

0_0805_5%
1 2 2 1 RT3667_TONSET 2 PWM4 GND1 9
+APU_VDD_VIN 0_0402_5% PJ5101 PJ5102

PR5104
TONSET GND2
JUMPER JUMPER

1
1 2 PR5111 PU5101

3
4
5
RT9610CGQW_WDFN8_2X2

2
6 VDDCR_VDD_ISEN1P
PC5112 0.1U_25V_K_X5R_0402
ISEN1P

1
PR5105
VDDCR_VDD_ISEN1N

1000P_0402_50V7K
D 5 2 1 PR5112 D

EMC_NS@
ISEN1N 2.74K_0402_1%
PR5106 1/16W_40.2_1%_0402 100K_0402_1%
RT3667_TONSETA

1
1 2 2 1 40 1 2
+APU_SOC_VIN 1/16W_536_1%_0402

PC5108
TONSETA

2
1 2 PC5113
PR5113 PC5107 0.1U_25V_K_X5R_0402

2
1 2
3 VDDCR_VDD_ISEN2P
PC5109 0.1U_25V_K_X5R_0402
ISEN2P
PR5114 0.1U_25V_K_X5R_0402
4 2 1 VDDCR_VDD_ISEN2N
ISEN2N
330P_0402_50V7K 56P_50V_J_NPO_0402 1/16W_536_1%_0402
PC5115 PC5110 1 2
1 2 1 2 VDDCR_SOC_COMP 30 VDDCR_VDD_ISEN1P
COMPA
PC5114 0.1U_25V_K_X5R_0402

7 VDDCR_VDD_ISEN3P
PR5115 10K_0402_1% PR5117
1 2 1 PR5116 2 1 2 ISEN3P
7 VDDCR_SOC_VCC_SENSE PR5118 VDDCR_VDD_ISEN3N VDDCR_VDD_ISEN1N
8 2 1
ISEN3N
1/16W_10_1%_0402 1/16W 47.5K 1% 0402
VDDCR_SOC_FB 31 1 2
1/16W_536_1%_0402
FBA
PR5120 PC5116 0.1U_25V_K_X5R_0402 @
1 2 VDDCR_SOC_VCC_SENSE_R 32
+VDDCR_SOC VSENA VDDCR_VDD_ISEN4P
PR5119 10K_0402_1%
10 2 1
100_0402_1%
ISEN4P
PR5121
VDDCR_VDD_ISEN4N
+5VALW
+5VALW
+APU_VDD_VIN
@ 9 2 1 2 1
RT3667_VCC ISEN4N

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
2 1 10K_0402_1%

0.1U_25V_K_X7R_0402
PR5123 PR5122 10K_0402_1%
1/16W_536_1%_0402 1 2 @
1 2 10K_0402_1% VDDCR_SOC_OFS 24
PR5124 1 1 1
OFSA
PC5117 0.1U_25V_K_X5R_0402

EMC@

PC5120

PC5118

PC5119
RT3667_VCC 2 1 10K_0402_1% VDDCR_VDD_OFS 23
PR5125 @
RT3667_PWMA1

2
OFS 42
1 2 10K_0402_1% PWMA1 2 2 2
PR5127 PR5126
41 2.2_0603_5%
PWMA2
PR5128 124K_0402_1% PR5129 1K_0402_1%

1
RT3667_VCC 2 1 2 1 2.2_0603_5% 0.22U_25V_K_X7R_0402 PQ5102
36 VDDCR_SOC_ISEN1P
1U_25V_K_X6S_0402 AON6982_DFN8-7
ISENA1P PR5133

2
2 1 2 1 25 PC5123
SET1 35 2 1 VDDCR_SOC_ISEN1N PC5122 4 2 1 1 2 1
PR5131 1/16W_1.78K_1%_0402
ISENA1N 2 1 8 BOOT
PR5130 49.9K_0402_1% PR5132 1/16W_732_1%_0402
1 2 VCC 3 VDD_UG2
PL5102
RT3667_PWM2 5 UGATE
0.15UH_PCME064T-R15MS0R665 36A_20%
PWM 2 VDD_PH2 7 VDD_PH2 1 2
PR5134 124K_0402_1% PR5135 1K_0402_1% PC5121 0.1U_25V_K_X5R_0402
RT3667_VCC 1 2 2 1 26
SET2 ISENA2P
33
PR5139
1 2 1
EN
PHASE
VDD_LG2
+VDDCR_VDD
@ 7 6 @ @

EMC_NS@
1

2
1 2 1 2 34 2 1 6 LGATE
+5VALW PR5136

0_0805_5%
ISENA2N GND1 9
@ 0_0402_5% PJ5103 PJ5104

PR5140
0_0402_5% PR5138 PR5137 1/16W_470_1%_0402 GND2
JUMPER JUMPER

1
10K_0402_1% PU5103

3
4
5
PR5141 RT9610CGQW_WDFN8_2X2

2
1 2 RT3667_IBIAS 29

1
IBIAS
56P_50V_J_NPO_0402 220P_0402_50V7K

1000P_0402_50V7K
100K_0402_1% PC5124 PC5125 PR5142

EMC_NS@
13 VDDCR_VDD_COMP 1 2 1 2
PC5126 1U_0402_6.3V6K 2.74K_0402_1%
COMP

1
2 1

PC5127

2
PC5128
PR5145 2.2_0603_5% PR5143 PR5144

2
1 2 RT3667_VDDIO 18 1 2 1 2 1 2
+1.8VALW VDDIO
1 2 29.4K_0402_1% 10K_0402_1% 0.1U_25V_K_X5R_0402
+1.8VS 12 VDDCR_VDD_FB
FB
PR5146 @ 2.2_0603_5%
VDDCR_VDD_ISEN2P
0_0402_5% PR5147
1 2 RT3667_EN 37 1 2 40.2_0402_1%
PR5148
EC_VR_ON
@
EN +VDDCR_VDD
1 2 11 VDDCR_VCC_SENSE_R 1 2 1/16W_10_1%_0402
PR5149
VSEN VDDCR_VCC_SENSE 7
VDDCR_VDD_ISEN2N
C PC5129 0.1U_10V_K_X5R_0402 C

2
0_0402_5% PR5150 PC5130
1 2 RT3667_PWROK 19
1000P_0402_50V7K
7 APU_PWROK PWROK
@

1
14 VDDCR_VSS_SENSE_R 1 2 1/16W_10_1%_0402
PR5151
2 1 39 RGND VDDCR_VSS_SENSE 7
+3VS PR5152 10K_0402_1% PGOOD PR5153 1 2 40.2_0402_1%
38
PGOODA +5VALW
+APU_VDD_VIN
VR_PWRGD

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
PR5154 @ 10K_0402_1% PH5101 PR5155
1 2 RT3667_OCPL 27 2 1 2 1
+3VS OCP_L 6.49K_0402_1% 1 1 1
1 2 PR5157 100K_0402_1%_NCP15WF104F03RC

EMC@

PC5131

PC5132

PC5133
P_APU_OCPL VDDCR_SOC_IMON
17 2 1 2 1
IMONA

2
PR5156 @ 0_0402_5% 1/16W_23.2K_1%_0402 PR5158 20K_0402_1%
20 PR5159 2 2 2
7 APU_SVC SVC
PH5102 PR5161 2.2_0603_5%
21 15 VDDCR_VDD_IMON 2 1 2 1 2 1
7 APU_SVD SVD IMON 13.7K_0402_1%

1
22 PR5160 100K_0402_1%_NCP15WF104F03RC 2.2_0603_5% 0.22U_25V_K_X7R_0402 PQ5103
7 APU_SVT SVT 2 1
4.87K_0402_1% 1U_25V_K_X6S_0402 AON6982_DFN8-7
PR5164

2
2 2 2 43 PC5138
44 NC1 PC5137 4 2 1 1 2 1
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402

PR5162 1/16W_12.7K_1%_0402
PC5135

PC5136

45 NC2 2 1 8 BOOT
PC5134

47 NC3 16 RT3667_V064/SET3 2 1 2 1 RT3667_VCC VCC 3 VDD_UG3


PL5103
1 1 1 48 NC4 V064/SET3 RT3667_PWM3 5 UGATE
0.15UH_PCME064T-R15MS0R665 36A_20%
GND

@ @ @ 49 NC5 PWM 2 VDD_PH3 7 VDD_PH3 1 2


PR5165 PR5163
NC6
330_0402_1% 26.1K_0402_1% 1 2 1 PHASE +VDDCR_VDD

EMC_NS@
VDD_LG3

1
LV3667BYGQW_WQFN52_6X6 EN 7 6
@ @ @

0_0805_5%
53

1
LGATE

2
19.6K_0402_1%
PR5166 6

PR5169
0_0402_5%
2
GND1 9
0_0402_5% PJ5105 PJ5106

PR5168
GND2
JUMPER JUMPER

PR5167

1
PU5104

3
4
5

2
RT9610CGQW_WDFN8_2X2

2
1

1
1000P_0402_50V7K
EMC_NS@
PR5171

1
0.022U_0402_25V7K
2.74K_0402_1%

PC5140
2
1/16W_340_1%_0402
PR5170

PC5139

2
PC5141

1
1 2

1
0.1U_25V_K_X5R_0402

VDDCR_VDD_ISEN3P

VDDCR_VDD_ISEN3N

+5VALW
+APU_VDD_VIN

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X7R_0402
1 1 1

EMC@

PC5142

PC5143

PC5144
2
PR5172 2 2 2
2.2_0603_5%

1
B 2.2_0603_5% 0.22U_25V_K_X7R_0402 PQ5104 B
1U_25V_K_X6S_0402 AON6982_DFN8-7
PR5173

2
PC5146
PC5145 4 2 1 1 2 1
2 1 8 BOOT
VCC 3 VDD_UG4 PL5104
RT3667_PWM4 5 UGATE
0.15UH_PCME064T-R15MS0R665 36A_20%
PWM 2 VDD_PH4 7 VDD_PH4 1 2
1 2 1
EN
PHASE
VDD_LG4
+VDDCR_VDD
@ 7 6 @ @

EMC_NS@
LGATE

2
PR5174 6

0_0805_5%
GND1 9
0_0402_5% PJ5107 PJ5108

PR5175
V20B+ GND2
JUMPER JUMPER

1
PU5105

3
4
5
RT9610CGQW_WDFN8_2X2

1
1000P_0402_50V7K
PR5176

EMC_NS@
0.1U_0402_25V6

1000P_0402_25V7-K

0.1U_0402_25V6

1000P_0402_25V7-K

0.1U_0402_25V6

1000P_0402_25V7-K

2.74K_0402_1%

PC5147
1

1
PC301

PC302

PC303

PC304

PC305

PC306

2
PC5148

2
1 2
2

0.1U_25V_K_X5R_0402

VDDCR_VDD_ISEN4P
EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

EMC_NS@

VDDCR_VDD_ISEN4N

+APU_SOC_VIN
1 2
PL5108
HCB2012KF-121T50_0805
1 2

+5VALW
PL5109 V20B+
HCB2012KF-121T50_0805

10U_25V_M_X5R_0603

10U_25V_M_X5R_0603
0.1U_25V_K_X5R_0402

0.1U_25V_K_X5R_0402
EMC@

EMC@
1 1 1 1

PC5156

PC5149

PC5150

PC5151
2
PR5177 2 2 2 2
2.2_0603_5%

1
2.2_0603_5% 0.22U_25V_K_X5R_0402 PQ5105
PC5152 AON6982_DFN8-7
PR5178

2
PC5153
1U_0402_10V6K 4 2 1 1 2 1
2 1 8 BOOT
VCC 3 SOC_UG1
PL5105
RT3667_PWMA1 5 UGATE
0.36UH_PCMB063T-R36MS3R205_20A_20%
PWM 2 SOC_PH1 7 SOC_PH1 1 2
1 2 1
EN
PHASE
SOC_LG1
+VDDCR_SOC
@ 7 6 @ @
VDDCR_SOC:TDC=15A PK=20A

EMC_NS@
LGATE

2
PR5179 6

0_0805_5%
0_0402_5% GND1 9 PJ5109 PJ5110

PR5180
GND2
JUMPER JUMPER

1
A PU5106 A

3
4
5
RT9610CGQW_WDFN8_2X2

1
1000P_0402_50V7K
PR5181

EMC_NS@
4.75K_0402_1%

PC5154

2
PC5155

2
1 2

0.1U_25V_K_X5R_0402

1 2

VDDCR_SOC_ISEN1P PR5182
1/16W_1.87K_1%_0402

VDDCR_SOC_ISEN1N

Security Classification LC Future Center Secret Data Title

Issued Date 2013/08/15 Deciphered Date 2013/08/15 PWR_VDD/SOC


THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF LC FUTURE CENTER. AND CONTAINS CONFIDENTIAL

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