Lecture 5 HO

Digital Electronics: EE 304
VHDL: Lecture 5
Introduction to Very High-Speed Integrated Circuit Hardware Description
Languages [VHDL]
.
Electrical and Electronic Department
Faculty of Engineering and the Built Environment
1 H.24.10.2022
M. Katongera Electrical and Electronic Department
OFFICE CD 37 mkatongera@eng.uz.ac.zw
SUMMARY
Introduction
VHDL Modules
VHDL Descriptions of Combinational Logic
2 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

INTRODUCTION

Introduction
A hardware description language (HDL) is a

computer-based language that describes the
hardware of digital systems in a textual form.
It can be used to represent logic diagrams, truth

tables, Boolean expressions, and complex
abstractions of the behaviour of a digital system

Introduction
HDL describes a relationship between the input

signals to a circuit and the output signals of the
circuit

Introduction: Documentation
As a documentation language, an HDL is used to

represent and document digital systems in a form
that can be read by both humans and computers.
Design entry creates an HDL-based description of

the functionality that is to be implemented in
hardware

Introduction: Documentation
The description can be in a variety of forms:

Boolean logic equations, truth tables, a netlist of
interconnected gates, or an abstract behavioural
model

Introduction: Logic Simulation
Logic simulation displays the behaviour of a digital

system through the use of a computer.
Errors that are detected during a simulation can

be corrected by modifying the appropriate HDL
statements.
The stimulus that tests the functionality of the

design is called a test bench

Introduction: Logic Simulation
An alternative and more complex approach to

testing relies on formal mathematical methods to
prove that a circuit is functional correct

Introduction: Logic Synthesis
Logic synthesis is the process of deriving a list of

physical components and their interconnections
(called a netlist).
The netlist can be used to fabricate an integrated

circuit or to lay out a printed circuit board.
Logic synthesis is like compiling a program in a

conventional high level language

Introduction: Logic Synthesis
The designs of today's large, complex circuits are

made possible by logic synthesis software

Introduction: Timing verification
Timing verification confirms that the fabricated

integrated circuit will operate at a specified speed.
Timing verification checks each signal path to

verify that it is not compromised by propagation
delay

Introduction: Timing verification
In VLSI circuit design fault simulation compares

the behaviour of an ideal circuit with the behaviour
of a circuit that contains a process-induced flaw

Introduction: VHDL
In the public domain, there are two standard

HDLs that are supported by the IEEE: VHDL and
Verilog

VHDL MODULES

VHDL Modules
To write a complete VHDL module like a logic

gate:
Declare all of the input and output signals using an
entity declaration, and
Specify the internal operation of the module using an

architecture declaration

VHDL Modules: Example
VHDL module with two logic gates:

VHDL Modules: Entity Declaration
VHDL Each entity declaration includes a list of

interface signals that can be used to connect to:
other modules
the outside world

Port interface in square brackets is optional:

Curly brackets indicate zero or more repetitions
Input signals are in mode in, and outputs are in

mode out.
Bidirectional signals are in mode inout

VHDL Modules: Architecture Declaration
Associated with each entity is one or more

architecture declarations of the form
In declarations section, we find signals or

components used within the architecture

VHDL Modules: Full Adder Example
Entity declaration of a full adder
Our input and output modes are of signal type

bit

Operation of the full adder is specified by an

architecture declaration
Note architecture name is Equations.
Entity name FullAdder should match a declared entity

Sum and Cout represent the logic equations

In the Cout equation, parentheses are required around
(X and Y) because VHDL does not specify an order of
precedence for the logic operators

Now we show how module FullAdder is used as a

component in VHDL

The VHDL code of four bit full adder

VHDL Modules: Signals and Constants
Input and output signals for a module are

declared in the ports
Signals internal to the module, are declared at

beginning of Architecture.
signal list_of_signal_names: type_name [constraint] [:=
initial_value];
signal A, B, C: bit_vector(3 downto 0):= “1111”;

VHDL Modules: Signals and Constants
Constants used within the module, are declared at

beginning of Architecture.
constant constant_name: type_name [constraint] [:=
constant_value];
constant limit : integer := 17;

VHDL Modules: Arrays
To use arrays, we first declare an array type and

then declare the array object after the array type.
type SHORT_WORD is array (15 downto 0) of bit;
signal DATA_WORD: SHORT_WORD;
signal ALT_WORD: SHORT_WORD := “0101010101010101”;
constant ONE_WORD: SHORT_WORD := (others => ‘1’);
Others will set all bits to 1.

VHDL Operators
There are seven classes of VHD operators

VHDL Packages and Libraries
Packages are used to reference frequently used

functions and components
Package declaration has the form:

The package body usually contains component

descriptions and the function and procedure
bodies
Package declaration has the form:

To use a package components and functions, at

the beginning of VHDL file you call package using
USE statement.
Say a library BITLIB has bit_pack package

library BITLIB;
use BITLIB.bit_pack.all;

To use a package components and functions, at

the beginning of VHDL file you call package using
USE statement.
Say a library ieee has std_logic_1164 package

library ieee;
use ieee.std_logic_1164.all;

Compilation and Simulation
After describing a digital system using VHDL one

can simulate the VHDL code by compiling.
If code has no error, compiler or analyser

generates intermediate code which can be used by
simulator.
Elaboration is done, ports are created, memory

reserved for variables and necessary settings.


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Digital Electronics: EE 304

VHDL Descriptions of Combinational Logic

2 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

3 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

A hardware description language (HDL) is a

It can be used to represent logic diagrams, truth

4 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

HDL describes a relationship between the input

5 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

As a documentation language, an HDL is used to

Design entry creates an HDL-based description of

6 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

The description can be in a variety of forms:

7 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Logic simulation displays the behaviour of a digital

Errors that are detected during a simulation can

The stimulus that tests the functionality of the

8 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

An alternative and more complex approach to

9 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Logic synthesis is the process of deriving a list of

The netlist can be used to fabricate an integrated

Logic synthesis is like compiling a program in a

10 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

The designs of today's large, complex circuits are

11 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Timing verification confirms that the fabricated

Timing verification checks each signal path to

12 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

In VLSI circuit design fault simulation compares

13 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

In the public domain, there are two standard

14 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

15 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

To write a complete VHDL module like a logic

Specify the internal operation of the module using an

16 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

VHDL module with two logic gates:

17 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

VHDL Each entity declaration includes a list of

the outside world

18 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Port interface in square brackets is optional:

19 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Curly brackets indicate zero or more repetitions

Input signals are in mode in, and outputs are in

Bidirectional signals are in mode inout

20 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Associated with each entity is one or more

In declarations section, we find signals or

21 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Entity declaration of a full adder

Our input and output modes are of signal type

22 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Operation of the full adder is specified by an

Entity name FullAdder should match a declared entity

23 24.10.2022 H. M. Katongera – mkatongera@eng.uz.ac.zw Electrical and Electronic Department

Sum and Cout represent the logic equations