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Am29F002B/Am29F002NB: Data Sheet
Am29F002B/Am29F002NB: Data Sheet
Am29F002B/Am29F002NB: Data Sheet
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Publication Number 21257 Revision D Amendment 0 Issue Date November 28, 2000
Am29F002B/Am29F002NB
2 Megabit (256 K x 8-Bit)
CMOS 5.0 Volt-only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation ■ Embedded Algorithms
— 5.0 Volt-only operation for read, erase, and — Embedded Erase algorithm automatically
program operations preprograms and erases the entire chip or any
— Minimizes system level requirements combination of designated sectors
— Embedded Program algorithm automatically
■ Manufactured on 0.32 µm process technology
writes and verifies data at specified addresses
— Compatible with 0.5 µm Am29F002 device
■ Minimum 1,000,000 write cycle guarantee per
■ High performance sector
— Access times as fast as 55 ns ■ 20-year data retention at 125°C
■ Low power consumption (typical values at — Reliable operation for the life of the system
5 MHz)
■ Package option
— 1 µA standby mode current
— 32-pin PDIP
— 20 mA read current
— 32-pin TSOP
— 30 mA program/erase current
— 32-pin PLCC
■ Flexible sector architecture
■ Compatibility with JEDEC standards
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
— Pinout and software compatible with
three 64 Kbyte sectors
single-power supply Flash
— Supports full chip erase
— Superior inadvertent write protection
— Sector Protection features:
■ Data# Polling and toggle bits
A hardware method of locking a sector to
prevent any program or erase operations within — Provides a software method of detecting
that sector program or erase operation completion
Sectors can be locked via programming equipment ■ Erase Suspend/Erase Resume
Temporary Sector Unprotect feature allows code — Suspends an erase operation to read data from,
changes in previously locked sectors or program data to, a sector that is not being
erased, then resumes the erase operation
■ Top or bottom boot block configurations available
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data (not available on Am29F002NB)
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Publication# 21527 Rev: D Amendment/0
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Issue Date: November 28, 2000
GENERAL DESCRIPTION
The Am29F002B Family consists of 2 Mbit, 5.0 Erase algorithm—an internal algorithm that automati-
volt-only Flash memory devices organized as 262,144 cally preprograms the array (if it is not already
bytes. The Am29F002B offers the RESET# function, programmed) before executing the erase operation.
the Am29F002NB does not. The data appears on During erase, the device automatically times the erase
DQ7–DQ0. The device is offered in 32-pin PLCC, pulse widths and verifies proper cell margin.
32-pin TSOP, and 32-pin PDIP packages. This device
The host system can detect whether a program or
is designed to be programmed in-system with the stan-
erase operation is complete by reading the DQ7 (Data#
dard system 5.0 volt VCC supply. No VPP is required for
Polling) and DQ6 (toggle) status bits. After a program
write or erase operations. The device can also be pro-
or erase cycle has been completed, the device is ready
grammed in standard EPROM programmers.
to read array data or accept another command.
This device is manufactured using AMD’s 0.32 µm
The sector erase architecture allows memory sectors
process technology, and offers all the features and
to be erased and reprogrammed without affecting the
benefits of the Am29F002, which was manufactured
data contents of other sectors. The device is fully
using 0.5 µm process technology.
erased when shipped from the factory.
The standard device offers access times of 55, 70, 90,
Hardware data protection measures include a low VCC
and 120 ns, allowing high speed microprocessors to
detector that automatically inhibits write operations during
operate without wait states. To eliminate bus conten-
power transitions. The hardware sector protection
tion the device has separate chip enable (CE#), write
feature disables both program and erase operations in
enable (WE#) and output enable (OE#) controls.
any combination of the sectors of memory. This can be
The device requires only a single 5.0 volt power achieved via programming equipment.
supply for both read and write functions. Internally
The Erase Suspend feature enables the user to put
generated and regulated voltages are provided for the
erase on hold for any period of time to read data from,
program and erase operations.
or program data to, any sector that is not selected for
The device is entirely command set compatible with the erasure. True background erase can thus be achieved.
JEDEC single-power-supply Flash standard. Com-
The hardware RESET# pin terminates any operation
mands are written to the command register using
in progress and resets the internal state machine to
standard microprocessor write timings. Register con-
reading array data. The RESET# pin may be tied to the
tents serve as input to an internal state-machine that
system reset circuitry. A system reset would thus also
controls the erase and programming circuitry. Write
reset the device, enabling the system microprocessor
cycles also internally latch addresses and data needed
to read the boot-up firmware from the Flash memory.
for the programming and erase operations. Reading
(This feature is not available on the Am29F002NB.)
data out of the device is similar to reading from other
Flash or EPROM devices. The system can place the device into the standby mode.
Power consumption is greatly reduced in this mode.
Device programming occurs by executing the program
command sequence. This initiates the Embedded AMD’s Flash technology combines years of Flash
Program algorithm—an internal algorithm that auto- memory manufacturing experience to produce the
matically times the program pulse widths and verifies highest levels of quality, reliability and cost effective-
proper cell margin. ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunneling.
Device erasure occurs by executing the erase
The data is programmed using hot electron injection.
command sequence. This initiates the Embedded
BLOCK DIAGRAM
DQ0–DQ7
VCC
Sector Switches
VSS
Erase Voltage Input/Output
RESET# Generator Buffers
n/a Am29F002NB
WE# State
Control
Command
Register
PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
Logic
OE#
Y-Decoder Y-Gating
STB
Address Latch
A0–A17
RESET#
RESET# 1 32 VCC
WE#
A16 2 31 WE#
A16
A17
VCC
A12
A15
A15 3 30 A17
A12 4 29 4 3 2 1 32 31 30
A14
A7 5 29 A14
A7 5 28 A13
A6 6 28 A13
A6 6 27 A8
A5 7 27 A8
A5 7 26 A9
A4 8 26 A9
A4 8 PDIP 25 A11 PLCC
A3 9 25 A11
A3 9 24 OE# A2 10 24 OE#
A2 10 23 A10 A1 11 A10
23
A1 11 22 CE# A0 12 22 CE#
A0 12 21 DQ7 DQ0 13 21 DQ7
DQ0 13 20 DQ6 14 15 16 17 18 19 20
DQ1 14 19 DQ5
VSS
DQ3
DQ6
DQ1
DQ2
DQ4
DQ5
DQ2 15 18 DQ4
VSS 16 17 DQ3
A11 1 32 OE#
A9 2 31 A10
A8 3 30 CE#
A13 4 29 DQ7
A14 5 28 DQ6
A17 6 27 DQ5
WE# 7 26 DQ4
VCC 8 25 DQ3
Standard TSOP
NC on Am29F002NB RESET# 9 24 VSS
A16 10 23 DQ2
A15 11 22 DQ1
A12 12 21 DQ0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3
supply tolerances)
VSS = Device ground
NC = Pin not connected internally
Am29F002B/
Am29F002NB T -55 P C
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
P = 32-Pin Plastic DIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032)
SPEED OPTION
See Product Selector Guide and Valid Combinations
DEVICE NUMBER/DESCRIPTION
Am29F002B/Am29F002NB
2 Megabit (256 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Program and Erase
AM29F002BT-70
PC, PI,
AM29F002BB-70
JC, JI,
AM29F002NBT-70
EC, EI
AM29F002NBB-70
AM29F002BT-90
AM29F002BB-90
5.0 V ± 10%
AM29F002NBT-90
AM29F002NBB-90 PC, PI, PE,
JC, JI, JE,
AM29F002BT-120 EC, EI, EE
AM29F002BB-120
AM29F002NBT-120
AM29F002NBB-120
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information. This function requires
the RESET# pin and is therefore not available on the Am29F002NB device.
Requirements for Reading Array Data sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power An erase operation can erase one sector, multiple sec-
control and selects the device. OE# is the output tors, or the entire device. The Sector Address Tables
control and gates array data to the output pins. WE# indicate the address space that each sector occupies.
should remain at VIH. A “sector address” consists of the address bits required
to uniquely select a sector. See the Command Defini-
The internal state machine is set for reading array data
tions section for details on erasing a sector or the entire
upon device power-up, or after a hardware reset. This
chip, or suspending/resuming the erase operation.
ensures that no spurious alteration of the memory
content occurs during the power transition. No After the system writes the autoselect command
command is necessary in this mode to obtain array sequence, the device enters the autoselect mode. The
data. Standard microprocessor read cycles that assert system can then read autoselect codes from the
valid addresses on the device address inputs produce internal register (which is separate from the memory
valid data on the device data outputs. The device array) on DQ7–DQ0. Standard read cycle timings
remains enabled for read access until the command apply in this mode. Refer to the “Autoselect Mode” and
register contents are altered. Autoselect Command Sequence sections for more
information.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica- I CC2 in the DC Characteristics table represents the
tions and to the Read Operations Timings diagram for active current specification for the write mode. The “AC
the timing waveforms. ICC1 in the DC Characteristics Characteristics” section contains timing specification
table represents the active current specification for tables and timing diagrams for write operations.
reading array data.
Program and Erase Operation Status
Writing Commands/Command Sequences During an erase or program operation, the system may
To write a command or command sequence (which check the status of the operation by reading the status
includes programming data to the device and erasing bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to “Write Operation
Autoselect Mode
The autoselect mode provides manufacturer and on the appropriate highest order address bits. Refer to
device identification, and sector protection verification, the corresponding Sector Address Tables. The
through identifier codes output on DQ7–DQ0. This Command Definitions table shows the remaining
mode is primarily intended for programming equipment address bits that are don’t care. When all necessary
to automatically match a device to be programmed with bits have been set as required, the programming
its corresponding programming algorithm. However, equipment may then read the corresponding identifier
the autoselect codes can also be accessed in-system code on DQ7–DQ0.
through the command register.
To access the autoselect codes in-system, the host
When using programming equipment, the autoselect system can issue the autoselect command via the
mode requires VID on address pin A9. Address pins A6, command register, as shown in the Command Defini-
A1, and A0 must be as shown in Autoselect Codes tions table. This method does not require V ID . See
(High Voltage Method) table. In addition, when veri- “Command Definitions” for details on using the autose-
fying sector protection, the sector address must appear lect mode.
Device ID: L L H
Am29F002B/Am29F002NB X X VID X L X L H B0h
(Top Boot Block) L L H
Device ID: L L H
Am29F002B/Am29F002NB X X VID X L X L H 34h
(Bottom Boot Block) L L H
01h
(protected)
Sector Protection Verification L L H SA X VID X L X H L
00h
(unprotected)
L = Logic Low = VIL, H = Logic High = VIH , SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in previously protected
program and erase operations in any sector. The hard- sectors.
ware sector unprotection feature re-enables both
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect
Completed (Note 2)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Cycles
Command
Sequence First Second Third Fourth Fifth Sixth
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01
Device ID,
4 555 AA 2AA 55 555 90 X01 B0
Auto- Top Boot Block
select Device ID,
4 555 AA 2AA 55 555 90 X01 34
(Note 7) Bottom Boot Block
Sector Protect Verify (SA) 00
4 555 AA 2AA 55 555 90
(Note 8) X02 01
Program 4 555 AA 2AA 55 555 A0 PA PD
Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 9) 1 XXX B0
Erase Resume (Note 10) 1 XXX 30
Legend:
X = Don’t care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.
RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A13 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
Notes:
1. See Table 1 for description of bus operations. 7. The fourth cycle of the autoselect command sequence is a
2. All values are in hexadecimal. read cycle.
3. Except when reading array or autoselect data, all bus cycles 8. The data is 00h for an unprotected sector and 01h for a
are write operations. protected sector. See “Autoselect Command Sequence” for
more information.
4. Address bits A17–A11 are don’t cares for unlock and
command cycles, except when PA or SA is required. 9. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend
5. No unlock or command cycles required when reading array mode. The Erase Suspend command is valid only during a
data. sector erase operation.
6. The Reset command is required to return to reading array 10. The Erase Resume command is valid only during the Erase
data when device is in the autoselect mode, or if DQ5 goes Suspend mode.
high (while the device is providing status data).
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1”. See text.
Figure 5. Toggle Bit Algorithm
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Ambient Temperature (TA) . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ± 5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for ± 10% devices . . . . . . . . . . . .+4.5 V to +5.5 V
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA
ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current (Notes 2, 3) CE# = VIL, OE# = VIH 20 30 mA
ICC2 VCC Active Write Current (Notes 2, 4, 5) CE# = VIL, OE# = VIH 30 40 mA
VCC
VIH Input High Voltage 2.0 V
+ 0.5
VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V
VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V
Notes:
1. RESET# is not available on Am29F002NB.
2. Maximum ICC specifications are tested with V CC = VCCmax.
3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Not 100% tested.
VOL Output Low Voltage IOL = 12 mA, VCC = VCC min 0.45 V
Notes:
1. RESET# is not available on Am29F002NB.
2. Maximum ICC specifications are tested with V CC = VCCmax.
3. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
4. ICC active while Embedded Erase or Embedded Program is in progress.
5. Not 100% tested.
6. ICC3 and ICC4 = 20 µA max at extended temperature (>+85° C).
Steady
Changing from H to L
Changing from L to H
JEDEC Std Description Test Setup -55 -70 -90 -120 Unit
CE# = VIL
tAVQV tACC Address to Output Delay Max 55 70 90 120 ns
OE# = VIL
tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns
Notes:
1. Not 100% tested.
2. See Table 7 and Figure 8 for test specifications.
tRC
tDF
tOE
OE#
tOEH
WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid
RESET#
n/a Am29F002NB
CE#, OE#
tRH
RESET#
n/a Am29F002NB
tRP
tReady
RESET#
n/a Am29F002NB
tRP
Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS
Addresses 555h PA PA PA
tAH
CE#
tCH
OE#
tWP tWHWH1
WE#
tWPH
tCS
tDS
tDH
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 11. Program Operation Timings
tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#
OE# tCH
tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (”see “Write Operation Status”).
Figure 12. Chip/Sector Erase Operation Timings
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data
High Z
DQ0–DQ6 Status Data Status Data True Valid Data
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
tRC
Addresses VA VA VA VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6/DQ2 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 15. DQ2 vs. DQ6
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
12 V
RESET#
0 or 5 V 0 or 5 V
tVIDR tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Addresses PA
tWC tAS
tAH
tWH
WE#
tGHEL
OE#
tCP tWHWH1 or 2
CE#
tWS tCPH
tDS
tDH
DQ7# DOUT
Data
tRH A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase
RESET#
Notes:
1. PA = Program Address, PD = Program Data, DQ7# = complement of data written to device, DOUT = data written to device.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 17. Alternate CE# Controlled Write Operation Timings
Notes:
1. Typical program and erase times assume the following conditions: 25×C, 5.0 V VCC , 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for ±5% devices), 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5
for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description Min Max
Input voltage with respect to VSS on all pins except I/O pins
–1.0 V 12.5 V
(including A9, OE#, and RESET#)
Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V
Note: Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. RESET# not available on Am29F002NB.
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Test Conditions Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years
tWLWH : changed the 55 speed option to 30 ns from 35 ns. Revision D (November 28, 2000)
AC Characteristics—Alternate CE# Controlled Global
Erase/Program Operations
Added table of contents.
tDVEH: Changed the 55 speed option to 25 ns from 30 ns.
Ordering Information
tELEH : Changed the 55 speed option to 30 ns from 35 ns.
Deleted burn-in option.
tELAX: Changed the 90 speed option to 45 ns from 50 ns.
Table 5, Command Definitions
In Note 4, changed the lower address bit of don’t care
range to A11.
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