A STUDY MATERIAL

EMBEDDED SYSTEMS

KOE062

GYANENDRA SINGH
 UNIT-1 - INTRODUCTION TO
EMBEDDED SYSTEMS

1. Define Embedded System. What are the components of embedded system?

An Embedded system is one that has computer hardware with software embedded in it as one of its most
important component. The three main components of an embedded system are (i) Hardware (ii) Main
application software (iii) RTOS
2. What are the types of embedded system?
Small scale embedded systems
Medium scale embedded systems
Sophisticated embedded systems
3. Name some of the hardware parts of embedded systems.
Power source
Clock oscillator circuit
Timers
Memory units
DAC and ADC
LCD and LED displays
Keyboard/Keypad
4. Give the characteristics of embedded system.
Single-functioned
Tightly constrained
Reactive and real time
5. What are the steps involved in the build process.
The steps involved are

Preprocessing
Compiling
Linking
Locating
6. What is a compiler and a cross compiler?
Compiler: Compiler is a program that creates an object file from the source codes. It checks the language
grammar/semantics. For eg: tcc. It converts high level language codes into machine codes.

1
Cross Compiler: A compiler that runs on one computer platform and produces code for another is called
a cross-compiler. The use of a cross-compiler is one of the defining features of embedded software
development.
7. List the important considerations when selecting a processor.
Instruction set
Maximum bits in an operand
Clock frequency
Processor ability
8. Classify the processors in embedded system.
a. General purpose processor
Microprocessor
Microcontroller

Embedded processor
Digital signal processor
Media processor

b. Application specific system processor

c. Multiprocessor system using GPP and ASSP GPP core or ASIP core integrated into either an
ASIC or a VLSI circuit or an FPGA core integrated with processor unit in a VLSI chip.

9. What are the various types of memory in embedded systems?

RAM (internal External)

ROM/PROM/EEPROM/Flash
Cache memory
(i) Program Flow control Unit. (ii) Execution Unit
10. What are the two essential units of a processor on a embedded system?
11. What are the different modes of DMA transfer? Which one is suitable
forembedded system?
 Single transfer at a time and then release of the hold on the system bus.
 Burst transfer at a time and then release of the hold on the system bus. A burstmay
be of a few kB.
 Bulk transfer and then release of the hold on the system bus after the transferis
completed.

2
12. Define ROM image and RAM.
ROM image: Final stage software is also called as ROM image .The final implement able software for a
product embeds in the ROM as an image at a frame. Bytes at each address must be defined for creating
the image.
RAM: RAM refers Random Access Memory. It is a memory location that can be accessed without
touching the other locations.
13. What are the uses of timers?
 The time intervals between two events can be computed
 Initiating an event after a preset time delay.
 Capturing the count value
 Watch dog timer
14. What is a watch dog timer?
The watch dog timer is a timing device that resets the system after a predefined
timeout. It is activated within the first few clock cycles after power-up. It has a number of
applications. Example: Mobile phone display turnoff in case of no interactions takes place
within a specified time.

15. Define Real Time Clock.

Real time clock is a clock which once the system starts does not stop and cannot be
reset and its count value cannot be reloaded.

1. Explain the build process for embedded system.

The build is often referred either to the process of converting source code files into

stand alone software artifacts that can be run on a computer or the result of doing so. The process of
converting the source code representation of the embedded software into an executable binary image
involves three distinct steps.
Each of the source files must be compiled or assembled into an object file.
All of the object files that result from the first step must be linked together toproduce a
single object file called the re-locatable program.
Physical memory addresses must be assigned to the relative offsets within there- locatable
program in a process called relocation.
The result of the final step is a file containing an executable binary image that is readyto run on the
embedded system.

3
 C/C++

Compiler Pre-processor

Object

Linker

Re-locatable

Locator

Executable

Figure: The Build Process Flowchart Chart

GCC (GNU compiler collection) is a compiler takes care of the compilation stages or builds
process by calling appropriate programs. The compiler, assembler, linker and locator run on a host
computer rather than on the embedded system itself. These tools combine their efforts to produce an
executable binary image that will execute properly only on the target embedded system.

>Led.c Embedded system

>Led.asm

>Led.o

>Led.exe Processor

Target
Host computer

Pre-processing: A C program has the following pre-processor structural elements

1. Include directive for the file inclusion

2. Definitions for preprocessor global variables (global means throughout the
 program module)
3. Definitions of constants
4. Declarations for global data type, type declaration and data structures, macros
and functions.
4
 Preprocessor constants, variables and inclusion of configuration files, text files, header files and
library functions are used in embedded C programs. A pre-processor directive starts with a sharp hash (#)
sign.
Line begins with # symbol are called commands of pre-processor. GCC includesa pre-processor
called CPP (C pre-processor) Example: #define, #include etc. during compilation, it is started with the
pre-processing directives. The pre-processor is a separate program in reality but it is invoked by a
compiler.
Example:
livesimple.c Program
#include<stdio.h> //Preprocessor directivesint main()
{

Printf(―LIVESIMPLE!‖);

Both pre-processor directives and livesimple.c combined together to form livesimple.ifile.

Syntax: [root@host ~] # CPP livesimple.c livesimple.i

Compilation: Compiler uses the complete set of codes. It may also include codes,
functions and expressions from the library routines. It creates a file called object file.

Compilation involves both gcc compiler and assembler. First, the gcc compiler converts
the livesimple.i file into livesimple.s file. The file livesimple.s Unit 2 and 3.docx assembly code.
The gcc conversion command is

Syntax: [root@host~]#gcc
assembly code without creating–s
thelivesimple.i
object file.
Second, The
the assembler
option –translates
s tells the
thelivesimple.s file into
gcc compiler to machine
convertlanguage format andcreating
the preprocessed codeantoobject file
called livesimple.o
Syntax: [root@host`]# as livesimple.s – o livesimple.o
The option – o converts the assembly file into object file.
Linking: A linker links the compiled codes of application software, object codes from library and OS
kernel. Linking is necessary because there are number of codes to be linked for the final binary file. The
linker file in the binary for run on a computer is commonly known as executable file or simply ‗.exe‘ file.
This process converts the object file into a new object file that is a special relocatable copy of
the program. No memory addresses have been assigned to the
5
code until this process. An object file needs to be linked with many C run time library files, system
functions etc., to form an executable object file. For example: in livesimple.c program, printf statement is
needed. So printf.o file must be linked. The linker (Id) will perform all those tasks.
Syntax: [root@host~] # Id – dynamic-linker/
Locating: The tool that performs the conversion from relocatable program to executable binary image
is called a locator. In embedded systems, the next step after linking is the use of locator for the program –
codes and data in place of the loader. The features of locator are,
The locator is specified by the programmer the available addresses at the RAM and ROM in
target. The programmer has to define the available addresses to
load and create file for permanently locating codes using a device programmer.

It uses cross-assembler output, a memory allocation map and provides the locator
program output file. It is the final step of software design process for the embedded
system.

The locator locates the I/O tasks and hardware device – driver codes at the addresses
without reallocation. This is because the port and device addresses for these are fixed
for a given system.

The locator program reallocates the linked file and creates a file for permanent location
of codes in a standard format.

Output:

Syntax : [root@host~] # ./ livesimple

The output is

In windows, the executable file is denoted as livesimple.exe but there is no need of .exeextension file in
LIVESIMPLE!
Linux environment.
2. Discuss in detail about the structural units in embedded processor.
Address

Processor Data
Memory

Control

Figure: Bus Interface between Processor and Memory

6
STRUCTURAL UNIT IN A PROCESSOR:
1. Memory Address Register (MAR): It holds the address of the byte or word to
be fetched from external memories. Processor issues the address of instructionor data to MAR
before it initiates fetch cycle.
2. Memory Data Register (MDR): It holds a byte or word fetched (or to sent) froman
external memory or IO address.
3. System Buses:
a. Internal Bus: It internally connects all the structural units inside the processor. Its width can
be 8, 18, 32, 48 or 64 bits.
b. Address Bus: An external bus that carries the address from MAR to memory as well as to
IO devices and other units of system.
c. Data Bus: An external bus that carries, during a read or write operation, the bytes for
instruction or data from or to an address. The address is determined by MAR.
d. Control Bus: An external set of signals to carry control signals to processor or

memory or device.
4. Bus Interface Unit (BIU): An interface unit between processor‘s internal unitsand
external buses.
5. Instruction Register (IR): It sequentially takes instruction codes (opcode) to
execution unit of processor.
6. Instruction Decoder (ID): It decodes the instruction received at the IR and
passes it to processor CU.
7. Control Unit (CU): It controls all the bus activities and unit functions needed for
processing.

8. Application Register Set (ARS)

7
 a. A set of on chip registers used during processing of instructions of anapplication
program.
b. A register window.
c. A subset of registers with each subset storing static variables of a software
routine or
d. A register file associated to a unit such as ALU or FLPU.
9. Arithmetic Logic Unit (ALU): A unit to execute arithmetic or logic instructions
according to the current instruction present at IR.
10. Program Counter (PC):
It generates an instruction cycle by sending the address defined by it to memorythrough MAR. It
auto increments as the instructions are fetched regularly and
sequentially. It is called instruction pointer in 80 x 86 processors.
11.Stack Pointer (SP): A pointer for an address, which corresponds to a stack-topin
memory.

ADVANCED PROCESSOR’S STRUCTURAL UNITS:

Advanced processor circuits consist of RISC architecture.

It executes most of the instruction in single clock cycle by using multiple register sets,
windows and files and by reducing the dependency on the external memory access for
data.
A RISC has only few addressing modes for arithmetic and logic instructions. It contains the
floating point unit.
Pipelining allows a processor to overlap the execution of several instructions,so that more
instructions can be executed in the same period of time.

Example: DSP processors TMS320C6000, Davinci processor, OMAP

processor etc.

1. Instruction Level Parallelism Unit (ILP):

For instruction level parallelism, the multistage pipeline processing, multiline superscalar
processing and dual, quad or multicore processing speeds up the performance from one
instruction per clock cycle.
2. Instruction Queue (IQ):
It is a queue of instruction so that the IR does not have to wait for the next instruction after one
has been processed.
3. Prefetch Control Unit (PFCU):

8
 A unit that controls the fetching of data into the I and D. caches in advance from the memory
units. The instructions and data are delivered when needed by the processor‘s execution units.
The processor does not have to fetch data just before executing the instruction. Pre-fetching unit
improves performance by fetching instruction and data in advance for processing.

4. Instruction Cache (I-Cache):

It sequentially stores, like an instruction queue, the instruction in FIFO mode. It lets the processor
execute instructions at great speed using PFCU compare to external system memories, which are
accessed at relatively much slower speeds.
5. Branch Target Cache (BT Cache):
It facilitates ready availability of the next instruction – set when a branch instruction like
jump, loop or call is encountered. Its fetch unit foresees a branching instruction at the I-
Cache.
6. Data Cache (D-Cache):
It stores the pre-fetched data from external memory. A data cache generally holds both the key
(address) and value (word) together at a location. It also stores write through data when so
configured. Write through data means data from the execution unit that transfer through the cache
to external memory addresses.
7. Memory Management Unit (MMU):
It manages the memories such that the instructions and data are readily availablefor processing.
8. System Register Set (SRS):

It is a set of registers used while processing the instructions of the supervisory system program.
9. Floating Point Processing Unit (FLPU):
A unit separate from ALU for floating point processing, which is essential in processing
mathematical function fast in a microprocessor or DSP.
10. Floating Point Register set (FRS):
A register set dedicated for storing floating point numbers in a standard format and used by FLPU
for its data and stack.
11. Multiply and Accumulate Unit (MAC):
There is also a MAC unit for multiplying coefficients of a series and accumulating these during
computations.
9
 12. Atomic Operation Unit (AOU):
It lets a user (compiler) instruction, when broken into a number of processor instruction called
atomic operations, finish before an intercept of a process occurs. This prevents problems from
arising out of shared data between various routines and tasks.

3. Write short note on (i) DMA (ii) Memory Management.

(i) DMA (DIRECT MEMORY ACCESS):
Definition: A direct memory access (DMA) is an operation in which data is copied from one resource to
another resource in a computer system without the involvement of the CPU. The task of a DMA
controller (DMAC) is to execute the copy operation of data from one resource location to another. The
copy of data can be performed from:

I/O device memory

Memory to I/O device
Memory to Memory

I/O device to I/O device

Figure: Logical Structure of System with DMA

DMAC is an independent resource of a computer added for theconcurrent

execution of DMA operations. The first two operation modes are ‗read from‘
and ‗write to‘ transfers of an I/O device to the main memory, which are the common operation of a DMA
controller.
The DMAC replaces the CPU for the transfer task of data from I/O device to the main
memory, otherwise it is executed by the CPU using the programmed input output mode (PIO). The
‗memcopy’ is used for PIO operation. The DMAC is a master/slave resource on the system bus,
because it supply the address for the resources involved in a DMA transfer. It requests the bus whenever a
data is available for transport, which is signalled from the device by ―REQ‖ signal.
DMA Operation: There are many modes of operation such as, Single
block transfer (most commonly used)

10
 Chained block transfers
Linked block transfers
Fly- by transfers

Figure: DMA Operation

Execution of a DMA – Operation (Single block Transfer)

For DMA operation, the CPU prepares the construction of a descriptor (1). It contains all
information for the DMAC to independently perform the DMA operation. It initializes the operation by
writing a command to a register in a DMAC (2a) or to a command area, where the DMAC can poll for the
command and/or the descriptor (2b). Then the DMAC addresses the device data register (3) and read the
data into a temporary data register (4). In another bus transfer cycle, it addresses the memory block (5)
and writes the data from the temporary data register to the memory block (6).
The DMAC increments the memory block address and continue with this loop

until the block length is reached. The completion of the DMA operation is signalled to the processor by
sending an IRQ signal.

(ii) MEMORY MANAGEMENT:

When a process is created, the memory manager allocates the memory addresses to it by mapping the
process address space. Threads of a process share the memory space of the process.
Memory Leak: A memory allocation that does not have a corresponding de-allocation.

11
 A memory leak is a gradual loss of available computer memory, when a program repeatedly fails
to return memory that it has obtained for temporary use. Due to memory leak, run out of memory problem
will occur.
Stack overflow means that the stack exceeds the allocated memory block when there is no
provision for additional stack space. Memory manager controls the memory leaks and stack overflows.
Memory Management strategies are

1. Fixed blocks allocation: Memory address space is divided into blocks with processes of small
address spaces getting a lesser number of blocks and processes of big address spaces getting a
large number of blocks.
2. Dynamic block allocation: Memory manager allocates variable size blocks dynamically
allocated from a free list of memory blocks description table atdifferent phases of a process.
3. Dynamic Page Allocation: Memory has fixed sized blocks called pages and the memory
management unit allocates the pages dynamically with a page descriptor table.
4. Dynamic data memory allocation: The manager allocates memory dynamically to
different data structures like the nodes of a list, queues and stacks.
5. Dynamic address relocation: The manager dynamically allocates the addresses

bound to the relative address. It adds the relative address to address with relocation register. This
is also called run-time dynamic address binding.
6. Multiprocessor Memory Allocation: it adopts the tight coupling or loose coupling
between two or more processors.
7. Memory protection to OS functions: It means that the system call and function call in
user space are distinct. The memory of kernel functions is distinct and can be addressed
only by the system calls. The memory space is called kernelspace.
8. Memory Protection among the tasks: Read and write operations are not permitted
to the particular memory space allocated to another task. This

12
 protection increases the memory requirement for each task and also theexecution time of the
code of the task.
The Manager optimizes the memory needs and memory utilization. The memorymanages the
following:
1. Use of memory addresses space.
2. Mechanism to share memory space
3. Mechanism to restrict sharing of a given memory space.
4. Optimization of memory.

4. Write short note on (i) ICE (ii) Timer &

Counter.
(i) IN – CIRCUIT EMULATOR (ICE):
In- circuit emulation is the use of a hardware device of in-circuit emulator
used to debug the software of an embedded system. It operates by using – processor with the
additional ability to support debugging operations as well as to carry out the main function of the
system.
ICE is a computer chip that is used to emulate a microprocessor, so that embedded system software can
be tested by developers. It allows a programmer to charge or debug the software in an embedded
system. The ICEs gives the option of debugging by single stepping.

Working Principle:
The programmer uses the emulator to load programs into the embedded system, run them, step
through them slowly and view and change data used by the system‘s software. It imitates the
central processing unit of the embedded system‘s computer.
The house of Microchip offers in circuit emulators are of 3 types: MPLAB ICE 2000, MPLAB
ICE 4000, REAL ICE.

13
 ICE consists of a small dual port pod. One port is a probe that plugs into the microprocessor
socket of the target system. The second port is interfaced to a computer (or) workstation.
Limitations of ICE:

Availability and cost

On chip functions
Transparency
Features and capabilities of ICE are

1. Ability to map resources between target and host.

2. Ability to run and test code in real time without target hardware.
3. Ability to step or run programs from/to specified states or break points.
4. Ability to observe and modify microprocessor registers.
5. Ability to Observe and modify memory contents.
6. Ability to trace program execution using internal Logic Analyzers.
(ii) TIMERS AND COUNTERS:

Timer is a very common and useful peripheral. It is a device that counts the regular interval (δT)
clock pulse at its input. The counts are stored and incremented on each pulse. It has output bits for the
period of counts. The counts multiplied by interval δT gives the time.
Number of counting the interval x δT = Time
Timer is a programmable device, (i.e) the time period can be adjusted by writing specific bit
patterns to some of the registers called timer-control registers.
A counter is more general version of the timer. It is a device that counts the input
for events that may occur at irregular or regular intervals. The count gives the number of

input events or pulses, since it was last read.

The simple timer has a 16 bit up counter which increments with each input clock pulse is shown
in figure (a). Thus the output value ‗Cnt‘ represents the number of pulses, since the counter was last reset
to zero. An additional output ‗top‘ indicates when the terminal count has been reached. It may go high for
a predetermined time as set by the programmable control word inside the timer unit. The count can be
loaded by the external program.

14
 The figure (b) provides the structure of another timer where a multiplexer is usedto choose
between an internal clock and external clock. The mode bit when set or reset
decided the selection. For internal clock (Clk) it behaves like the timer in Figure (a). For

the external coun- in (Cnt-in) it just counts the number of occurrences.

Figure (c): Timer with a terminal count

The figure (c) shows a timer with the terminal count. This can generate an event
if a particular interval of time has been elapsed. The counter restarts after every terminal count. For
example, in 8051 microcontroller, there is a presence of two bit timer/counter registers, Timer 0 and
Timer 1.
In timer mode, register is incremented after every machine cycle.
1 machine cycle = 12 Oscillator periods
So count rate = 1/12 of Oscillator frequency.
If crystal frequency is 12 MHz, then timer clock frequency is 1 MHz.
In counter mode, Register is incremented in response to 1 to 0 transition at the corresponding external
input pin T0 and T1.

15
Blind Counting Synchronisation:
A blind counting free running counter with prescaling, compare and capture registers has a
number of applications. It is useful for action or initiating a chain of actions and processor interrupts at
the present instances as well as for noting the instances of occurrences of the events and processor
intercepts for requesting the processor to use the captured counts on the events for future actions.
Watch dog Timer:
It is a timing device that resets the system after a predefined time out. It starts
after a few clock cycles from power up. After restart, system works normally, if any failure occurs in
past.
A watch dog timer is a piece of hardware that can be used to automatically detect
software abnormalities and reset the processor if any. It is based on the counter that counts down from
some initial value to zero.
The watchdog timer is a chip external to the processor. However, it could also be included within
the same chip as the CPU. This is done in many microcontrollers.
The process of restarting the watch dog timer‘s counter is sometimes called
“Kicking the dog”.

Real Time Clock (RTC):

It is a clock that keeps track of the time even when computer is turned off. Real time clocks
(RTC) run on a special battery that is not connected to the normal power supply. In contrast, clocks that
are not real time do not function when the computer isoff. Do not confuse a computer‘s real time clock
with its CPU clock. The CPU clock regulates the execution of instructions.
Real time clock provides system clock and it has a number of applications. It is a clock that
generates system interrupts at preset intervals. An Interrupt Service Routine (ISR) executes on each
tick or timeout or overflow of this clock. Once the device

16
started, it never resets or never reloaded to another value. Example: DS1307 chip is a real time clock
integrated circuit.
Consider the block diagram shown below. The Arduino UNO is used for reading time from
DS1307 and display it on 16X2 LCD. DS1307 sends time/data using 2 lines to Arduino. A buzzer is also
used for alarm indication, which beeps when alarm is activated.

PROCESSOR:

A processor is the heart of the embedded system. For an embedded systemdesigner,

knowledge of microprocessors and microcontrollers is a prerequisite.
PROCESSOR IN A SYSTEM:
A processor has 2 essential units.
1. Program flow Control Unit (CU)
2. Execution Unit (EU)
The CU includes a fetch unit for fetching instructions from the memory. The EU has circuits that
implement the instructions pertaining to data transfer operations and data conversions from one form to
another. The EU includes the Arithmetic and Logic Unit (ALU) and also the circuits that execute
instructions for a program control task, say halt,
interrupt or jump to another set of instructions. It can also execute instructions for a call

5. How to select the processor based upon its architecture and

applications?
or branch to another program and for a call to a function.
A processor runs the cycles of fetch and execute. The instructions defined in the processor
instruction set are executed in the sequence that they are fetched from the memory. An embedded system
processor chip can be one of the following:
1. General Purpose Processor (GPP)
 Microprocessor
 Microcontroller
 Embedded Processor
 Digital Signal Processor (DSP)
 Media Processor
2. Application Specific System Processor (ASSP) as additional processor.
17
 3. Multiprocessor System using General Purpose Processor (GPP) and Application
Specific Instruction Processor (ASIP)
4. GPP cores or ASIP cores integrated into an Application SpecificIntegrated circuit
(ASIC), a Very Large Scale Integrated Circuit (VLSI) circuit, or an FPGA core
integrated with processor units in a VLSI (ASIC) chip.

SELECTION OF PROCESSOR:
Most embedded systems need some type of processor. For a system designer,the following are
important considerations when selecting a processor.
1. Instruction set
2. Maximum bits in an operand
3. Clock frequency in MHz
4. Processing speed in Million Instructions Per Second (MIPS)
5. Processing ability to solve the complex algorithms used in meeting thedeadlines for their
processing.
6. Register – windows provides fast context switching in a multitasking system.
7. Power efficient embedded system requires a processor that has auto-shut down feature for its
units and programmability for disabling use of caches when the processing need for a
function or instruction set does not have constraint of execution time. It is also required to
have stop, sleep, and wait instructions. It may alsi require special cache design
8. Burst mode accesses external memories fast, reads fast and writes fast.
9. Atomic operation unit provides hardware solution to shared data problem, when designing
embedded software or else special programming skills and

efforts are to be made when sharing the variables among the multiple tasks.
10. A processor may also be configured at the initial program stage big-endian orLittle endian
storage of words. Eg: ARM processors.
11. The strong ARM family processors from Intel and Tiger SHARC from Analogdevices have
high power efficiency features.

SELECTION OF MICROCONTROLLER VERSION:

A version and microcontroller is selected for embedded system design as per theapplication as well
as its cost.
1. Embedded system in an automobile requires CAN controller and CANtransceiver.

18
 2. 8051 has only 2 timers Times 0 & Times 1, but 8052 has an additional timer
– Timer 2, which is used for the development of Real Time OperatingSystem.
3. Some Microcontrollers support master slave mechanism with the features ofI2C
and SPI supported in-built pins.
4. 8051 family member 83C152JA has two direct memory access (DMA)channels on-
chip.
5. For interfacing more number of devices, we need more pins in
microcontrollers to develop a particular application.
6. 80196KC has a PTS (Peripheral Transactions Server) that supports DMA
functions.
MICROPROCESSORS:

Microprocessor is a single VLSI chip that has a CPU and may have some other units.
Example: caches, floating point processing, arithmetic unit, pipelining etc. RAM, ROM and I/O
units will not present within a CPU chip itself. Microprocessor accepts binary data as input &
process data according to the instructions given and provides results as output. CPU has two
basic functional units such as Control unit and Arithmetic Logic Unit (ALU). Example: 8085,
8086.

MICROCONTROLLER:

Microcontroller is a device, which integrates a number of the components of a microprocessor

system onto a single microchip. It combines the CPU core, memory (ROM & RAM) and some parallel
digital I/O ports onto the same microchip. Program memory is ROM and Data Memory is RAM.
Example: 8051, PIC18F, PIC19F.
19
 A microcontroller is a single chip VLSI unit, through which having limited computational
capabilities, possesses enhanced input- output capabilities and a numberof on-chip functional units.

MECHANISM IN MICROCONTROLLERS:

STEPS:

1. CPU gets the Instruction (MOV,MVI) from ROM.

2. CPU also gets the data (A=5, B=6) from RAM or from Peripheral Registers.
3. Now CPU registers are having the data and send data to the ALU unit to performthe
mathematical or logical operation.
4. Finally the results are returned back to the CPU registers. In the turn CPUregisters send the data
to RAM or to peripheral devices.
PROCESSOR ARCHITECTURES:
A processor is the logic circuitry that responds to and processes the basic instructions that drive a
system. The term processor has generally replaced the term central processing unit. The processor in a
personal computer or embedded in small
devices is often called a microprocessor. The presence of Microprocessor and Memory
within a single chip is called as Microcontroller. The various processor architectures are
1. Von Neumann Architecture
2. Harvard Architecture
3. Super Harvard Architecture
4. Layered Architecture

VON NEUMANN ARCHITECTURE

Fig: Von Neumann Architecture

20
 Single memory and single bus for transferring the data into and out of the CPU. Multiplication of
two numbers require atleast three clock cycles.

HARVARD ARCHITECTURE

Seperate memory for data and program with separate buses for each. Both program instructions
and data values can be fetched at the same time. Operational speed is higher than Von Neumann
architecture.
Examples:

8051 Microcontroller is a Harvard Architecture with CISC Instruction Set PIC

Microcontroller is a Harvard Achitecture with RISC Instruction Set

SUPER HARVARD ARCHITECTURE (DSP Processors)

DSP algorithms spend their most of the time in loops. So instruction cache is added. DSP
processors are capable of processing many high frequency signals in real time. The significant
feature present in the DSP processor is Multiply – Accumulate operation

Example: a <- a+(B X C)

By using this feature this mathematical part will performed in a single clock cycle. Applications
performed in this processor are fixed point & floating point operations, matrix operations, convolution,
correlation, parallelism etc.

21
 Examples: C5000, C6000 single core processor families are manufactured byTexas Instruments.
C6000 processor fetch eight 32 bit instructions per clock cycle.

ARCHITECTURE OF EMBEDDED SYSTEMS:

to the very effective embedded systems.
The combination of hardware, operating software and application software leads
Case studies

Case-I : When the processor instruction cycle time is 1 microsecond

On chip devices and memory is sufficient. A microcontroller can be selected.

Examples : Automatic chocolate vending machine,56kbps modem, Robots, Data acquisition systems like
an ECG recorder, Weather recorder, Multipoint temperature and pressure recorder and realtime Robotic
controller.
Case-II : When the processor instruction cycle time is 10 to 40 nanosecond
On chip devices and memory is not sufficient. A microprocessor is required.
Examples : 52Mbps router, image processing, voice data acquisition,voice and video compression and
adaptive cruise control.
Case-III : When the processor instruction cycle time is 5 to 10 nanosecond

High MIPS(Million Instruction per second) or MFLOP (Million Floating Point IPS) multiprocessor
system is required,
Examples : Multi port 100Mbps network transceiver, fast 100 Mbps switches, routers,multichannel fast
encryptions and decryptions system.

Case-IV : When the processor instruction cycle time is 1 nanosecond

Microprocessor and DSP based multiprocessor system is needed.
Examples : Voice and video processing, real time audio and video processing andmobile phone
systems.
6. Discuss in detail about Target hardware Debugging.
Most of these debugging techniques can be applied to any microcontroller since they donot use any
specific tools.
22
There are many ways to debug hardware, they are,
1. ICE (In Circuit Emulator)
2. ICD (In Circuit Debug)
3. Simulation
4. Serial RS-232
5. LCD
6. LED
7. Hardware pins
8. Logic Analyzer
ICE (In Circuit Emulator): In Circuit Emulator is the most expensive way to debug your hardware. It
takes a special processor that physically takes place of the normal
processor. This special processor allows software access to the internal operation of the
processor.

ICD (In Circuit Debug): The next best thing to ICE is ICD (In Circuit Debug). This is for PIC
microcontroller. BDM (Background Debug Mode) is for non PIC microcontroller. For ICD the
processor has a small amount of built-in hardware that can halt the processor when the
program reaches a specific address. The software can then read back all the registers and
processor state.

Simulation: With a source code simulator you can step through the high level language code
and see its effect on memory and variables without having to look at the assembler code
directly. This let you focus on high level language operation and let you concentrate on the
problem you are trying to solve. One great advantage of simulator is that you do not have to
wait toRS232:
Serial download and
New program the target
microcontrollers have a processor. So you
built-in UART cangives virtually free debug tool that
which
uses minimum resources and need very little software coding. For debug output you need to connect the
cut out the time consuming programming just by using the simulator.
UART output in TX to a suitable level translator circuit a MAX 232 chip. You may even get away with
direct connection to the input of your PC serial port – using a translator chip will always work.
Advantages: Minimal coding, simple to use, minimal extra hardware.
Disadvantage: a) Takes long time to output a character (~1ms)

b) Takes even longer for blocks of characters (~10sf ms)

c) Need extra hardware.
Even though it takes time to output a character, it is a useful debug tool as you can output the value of
variable to see what the microcontroller is really doing.
23
LCD: An LCD (Liquid crystal Display) gives a convenient way of displaying debugging information. It
is also useful for many different applications that need a text display output. It is a module that displays
text characters and a common screen size is 2 rows of 16 characters. Most LCD modules use the
HD44780 controller chip which is why LCDroutines built into high level language always work.
Advantage: a) Very quick update (40 µs 4 bit data bus)

b) Useful in many projects as the main display interface.

c) Simple to interface to an 8-bit port (only needs six of the 8-bits)
Disadvantage: a) Uses up an 8-bit port

b) Hardware is more expensive (Example: compared to a serial port chip)

LED: Using an LED as a microcontroller ―alive‖ indicator. Even though it is such a
simple thing to blink an LED on and off it is extremely useful as a debugging tool as you can tell at a
glance whether the code you just downloaded is working sometimes you can will incorrectly set
parameter on the programming software or compiler which will stop the code dead.
The LED indicator gives a quick health check for your microcontroller which is easy to see.
Pin Debugging: This is the simplest and rudest debugging method using any availableport pin.
Simply set and reset this pin at any point in the code that you want to monitor. It has minimal impact on
the code speed or size and can give you the followinginformation.
You can tell if the code is active.
It gives you the repetition rate
It gives you the routine time length (if you set the pin at the start and reset it at

the end).
Logic Analyzer: This tool attaches to the pins you want to observe and captures the waveforms
displaying multiple traces on a single display. It uses a trigger module that can be set to activate the
combinations of the input signals or on their length. So you can trigger on specific patterns or on glitches
or both.
For non-microcontroller based systems where the data and address bus are exposed, a logic analyzer can
show the address and data organised into hex words i.e. readable. Some can disassemble the instruction
showing what the processor was doing at the trigger point.

24
For a microcontroller based system the logic analyzer can be useful in examining peripheral operation.
Example: for debugging the SPI or I2C buses some logic analyzers also have built in support for these
protocols.
Another use of the logic analyzer is to capture output over a long period of timedepending on the memory
capacity of the logic analyzer.

25
 (P) 2348-0017

Unit-II

Input Output Ports

Ports: The connection point acts as an interface between the computer and
external devices like printers, modems, etc.

There are two types of ports :

1. Internal Port: It connects the system’s motherboard to internal devices

like hard disk, CD drive, internal Bluetooth, etc.
2. External Port: It connects the system’s motherboard to external devices
like a mouse, printer, USB, etc.

Types of ports

3
0
 (P) 2348-0017

Some important types of ports are as per follows:

1. Serial Port :

 Used for external modems and older computer mouse

 Two versions-9pin,25pin
 Data travels at 115 kilobits per second
2. Parallel Port :
 Used for scanners and printers
 25 pin model
3. Universal Serial Bus (or USB) Port :
 It can connect all kinds of external USB devices such as external hard
disks, printers, scanners, mouse, keyboards, etc.
 Data travels at 12 megabits per second.
4. Firewire Port :

 Transfers large amounts of data at a very fast speed.

 Connects camcorders and video equipment to the computer.
 Data travels at 400 to 800 megabits per second.
5. Ethernet Port :
 Connects to a network and high-speed Internet.
 Data travels at 10 megabits to 1000 megabits per second depending upon
the network bandwidth.

RS232C for Data Transfer

RS232 is an Interface and the protocol between DTE(data terminal

equipment) and DCE(data communication
3 equipment) using serial binary
1
 data exchange. Here C is used for the current version. Universal
Asynchronous Data Receiver & Transmitter (UART), attached in a
(P) 2348-0017
motherboard, used in connection with RS2 32 for transmitting data to any
serial device like modem or printer from its DTE interface.

Electrical Specifications :
1. Voltages:
There can be two states in the signal level of RS232C pins.
 Mark state – It is the high bit which is represented by binary 1 and have
negative voltages. Its voltage limits for transmitting signal ranges from -5 to -
15V. Its voltage limits for receiving signals ranges from -3 to -25V.
 Space state – It is the low bit which is represented by binary 0 and have
positive voltages. Its voltage limits for transmitting signal ranges from +5 to
+15V. Its voltage limits for receiving signals ranges from +3 to +25V.
2. Cables and Wires :
The maximum cable length for RS232C is equals to
15.24 meters or equal to the capacitance of 2500pF. Limits for the impedance of
wires ranges from 3 ohms to 7 ohms.
3 Data and Slew rates :
Rate of data transmission through RS232C is up to 20Kbps. The rate of change
in signal levels ie. slew rate is up to 30V/microsecond.
4. Current :
Maximum current rating is 3Amps at the maximum operating voltage of 250V
AC.
Pins and Working :

3
2
 (P) 2348-0017

RS232C requires 25 pins connector for connecting DTE and DCE. Here is the
list of pins and signals of RS232C and the connection between DTE and DCE
using drivers and receivers.
1. TXD & RXD –
Transmit Data and Receive Data on the DTE are the serial data lines. These
lines have opposite functions on a DCE. TXT sends outgoing data to DCE.
RXD receives incoming data from DTE.

2. RTS & CTS –

Transmitter activates the Request to Send when it requires to transmit data
over the line. The line itself gets deactivated when the communication stops.
Receiver activates the Clear To Send to tell the transmitter whether it is ready
or not to receive the data. It remains active during the transmission.

3. DTR & DSR –

Through the Data Terminal Ready line, DTE informs the DCE that it is in
online mode and the process of communication can occur. The main task of
Data Set Ready signal is to inform that DCE is ready for communication.

4. DCD –
DCE activates the Data Carrier Detect in order to show that it has been
connected to DTE.

5. RI –
When an incoming call on the telephone line is detected by DCE, then the
Ring Indicator gets activates.

3
3
Handshaking:
Before the actual data transfer, signals are transmitted from DTE(P)to2348-0017
DCE in
order to make connections by a process known as handshaking. Following is the
sequence of signal handshaking:
 Initially, the computer activates RTS signal to modem when a data is
transferred from computer to modem.
 Modem in turn activates the DCD and then the CTS gets activated.
 Computer then sends data on TXD. After the data transmission is
completed, the computer deactivates the RTS which causes the modem to
deactivate CTS.
Applications :
However, most of functions performed by RS232C has been taken by the USB,
but they are still successful in performing following applications.
1. It is used in establishing communication between the computer and
embedded systems.
2. Due to its lower costs, It plays a vital role in CNC machines and servo
controllers
3. Some microcontroller boards and PLC machines use RS232C.
4. RS232C ports are used to communicate in headless systems in the absence
of any network connection.
5. Many Computerized Numerical Control Systems are contains RS232C
port.
Limitations :
1. It cannot be used for chip to chip or chip to sensor device communication
2. It degrades the performance of the system in the presence of noise and
requires shorter cables due to having common grounds between DTE and
DCE
3. The cost of system increases as RS232C interface needs separate
transceiver chips.
4. Its performance degrades to short distances only when transfer speed is
high.

RS422 protocol

RS422 is similar to RS232 protocol, and can be programmed in the same way,
3
however, offers a few advantages and disadvantages. One problem is that you need to
4
purchase an RS422 port or at least an RS422 to RS232 converter, since PC's don't
come standard with this interface. Also, you may find that there are fewer(P)devices
2348-0017
supporting RS422. Some advantages are:

1. Long Distance Runs - Up to 500 feet is generally supported, and with repeaters,
even further distances can be achieved.
2. Multi-Drop - Usually, up to 32 devices can be connected per port, and even
more using repeaters. Devices are distinguished by unique addresses that are
assigned to each device. For example, if you have 5 devices attached to a port,
they would be addressed as units 1 to 5. If you want to communicate to unit #1,
you send a command to unit #1. All units HEAR the command, but only the
addressed unit will respond. This also applies to RS485. The addresses can be
set via switches or software, depending on the design of the device.
3. Noise Resistant - Since it uses a separate FLOATING transmit and receive pair
(four wires), it offers better noise immunity than RS232.

RS485 protocol

RS485 is very similar to RS422. So much so that it often causes confusion. Both are
multi-drop, and both can communicate via very long distances, so then why choose
one over the other? First of all, RS485 is generally a 2-wire system, although some
manufacturers may specify 4-wire RS485, which is far less common and very similar
to RS422 protocol. It is important that you identify which one is being employed
when considering an instrument. Here are some main differences between 2-wire
RS485 and RS422:

1. RS485 can have multiple Commanding Devices and multiple Listening

Devices. RS422 can have only one Commander and multiple Listeners. For
example, you can connect one PC (the Commanding device) to 10 temperature
controllers (listeners). The PC can instruct any of the controllers to change
setpoint, or to send a temperature reading, but none of the controllers can
command any of the other controllers. With RS485, you can have multiple PC's
and multiple controllers on one bus, so that one PC can send a command to
change a setpoint,and another PC can send a command to send back data, etc.
3
5
 Remember that all devices on the bus must have a unique unit address, so that
only the addressed unit will respond. (similar to RS422) (P) 2348-0017
2. RS485 pinout wiring is easier since you are only dealing with 2 wires instead
of 4.
3. Programming RS485 is more difficult, since you are sending and receiving on
the same two wires, you need to enable and disable the transmitter at the
correct time so that you may perform proper communications. Imagine sending
a command USD$2SEND out of the transmitter. If the transmitter is not turned
off in time, then data being sent by another device will be missed. If the
transmitter is turned off too quickly, there is a chance that part of the command
USD$S2END will be truncated before it ever has a chance finishing the
transmission of the character bits. When programming an RS485 plug-in card,
you would read the STATUS REGISTER to determine if it is time to switch or
not. Some cards, such as the OMG-ULTRA-485 has an AUTO mode where it
is intelligent enough to do this automatically, making it transparent to the
programmer. Since RS422, and RS232 for that matter, have separate transmit
and receive lines, they are easier to implement. Of course, there are other
matters to consider such as handshaking, but will not be covered in this brief
description.

Note:it may be easier to use an rs232 to rs485 converter that sits outside the pc. Make
sure that the converter has intelligent control of the transmitters so that it will
automatically take care of the switching for you and will be transparent to the user.
Then, program the device as you would an rs422 or rs232 device. One such device is
our model cat-285.

What is CAN?

CAN is short for ‘controller area network’. Controller area network is an electronic communication bus
defined by the ISO 11898 standards. Those standards define how communication happens, how wiring is
configured and how messages are constructed, among other things. Collectively, this system is referred to as
a CAN bus.

3
6
 What We'll Cover
(P) 2348-0017

To get deeper into the details of CAN, the CAN bus is a broadcast type of bus. This means that all nodes can
“hear” all transmissions. There is no way to send a message to just a specific node; all nodes will invariably
pick up all traffic. The CAN hardware, however, provides local filtering so that each node may react only on
the interesting messages. We’ll discuss this more in Section 2, “CAN Messages”.
We’ll also discuss how the bus uses Non-Return To Zero (NRZ) with bit-stuffing. In this system, the
modules are connected to the bus in a wired-and fashion: if just one node is driving the bus to a logical 0,
then the whole bus is in that state regardless of the number of nodes transmitting a logical 1.

The CAN standard defines four different message types. The messages uses a clever scheme of bit-wise
arbitration to control access to the bus, and each message is tagged with a priority.

The CAN standard also defines an elaborate scheme for error handling and confinement which is described in
more detail in Section 7, “CAN Error Handling”.
Bit timing and clock synchronization is discussed in Section 6 of this tutorial. Here’s a bit timing
calculator you can use to calculate the CAN bus parameters and register settings.
CAN bus wiring may be implemented using different physical layers (Section 3), some of which are
described here, and there are also a fair number of CAN bus connector types (Section 5) in use. We also
provide a number of oscilloscope pictures (Section 4) for those interested in the details of a message.
CAN Messages

The CAN bus is a broadcast type of bus. This means that all nodes can ‘hear’ all transmissions. There is no
way to send a message to just a specific node; all nodes will invariably pick up all traffic. The CAN
hardware, however, provides local filtering so that each node may react only on the interesting messages.

The CAN messages

CAN uses short messages – the maximum utility load is 94 bits. There is no explicit address in the messages;
instead, the messages can be said to be contents-addressed, that is, their contents implicitly determines their
address.
Message Types
There are four different message types (or ‘frames’) on a CAN bus:
1. the Data Frame
2. the Remote Frame
3. the Error Frame
4. the Overload Frame

The Data Frame

The Data Frame is the most common message type. It comprises the following major parts (a few details are
omitted for the sake of brevity):

3
7
 the Arbitration Field, which determines the priority of the message when two or more nodes are
contending for the bus. The Arbitration Field contains:
(P) 2348-0017
 For CAN 2.0A, an 11-bit Identifier and one bit, the RTR bit, which is dominant for data
frames.

 For CAN 2.0B, a 29-bit Identifier (which also contains two recessive bits: SRR and IDE) and
the RTR bit.

the Data Field, which contains zero to eight bytes of data.

the CRC Field, which contains a 15-bit checksum calculated on most parts of the message. This
checksum is used for error detection.

an Acknowledgement Slot; any CAN controller that has been able to correctly receive the message
sends an Acknowledgement bit at the end of each message. The transmitter checks for the presence of the
Acknowledge bit and retransmits the message if no acknowledge was detected.

Note 1: It is worth noting that the presence of an Acknowledgement Bit on the bus does not mean that any of
the intended addressees has received the message. The only thing we know is that one or more nodes on the
bus has received it correctly.

Note 2: The Identifier in the Arbitration Field is not, despite of its name, necessarily identifying the contents
of the message.

A CAN 2.0A (“standard CAN”) Data Frame.

A CAN 2.0B (“extended CAN”) Data Frame.

3
8
 (P) 2348-0017
The Remote Frame

The Remote Frame is just like the Data Frame, with two important differences:

 it is explicitly marked as a Remote Frame (the RTR bit in the Arbitration Field is recessive), and

 there is no Data Field.

The intended purpose of the Remote Frame is to solicit the transmission of the corresponding Data Frame. If,
say, node A transmits a Remote Frame with the Arbitration Field set to 234, then node B, if properly
initialized, might respond with a Data Frame with the Arbitration Field also set to 234.

Remote Frames can be used to implement a request-response type of bus traffic management

The Error Frame

Simply put, the Error Frame is a special message that violates the framing rules of a CAN message. It is
transmitted when a node detects a fault and will cause all other nodes to detect a fault – so they will send
Error Frames, too. The transmitter will then automatically try to retransmit the message. There is an elaborate
scheme of error counters that ensures that a node can’t destroy the bus traffic by repeatedly transmitting Error
Frames.
The Error Frame consists of an Error Flag, which is 6 bits of the same value (thus violating the bit-stuffing
rule) and an Error Delimiter, which is 8 recessive bits. The Error Delimiter provides some space in which the
other nodes on the bus can send their Error Flags when they detect the first Error

The Serial Peripheral Interface (SPI) is a synchronous serial communication interface

specification used for short-distance communication, primarily in embedded systems. The interface
was developed by Motorola in the mid-1980s and has become a de facto standard. Typical
applications include Secure Digital cards and liquid crystal displays.
SPI devices communicate in full duplex mode using a master-slave architecture usually with a
single master (though some Atmel devices support changing roles on the fly depending on an
external (SS) pin). The master (controller) device originates the frame for reading and writing.
Multiple slave-devices may be supported through selection with individual chip select (CS),
sometimes called slave select (SS) lines.
Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-wire serial
buses. The SPI may be accurately described as a synchronous serial interface, [1] but it is different
from the Synchronous Serial Interface (SSI) protocol, which is also a four-wire synchronous serial
communication protocol. The SSI protocol employs differential signaling and provides only a
single simplex communication channel. For any given transaction SPI is one master and multi slave
communication.
The SPI bus specifies four logic signals: 3
9
 SCLK: Serial Clock (output from master)
 MOSI: Master Out Slave In (data output from master) (P) 2348-0017
 MISO: Master In Slave Out (data output from slave)
 CS /SS: Chip/Slave Select (often active low, output from master to indicate that data is being
sent)
MOSI on a master connects to MOSI on a slave. MISO on a master connects to MISO on a slave.
Slave Select has the same functionality as chip select and is used instead of an addressing concept.
Note: on a slave-only device, MOSI may be labeled as SDI (Serial Data In) and MISO may be
labeled as SDO (Serial Data Out)
The signal names above can be used to label both the master and slave device pins as well as the
signal lines between them in an unambiguous way, and are the most common in modern products.
Pin names are always capitalized e.g. "Chip Select," not "chip select."
Many products can have nonstandard SPI pin names:
Serial Clock:

 SCK .
Master Output → Slave Input (MOSI):

 SIMO, MTSR - correspond to MOSI on both master and slave devices, connects to each
other
 SDI, DI, DIN, SI - on slave devices; connects to MOSI on master, or to below connections
 SDO, DO, DOUT, SO - on master devices; connects to MOSI on slave, or to above
connections
Master Input ← Slave Output (MISO):

 SOMI, MRST - correspond to MISO on both master and slave devices, connects to each
other
 SDO, DO, DOUT, SO - on slave devices; connects to MISO on master, or to below
connections
 SDI, DI, DIN, SI - on master devices; connects to MISO on slave, or to above connections
Slave Select:

 SS, SS, SSEL, nSS, /SS, SS# (slave select)

 CS, CS (chip select)
 CSN (chip select/enable)
 CE (chip enable)

Operation[edit]
The SPI bus can operate with a single master device and with one or more slave devices.
If a single slave device is used, the SS pin may be fixed to logic low if the slave permits it. Some
slaves require a falling edge of the chip select signal to initiate an action. An example is
the Maxim MAX1242 ADC, which starts conversion on a high→low transition. With multiple slave
devices, an independent SS signal is required from the master for each slave device.
4
0
Most slave devices have tri-state outputs so their MISO signal becomes high
impedance (electrically disconnected) when the device is not selected. Devices without tri-state
(P) 2348-0017
outputs cannot share SPI bus segments with other devices without using an external tri-state buffer.
Data transmission[edit]
(Note: refer to the ‘Variations’ section later in this article for further details.)

A typical hardware setup using two shift registers to form an inter-chip circular buffer

To begin communication, the bus master configures the clock, using a frequency supported by the
slave device, typically up to a few MHz. The master then selects the slave device with a logic level
0 on the select line. If a waiting period is required, such as for an analog-to-digital conversion, the
master must wait for at least that period of time before issuing clock cycles.
During each SPI clock cycle, a full-duplex data transmission occurs. The master sends a bit on the
MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads
it. This sequence is maintained even when only one-directional data transfer is intended.
Transmissions normally involve two shift registers of some given word-size, such as eight bits, one
in the master and one in the slave; they are connected in a virtual ring topology. Data is usually
shifted out with the most significant bit first. On the clock edge, both master and slave shift out a bit
and output it on the transmission line to the counterpart. On the next clock edge, at each receiver the
bit is sampled from the transmission line and set as a new least-significant bit of the shift register.
After the register bits have been shifted out and in, the master and slave have exchanged register
values. If more data needs to be exchanged, the shift registers are reloaded and the process repeats.
Transmission may continue for any number of clock cycles. When complete, the master stops
toggling the clock signal, and typically deselects the slave.
Transmissions often consist of eight-bit words. However, other word-sizes are also common, for
example, sixteen-bit words for touch-screen controllers or audio codecs, such as the TSC2101
by Texas Instruments, or twelve-bit words for many digital-to-analog or analog-to-digital
converters. Multiple SPI devices may also be daisy-chained to conserve pins.
Every slave on the bus that has not been activated using its chip select line must disregard the input
clock and MOSI signals and should not drive MISO (i.e., must have a tristate output) although some
devices need external tristate buffers to implement this.

Serial Peripheral Interface (SPI)

Introduction
Serial Peripheral Interface or SPI is a synchronous serial communication protocol that provides full
– duplex communication at very high speeds. Serial Peripheral Interface (SPI) is a master – slave
4
1
type protocol that provides a simple and low cost interface between a microcontroller and its
peripherals.
(P) 2348-0017

SPI Interface bus is commonly used for interfacing microprocessor or microcontroller with memory
like EEPROM, RTC (Real Time Clock), ADC (Analog – to – Digital Converters), DAC (Digital –
to – Analog Converters), displays like LCDs, Audio ICs, sensors like temperature and pressure,
memory cards like MMC or SD Cards or even other microcontrollers.

In UART (or any common serial port), where the communication happens over RX and TX line,
there is no clock signal i.e. it is an asynchronous communication. In this type of communication,
there is no control over the data sent or whether the transmitter and receiver have same data rates.

In order to overcome this, UART uses synchronisation bits i.e. Start bit and Stop bits and also a pre
agreed data transfer speeds (typically 9600 bps). If the baud rates of transmitter and receiver are not
matched, the data sent from the transmitter will not reach the receiver properly and often garbage or
junk values are received.

For short distance communication, Synchronous Serial Communication would be a better choice
and in that Serial Peripheral Interface or SPI in particular is the best choice. When we say short
distance communication, it often means communication with in a device or between the devices on
the same board (PCB).

The other type of Synchronous Serial Communication Protocol is I2C (Inter – Integrated
Communication, often called as I Squared C or I Two C). For this article, we will focus on SPI.

SPI is a Synchronous type serial communication i.e. it uses a dedicated clock signal to synchronise
the transmitter and receiver or Master and Slave, speaking in SPI terms. The transmitter and receiver
are connected with separate data and clock lines and the clock signal will help the receiver when to
look for data on the bus.

4
2
 (P) 2348-0017

The clock signal must be supplied by the Master to the slave (or all the slaves in case of multiple
slave setup). There are two types of triggering mechanisms on the clock signal that are used to
intimate the receiver about the data: Edge Triggering and Level Triggering.

The most commonly used triggering is edge triggering and there are two types: rising edge (low to
high transition on the clock) and falling edge (high to low transition). Depending on how the
receiver is configured, up on detecting the edge, the receiver will look for data on the data bus from
the next bit. S

Since both the clock and data are sent by the Master (or transmitter), we need not worry about the
speed of data transfer.

What makes SPI so popular among other Synchronous Serial Communication protocols (or any
serial communication for that matter) is that it provides a high speed secured data transfer with
reasonably simple hardware like shift registers at relatively less cost.

How SPI Works?

SPI or Serial Peripheral Interface was developed by Motorola in the 1980’s as a standard, low – cost
and reliable interface between the Microcontroller (microcontrollers by Motorola in the beginning)
and its peripheral ICs.

Because of its simple interface, flexibility and ease of use, SPI has become a standard and soon
other semiconductor manufacturers started implementing it in their chips.

In SPI protocol, the devices are connected in a Master – Slave relationship in a multi – point
interface. In this type of interface, one device is considered the Master of the bus (usually a
4
3
Microcontroller) and all the other devices (peripheral ICs or even other Microcontrollers) are
considered as slaves.
(P) 2348-0017

In SPI protocol, there can be only one master but many slave devices.

The SPI bus consists of 4 signals or pins. They are

 Master – Out / Slave – In (MOSI)

 Master – In / Slave – Out (MISO)
 Serial Clock (SCLK) and
 Chip Select (CS) or Slave Select (SS)
NOTE: Different manufacturers uses different nomenclature for the SPI bus. Refer the data sheet
for exact information.

Since, the SPI bus is implemented using 4 signals or wires, it is sometimes called as Four Wire
Interface. Let us first see a simple interface between a single master and single slave that are
connected using SPI protocol and then we will explain about the 4 wires.

The following image depicts a Master (Processor) connected to a Slave (Peripheral) using SPI

bu
s.

Master – Out / Slave – In or MOSI, as the name suggests, is the data generated by the Master and
received by the Slave. Hence, MOSI pins on both the master and slave are connected together.
Master – In / Slave – Out or MISO is the data generated by Slave and must be transmitted to Master.

MISO pins on both the master and slave are ties together. Even though the Signal in MISO is
produced by the Slave, the line is controlled by the Master. The Master generates a clock signal at
SCLK and is supplied to the clock input of the slave. Chip Select (CS) or Slave Select (SS) is used
to select a particular slave by the master.

Since the clock is generated by the Master, the flow of data is controlled by the master. For every
clock cycle, one bit of data is transmitted from master to slave and one bit of data is transmitted
from slave to master.
4
4
This process happen simultaneously and after 8 clock cycles, a byte of data is transmitted in both
directions and hence, SPI is a full – duplex communication.
(P) 2348-0017

If the data has to be transmitted by only one device, then the other device has to send something
(even garbage or junk data) and it is up to the device whether the transmitted data is actual data or
not.

This means that for every bit transmitted by one device, the other device has to send one bit data i.e.
the Master simultaneously transmits data on MOSI line and receive data from slave on MISO line.

If the slave wants to transmit the data, the master has to generate the clock signal accordingly by
knowing when the slave wants to send the data in advance. If more than one slave has to be
connected to the master, then the setup will be something similar to the following image.

Even though multiple slaves are connected to the master in the SPI bus, only one slave will be
active at any time. In order to select the slave, the master will pull down the SS (Slave Select) or CS
(Chip Select) line of the corresponding slave.

Hence, there must by a separate CS pin on the Master corresponding to each of the slave device. We
need to pull down the SS or CS line to select the slave because this line is active low.
4
5
SPI Hardware
The hardware requirement for implementing SPI is very simple when compared to UART(P) 2348-0017
and I2C.
Consider a Master and a single Slave are connected using SPI bus. The following image shows the
minimal system requirements for both the devices.

From the image, the Master device consists of a Shift Register, a data latch and a clock generator.
The slave consists of similar hardware: a shift register and a data latch. Both the shift registers are
connected to form a loop. Usually, the size of the register is 8 – bits but higher size registers of 16 –
bits are also common.

During the positive edge of the clock signal, both the devices (master and slave) read input bit into
LSB of the register. During the negative cycle of the clock signal, both the master and slave places a
bit on its corresponding output from the MSB of the shift register.

Hence, for each clock cycle, a bit of data is transferred in each direction i.e. from master to slave
and slave to master. So, for a byte of data to be transmitted from each device, it will take 8 clock
cycles.

SPI Modes of Operation

We have already seen that it is the job of the Master device to generate the clock signal and
distribute it to the slave in order to synchronise the data between master and slave. The work of
master doesn’t end at generating clock signal at a particular frequency.

In fact, the master and slave have to agree on certain synchronization protocols. For this, two
features of the clock i.e. the Clock Polarity (CPOL or CKP) and Clock Phase (CPHA) come in to
picture.

Clock Polarity determines the state of the clock. When CPOL is LOW, the clock generated by the
Master i.e. SCK is LOW when idle and toggles to HIGH during active state (during a transfer).
Similarly, when CPOL is HIGH, SCK is HIGH during idle and LOW during active state.

Clock Phase determines the clock transition i.e. rising (LOW to HIGH) or falling (HIGH to LOW),
at which the data is transmitted. When CPHA is 0, the data is transmitted on the rising edge of the
clock. Data is transmitted on the falling edge when4CPHA is 1.
6
Depending on the values of Clock Polarity (CPOL) and Clock Phase (CPHA), there are 4 modes of
operation of SPI: Modes 0 through 3.
(P) 2348-0017

Mode 0:
Mode 0 occurs when Clock Polarity is LOW and Clock Phase is 0 (CPOL = 0 and CPHA = 0).
During Mode 0, data transmission occurs during rising edge of the clock.

Mode 1:
Mode 1 occurs when Clock Polarity is LOW and Clock Phase is 1 (CPOL = 0 and CPHA = 1).
During Mode 1, data transmission occurs during falling edge of the clock.

Mode 2:
Mode 2 occurs when Clock Polarity is HIGH and Clock Phase is 0 (CPOL = 1 and CPHA = 0).
During Mode 2, data transmission occurs during rising edge of the clock.

Mode 3:
Mode 3 occurs when Clock Polarity is HIGH and Clock Phase is 1 (CPOL = 1 and CPHA = 1).
During Mode 3, data transmission occurs during falling edge of the clock.

SPI Configurations
There are two types of configurations in which the SPI devices can be connected in an SPI bus.
They are Independent Slave Configuration and Daisy Chain Configuration.

In Independent Slave Configuration, the master has dedicated Slave Select Lines for all the slaves
and each slave can be selected individually. All the4 clock signals of the slaves are connected to the
master SCK. 7
Similarly, all the MOSI pins of all the slaves are connected to the MOSI pin of the master and all
the MISO pins of all the slaves are connected to the MISO pin of the master.
(P) 2348-0017

In Daisy Chain Configuration, only a single Slave Select line is connected to all the slaves. The
MOSI of the master is connected to the MOSI of slave 1. MISO of slave 1 is connected to MOSI of
slave 2 and so on. The MISO of the final slave is connected to the MISO of the master.

Consider the master transmits 3 bytes of data in to the SPI bus. First, the 1st byte of data is shifted to
slave 1. When the 2nd byte of data reaches slave 1, the first byte is pushed in to slave 2.

Finally, when the 3rd byte of data arrives in to the first slave, the 1st byte of data is shifted to slave 3
and the second byte of data is shifted in to second slave.

If the master wants to retrieve information from the slaves, it has to send 3 bytes of junk data to the
slaves so that the information in the slaves comes to the master.

4
8
Applications of SPI
 Memory: SD Card , MMC , EEPROM , Flash (P) 2348-0017
 Sensors: Temperature and Pressure
 Control Devices: ADC , DAC , digital POTS and Audio Codec.
 Others: Camera Lens Mount, touchscreen, LCD, RTC, video game controller, etc.

Advantages
 SPI is very simple to implement and the hardware requirements are not that complex.
 Supports full – duplex communication at all times.
 Very high speed of data transfer.
 No need for individual addresses for slaves as CS or SS is used.
 Only one master device is supported and hence there is no chance of conflicts.
 Clock from the master is configured based on speed of the slave and hence slave doesn’t have to
worry about clock.

Disadvantages
 Each additional slave requires an additional dedicated pin on master for CS or SS.
 There is no acknowledgement mechanism and hence there is no confirmation of receipt of data.
 Slowest device determines the speed of transfer.
 There are no official standards and hence often used in application specific implementations.
 There is no flow control.

I2C Communication Protocol

I2C stands for Inter-Integrated Circuit. It is a bus interface connection protocol incorporated
into devices for serial communication. It was originally designed by Philips Semiconductor in
1982. Recently, it is a widely used protocol for short-distance communication. It is also known as
Two Wired Interface(TWI).
Working of I2C Communication Protocol :
It uses only 2 bi-directional open-drain lines for data communication called SDA and SCL. Both
these lines are pulled high.
Serial Data (SDA) – Transfer of data takes place through this pin.
Serial Clock (SCL) – It carries the clock signal.
I2C operates in 2 modes –
 Master mode
 Slave mode
Each data bit transferred on SDA line is synchronized by a high to the low pulse of each clock on
the SCL line.

4
9
 (P) 2348-0017

According to I2C protocols, the data line can not change when the clock line is high, it can change
only when the clock line is low. The 2 lines are open drain, hence a pull-up resistor is required so
that the lines are high since the devices on the I2C bus are active low. The data is transmitted in
the form of packets which comprises 9 bits. The sequence of these bits are –
1. Start Condition – 1 bit
2. Slave Address – 8 bit
3. Acknowledge – 1 bit
Start and Stop Conditions :
START and STOP can be generated by keeping the SCL line high and changing the level of SDA.
To generate START condition the SDA is changed from high to low while keeping the SCL high.
To generate STOP condition SDA goes from low to high while keeping the SCL high, as shown in
the figure below.

Start and Stop Condition

Repeated Start Condition :

Between each start and stop condition pair, the bus is considered as busy and no master can take
control of the bus. If the master tries to initiate a new transfer and does not want to release the bus
before starting the new transfer, it issues a new START condition. It is called a REPEATED
START condition.
Read/Write Bit :
A high Read/Write bit indicates that the master is sending the data to the slave, whereas a low
Read/Write bit indicates that the master is receiving data from the slave.
ACK/NACK Bit :
After every data frame, follows an ACK/NACK bit. If the data frame is received successfully then
ACK bit is sent to the sender by the receiver.
Addressing :
The address frame is the first frame after the start bit. The address of the slave with which the
master wants to communicate is sent by the master to every slave connected with it. The slave
then compares its own address with this address and sends ACK.
I2C Packet Format :
5
0
In the I2C communication protocol, the data is transmitted in the form of packets. These packets
are 9 bits long, out of which the first 8 bits are put in SDA line and the 9th bit is reserved for
(P) 2348-0017
ACK/NACK i.e. Acknowledge or Not Acknowledge by the receiver.
START condition plus address packet plus one more data packet plus STOP
condition collectively form a complete Data transfer.
Features of I2C Communication Protocol :
 Half-duplex Communication Protocol –
Bi-directional communication is possible but not simultaneously.
 Synchronous Communication –
The data is transferred in the form of frames or blocks.
 Can be configured in a multi-master configuration.
 Clock Stretching –
The clock is stretched when the slave device is not ready to accept more data by holding the
SCL line low, hence disabling the master to raise the clock line. Master will not be able to
raise the clock line because the wires are AND wired and wait until the slave releases the SCL
line to show it is ready to transfer next bit.
 Arbitration –
I2C protocol supports multi-master bus system but more than one bus can not be used
simultaneously. The SDA and SCL are monitored by the masters. If the SDA is found high
when it was supposed to be low it will be inferred that another master is active and hence it
stops the transfer of data.
 Serial transmission –
I2C uses serial transmission for transmission of data.
 Used for low-speed communication.
Advantages :
 Can be configured in multi-master mode.
 Complexity is reduced because it uses only 2 bi-directional lines (unlike SPI
Communication).
 Cost-efficient.
 It uses ACK/NACK feature due to which it has improved error handling capabilities.
Limitations :
 Slower speed.
 Half-duplex communication is used in the I2C communication protocol

5
1
 Unit-III
(P) 2348-0017

Embedded product development life cycle

Embedded product development life cycle is an “Analysis-Design –Implementation” based standard

problem solving approach for Embedded product Development.

In any product development application, we consider

1.What product needs to be developed (Analysis)

2. Good approach for building it (design)

3. To develop it ( Implementation).

EDLC is an Analysis-Design-implementation based problem solving approach for

embedded systems development.

Analysis involves understanding what product needs to be developed.

Design involves what approach to be used to build the product.

Implementation is developing the product by realizing the design.

5
2
 (P) 2348-0017

Need for EDLC :

1. EDLC is essential for understanding the scope (fesilities) and complexity of the work involved in
embedded systems development.

2. It is used for any developing embedded product.

3. EDLC defines interaction and activities among various groups of a product development phase.

Eg: Project management, system design

5
3
 (P) 2348-0017

*** Discuss about objectives of EDLC

1. The ultimate aim of any embedded product in a commercial production setup is to produce Marginal
benefit.

2. Marginal is expressed in terms of ROI ( Return On Investment).

3. The investment for product development includes initial investment, manpower, infra structure
investment etc.

EDLC has three primary objectives :

1. Ensuring high quality for products.

2. Risk minimization and Defect prevention through Management.

3. Maximize the productivity.

Ensuring high Quality for products:

Quality in any product development is Return On Investment (ROI) achieved by the product.

The expenses for developing the product are

1. Initial Investment

2. Developer recruiting.

3. Training
5
4. Infra structure requirement. 4
Risk minimization defect prevention in product development through project management

Product development “loose” or “tight” project management. (P) 2348-0017

“project management is essential for “predictability co-ordination and risk minimization.

Place the resources is critical and having a direct impact on investment.

Eg: Microsoft @ project Tool.

Maximize the productivity ;

Productivity is a measure of efficiency as well as Return On Investment (ROI).

This productivity measurement is based on total man power efficiency.

Productivity in which, when, product is increased then investment is fall down. Saving man
power.

*** Different Phases of EDLC (OR) Discuss about different

5
5
Phases of EDLC.

NEED (P) 2348-0017

Phase:
The “need” may come from individual (or) from the public (or) from a company.

“Need” should be initiate the “Development Life Cycle”

“Need “ can be visualized in any one of the 3 Needs :

1. New (or) Custom product Development.

2. Product Re-engineering

3. Product Maintenance.

Conceptualization phase:

It defines the scope of concept. It performs cost benefit analysis and prepare project
management and risk management plans & feasibility study.

Activities in conceptualization:

1. Feasibility study : Examine the need and suggest possible solutions.

2. Cost Benefit Analysis (CBA) : Revealing and assessing the total development cost and profit
expected from the product.

3. Product scope : Deals with the activities involved in the product to be made.

4. Planning Activities: It requires various plans to be developed first, before development like resource
planning & Risk management plans.

Analysis Phase :

The product is defined in detailed with respect to the inputs, processes, outputs and interfaces
at a functional level.

Activities in Analysis:

1. Analysis & Documentation: It specifies the business needs of the product under development.

2. Requirements that need to be addressed.

· Functional capabilities like performance.

· Operational & Non-operational quality attribute.

· Product external interface requirements.

· Data requirements, user manuals

· Operational requirements.

· Maintenance requirements

· General assumptions.
5
6
Defining Test plan and procedures phase :

In product development there are various types of testing is performed they are (P) 2348-0017

◊ Unit testing : Testing individual modules

◊ Integration Testing : Testing a group of modules for required functionality.

◊ System Testing : Testing functional aspects (or) functional requirements of the product after
integration.

◊ User acceptance testing : Testing the product to meet the end user requirements.

Design phase:

It identifies application environment and creates an over all architecture for the product.

§ It starts with the preliminary Design.

§ It establishes the top level architecture for the product.

§ On completion it resembles a “black box” , that defines only the inputs and outputs.

§ The final product is called preliminary Design Document (PDD)

§ After PDD the end user create the “Detailed Design”.

§ The operational manual design, maintenance manual design, product Training material Design all
together called the “Detailed Design Document”.

Development and Testing Phase:

Development means designing the particular product into hardware and software.

Testing can be divided into independent testing of software & Hardware .

v Unit testing

v Integration testing

v System testing

v User acceptance testing

Deployment Phase:

Deployment is the process of launching the first

fully functional model of the product in the market.

It is also known as first customer shipping (FCS)

Support phase:

The support deals with the operational & maintenance of the product in the production
environment.

Activities involved in support phase 5

7
 It providing 24x7 supports for the product after launching.

Identify the areas of improvement. (P) 2348-0017

Upgrades Phase:

Deals with the development of up grades (new version) for the product, which is already present
in the market.

During the upgrade phase the system is subject to design modification in major areas.

Retirement/Disposal;

The retirement/disposal of the product is a gradual process.

This phase is the final phase in a product development life cycle.

The product is declared as discontinued from the market.

The disposal of a product is essential due to

1. Increased user needs.

2. Rapid technology advancement.

*** Discuss about Trends in Embedded industry

The trends in the embedded systems

1.Processor Trends:

5
8
 There is a points of difference between the first generation of processor/controller and today’s
processor/controller. (P) 2348-0017

2. Number of IC’s per chip;

Early processors has few number of IC/gates per chip.

Today’s processors with VLSI technology can pack (together) ten of thousands of IC/gates
per processor.

3.Need for individual components:

Early processors need different components like timers, DAC/ADC separately interfaced.

Today’s processors have all these components on the same chip as the processor.

4. Speed of execution:

Early processors were slow in execution speed.

Today’s processor with advanced architecture support features like instruction pipeline,
improving the execution speed.

5.Clock Frequency:

Early processors execute at few MHz.

Today’s processors are capable of execute at GHz range.

6.Application Specific Processor:

Early systems designed available at that time.

Today it is possible according to a product requirement.

7.Major Trends in Processor architecture in Embedded development.

System On-Chip (SOC) :

This concept makes possible to integrate all functional systems required to build an embedded
product into a single chip.

SOC are now available for a wide variety of diverse applications as Media players, PDA etc.

SOC integrate multiple functional components on the same chip.

8.Multicore processors/Chip level Multi processor:

This concept specifies multiple cores on the same processor chip, operating at the same
clock frequency and battery.

Based on the number of cores :

v Dual core-2 cores

v Tri core-3cores
5
v Quad core-4 cores. 9
 Each core implements pipelining and multi threading.

9. Reconfigurable processors: (P) 2348-0017

It is a hardware feature. Depending on the requirement, re configurable processors can change

their functionality to the new requirement.

Eg: The heart of a camera, Media player.

10.Operating system Trends:

The advancements in processor technology caused a major change in the Embedded operating
System Industry.

There are lots of options for Embedded operating System to select both commercial and open
source.

Virtualization concept is used in embedded OS industry.

11. Development Language Trends:

There are two aspects to Development languages w.r.to Embedded systems Development.

i. Embedded Firmware:

It is application to responsible for execution of Embedded System.

It is the software to perform low level hardware interaction , memory management.

ii Embedded Software;

It is the software that is responsible for interfacing with the Embedded System.

It is the user application that executes on top of the Embedded system on a Host Computer.

Early languages available for Embedded systems development were limited, they are C &
C++ only.

Now ASP,▪ NET , VB, Java are available.

12. Open Standards, Frame works and Alliances:

Standards are necessary for ensuring inter operation.

Open Source Standards and frame works Specific to the mobile hand set industry.

OMA (Open Mobile Alliance) is a standard body for creating open standards for mobile
industry.

The Goal of OMA is deliver High Quality.

OHA (Open Handset Alliance) is a group of 84 technology and mobile companies.

Eg: Andriod, Openmoko.

13. Bottlenecks faced by Embedded industry

6
Memory performance 0
The rate at which processors can process their memory speed increasing.

Lack of Standards/conformance to Standards (P) 2348-0017

Lack of skilled Resource.

6
1
 (P) 2348-0017

Issues in Hardware/Software Co-Design

INTRODUCTION
Most engineering designs can be viewed as systems, i.e., as collections of several components whose
combined operation provides useful services. Components can be heterogeneous in nature and their
interaction may be regulated by some simple or complex means. Most examples of systems today are
either electronic in nature (e.g., information
processing systems) or contain an electronic
subsystem for monitoring and control (e.g., plant
control) [1]. Any system can be partitioned in to data
unit and control unit. The data unit performs different
operations on data elements like addition, subtraction
etc. The control unit controls the operations of data
unit by using control signals. The block diagram of a
general system is shown in Fig.1.
Fig.1: Block Diagram of a General System

The total design of data and control units can be done by using Software only, Hardware only or
Hardware/Software Co design methodologies. The selection of design methodology can be done by
using different non functional constraints like area, speed, power, cost etc. The software design
methodology can be selected for the systems with specifications as less timing related issues and less
area constraints. Using the software design system less area and low speed systems can be designed.
To design a system with high speed, timing issues 6 need to be considered. The hardware design
2
methodology is one solution to design high speed systems with more area compared to software
designs. Because of present SoC designs, systems with high speed, less area, portability, low power
(P) 2348-0017
have created the need of combining the hardware and software design methodologies called as
Hardware/Software Co-Design. The co-design can be defined as the process of designing and
integrating different components on to a single IC or a system. The components can be a hardware
component like ASIC, software component like microprocessor, microcontroller, electrical
component or a mechanical component etc.

6
3
The Software design methodology for a microprocessor with design flow is explained in section II
and the hardware design methodology for an FPGA with design flow is explained in section III. The
Hardware/Software Co-Design methodology issues are explained by using design flow in section IV
then conclusion and references.
SOFTWARE DESIGN METHODOLOGY
In general the design of a system with software based needs a design entry as
programming language like c, c++ etc. The design flow is shown in Fig.2.

In this methodology the constraints are with respect to area but not speed.
The system design information can be specified by using user requirements to
the system designer. The user requirements are verified according to the
target board (like processor), area, speed and other non functional constraints.
If the user requirements satisfy existing elements then the design will move
forward, otherwise user has to refine the requirements. General programming
languages like c, c++ etc can be used as the design entry and compilation will
be done to check the functionality is with respect to specifications or not.
Finally hex file or bit file is generated according to the target device.
Fig.2: Software Based Design Flow

The advantage of this design process is easy to design and implement with less area but timing issues
and speed cannot be improved. The timing issues and speed can be considered by using the hardware
based design methodology.
HARDWARE DESIGN METHODOLOGY

The systems with hardware components considering timing can be designed by using a programmable
devices like PLA, PAL, PGA, FPGA or a non programmable device like ASIC. The systems behavior
can be expressed by using a Hardware Description Language like Verilog HDL, VHDL etc. instead of
a programming language. These HDL languages describe the timing behavior of the hardware
elements. The design flow for an FPGA is shown in Fig.3.

The system design starts with the refined

specifications. The specifications are converted
into architecture. The architecture functionality
is expressed by using Hardware Description
Langue (HDL) like VHDL or Verilog HDL.
The functionality can be verified by using
simulation with the help of test bench. After
the functional verification the design can be
converted into gate level structural
interconnected form called as net list with the
help of synthesis. The synthesized net list will
be placed and routed on the selected target
FPGA board. A bit file will be generated to
load the designed system on to the target
FPGA.
Fig.3: FPGA Design Flow

2
 The advantage of hardware based design methodology is the timing information can be specified by
using HDL and high speed systems can be designed compared to software based methods.

HARDWARE/SOFTWARE CO-DESIGN METHODOLOGY

The systems with less area and simple elements can

be designed by using software and the systems with
timing/speed can be designed by using hardware.
Because of portability, battery based designs;
System on Chip concepts, low power high speed
issues there is a need to integrate hardware and
software components together. The integration of
hardware and software components together is
called as co-design. Designing of a co-design
system needs a generic co-design methodology. The
generic co-design flow is shown in below Fig.4.

The generic co-design flow for hardware software

co-design system consists of the following steps.

A. Specifications
The specifications can be refined from the user
requirements such that the target system can fit into
any one of the available hardware component or
software element. This caring of specifications is
not available in the HW or SW design
methodologies. Because of the HW/SW elements in
the target system specifications must be properly
selected.
Fig 4: Generic Co-Design Flow
B. Design Entry

The specifications can be expressed by using different types of models, languages etc. One best
method of design entry is combining some programming language features with hardware description
language features or vice versa. This combination of different languages leads to a new co-design
language. The design entry can be selected based on the following criteria.

If the specifications can not be partitioned /separated into hardware blocks or software blocks
then use this co-design language.
The languages can be combined based on the performance criteria i.e. primal approach or dual
approach.
The number of registers of the target processor is also a constraint in the language selection.
The language selection can be based on target compiler availability also.
Some of the co-design specification languages are like LOTOS, SDL, and HardwareC etc.

3
C. Co-Simulation

The system functionality of a hardware system can be verified by simulation; software system can be
verified by using compilation. But functionality of a system with both hardware and software parts
can not be verified by using simulation or compilation. This is due to the following reasons.

The system feature with HDL language elements can not be verified by using compilation.
The system feature with programming language can not be verified by using simulation.
The present available compilers can not be used for the verification because of register
widths, processor capacity and new features because of multiple systems integration.
Hence, to verify the HW/SW co-design system functionality a new tool called as co-simulation is
required. The design of a co-simulator is also a complex process. After the co simulation, the design
can be applied to HW/SW portioning block.

D. HW/SW Partitioning

After the co simulation of the system some of the elements can be portioned into hardware/software
elements. This partitioning consists of following three portions to avoid functionality mismatch.

Hardware Part
Software Part
Communication Synthesis
The system is partitioned into hardware part which consists of hardware elements and software part
which consists of software elements. The integration of these hardware and software parts to maintain
the functionality can be done by using communication synthesis.

E. Hardware Part
The hardware part consists of hardware specifications that can be observed from the given system
specifications. The hardware specifications can be converted into hardware elements by using
synthesis, placement and routing. This process is similar to normal hardware design methodology.

F. Software Part

The software part consists of software specifications that can be observed from the given system
specifications. The software specifications can be mapped to software elements by using compilation,
software implementation model with respect to the target processor. This process is similar to normal
software design methodology.

G. Communication Synthesis

The communication synthesis acts as a controller in between hardware part and software part. This block
integrates the signals of both hardware and software parts to avoid functionality mismatches. The design of
communication synthesis is complex because of communication between different blocks.

H. HW/SW System

The total system can be designed by generating the final bit file for the entire hardware block,
software block and communication synthesis blocks etc. This block generates combined bit file for the
entire system for the given specifications.

4
 The hardware software co design based system can be designed by using the partitioning of hardware and software
resources using partitioning techniques. After the partitioning the design uses hardware flow and software flows for
the concerned steps and at the end these two blocks are communicated to complete the total system. The
partitioning of the co design system is done based on the optimization goal. The optimization goals can be
approach.area, speed, power etc. Two major approaches are used for partitioning, i.e. Primal approach and Dual

PROGRAM MODELS

MODELLING OF EDLC: (EDLC APPROACHES)

The various approaches in modelling the EDLC are:

Linear or water fall model:

In this model, each phase of EDLC is executed in sequence and the flow is unidirectional with
output of one phase serving as the input to the next phase. The feedback of each pulse is available
locally and only after they are executed.
  Review mechanisms are employed to ensure that the process flow in right
direction.
 Bugs are not fixed immediately and they are postponed to support phase.
Advantages:
 Rich documentation

 Easy project management

 Good control over cost & schedule

Drawbacks:
 Analysis can be done without any design
 Risk analysis is performed only once throughout the development
 Bugs are fixed only at support phase

Iterative / Incremental / Fountain EDLC Model:

The iterative model can be viewed as a cascaded series of linear models.
Do some analysis, follow some design, the some implementation, evaluate it and based on
short comings, cycle back through and conduct more analysis, opt for new design and implementation.
Repeat the cycles until the requirements are met.

52
 The incremental model is a superset of iterative model where the requirementsare known at
the beginning.

Fig: Fountain model

Advantages:
 Feedback is at each function. So each cycle can act as a maintenance phase for
previous cycle
 Risk is spread across each individual cycle and can be minimized easily Project

 management as well as testing is much simpler to the linear model

 Product development can be stopped at any stage

Drawbacks:
 Extensive review requirement at each cycle
 Training is required for each new deployment at the end of each development cycle.

Prototyping / Evolutionary Model:

 This model is similar to the iterative model and the product is developed in multiple
cycles
 The only difference is the model produces more refined prototype of the product at
each cycle instead of just adding the functionality at each cycle like in interval model

53
  The short comings of the protomodel after each cycle are evaluated and it isfixed
in the next cycle
 After the initial requirement analysis, design is made and development process is
started. Then this prototype is sent to the customer for evaluation. The customer
provides the feedback to the developer for further improvement.

 Then the developer repeat the process with some additional features and finally
delivered to the outside world
Advantages:

 Feedback after each implementation and fire tuning is also possible

 By using the prototype model, the risk is spread across each proto developmentcycle
& it is under control
Drawbacks:

 Deviations from expected cost and schedule due to requirements refinement.

 Increased project management
prototype traceability
 Minimal documentation on each prototype may create problems in backward
 Increased configuration management activities

Spiral Model:
 Spiral model is best suited for the development of complex embedded products &
situations where the requirements are changing from customer side
 Risk evaluation in each stage helps in reducing risk
54
  Spiral model is best suited for the development of complex embedded products &
situations where the requirements are changing from customer side
 Risk evaluation in each stage helps in reducing risk

 It is the combination of linear & prototype models to give the best possible risk
minimized EDLC model. The activities in the spiral model present in the 4
quadrants are:

o Determine objectives, alternatives, constraints

o Evaluate alternatives, identity & resolve risks
o Develop & test
o Plan
4. What are the fundamental issues in Hardware-Software co-design?
Co design

The meeting of system-level objectives by exploiting the trade-offs between hardwareand

software in a system through their concurrent design

o Key concepts hardware and software developed at the same time on parallel
Concurrent:
paths
o Integrated: interaction between hardware and software developments to
produce designs that meet performance criteria and functional specifications Fundamental
issues:
The problem statement is hardware software co-design and its issues. Some of theissues are:

Selecting the model:

 A model is a formal system consisting of objects & composition rules. It is hard tomake
a decision on which model should be followed in a particular system design
 Models are used for capturing & describing the system characteristics
55
  Designers switch between a variety of models, because the objective varies with each
phase

Selecting the architecture:

The architecture specifies how a system is going to implement in terms of the number & types of
different components and the interconnection among them. Some type of architecture falls into
application specific architecture class, while others fall into either general purpose architecture class or
parallel processing class. The commonly used architectures is system design are:
1. The controller Architecture – implements the finite state machine model using a state register holds
the present state and the combinational circuits holds the next state & output
2. The data path architecture – suitable for implementing the data flow graph model.
A datapath represents a channel between the input and output. The datapath contains
registers, counters, memories & ports. Ports connect the datapath to multiple buses.

3. The finite state machine datapath – this architecture combines the controller
architecture with datapath architecture. The controller generates the control input,
whereas the datapath processes the data.
4. The complex instruction set computing (CISC) – this architecture uses an instruction set
for solving complex operations. The use of a single complex instruction in place of multiple
simple instructions greatly reduces the program memory access & program memory size
requirement. On the other hand, Reduced Instruction Set Computing (RISC) architecture uses
the multiple RISC instructions to perform a complex operation. RISC architecture supports
extensive pipelining
units in the datapath
5. The Very Long Instruction Word (VLIW) – this architecture implements functional
6. Parallel processing architecture – implements multiple concurrent processing elements and each
processing element may associate a datapath containing register & local memory. Single Instruction
Multiple Data (SIMD) & Multiple Instruction Multiple Data (MIMD) architectures are examples for
parallel processing architecture. SIMD – eg: Reconfigurable process, MIMD – eg: Multiprocessor
systems

Selecting the language:

A programming language captures a ‗Computational Model‘ and maps it into architecture. A model can
be captured using multiple programming languages like C, C++, C#, Java, etc. for software
implementations and languages like VHOL, system C,

56
 verilog, etc. for hardware implementations. C++ is a good language for capturing anobject oriented
model.

Partitioning system requirements into hardware &

software:
Various hardware software trade-offs are used for making a decision on thehardware-software
portioning.

5. Discuss about the various computational

models in embedded design.
COMPUTATIONAL MODELS IN
EMBEDDED DESIGN
The commonly used computational models in embedded system design are

(i) Data flow graph model(DFG):

This model translates the data processing requirement into a data flow graph. It is adata model. This
model emphasis on the data and operations on the data which
transforms the Input data to output data. In DFG model, Data is represented by a circledata
flow is represented arrows.An inward arrow to the process denotes the output

data. Data driven Embedded are modeled using DFG.

A DFG model is said to be either acyclic DFG (does not contain multiple input values &
multiple output values) or non-acyclic DFG (output is feedback to the input).

(ii) State machine model:

The state machine model explains the system behaviours with states, events, actions and transitions. The
representation of a state is current situation. An event is an input to the state. The event acts as stimulus
for state transition. The activity evolved in state machine is action. This model is used for event driven
embedded systems. Eg: control and industrial applications.
A Finite State Machine (FSM) model is one in which the number of states are finite. Consider the FSM
model for automatic seat belt warning system as an example.
Motor control software design is another example for state machine model.

(iii) Sequential Program Model:

The functions are executed in a sequential order, which is same as the conventional procedural
programming. The program instructions are iterated and executed with condition and the data gets
transformed through a series of operations. The tools for sequential program model are FSM &
flowcharts. Consider an example ‗Seat Belt warning system‘ programming.

# define ON 1 #
define OFF 0#
define YES 1#
define NO 0
Void seatbelt_caution ()
{
Waiting ( );
If (checkIgnition ( ) = = ON)
{
If (checkseat belt ( ) = = OFF)
{

58
 SetTimes (3); Start
Alarm ( );
While ((check seat belt ( ) = = OFF) && (check Ignition ( ) = = OFF) &&(Timer Expire ( )
= = NO));
Stop Alarm ( );
}
}
}

Flow chart Approach:

(iv) Concurrent Process model:

This model executes the processes concurrently. It is easier to implement than the
conventional sequential execution. Sequential execution leads to poor processor utilization. Concurrent
processing model requires additional overheads in task scheduling, task synchronization and
communication. Now consider the example of seat belt warning system in concurrent processing model.
We can split the tasks into:
1. Timer task for waiting 10 seconds
2. Task for checking the ignition key status
3. Task for checking the seat belt status
4. Task for starting & stopping the alarm
5. Alarm timer task for waiting 3 seconds
These tasks are needed to synchronize.

59
Figure: Concurrent Processing program model for seat belt warning system.

The concurrent processing model is commonly used for the modeling of real timesystem.
(v) Object – oriented model:
 It is an object based model
 It splits the complex software requirement into well defined pieces called objects
 It brings re-usability, maintainability & productivity in system design
 Each object is characterized by a set of unique behavior & state. A class is anabstract of a
set of objects.
 A class represents the state of an object through member variables and object

behavior through member functions.

 The member variables can be public, private or protected
 Private member access within the class and public member access within theclass
as well as outside the class.
 The concept of object & class brings abstraction, holding and protection.
 UNIT IV
Real Time Operating System (RTOS)
Real-time operating systems (RTOS) are used in environments where a large number of events,
mostly external to the computer system, must be accepted and processed in a short time or within
certain deadlines. such applications are industrial control, telephone switching equipment, flight
control, and real-time simulations. With an RTOS, the processing time is measured in tenths of
seconds. This system is time-bound and has a fixed deadline. The processing in this type of system
must occur within the specified constraints. Otherwise, This will lead to system failure.
Examples of the real-time operating systems: Airline traffic control systems, Command Control
Systems, Airlines reservation system, Heart Pacemaker, Network Multimedia Systems, Robot etc.
The real-time operating systems can be of 3 types –

1. Hard Real-Time operating system:

These operating systems guarantee that critical tasks be completed within a range of time.
For example, a robot is hired to weld a car body. If the robot welds too early or too late, the car
cannot be sold, so it is a hard real-time system that requires complete car welding by robot hardly
on the time.

2. Soft real-time operating system:

This operating system provides some relaxation in the time limit.
For example – Multimedia systems, digital audio systems etc. Explicit, programmer-defined and
controlled processes are encountered in real-time systems. A separate process is changed with
handling a single external event. The process is activated upon occurrence of the related event
signalled by an interrupt.
Multitasking operation is accomplished by scheduling processes for execution independently of
each other. Each process is assigned a certain level of priority that corresponds to the relative
importance of the event that it services. The processor is allocated to the highest priority
processes. This type of schedule, called, priority-based preemptive scheduling is used by real-time
 systems.

3. Firm Real-time Operating System:

RTOS of this type have to follow deadlines as well. In spite of its small impact, missing a deadline
can have unintended consequences, including a reduction in the quality of the product. Example:
Multimedia applications.

Advantages:
The advantages of real-time operating systems are as follows-
1. Maximum consumption –
Maximum utilization of devices and systems. Thus more output from all the resources.

2. Task Shifting –
Time assigned for shifting tasks in these systems is very less. For example, in older systems, it
takes about 10 microseconds. Shifting one task to another and in the latest systems, it takes 3
microseconds.

3. Focus On Application –
Focus on running applications and less importance to applications that are in the queue.

4. Real-Time Operating System In Embedded System –

Since the size of programs is small, RTOS can also be embedded systems like in transport and
others.

5. Error Free –
These types of systems are error-free.

6. Memory Allocation –
Memory allocation is best managed in these types of systems.
Disadvantages:
The disadvantages of real-time operating systems are as follows-

1. Limited Tasks –
Very few tasks run simultaneously, and their concentration is very less on few applications to
avoid errors.

2. Use Heavy System Resources –

Sometimes the system resources are not so good and they are expensive as well.
3. Complex Algorithms –
The algorithms are very complex and difficult for the designer to write on.

4. Device Driver And Interrupt signals –

It needs specific device drivers and interrupts signals to respond earliest to interrupts.

5. Thread Priority –
It is not good to set thread priority as these systems are very less prone to switching tasks.

6. Minimum Switching – RTOS performs minimal task switching.

Real Time Systems

A real-time system means that the system is subjected to real-time, i.e., the response should be
guaranteed within a specified timing constraint or the system should meet the specified deadline. For
example flight control systems, real-time monitors, etc.

Types of real-time systems based on timing constraints:

1. Hard real-time system: This type of system can never miss its deadline. Missing the deadline
may have disastrous consequences. The usefulness of results produced by a hard real-time system
decreases abruptly and may become negative if tardiness increases. Tardiness means how late a
real-time system completes its task with respect to its deadline. Example: Flight controller
system.
2. Soft real-time system: This type of system can miss its deadline occasionally with some
acceptably low probability. Missing the deadline have no disastrous consequences. The usefulness
of results produced by a soft real-time system decreases gradually with an increase in tardiness.
Example: Telephone switches.

Reference model of the real-time system:

Our reference model is characterized by three elements:

1. A workload model: It specifies the application supported by the system.
2. A resource model: It specifies the resources available to the application.
3. Algorithms: It specifies how the application system will use resources.

Terms related to real-time system:

1. Job: A job is a small piece of work that can be assigned to a processor and may or may not
require resources.
2. Task: A set of related jobs that jointly provide some system functionality.
3. Release time of a job: It is the time at which the job becomes ready for execution.
4. Execution time of a job: It is the time taken by the job to finish its execution.
5. Deadline of a job: It is the time by which a job should finish its execution. Deadline is of two
types: absolute deadline and relative deadline.
6. Response time of a job: It is the length of time from the release time of a job to the instant
when it finishes.
7. The maximum allowable response time of a job is called its relative deadline.
8. The absolute deadline of a job is equal to its relative deadline plus its release time.
9. Processors are also known as active resources. They are essential for the execution of a job. A
job must have one or more processors in order to execute and proceed towards completion.
Example: computer, transmission links.
10. Resources are also known as passive resources. A job may or may not require a resource
during its execution. Example: memory, mutex
11. Two resources are identical if they can be used interchangeably else they are heterogeneous.

Difference between Multiprogramming,

multitasking, multithreading and multiprocessing
1. Multiprogramming – A computer running more than one program at a time (like running
Excel and Firefox simultaneously).
2. Multiprocessing – A computer using more than one CPU at a time.
3. Multitasking – Tasks sharing a common resource (like 1 CPU).
4. Multithreading is an extension of multitasking.
1. Multi programming –
In a modern computing system, there are usually several concurrent application processes which want
to execute. Now it is the responsibility of the Operating System to manage all the processes
effectively and efficiently.
One of the most important aspects of an Operating System is to multi program.
In a computer system, there are multiple processes waiting to be executed, i.e. they are waiting when
the CPU will be allocated to them and they begin their execution. These processes are also known as
jobs. Now the main memory is too small to accommodate all of these processes or jobs into it. Thus,
these processes are initially kept in an area called job pool. This job pool consists of all those
processes awaiting allocation of main memory and CPU.
CPU selects one job out of all these waiting jobs, brings it from the job pool to main memory and
starts executing it. The processor executes one job until it is interrupted by some external factor or it
goes for an I/O task.

Non-multi programmed system’s working –

 In a non multi programmed system, As soon as one job leaves the CPU and goes for some
other task (say I/O ), the CPU becomes idle. The CPU keeps waiting and waiting until this job
(which was executing earlier) comes back and resumes its execution with the CPU. So CPU
remains free for all this while.
 Now it has a drawback that the CPU remains idle for a very long period of time. Also, other
jobs which are waiting to be executed might not get a chance to execute because the CPU is still
allocated to the earlier job.
This poses a very serious problem that even though other jobs are ready to execute, CPU is not
allocated to them as the CPU is allocated to a job which is not even utilizing it (as it is busy in I/O
tasks).
 It cannot happen that one job is using the CPU for say 1 hour while the others have been
waiting in the queue for 5 hours. To avoid situations like this and come up with efficient
utilization of CPU, the concept of multi programming came up.
The main idea of multi programming is to maximize the CPU time.
Multi programmed system’s working –
 In a multi-programmed system, as soon as one job goes for an I/O task, the Operating System
interrupts that job, chooses another job from the job pool (waiting queue), gives CPU to this new
job and starts its execution. The previous job keeps doing its I/O operation while this new job does
CPU bound tasks. Now say the second job also goes for an I/O task, the CPU chooses a third job
and starts executing it. As soon as a job completes its I/O operation and comes back for CPU
tasks, the CPU is allocated to it.
 In this way, no CPU time is wasted by the system waiting for the I/O task to be completed.
Therefore, the ultimate goal of multi programming is to keep the CPU busy as long as there are
processes ready to execute. This way, multiple programs can be executed on a single processor by
executing a part of a program at one time, a part of another program after this, then a part of
another program and so on, hence executing multiple programs. Hence, the CPU never remains
idle.
In the image below, program A runs for some time and then goes to waiting state. In the mean time
program B begins its execution. So the CPU does not waste its resources and gives program B an
opportunity to run.
2. Multiprocessing –
In a uni-processor system, only one process executes at a time.
Multiprocessing is the use of two or more CPUs (processors) within a single Computer system. The
term also refers to the ability of a system to support more than one processor within a single computer
system. Now since there are multiple processors available, multiple processes can be executed at a
time. These multi processors share the computer bus, sometimes the clock, memory and peripheral
devices also.

Multi processing system’s working –

 With the help of multiprocessing, many processes can be executed simultaneously. Say
processes P1, P2, P3 and P4 are waiting for execution. Now in a single processor system, firstly
one process will execute, then the other, then the other and so on.
 But with multiprocessing, each process can be assigned to a different processor for its
execution. If its a dual-core processor (2 processors), two processes can be executed
 simultaneously and thus will be two times faster, similarly a quad core processor will be four
times as fast as a single processor.
Why use multi processing –
 The main advantage of multiprocessor system is to get more work done in a shorter period of
time. These types of systems are used when very high speed is required to process a large volume
of data. Multi processing systems can save money in comparison to single processor systems
because the processors can share peripherals and power supplies.
 It also provides increased reliability in the sense that if one processor fails, the work does not
halt, it only slows down. e.g. if we have 10 processors and 1 fails, then the work does not halt,
rather the remaining 9 processors can share the work of the 10th processor. Thus the whole system
runs only 10 percent slower, rather than failing altogether.

Multiprocessing refers to the hardware (i.e., the CPU units) rather than the software (i.e., running
processes). If the underlying hardware provides more than one processor then that is multiprocessing.
It is the ability of the system to leverage multiple processors’ computing power.
Difference between Multi programming and Multi processing –
 A System can be both multi programmed by having multiple programs running at the same
time and multiprocessing by having more than one physical processor. The difference between
multiprocessing and multi programming is that Multiprocessing is basically executing multiple
processes at the same time on multiple processors, whereas multi programming is keeping several
programs in main memory and executing them concurrently using a single CPU only.
 Multiprocessing occurs by means of parallel processing whereas Multi programming occurs by
switching from one process to other (phenomenon called as context switching).
3. Multitasking –
As the name itself suggests, multi tasking refers to execution of multiple tasks (say processes,
programs, threads etc.) at a time. In the modern operating systems, we are able to play MP3 music,
edit documents in Microsoft Word, surf the Google Chrome all simultaneously, this is accomplished
by means of multi tasking.

Multitasking is a logical extension of multi programming. The major way in which multitasking
differs from multi programming is that multi programming works solely on the concept of context
switching whereas multitasking is based on time sharing alongside the concept of context switching.

Multi tasking system’s working –

 In a time sharing system, each process is assigned some specific quantum of time for which a
process is meant to execute. Say there are 4 processes P1, P2, P3, P4 ready to execute. So each of
them are assigned some time quantum for which they will execute e.g time quantum of 5
nanoseconds (5 ns). As one process begins execution (say P2), it executes for that quantum of
time (5 ns). After 5 ns the CPU starts the execution of the other process (say P3) for the specified
quantum of time.
 Thus the CPU makes the processes to share time slices between them and execute accordingly.
As soon as time quantum of one process expires, another process begins its execution.
 Here also basically a context switch is occurring but it is occurring so fast that the user is able
to interact with each program separately while it is running. This way, the user is given the
illusion that multiple processes/ tasks are executing simultaneously. But actually only one process/
task is executing at a particular instant of time. In multitasking, time sharing is best manifested
because each running process takes only a fair quantum of the CPU time.
In a more general sense, multitasking refers to having multiple programs, processes, tasks, threads
running at the same time. This term is used in modern operating systems when multiple tasks share a
common processing resource (e.g., CPU and Memory).
 As depicted in the above image, At any time the CPU is executing only one task while other
tasks are waiting for their turn. The illusion of parallelism is achieved when the CPU is reassigned
to another task. i.e all the three tasks A, B and C are appearing to occur simultaneously because of
time sharing.
 So for multitasking to take place, firstly there should be multiprogramming i.e. presence of
multiple programs ready for execution. And secondly the concept of time sharing.
4. Multi threading –
A thread is a basic unit of CPU utilization. Multi threading is an execution model that allows a single
process to have multiple code segments (i.e., threads) running concurrently within the “context” of
that process.
e.g. VLC media player, where one thread is used for opening the VLC media player, one thread for
playing a particular song and another thread for adding new songs to the playlist.
Multi threading is the ability of a process to manage its use by more than one user at a time and to
manage multiple requests by the same user without having to have multiple copies of the program.

Multi threading system’s working –

Example 1 –
 Say there is a web server which processes client requests. Now if it executes as a single
threaded process, then it will not be able to process multiple requests at a time. Firstly one client
will make its request and finish its execution and only then, the server will be able to process
another client request. This is really costly, time consuming and tiring task. To avoid this, multi
threading can be made use of.
 Now, whenever a new client request comes in, the web server simply creates a new thread for
processing this request and resumes its execution to hear more client requests. So the web server
has the task of listening to new client requests and creating threads for each individual request.
Each newly created thread processes one client request, thus reducing the burden on web server.
Example 2 –
 We can think of threads as child processes that share the parent process resources but execute
independently. Now take the case of a GUI. Say we are performing a calculation on the GUI
(which is taking very long time to finish). Now we can not interact with the rest of the GUI until
this command finishes its execution. To be able to interact with the rest of the GUI, this command
of calculation should be assigned to a separate thread. So at this point of time, 2 threads will be
executing i.e. one for calculation, and one for the rest of the GUI. Hence here in a single process,
we used multiple threads for multiple functionality.
The image below completely describes the VLC player example:
Advantages of Multi threading –
 Benefits of Multi threading include increased responsiveness. Since there are multiple threads
in a program, so if one thread is taking too long to execute or if it gets blocked, the rest of the
threads keep executing without any problem. Thus the whole program remains responsive to the
user by means of remaining threads.
 Another advantage of multi threading is that it is less costly. Creating brand new processes and
allocating resources is a time consuming task, but since threads share resources of the parent
process, creating threads and switching between them is comparatively easy. Hence multi
threading is the need of modern Operating Systems.

1. Discuss deeply about the pre-emptive & non –pre-emptive

scheduling with suitable diagrams.

NON – PREEMPTIVE SCHEDULING:

Non- Preemptive scheduling is employed in non-preemptive multitasking systems. In this scheduling

type, the currently executing task/process is allowed to run until it terminates or enters the wait state
waiting for an I/O or system resource. The various types of non-preemptive scheduling algorithms are,
62
 1. First Come First Served (FCFS)
FCFS also known as first in first out (FIFO) is the simplest scheduling policy. Arriving jobs are
inserted into the tail (rear) of the ready queue and process to be executed next is removed from the head
(front) of the queue.
FCFS performs better for long jobs. Relative importance of jobs measured onlyby arrival time.
A long CPU bound job may hog the CPU and may force shorter jobs to wait prolonged periods. This in
turn may lead to a lengthy queue of ready jobs and hence to the convoy effect.
Turnaround Time = Waiting Time + Service Time

Advantages:
1. Better for long process

2. Simple method

3. No starvation
Disadvantages:
1. Convoy effect occurs. Even very small process should wait for its turn to come to
utilize the CPU. Short process behind long process results in lower CPU utilization.
2. Throughput is not emphasized.
2. Shortest Job First Scheduling (SJF):
This algorithm associated with each process the length of the next CPU burst. Shortest job first
scheduling is also called shortest process next (SPN). The process with the shortest expected processing
time is selected for execution among the available process in the ready queue. Thus, a short process will
jump to the head of the queue over long jobs.
If the next CPU bursts of two processes are the same then FCFS scheduling is cued to break the tie. SJF
scheduling algorithm is probably optimal. It gives the minimum average time for a given set of processes.
It cannot be implemented at the level of short

63
 term CPU scheduling. There is no way of knowing the shortest CPU burst. SJF can be preemptive or non-
preemptive.
A preemptive SJF algorithm will preempt the currently executing process, if the next CPU burst of
newly arrived process may be shorter than what is left to the currently executing process.
A non-preemptive SJF algorithm will allow the currently running process to finish. Preemptive SJF
scheduling is sometimes called shortest remaining time first algorithm.

Advantages:
1. It gives superior turnaround time performance to shortest process next because
a short job is given immediate preference to a running longer job.

2. Throughput is high.

Disadvantages:

1. Elapsed time must be recorded, it results an additional overhead on theprocessor.

2. Starvation may be possible for the longer processes.
PRE-EMPTIVE SCHEDULING:

In preemptive mode, currently running process may be interrupted and forces the currently active
process to release the CPU on certain events such as a clock interrupt, some I/O interrupts or a system call
and they moved to the ready state by the OS.
When a new process arrives or when a interrupt occurs, preemptive policies may incur greater
overhead than non-preemptive version but preemptive version may provide better results.
It is desirable to maximize CPU utilization and throughput and to minimize turnaround time,
waiting time and response time.
The various types of pre-emptive scheduling are
1. Priority – Based Scheduling:

64
 Each process is assigned a priority. The ready list contains an entry for each process ordered by
its priority. The process at the beginning of the list (highest priority)is picked first.
A variation of this scheme allows preemption of the current process when a higher priority
process arrives.
Another variation of the policy adds an aging scheme, whether the priority of a process increases
as it remains in the ready queue. Hence, this will eventually execute to completion.
If the equal priority process is in running state, after the completion of the present running
process CPU is allocated to this, even though one more equal priority processis to arrive.

Advantage:

Very good response for the highest priority process over non-pre-emptive versionof it.

Disadvantage:

Starvation may be possible for the lowest priority processes.

2. Write about the interrupt routines in RTOS.

Interrupts is a mechanism for alleviating the delay caused by uncertainty and for maximizing system
performance.

Interrupt Mechanism
Instead of polling the device or entering a wait state, the CPU continuously executing its
instruction and performing useful work.
When the I/O device is ready to transfer data, it sends an interrupt request to the CPU.
This is done via a dedicated signal on the control bus.

65
Scenario of Interrupt service Routine in RTOS:
Embedded application running on top of real time operating systems require Interrupt Service
Routines (ISRs) to handle interrupt generated by external event. External events can be caused by just
about anything, form an asynchronous character arrival on a UART to a periodic timer interrupt.
ISRs have the responsibility of acknowledging the hardware condition and provide the initial
handling of data sent or received as required by the interrupt.
An ISR often is responsible for providing the RTOS with information necessary to provide services to
application threads. Examples include moving data into a buffer for processing, adding an entry to a
queue for processing, setting a value to indicate that an event has occurred and so on.
Since application code execution is interrupted during the execution of an ISR, most application
minimize the amount of code in the ISR and rely instead on non- ISR code (Thread or Task) to
complete the processing. This allows the highest priority application code to be executed as
quickly as possible and delayed as little as possible, even in situations with intense interrupt activity.
Interrupt Routines in RTOS Environment and Handling of Interrupt source calls:

ISRS have the higher priorities over the RTOS function and the tasks. So

ISR should not wait for a semaphore, mailbox, message or queue message.
An ISR should not also wait for mutex else it has to wait for othercritical
section code to finish before the critical codes in the ISR can run.
Only the IPC accept function for these events can be used, not the postfunction.
There are 3 alternative systems for the RTOS is to respond to the
hardware source calls from the interrupts.
1. Direct call to an ISR by an interrupting source and ISR sending an
ISR Enter message:
On an interrupt, the process running at the CPU is interrupted and the
ISR corresponding to that source starts executing (1).

66
 A hardware source calls an ISR directly. The ISR just sends an ISR enter message to the RTOS.
ISR enter message is to inform the RTOS than an ISR has taken control of the CPU (2).

The case involves the two function such as ISR and OS function in two memory block.
ISR code can send into a mailbox or message queue(3), but the task waiting for a
mailbox or message queue does not start before the return from the ISR (4).
When ISR finishes, it sends Exit message to OS.
On return from ISR by retrieving saved context, the RTOS later on returns to the interrupted
process or reschedules the process.
RTOS action depends on the event messages, whether the task waiting for the event messages
from the ISR is a task of higher priority than the interrupted task on the interrupt.
The special ISR semaphore used in this case is OSISRSemPost ( ) which
executes the ISR. OS ensures that OSISRSemPost is returned after any system call

from the ISR.

2. RTOS first interrupting on an interrupt, then RTOS calling
thecorresponding ISR:
On interrupt of a task, say, Nth task, the RTOS first gets itself the hardware source call (1) and
initiates the corresponding ISR after saving the present processor status (2).
Then the ISR (3) during execution then can post one or more outputs (4) for the events and
messages into the mail boxes or queues.

67
 Figure: System 2 (Three memory
blocks)
This case involves the one ISR function (ISR k) and two processes (OS and pth task) in three memory
blocks other than the interrupted Nth task.
When the interrupt source k is interrupted (1), OS finishes the critical code till the
pre emption point and calls the ISR routine for interrupt k called as ISRk (3) after saving the context of a
previous task N onto a stack (2)
After executing the ISRk routine, the ISR in step (4) can post the event ormessage to the OS for
initiating the Nth or P th task after the return (5) from the ISR and after retrieving the Nth or Pth task
context.
The OS initiates the Nth or Pth task based upon their priorities.
The ISR must be short and it must put post the messages for another task.
3. RTOS First Interrupting on an Interrupt, then RTOS initiating the ISR and
then an ISR:

The two levels of ISR in RTOSes are Fast Level ISR (FLISR) and Slow Level ISR (SLISR).
FLISR is also called as hardware interrupt ISR and SLISR is also called as software interrupt ISR. FLISR
is just the ISR in RTOS and SLISR is called as Interrupt
Service Thread (IST).

FLISR reduces the interrupt latency and jitter for an interrupt service. A kth IST is a thread to
service an kth interrupt source call. An IST function is referred as deferred procedure call of the ISR.
68
 When an interrupt source k is interrupted (1), OS finishes the critical code till thepre emption
point and calls the ISR routine for interrupt k called as ISRk (3) after saving
the context of a previous task N onto a stack (2)

The ISR during execution can send one or more outputs for the events and messages
into the mailboxes or queues for the ISTs (4). The IST executes the device and platform
independent code.

The ISR just before the end enables further pre-emption from the same or other
hardware sources (5). The ISR can post messages into the FIFO for the ISTs after recognizing the
interrupt source and its priority. The ISTs in the FIFO that have received the messages from the
ISR executes (6) as per their priorities on return (5) from the ISR.

The ISR has the highest priority and preempts all pending ISTs and tasks, when

no ISR or IST is pending execution in the FIFO, the interrupted task runs on return (7).

3) Write brief notes on i) Process ii) Threads iii) Tasks

i) PROCESS
Defn: Process is defined as a computational unit that processes on a CPU and whose state changes under
the control of kernel of an OS. It has a state ,which at an instance defines by the process status(running,
blocked or finished),process structure –its data, objects and resources and process control block.
A process runs on scheduling by OS (kernel) which gives the control of CPU to the process.
Process runs instructions and the continuous changes of its state take place as the Program counter
changes.

69
 Fig: Processes
Process control block

PCB is a data structure having the information using which the OS controls the process state. The PCB
stores in the protected memory addresses at kernel.The PCB consists of the following information about
the process state.
1. Process ID,process priority,parent process,child process and address to the next process PCB
which will run next.
2. Allocated program memory address blocks in physical memory and in secondary
memory for the process codes.
3. Allocated process-specific data address blocks.
4. Allocated process heap addresses.
5. Allocated process stack addresses for the functions called during running of theprocess.
6. Allocated addresses of the CPU register
7. Process-stae sugnal mask.
8. Signals dispatch table
9. OS-allocated resources descriptors
10. Security restrictions and permissions.
ii) THREAD

Application program can be said to consist of a number of threads or a number ofprocesses and
threads

1.A thread consists of sequentially executable program(codes) under state-control by anOS.

2. The state of information of a thread is represented by thread- state(started, running, blocked
or finished),thread structure –its data, objects and a subset of the process resources and
thread-stack.
3. A thread is a light weight entity
Defn: A thread is a process or sub process within a process that has its own PC, its own SP and
stack ,its own priority and its own variables that load into the processor registers on context switching and
is processed concurrently along with other threads.

70
 Fig :Threads
A multiprocessing OS runs more than one process. When a process consists ofmultiple threads, it
is called multithreaded process.
A thread can be considered as a daughter process.
A thread defines a minimum unit of a multithreaded process that an OS
schedules onto the CPU and allocates the other system resources.
Different threads of a process may share a common process structure.
Multiple threads can share the data of the process.
Thread is a concept used in Java or Unix.
Thread is a process controlled entity

iii) TASKS

Task is the term used for the process in the RTOSes for the embedded systems. A task is similar to a
process or thread in an OS.
Defn: Task is defined as an embedded program computational unit that runs on a CPU under the state-
control of kernel of an OS. It has a state, which at an instance defines by status ( running, blocked or
finished),structure – its data, objects and resources and control block.

Fig:
OS. Tasks
A task consists of a sequentially executable program under a state-control by an

The state information of a task is represented by the task state (running, blocked
or finished),structure – its data, objects and resources and task control block.
Embedded software for an application may consist of a number of tasks .
Each task is independent in that it takes control of the CPU as scheduled by the
scheduler at the OS.
A task is an independent process
71
 No task can call another task
The task can send signals and messages that can let another task waiting for this
signal.

Task states
1. Idle(created)state
2. Ready(active)state
3. Running state
4. Blocked(waiting)state
5. Deleted(finished)state

4) Explain briefly on how embedded

processors have improved efficiency with use
of multitasking.
Embedded OSs manages all embedded software using tasks, and can be either unitasking or
multitasking.

In unitasking environments, only one task can exist at any given time.
In multitasking OS, multiple tasks are allowed to exist simultaneously.

In multitasking environment each process remain independent of others and do

Some multitasking
not affect OSs also provides threads as an additional alternative means
other process.
for encapsulating an instance of a program.

Threads are created within the context of a task and depending on the OS the
task can own one or more threads

Threads of a task share the same resources like working directories, files, I/O
devices, etc., but have their own PCs, stack and scheduling information.

space orAcan
task can contain atmany
contain leastthreads
one thread executing
executing differentone program
portions of onein one address
program inone address
space.

Multitasking OS
Task 1

Program1
Program 1
Task 1 Registers

Task 1 Stack
 OS
Program 2
Process 2
Tasks and threads
Program1
….. Task 2 Registers

Task 2 Stack
72
Process 3

Program 2

Task 3 Stack
 Thread 1
Part of Program1
Task 1 Thread 2
Program1 Part of Program1
Program 1 Task 1
Registers Thread 3
Program 2 Part of Program1
Memor
Process 2 y
OS Program1
….. Task 2
Registers

Process 3

Program 2

Task 3
Registers
Multitasking and process management

When an OS allows multiple tasks to coexist, one master processor or an embedded

board can only execute one task or thread at any given time.

Therefore multitasking embedded OSs must find some way of allocating each task a
certain amount of time to use the master CPU and switching the master processor between
the various tasks

This is done through task implementation, scheduling, synchronization and inters task
communication.

Gives an illusion that single processors simultaneously

Interleaving tasks run multiple tasks.

process1
process2
Time
process3
process1
Process 1 Process 2 Process 3

Process 4
process2
process3
OS process1
process3
process1
process4
process3
process4
process3

73
 Task hierarchy
OS Initial Task

Task Task Task

Task Task Task Task

Tasks are structured as a hierarchy of parent and child tasks and when anembedded kernel
starts up only one task exists.
All tasks create their child task through system calls.
The OS gains control and creates the Task Control Block (TCB)
Memory is allocated for the new child task ,its TCB and the code to be executedby the child task.
After the task is set up to run, the system call returns and the OS releases controlback to the main
program.
Types of Multitasking:

Multitasking involves the switching of execution among multiple tasks. It can beclassified into
different types.

1. Cooperative multitasking – this is the most primitive form of multitasking in which a

task/process gets a chance to execute only when the currently executing task/process
voluntarily relinquishes the CPU. In this method, any task/process can hold the CPU as
much time as it wants. Since this type of implementation involves the mercy of the tasks
each other for getting the CPU time for execution, it is known as cooperative
multitasking. If the currently executing task is non- cooperative, the other tasks may
have to wait for a long time to get the CPU.
2. Preemptive multitasking: This ensures that every task gets a chance to execute.
When and how much time a process gets is dependent on the implementation of the
preemptive scheduling. In preemptive scheduling, the
74
 currently running task is pre empted to give a chance to other tasks to execute. The preemption of
task may be based on time slots or task/process priority.
3. Non-Preemptive Multitasking: In non- preemptive multitasking, the task which is
currently given the CPU time is allowed to execute until it terminates or enters the
Blocked/wait state waiting for an I/O or system resource. The cooperative and non-
preemptive multitasking differs in their behavior when they are in the blocked/wait
state.
In cooperative multitasking, the currently executing process/task need not relinquish the CPU when it
enters the ‗Blocked/wait‘ state waiting for an I/O or a shared resource access or an event to occur where
as in non-preemptive multitasking the currently executing task relinquishes the CPU when it waits for
an I/O or system resource or an
event to occur.

5) Explain briefly about inter process communication. A) Semaphores B) Mailbox C)

Pipe

SEMAPHORE

Suppose that there are two trains. Assume that they use an identical track. When the
first train A is to start on the track, a signal or token for A is set and the signal or token for the
other train B is reset.

Semaphore is used for signaling or notifying of a certain action and also for notifying the
acceptance of the notice or signal.

Release of a token is the occurrence of the event and acceptance of the token is taking
note of that from
s increments event.
0 to 1 for signaling or notifying occurrence of an event from asection of codes
in a task or thread.
Let a Boolean variable, s represent a semaphore.
s decrements from 1 to 0 when the event is taken note by a section in anothertask waiting for that
event and the waiting task codes start at another action

75
 Fig: Action on the function call in a program, Action on pre-emption of task A by B,
program counter assignments

Binary Semaphore

A semaphore is called binary semaphore when its value is 0, it is assumed that it has been
taken or accepted and when it is 1, it is assumed that it has been released or sent

or posted
Anand
ISRno
cantask has taken
release it yet.
the token, A task can release the token as well accept thetoken or wait for
taking the token.

Example
Consider an Automatic Chocolate Vending Machine(ACVM).After the task delivers the chocolate , it has
to notify to the display task to run a waiting section of the code to display , ―Collect the nice chocolate,
Thank you, Visit Again‖. The waiting section for the display of the thank you message takes this notice
and then it starts the display of thank you message.

MAILBOX
76
 A message mailbox is for an IPC message that can be used only by asingle destined
task.
The mailbox message is a message pointer or can be a message.
The source(mail sender) is the task that sends the message pointer to acreated mailbox .
The destination is the place where the OSMBoxPend function waits for themailbox message
and reads it when received.

Example:
A mobile phone LCD display task

In the mailbox, when the time and data message from a clock-process
arrives , the time is displayed at side corner on top line.
When the message is from another task to display a phone number, it isdisplayed at
the middle.
When the message is to display the signal strength of the antenna, it isdisplayed at
the vertical bar on the left.
Mailbox types at the different operating systems (OSes)

1. Multiple Unlimited Messages Queueing up

2. One message per mailbox
3. Multiple messages with a priority parameter for each message
A queue may be assumed a special case of a mailbox with provision formultiple
messages or message pointers.
An OS can provide for queue from which a read can be on a FIFO basis
Or an OS can provide for multiple mailbox messages with each message

having a priority parameter.

Even if the messages are inserted in a different priority, the deletion is as perthe assigned
priority parameter.

OS functions for the Mailbox

Create

Write(Post)
Accept
Read(Pend)
Query
77
RTOS functions for the Mailbox
1. OSMBoxCreate : Creates a box and initializes the mailbox contents with a NULL
pointer
2. OSMBoxPost: Sends a message to the box
3. OSMBoxAccept: Reads the current message pointer after checking thepresence
yes or no.Deletes the mailbox when read.
4. OSMBoxWait:Waits for a mailbox message , which is read when received.
5. OSMBoxQuery: Queries the mailbox when read and not needed later.

PIPE
A message-pipe is a device for inserting (writing) and deleting(reading) from thatbetween two given
interconnected tasks or two set of tasks. Writing and reading from a
pipe is like using a C command fwrite with a file name to write into a named file, and fread with
a file name to read from the named file. Pipes are also like Java PipeInputOutputStreams.

1. fwrite task can insert(write) to a pipe at the back pointer address,*pBACK

2. fread task can delete (read) from a pipe at the front pointer address,*pFRONT
3. In a pipe there are no fixed number of bytes per message, but there is a end pointer.
Pipe can have a variable number of bytes per message between the initial and final
pointers.
4. Pipe is unidirectional. One thread or task inserts into it and the other one deletes from
it.
Functions at Operating systems

The OS functions for pipe are the following :

1. pipeDevCreate : Create a device which functions as pipe.

2. open( ) :Opening the device to enable its use from beginning of its allocated
buffer
3. connect( ) :Connecting a thread or task by inserting bytes to the thread or taskand
deleting bytes from the pipe.
4. write ( ) :Inserting from the bottom of the empty memory space in the buffer
allotted to it.
5. read( ) :Deleting from the bottom of the unread memory spaces in the buffer filledafter
writing into the pipe.
6. close( ) :Closing the device to enable its use from beginning of its allocated
buffer only after opening it.
78
 Fig: a) Function at operating system and use of write and read function by
task A and task B, b)Pipe messages in a message buffer

6. Write short notes on i) shared memory, ii) message passing, iii) priority
inheritance iv) priority inversion.

Shared Memory:

Shared Memory is an efficient means of passing data between programs. One

program will create a memory portion which other processes can access.

A shared memory is an extra piece of memory that is attached to some addressspaces

for their owners to use. As a result, all of these processes share the same
memory accesses are not handled properly. The following figure shows two processand their address
spaces.
memoryThe rectangleand
segment boxhave
is a shared
accessmemory attached to bothrace
to it. Consequently, address spaces and
conditions mayboth process
occur if 1 and
process 2 can have access to this shared memory as if the shared memory is past of its own address space.
In some sense, the original address space is ''extended" by attaching this shared memory.

79
 Shared memory is a feature supported by UNIX system 5, including Linux, Sun OS and Solaris.
One process must explicitly ask for an area, using a key to be shared by other processes. This process
will be called the server. All other processes, the clients that know the shared area can access it. However,
there is no protection to a shared memory and any process that knows it can access it freely. To protect a
shared memory from being accessed at the same time by several processes, a synchronization protocol
must be setup.
A shared memory segment is identified by a unique integer, the shared memory ID. The shared
memory itself is described by a structure of type shmid-ds in header file sys / shm.h. To use this file, files
sys / types.h and sys / ipc.h must be included. Therefore, your program should start with the following
lines:
# include <sys / types.h>#
include <sys / ipc.h>

# include <sys / shm.h>

A general scheme of using shared memory is the following:

For aserver, it should be started before any client. The server should perform the
following tasks:

1. Ask for a shared memory with a memory key and memorize the returned
shared memory ID. This is performed by system call shmget ().
2. Attach this shared memory to the server's address space with system callshmat
().
3. Initialize the shared memory, if necessary.
4.
6. Remove the Shared
Do something andmemory with
wait for all system
client'scall shmctl ().
completion. For the
client part,
5. the procedure
Detach is almost
the shared the same:
memory with system call shmdt ().
1. Ask for a shared memory with the same memory key and memorize the
returned shared memory ID.
2. Attach this shared memory to the client's address space.
3. Use the memory.
4. Detach all shared memory segments, if necessary.
5. Exit.
Message Passing:
Most general purpose OS actually copy messages as twice as they transfer there fromtask to task via a
message queue. In RTOS, the OS copies a pointer to the message,
80
delivers the pointer to the message - receiver task and then deletes the copy of thepointer with
message sender task.

Message Passing is an asynchronous / synchronous information exchange mechanism used for

Inter process or thread communication. The major difference between shared memory and message
passing technique is that, through shared

memory lots of data can be shared where as only limited amount of info / data is passed through message
passing. Also message passing is relatively fast and free from the synchronisation overheads compared to
shared memory.
Message passing constructs:

There are 2 basic message passing primitives such as send and receive.
Send primitive: Sends a message on a specified channel from one process toanother,
Receive primitive: Receives a message on a specified channel from otherprocesses.

Message passing is classified into message queue, Mail box and signalling.

Message Queue:

The process which wants to talk to another process posts the message to a First-

In-First-Out queue called message queue, which stores the messages temporarily in a system defined
memory object to pass it to the desired process.
Messages are sent and received through send and receive methods. the messages are exchanged
through a message queue.
The message mechanism is classified into synchronous and asynchronous based on the
behaviour of the message posting thread. In asynchronous messaging, the message posting
thread just posts the message to the queueand it will not wait for an acceptance from the thread
to which the message is posted.
In synchronous messaging, the thread which posts a message enters waiting state and waits for
the message result from the thread to which the message is
81
 posted.
The features of a message queue IPC are

1. An OS provides for inserting and deleting the message pointers or messages.

2. Each queue for the message needs initialization before using functions inkernel
for the queue.
3. Each Created queue has an ID.
4. Each queue has a user defined size.
5. When an OS call is to insert a message into the queue, the bytes are as perthe
pointed number of bytes.
6. When a queue becomes full, there is error handling function to handle that.

Q HEAD and
Q TAIL

The µC/OS - II Functions for a queue are

1. OSQ Create 2. OSQ POST 3. OSQ PEND 4. OSQ ACCEPT 5. OSQ FLUSH 6.OSQ QUERY 7.
OSQ POST Front.

Figure: OS functions for Queue between task 1 and task 2

There is a presence of two pointers for queue head and tail memory locations are.

Priority Inversion
Priority inversion is the byproduct of the combination of blocking based process synchronization
and preemptive priority scheduling. Priority inversion is the condition in which a high priority task
needs to wait for a low priority task to release a resource which is share between the high priority
task and the low priority task and a medium priority task which doesn‘t require the shared resource
continue its execution by pre emptying the low priority task.
Priority based preemptive scheduling technique ensures that a high priority task is always
executed first, whereas the lock based process synchronization mechanism ensures that a process will
not access a shared resource, which is currently in use by

82
another process. The synchronization technique is used to avoid conflients in the concurrent access of the
shared resources.
Let process A, process B and process C be three processes with priorities High, Medium and Low
respectively. Process A and Process C share a variable X and the access to this variable is
synchronized through a mutual exclusion mechanism like Binary semaphore.
Imagine a situation where process C is ready and is picked up for execution by the schedules and
Process C tries to access the shared variable X.
Immediately after process C acquires the semaphore S, Process B enters the Ready state. Since
Process B is of higher priority compared to process C. Process C is preempted and Process B
starts executing.\

Now process A is of higher priority than process B, Process B is preempted and process A is
scheduled for execution. Process A tries to access shared variable X which is currently accessed
by process C. So Process A will not be able to access if and then it enters into the blocked state.
Now process B gets the CPU and it continued its execution until it relinquishes the CPU
voluntarily or enters a wait state or preempted by another high priority task.
Process A has to wait till process C gets a chance to execute and release the semaphore. This
produces unwanted delay in the execution of the high priority task which is supposed to be
executed immediately when it was ready.
Priority Inversion may be sporadic in nature but can lead to potential damages as a result of
missing critical dead lines.

83
Priority Inheritance
A low-priority task that is currently accessing (by holding the lock) a shared resource requested
by high priority task temporarily ‗inherits‘ the priority of that high- priority task, from the moment the
high-priority task raises the request Boosting the priority of the low priority task to that of the priority of
the task which requested the shared resource holding by the low priority task eliminates the preemption of
the low priority task by other task whose priority are below that of the task requested the shared resource
and thereby reduces the delay in waiting to get the resource requested by the high priority task. The
priority of the low priority task which is temporarily boosted to high is brought to the original value
when it relaeases the shared resource. Implementation of priority inheritance work around in the
priority inversion problem discussed for
process A, Process B and process C example will change the execution sequence as shown in
figure.

Priority inheritance is only a work around and it will not eliminate the delay in waiting
the high priority task to get the resource from the low priority task. The only thing is that it helps
the low priority task to continue its execution and release the shared resource as soon as
possible. The moment, at which the low priority task releases the shared resource, the high
priority task kicks the low priority task out and grabs the CPI – A true form of selfishness.
Priority inheritance handles priority inversion at the cost of run-time overhead at schedules. It
imposes the overhead of checking the priorities of all tasks which tries to access shared
resources and adjust.

84
 7. Write about the features of µC/OS- II , Vx
Works and RT Linux .
i) µC/OS – II
µC/OS – II is a highly portable, ROMable, very scalable, preemptive real time,deterministic,
multitasking kernel.
It can manage up to 64 tasks (56 uses task available)
It has connectivity with µc/GUI and µc/ FS (GUI and file systems for µc/OS – II) It is
ported to more than 100 microprocessors and microcontrollers.
It is simple to use and simple to implement but very effective compared to theprice/performance
ratio.
It supports all type of processors from 8-bit to 64-bit.
Task Management Services:
Task features
Task creation
Task stack and stack checkingTask
deletion
Change a task‘s priority Suspend
and resume a taskGet information
about a task
Task feature:
µc/OS- II can manage up to 64 tasks.
The four highest priority tasks and the four lowest priority tasks are reserved forits own use.
This leaves us with 56 application tasks.
The lower the value of the priority, the higher the priority of the task.

The task priority number also serves as the task identifier.

Rate monotonic scheduling:
In rate monotonic scheduling tasks with the highest rate of execution are giventhe
highest priority.
Assumptions

1. All tasks are periodic

2. Tasks do not synchronize with one another, share resources, etc.
3. Preemptive scheduling is used (always runs the highest priority task that isready)

85
 Under these assumptions, let n be the number of tasks, Ei be the execution time of task i,
and Ti be the period of task i. Then, all deadlines will be met if the following inequality is
satisfied.
ΣEi/Ti ≤ n(2 1/n – 1)
Example: suppose we have 3 tasks. Task 1 runs at 100Hz and task 2 ms. Task 2 runs at
50Hz and takes 1ms. Task 3 runs at 66.7 Hz and takes 7 ms. ApplyRMS theory.
(2/10) + (1/20) + (7/15) = 0.707 ≤ 3(2 1/3 – 1) = 0.780
Thus, all the deadlines will be met.
General solution:
As n goes infinity, the right hand side of the inequality goes to in (2) = 0.6931.
Thus you should design your system to use less than 60 – 70% of the CPU.
Task creation:

Two functions for creating a task are

o OS task create ( )
o OS task create E X t ( )
Task Management:

After the task is created, the task has to get a stack in which it will store its
data.
A stack must consist of contiguous memory locations.
It is necessary to determine how much stack space a task actually uses. Deleting a task means
the task will be returned to its dormant state and does

not mean that the code for the task will be deleted. The calling task can delete itself. If
another task tries to delete the current task, the resources are not freed andthus are lost. So the task has
to delete itself after it uses its resources.
Priority of the calling task or another task can be changed at run time.
A task can suspend itself or another task; a suspended task can resume itself.

86
 A task can obtain information about itself or other tasks. This information canbe used to
know what the task is doing at a particular time.
Memory Management:
The memory management includes:
1. Initializing the memory manager
2. Creating a memory partition
3. Obtaining status of a memory partition
4. Obtaining a memory block
5. Returning a memory block
6. Waiting for memory blocks from a memory partition.
Each memory partition consists of several fixed – sized memory blocks.
A task obtains memory blocks from the memory partition.
A task must create a memory partition before it can be used.
Allocation and de-allocation of these fixed – sized memory blocks is done inconstant
time and is deterministic.
Multiple memory partitions can exist, so a task can obtain memory blocks ofdifferent
sizes.
A specific memory block should be returned to its memory partitions from which itcame.
Time management:

Clock Tick: A clock tick is a periodic time source to keep track of time delays andtime
outs.
o Time intervals: 10~100 ms
o The faster the tick rate, the higher the overhead imposed on the system.

Whenever a clock ticks occurs, µC/OS – II increments a 32 – bit counter.

o The counter starts at zero and rolls over to 2 32-1 ticks.
A task can be delayed and a delayed task can be also be resumed. Five
services:
o OSTime_DLY ( )
o OSTime_DLYHMSM ( )
o OSTime_DLYResume ( )
o OSTime_GET ( )
o OSTime_Set ( )
Inter task communication:

87
 Inter task or inter process communication in µC/OS takes place using, Semaphore
Message mailbox
Message queues
Tasks and interrupt service routines (ISR) can interact with each other through an ECB(Event Control
Block)

Single task waiting:

Multiple tasks waiting and signalling:

Tasks can wait and signal along with an optional time out.

µC/OS-II semaphores consist of two elements

o 16 – bit unsigned integer count.
o List of tasks waiting for semaphore.
µC/OS – II provides
Create, post, pend accept and query services.

88
 µC/OS – II message mailbox: an µC/OS – II object that allows a task or ISR tosend a pointer
sized variable (pointing to a message) to another task.

µC/OS – II message – queues

Available services: create, post (FIFO), postfront (LIFO), pend, accept – query,flush.
N = Addition of entries in the queue: queue full if post or post front called N times beforea pend or
accept.

µC/OS – II message – queue organized at circular buffers.

89
 ii) Vx Works RTOS:
Introduction:
Vx works is a real time operating system developed as proprietary software by windriver systems. It in
a high performance, Unix like, scalable RTOS and supports ARM,
Pentium, Intel X-scale, super H and other popular processors for embedded system design. Vx
works design is hierarchical and well suited for real time applications. It support kernel mode
execution of tasks for fast execution of application codes. Vx works is supported with powerful
development tools that make it easy and efficient to use.

Many simulation tools, time performance analysis tools, debug and test tools are provided.
Making Vx works as an RTOS that supports development of almost any embedded application,
providing a complete solution for all stages of the design cycle. The latest version Vx works 6.9
in the first commercial grade RTOS to fully support both 32-bit and 64-bit processing on Intel
Architecture.

Basic Features:

1. Multi tasking environment using standard POSIX scheduler.

2.
3. Ability
Multipletofile
runsystems
two concurrent operating
and systems systems
that enable on a single
advanced processing
multimedia layer.
functionality.
4. Synchronization using a full range of IPC option.
5. Different context saving mechanisms for the tasks and ISRs.
6. Virtual IO devices including pipes and sockets.
7. Victual memory management functions.
8. Power management functions to enhance the ability to control power
consumption.
9. Interconnecting functions that support large number of protocols.
10. Pipe drivers for DPCS.
11. Network transparent sockets.

90
 12. Network derivers for shared memory and Ethernet.
13. RAM dist drivers for memory resident files.
14. Processor arbitration layer to enable application system design by user whenusing
new versions of processor architecture.

Architecture:
Vx Works was initially a development and network environment for VRTX. Later wind River systems
developed. Their own micro kernal. So the Vx works is of "client-server" architecture from the beginning.
The heart of the Vx works run-time system is the wind microkernel. This micro kernel supports a full
range of real-time features including multi- tasking, scheduling. Inter task synchronization
communication and memorymanagement. All the other functionality is implemented as processes.
Vx Works is highly scalable. By including or excluding various models, Vx works can be
configured for the use in small embedded system with tough memory constraints to complex
systems where more functions are needed. Furthermore, individual modules themselves are
scalable. Individual functions may be removed from the library or specific kernel
synchronization objects may be omitted if they are not required by the application.

Task Management:
The Vx works real-time kernels provides a basic multitasking environment. Vx works offers both posix
and a proprietary scheduling mechanisms. Both preemptive priority and round robin scheduling
mechanism are available. The difference between POSIX and wind scheduling is that wind scheduling
is that wind scheduling mechanism are
available.
91
The difference between a POSIX and wind scheduling is that wind scheduling applies the scheduling
algorithm on a system wide basis, whereas POSIX scheduling algorithms are applied on a process by
process basis.
In Vx works, the states encountered by the task are of 8 different types.

1. Suspended: Idle state just after creation or stated where execution is inhibited.
2. Ready: Waiting for running and CPU access in case scheduled by the scholar but not
waiting for a message through IPC.
3. Pending: The task is blocked as it waits for a message from the IPC or from a
resource only then will the CPO be able to process further.
4. Delayed: Send to sleep for a certain time interval.
5. Delayed + suspended: Delayed and then suspended if it is not pre-emptied
during the delay period.
6. Pended for an IPC _ suspended: Pended and then suspended if the blocked
state does not change.
7. Pended for an IPC + delayed: Pended and than pre-emptied after the delayed
time interval.
8. Pended for an IPC + suspended: Pended and suspended after delayed time
interval.

Kernel library functions are included in the header file 'Vx works.h' and 'kernel Lib.h'. Task and
system library functions are included in 'task Lib.h' and 'sys Lib.h' User task priorities are
between 101 and 255. Lowest priority means task of highest priority number (255). System
tasks have the priorities from 0 to 99. For tasks, the highest priority is 100 by default..

The functions involved in task management:

1. Task Spawn function: It is used for creating and activating a task. Prototype is unsigned
int task ID = task spawn (name, priority, options, stack size, main, argo, art1, arg2, ... arg9).
2. Task suspending and Resuming functions: Task suspend (task ID): inhibits the
execution of task indentified by task Id.
Task Resume (task ID): Resumes the execution of the task identified by task ID.
Task Restart (task ID): First terminates a task and then spawn again with its original
assignes arguments.

3. Task deletion and deletion protection function: Task Delete (task Id): this
permanently inhibits the execution f the task identified by task Id and cancels theallocations of
the memory block for the task stack and TCB.
92
 Many time each task should itself execute the codes for the following:
Memory de-allocation.
Ensure that the waiting task gets the desired IPC
Close a file, which was opened there.

Delete child tasks when the parent task executes the exit ( ) function.
4. Delaying a task to let a lower priority task get access:
intSysClkRateGet ( ) returns the frequency of the system ticks. Therefore to delay by
0.25 seconds, the function task Delay (SysclkRateGet ( ) /4) is used.
Memory Management:
In Vx works, all systems and all application tasks share the same address space. Thismeans that
faulty application could accidently access system resources and
compromise the stability of entire system. An optional tool named Vx VMI is available that can
be used to allow each task to have its own address space. Default physical page size used is 8
KB. Virtual memory support is available with Vx VMI tool. Vx works does not offer privilege
protection. The privilege level is always 0.

Interrupts:

To achieve the fastest possible response to external interrupts, Interrupt service routines in Vx
works run in a special context outside of any thread's context, so that there are no thread
context switches involved. The C function that the user attaches to a interrupt vector is not
actual ISR. Interrupts cannot directly vector to C functions.

The ISR's address is stored in the interrupt vector table and is called directly from the hardware.
The ISR performs some initial work and then calls the C function that was attached by the user.
For
task this reason, we use the term interrupt handler to designate the
design.
The features of the ISR in Vx works are:
user installed C handler function. Vx Works uses an ISR design that is different from a
1. ISRs have the highest priorities and can pre-empt any running task.
2. An ISR inhibits the execution of tasks till return.
3. An ISR does not execute like a task and does not have regular task context.
4. An ISR should not use mutex semaphore.
5. ISR should just write the required data at the memory or buffer.
6. ISR should not use floating – point functions as these take longer time to
execute.

Performance:
93
 Real time performance: Capable of dealing with the most demanding time constraints, Vx
works is a high-performance RTOS tuned for both determinism and responsiveness.
Reliability: A high – reliability RTOS, Vx works provides certification evidence required
by strict security standard. Even for non-safety – critical systems, Vx works is counted on to run
forever, error free.
Scalability: An indispensable RTOS foundation for very small – scale devices, large scale
networking systems and everything in between, Vx works is the first RTOS to provide full 64-bit
processing to support the over growing data requirements for embedded real time systems. Vx works is
scalable in terms of memory foot print and functionality so that it can be tuned as per the requirements of
the project.
Interrupt latencies: The time elapsed between the execution of the last instruction of
the interrupted thread and the first instruction in the interrupts handler to the next task
scheduled to run is interrupt dispatch latency. Vx works exhibits an Interrupt latency of

1.4 to 2.6 micro seconds and dispatch latency of 1.6 to 2.4 s

Priority inheritance: Vx works has a prioriy inheritance mechanism that exhibits an

optimal performance, which is essential for an RTOS.

Foot print: Vx works has a completely configurable and tunable small memory foot
print for today's memory – constrained systems. The user can control how much of the
operating system he needs.

Applications:

Vx Works RTOS is widely used in the market, for a great variety of applications. Its
Helicopter, Boeing 787, 747-8 and Airbus A 400 M. It is also used in on ground avionic systems such as
reliability makes it a popular choice for safety critical applications Vx works has been
in both civilian and military radar stations. Another safety critical application that entrusts Vx works is
BMW's i – Drive system.
success fully used in both military and civilian avionics, including the Apache Attack
However, Vx works is also widely used in non-safety – critical applications where performance
is at premium. The xerox phasor, a post – script printer is controlled by a Vx works powered platform
link sys wireless routers use Vx works for operating switches.
Vx works has been used in several space application's. In space crafts, where design challenges are
greatly increased by the need of extremely low power consumption and lack of access to regular
maintenance, Vx works RTOs can be chosen as the operating

94
 system for on Board Computer (OBC). For example 'clementine' launched in 1994 is running Vx works
5.1 on a MIPS – based CPU responsible for the star Tracker and image processing algorithms. The 'spirt'
and opportunity mars exploration rovers were installed with Vx works. Vx works is also used as operating
system in several industrial robots and distributed control systems.
Summary:
The need to develop for real-time embedded applications is always a challenge, especially when
expensive hardware is at risk. The complex nature of such systems require many special design
considerations an understanding of physical systems, and efficient Management of limited resources
perhaps one of the most difficult choice the embedded system designers have to make in which operating
system they are going ot
use. It is critical to have operating system that will be able to be fail-safe, secure, scalable, fast
and robust in multi task management, while being friendly to the application developers, Vx
works is an RTOs which meets almost all of these requirements.

iii) RT Linux

RT linux is a hard real time RTOS microkernel that runs the entire linux operating system as a
fully preemptive process. It was developed by Victor Yodaiken, Michael Barabanov and others
at the New Mexico Institute of Mining and Technology and then as a commercial product at
FSM Labs. FSM Labs has 2 editions of RT Linux.

RT Linux pro and RT Linux free. RT Linux pro is the priced edition and RT Linux is the
open source release. RT Linux support hard real time applications. The Li nux kernel has been
modified by adding a layer of software between the hardware and the

required for RT Linux.

Linux kernel. This additional layer is called ‗Virtual Machine‘. A footprint of 4 MB is
The new layer, RT Linux layer has a separate task Scheduler. This task scheduler assigns lowest priority
to the standard to the standard Linux kernel. Any task that has to met real-time constraints will run under
RT Linux. Interrupts from Linux are disabled to achieve real time performance.

95
In RT Linux location of the various files are:
RT Linux will be installed in the directory/usr/rtlinux-XXX, where XXX is the
version name.
/usr/rtlinux/include contains all the include files necessary for development project.

/usr/doc/rtlinux/man contains the manual pages for the RT Linux.

/usr/rtlinux/modules contains the core RT Linux modules

The two important aspects while doing programming in RT linux are:

By default, the RT Linux tasks do not have access to the computer‘s floatingpoints
unit. Hence need to explicitly set the permissions for every RT Linux task.

It cannot pass arguments from the command prompt.

RT Linux Modules:

RT files
into object Linux programe
using are not created
the gcc command as stand-alone
with the argument C flag. Inunits,
the Cthey are
file the created
main ( as
modules. Which
) function gets are loaded
replced with theinto the linux
following lines.kernel space. The C source files are complied
Int init-module ( ).
Void cleanup_module ( ).
Init-module is called when the module is first loaded into the kernel. This functionreturns O if the
module is successfully loaded. It returns a negative value in case offailure. When the module is loaded is
to be unloaded, the cleanup_module ( ) is called. Executing the RT Linux Modules:
In RT Linux, Load and stop user modules are using the RT Linux command. Using this
command, we can obtain status information about RT Linux modules. The command syntax is:
96
 $ rtlinux start my-program
$ rtlinux stop my-program $
rtlinux status my-programCreating RT
Linux POSIX Threads
A real time program generally consists of a number of threads. Each thread share a common
address space. Pthread_create () function is used to create a new real-time thread. The corresponding
header file is
# include <pthread.h>
To achieve real time performance, the various POSIX compliant API functioncalls are
used. There function calls are related to create and cancel semaphores.
To implement mutex, we have to include the header file <rtl-mutex.h) in the C
program.
To cancel a thread, the system call is pthread cancel.
Timer Management

A number of internal clocks are available in RT Linux to manage the timers. Thecurrent clock
reading is obtained using command is:
Clock-set time ( ) function
Clock-id gives the identification of the clock to be read.

97
 UNIT-V
EMBEDDED SYSTEM APPLICATION DEVELOPMENT

1. What is Multi-state system?

A system that can exist in multiple states (one-state at a time) and transition from onestate to another state
is known as multistate system. There are 3 types of multi state system:
 Timed multi state system
 Input – based multi state system
 Input – based / Timed multi state system
2. What is a motor driver?
A motor driver is a little current amplifier. The function of motor drivers is to take a low current control
signal and then turn it into a higher current signal that can drive a motor.
3. Define RTC
A real time clock is a computer clock that keeps track of the current time even whenthe computer is
turned off. Real Time Clock (RTC) runs on a special battery that is not connected to the normal power
supply.
4. Write in brief about the PIC microcontroller.
PIC (Peripheral Interface Controller) is a family of Harvard Architecture microcontrollers made by
Microchip Technology. It has an in built PWM generator, which is very useful to control the motors
5. What is Smart Card?
Smart Card stores and process information through electronic circuits embedded in the silicon in a
plastic substrate body. It is portable and tamper resistant computer. It

carries both processing power and information.

6. Define class and objects.
Class: A class is a user defined type or data structure declared with keyword class that has data and
functions as its members whose access is governed by the three accesses specifies private, protected or
public. Class is a collection of data member andmember function
Object: Object is a class type variable, objects are also called instance of the class. Each object
contains all members declared in the class.
7. What is synchronization in RTOS?

98
 To let each section of codes, tasks and ISRS run and gain access to the CPU one after the other
sequentially or concurrently, following a scheduling strategy, so that there is a predictable operation at
any instance.
8. List the characteristics of multi – state system.
The system will operate in two or m ore states.
Each state may be associated with one or more function calls.
Transitions between states may be controlled by the passage of time, bysystem inputs or
by a combination of time and inputs.
Transition between states may also involve function calls.
9. What is an adaptive control algorithm?
An adaptive control algorithm refers to algorithm parameters which adapt to the present
status of the control inputs in place of a constant set of mathematical parameters in
algorithmic equations.

10. What are the task functions for a smart card?

resetTask

task_Read Port
task_PW

task_Appl

UNIT – 5
1. Discuss in deeply about the case study of washing machine design.
PART-B(16 marks)
Automatic washing machine is a Multi-state Input/Timed system. The characteristics of

multi state system are:

The system will operate in two or more states.
Each state may be associated with one or more functional calls.
Transitions between states may be controlled by the passage of time, by systemInputs or by a
combination of time and inputs.
Transitions between states may also involve function calls.

99
Outline design of inputs and outputs:

Start
Water
Switch
Value
Water
Selector Heater
Dial
Water
Pump
Water
level
Drum
Motor
Temperature
sensor Washing
Detergent LED or LCD
Machine
Hatch
Controller indicators

Figure: Outline Design

Microcontroller based washing machine design:

PIC18F series microcontroller acts as a washing machine controller. Single phase motor is
considered for the design. Front panel consists of a keypad and LCD display. Keypad provides automatic
and manual wash options to the user. LCD displayis convenient to convey machine information to user.
Modern washing machines are designed with BLDC motors owing to efficiency and energy conversation.
But in his case, single phase universal motor has been used to design prototype.
Design Specifications:
This include both hardware and software specifications.
1. The system should provide fully automatic mode, semi automatic mode andmanual mode.
Modes should be selected by a keypad.
2. Under fully automatic mode, user intervention requirement should be zero.

Once the system is started in this mode, it should perform its work independently and after the completion
of work it should notify the user about the completion of work. This mode instantaneously should sense
cloth quality and requirement of water, water temperature, detergent, load, wash cycle time and perform
operation accordingly.
3. In semi – automatic mode also, user requirement should be nil. But user has to
choose any one of the semi automatic mode in which washing conditions are predefined. Once
the predefined mode is started, the system should perform its job and after completion, it
should inform the user.
4. In manual mode, continuous intervention of user is required. For example, a user
needs to choose wash mode, wash time, amount of water and the load. After these data are
entered, the user should start the machine.
100
 5. When the lid is open, system should not work. If door is accidently opened in
between wash operation, then the system should stop working in minimum possible time.
6. The system should provide all the basic features of a washing machine like washing,
rinsing, spinning, drying, cold wash, hot wash etc.
7. The system should provide easy option for upgrading the new features.
8. The system should work on single phase AC from 190V AC to 250V AC. The system
should protect itself from power supply voltage variations.
9. In the event of power failure, the washing machine should automatically start its
cycle from the point of interruption when power is resumed.

Hardware Design:
PIC18F452 is a heart of the system. Most of the peripheral features have been utilized to
implement the design. Controlling the motor is very crucial part of the design. The PWM feature of the
microcontroller controls motor speed. PWM output is feed to driver circuit and then to motor.
To rotate the motor in two different directions forward and reverse direction, control blocks
are used. Motor speed sensor is interfaced to microcontroller. Microcontroller reads the speed of the
motor and approximately controls the speed of the motor in different phases of washing using PWM
output. Door sensor, pressure sensor, keypad are also interfaced to microcontroller. EEPROM and RTC
are interfaced to MSSP module of controller. In-circuit serial programming facility is provided for quick
and easy programming and debugging.

101
 Washing machine parameters are stored in external EEPROM and internal EEPROM of the PIC.
RTC (Real Time Clock) is interfaced to SPI (Serial Peripheral Interface) port of the microcontroller.
It is used as a timing reference for all timing calculation of machine.
Door sensor is connected to external interrupt 0. High priority is assigned to this interrupt. Thus
opening of the door causes triggering of INT0 and INT0 ISR immediately to stop the machine and
informs the user.
All the sensor outputs are connected to the analog pins of PIC (AN0, AN1, AN2 etc.) Keypad is
connected to port D. when any of the keys is pressed; output becomes high and INT1 triggers. Int1
ISR does a keypad scan and approximately performs the operation.

Motor speed sensor is given to T1, CLK which is an external clock input to timer 1 / timer 3. Timer is
configured in counter mode for calculating the speed. Speed is calculated by counting pulse output from
the sensor for one second.
Motor driver circuit determines the direction of the motor corresponding to the output obtaining from
the microcontroller.
Speed of the motor is controlled by the PWM generation from the microcontroller. The duty
cycle of PWM pulses are changed according to the output obtained from the speed sensor to maintain
the desired response during wash cycles.
Dedicated LCD with 3 wire interface is used, which consist of data line, clock and chip select.
Backlight control is also provided.

Software Design:
A provisional list of functions that could be used to develop a washing machine
are:

Read_Select_Dial ( )
Read_Start_Switch ( )
102
 Read_Water_Level ( )

Read_Water_Temperature ( )
Control_Detergent_Hatch ( )
Control_Door_Lock ( )
Control_Motor ( )
Control_Pump ( )

Control_Water_Heater ( )
Control_Water_Valve ( )
Frame Work:

1. System states – Initialization, start, fill drum, heat water, Wash 1, Wash 2, Error.
2. User defined data – a) Maximum Fill duration – 1000 seconds. b) Maximum
water heat duration – 1000 seconds. c) Maximum wash 1 duration – 3000 seconds.
3. Functions involved in each state or function call

Initialization:

 Control_Motor (OFF)
 Control_Pump (OFF)
 Control_Water_Heater (OFF)
 Control_Water_Valve (OFF)
 Read_Select_Dial (ON)
Now switch on to start state.

Start:

 Control_Door_Lock (ON)
 Control_Detergent_Hatch (ON)
 Control_Water_Valve (ON)
Now switch on to fill drum state.

Fill Drum:
 Read_Water_Level (ON)
 Control_Water_Heater (ON)
Now switch on to either heat water state or Wash 1 state depends upon thecondition.

Heat Water:
Read_Water_Temperature (ON) Now
switch on to Wash 1 state.

103
 Wash 1:
 Control_Motor (ON)
After the completion of duration, the system switches to the wash 2 state.
Wash 2:
In Wash 2 state, the system performs the washing operation until its duration is expired.
Error:
In any crash or error happens between the states, the system goes to thedefault state called
error state. It restarts the particular state, where the error occurs.
4. Function definitions:
Thus the software design is clearly explained with states and functions.

2) Explain the case study of an embedded system for an automotive application.

Present day automobiles have many embedded systems. A car contains many control systems.
One among them is ACC(Adaptive Cruise Control) which automatically controls the car speed.
Requirements
1. Purpose
2. Inputs
3. Signals, events and notifications
4. Outputs
5. Control panel
6. Functions of the system
7. Design metrices
a. Power source and dissipation

a. Resolution
b. Performance
c. Process deadlines
d. User interfaces
e. Extendibility
f. Engineering cost
g. Manufacturing cost
8. Test and validation conditions

ACC (Adaptive Cruise Control)

104
 This control method is used to maintain constant speed in cruise mode and to decelerate when a
vehicle comes in front at a distance less than safe and to accelerate again to cruise mode by using
adaptive control algorithm.

Adaptive Control algorithm

An adaptive control algorithm refers to an algorithm parameters in which adapt to the present
status of the control inputs in place of a constant set of mathematical parameters in the algorithmic
equations. Parameters adapt dynamically.
For an ACC system, an adjustable-system subunit generates output control signal for throttle
valve.
The desired preset cruise velocity vt,desired preset distance dset and safe preset distance dsafe are
the inputs to measuring subunit.

The measured velocity v and distance d are inputs to computing unit.

The comparison and decision subunit sends outputs which are inputs toadjustable
systems.

Fig : Model for an adaptive control algorithm adaption and functions

Class diagram
ACC system measurements of front end car range, distance and error estimations and adaptive control can
be modeled by two class diagrams of abstract classes, Task_ACC and Task_Control

105
 .
1.Task_ACC is an abstract class from which extended classes like
Task_Align,Task_Signal,Task_ReadRange, Task_RangeRate and Task_Algorithm are
derived to measure range and errors.

2. Task_Control is an abstract class from which extended classes like

Task_Brake,Task_Throttle and Task_Speed are derived to measure range and errors.
3. There are two ISR objects ISR_ThrottleControl and ISR_BrakeControl
ACC Hardware Architecture

ACC embeds the following hardware units:

Microcontroller-Runs the service routines and tasks except task_Algorithm.CAN port

interfaces with the CAN bus at the car.

Processor with RAM/ROM- To execute task_Algorithm

Speedometer

Stepper motor-based alignment unit.

plastic plates.
Stepper motor-based throttle control unit.
Display panel
Transceiver –For transmitting pulses through an antenna hidden under the
Port devices-Five port devices are
Port_Align,Port_Speed,Port_ReadRange,Port_Throttle and Port_Brake

106
ACC Software
For the ACC systemsArchitectur
Basic Conformance Class I (BCCI) is used.The following tablelists the BCCI
tasks,functions and IPCs

BCC 1 Task BCC 1 Action IPCs pending

function Priority
task_Align 101 Starts an event and send signal to Reset
Port_Align and Port_Ranging
task_Read 103 Disable interrupts,gets signal from Align
Range Port.Finds the time difference and
enable interrupts

task_Speed 105 Start a timer,wait for 10 counts and ---

outputs deltaT from port
task_RangeRa 107 Get preset cruising speed Speed
te compare it with current speed
task_Algorithm 109 Get errors of speed and range, errors ACC
of other vehicles, other vehicles brake
status,present throttle position.Send
throttle adjust output,signal to
Port_Brake in case of emergency
braking action.Port_Brake transmits
theaction needed to other vehicles
also.
107
Synchronization Model
1.The task,task_Align sends the signal to a stepper motor port Port_Align andPort_Ranging.The stepper
motor moves by one step clockwise or anticlockwise.
2.A task,task_ReadRange is for measuring front-end car range.
3. task_Speed gets the port reading at a port Port_Speed.Task sends v, using thecountN and
count() interval between the initial and Nth rotation.
4. task_RangeRate sends the rangeNow.Calculates both range and rate errors andtransmits

both rangeNow and speedNow.

5. task_Algorithm runs the main adaptive algorithm.It gets inputs from task_RangeRateand

outputs are events to Port_Throttle and brake.Port_Throttle attaches to the vacuum

actuator stepper motor.

3. Write about the design and interface of smart card system.

Smart Card Basics:

Smart card stores and process information through electronic circuits embedded in the silicon in a plastic
substrate body. It is portable and tamper resistant computer. It carries both processing power and
information.
Smart card has an embossed area on one face and magnetic stripe on other, it defines by ISO7816
standard. To communicate with the outside world, Smart card is placed inside a card Acceptance device.

108
Requirements:
Assume a contact less smart card for bank transactions. Let it not be magnetic.Requirements of Smart card
communication system with a host are.

1. Purpose:
Enabling authentication and verification of card and card holder by a host and enabling GUI at host
machine to interact with the card holder / user for the required transactions: for example, financial
transactions with a bank or credit card transaction.
2. System Functioning:
1. The cards inserts at host machine. The radiations from the host activate a chargepump at card.
2. On power up, system reset signals reset task to start. The reset task sends the messages - request
Header and request start for waiting task. task_ReadPort.
3. task_Read Port sends requests for host identification and reads through the port_IO the host -
identification and reads the request start from host for card identification.
4. The task_PW sends through Port_IO the requested card identification after

system receives the host identity through Port_IO

5. The task_Appl then runs required API. The request Appl close message closesthe
application.
6. The card can now be withdrawn and all transactions between card holder usernow
takes place through GUIs using at the host control panel.
3. Inputs:
Receives header and messages at IO Port_IO from host through the antenna.
4. Signals and Events and Notifications:
1. On power up by radiation powered charge - pump supply of the card, a signal tostart
the system boot program at reset task.
2. Card start request header message to task - Read Port from reset Task.
109
 3. Host authentication request start message to task_Read Port from reset Task toenable
request for Port_IO
4. User PW verification message (notification) through Port_IO from host.
5. Card application close request Applcase message to Port_IO
5. Outputs:
Transmitted headers and messages at port_IO through antenna.
6. Control Panel:
No control panel is at the card. The control panel and GUIs activate at the hostmachine.
7. Design Metrics:
1. Power source and dissipation: Radiation powered contact - less operation.

2. Code Size: Code size generated should be optimum. The card system memory needs should not
exceed 64 KB Memory.
3. File System(s): Three layered file system for the data. One file for the master file to store all file
headers. A header has strings for file status, access conditions and file-lock. The second file is a dedicated
file to hold a file grouping and heads. The third file is the elementary file to hold the file header and file
data.
4. File Management: There is either a fixed length file management or variable file length
management with each file with a predefined offset.
5. Micro controller hardware: Generates distinct coded physical addresses for the program and
data logical addresses. Protected once writable memory space.
6. Validity: System is embedded with expiry date, after which the card authorizations through the
hosts disable.
7. Extendibility: The system expiry date is extendable by transactions and

authorization of master control unit.

8. Performance: Less than 1s for transferring control from the card to host machine
9. Process Deadlines: None.
10. User Interfaces: At host machine, graphic at LCD or touch screen display on LCDand
commands for card holder (card user) transactions.
11. Engineering Cost: US $ 50,000 (assumed)
12. Manufacturing Cost: US $ 1 (assumed)
Test and Validation Conditions:
 Tested on different host Machine versions for fail proof card-host communication.
Class Diagram:
An abstract class is Task Communication. The figure shows the class diagram of
110
Task_Card communication. A cycle of actions and card - host synchronization in the card leads us to the
model Task_Card communication for system tasks. Card system communication to host for identifying
host and authentication itself to the host. ISR1_Port_IO, ISR2_Port_IO and ISR3_Port_IO are interfaces
to the tasks. The task_Appl, taskPW, taskRead port and reset_Task are the objects of Task_appl,
Task_PW, Task_Read Port and Task_Reset, respectively. These classes are extended classes of abstract
class Task_Card communication.

Task_card communication is an abstract class from which extended is class derive to read port
and authenticate. The tasks are the instances of the classes Task_Appl, Task_Reset, Task_Read Port and
Task_Reac Range.
Task_Read Port interfaces ISR1_Port_IO

The task_PW is object of Task_PW and interfaces ISR2_Port_IO. Task_Appl interfaces ISR3-
Port_IO
Hardware and Software Architecture:

Software using Java card provides one solution. JVM has thread scheduler built in. No separate
multitasking OS in thus needed when using Java because all Java byte codes run in JVM environment.
Java provides the features to support (i) security using class java.lang. Security Manager, (ii)
cryptographic needs. Java provides support to connections, datagrams, IO streams and network sockets.
111
 Java mix is a new technology in which the native applications of the card run in C or C++ and
downloadable applications run in Java Card. The system OS and JVM both. Smart OS in an assumed
hypothetical OS in this example, as RTOS in the card.
Remember that a similar OS function name is used for understanding purpose identical to MUCOS but
actual smart OS has to be different from MUCOS. Its files structure in different. It has two function as
follows.
The function unsigned than ( ) smart OS encrypy (unsigned char * applstr, EnType type) encrypts as per
encryptes method, EnType = "RSA" or "DES" algorithm chosen and returns the encrypted string.

List of Task functions and IPCs:

112
Synchronization Model:
Following are the actions on the card places near the host machine antenna in a machine
slot.
Step 1: Receive from the host, on card installation, the radiation of carrier frequency or
clock signals in case of contact with the card. Extract charge for the system power
supply for the modem, processor, memories and port IO device.
Step 2: Execute codes for a boot up task on reset resetTask. Let us code in a similar
way as the codes for First task. The codes begin to execute from the main and the main
creates and initiates this task and starts the smart OS.