Fully Integrated Folded Cascode OTA with

Common mode feedback

Assigned to Analog track students.

Important Instructions
- This is a group task (max 4 students per group), do not cooperate between groups, otherwise your grade will be
affected.

Objective

This project aims to design and simulate fully differential folded-cascode OTA achieving given specifications. Design
the common mode feedback circuit for FCOTA. Implement the layout for the design and do a post-layout simulation
that achieves the specification.

Description:

The specifications are described in Table.1 according to UMC 65n technology. In addition, the proposed topology is
shown in Fig.1

Specifications
Supply Voltage 1.2 V Closed Loop Gain 2
≥ 70o 10
Phase Margin Closed Loop BW MHz
≥ 0.6 V pk − ≤ 80
Differential Output to − pk OTA Current uA
Swing Consumption
CM Input Range 0 < CM ≤ 0.6 CMFB Current ≤ 40
V uA
Consumption
1 pF 50 dB
Capacitance Load DC Loop Gain
Tabel.1 Specification of FCOTA
Since the CM input range is close to the GND rail → Choose PMOS input devices
 Figure.1. FCOTA Schematic.

Figure.2. common mode feedback circuit Schematic.

Design procedure:
𝑔𝑚
• Design the sizing of a transistor utilizing methodology.
𝐼𝑑
• DC analysis to make certain the right DC operating point of all devices.
• Design the feed-back common mode circuit.
• AC analysis to guarantee the required Gain and phase margin.
• Stability analysis.
• Transient analysis using pulse signal as input to test the stability of two loops.
• Transient analysis using sinewave signal as input to test the output voltage swing.
• Design the layout of active components.
• Verify your design utilizing DRC & LVS.
• Perform a parasitic extraction PEX and post-layout simulation.

The following need to be delivered:

— A technical PPT including:

𝑔𝑚
• Hand analysis calculation from specifications to sizing parameters for FC and CMFB circuits.
𝐼𝑑

• Snap of the final schematic including the optimized dimensions of the proposed devices.

• Table of DC operating points for both designs.

• Snaps of AC results that show the optimized Gain and phase margins.

• Stability result.

• Result for a sinusoidal input signal by plotting the spectrum with comment.

• The floor planning for design with matching patterns for each block.

• Snap of the FCOTA layout.

• The result of verification analyses (clean DRC & LVS).

 • Post layout simulations for all pre-layout results with comments on results.

• Library files submission.

Assessment Criteria:
— Hand analysis calculations ---10%
— Circuit design and implementation and comments --- 30%
— Layout of the proposed design --- 30%
— Targeting the required aspects --- 20%
— PPT--- 10%

Appendix: you can use these lab procedures as a reference link: Google Drive

Best of Luck