Lab_5 Advanced Analog :

Design of Differential amplifier layout (back end)

Contents
Objective:....................................................................................................................................................................
main content: ..............................................................................................................................................................
• Concept of DRCs and LVS ……………………….……………………………………………………………………………………………
• Latch-up effect and antenna rule concept…………………………………………………………………………………………….
• Design the layout of Differential amplifier …………..……………………….……..……………………………………………
• In lab Task ……………………….……..…………………………………………………………………………………………..

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 Objective:
1) To be familiar with the practical concept of DRC and LVS.
2) knowing the definition of latch-up and antenna rules.
3) Design the placement of differential pairs using the interdigitation technique.
4) Design the local routing using the concept of channel for routing.
5) Design the local routing using the concept of channel for routing.
6) Design shielding to input differential signal.

Concept of DRCs rule

Set of rules that guarantees proper transistor and interconnect fabrication despite various
tolerances in each step of processing.
these rules are classified under four categories:
* Minimum width:
if a rectangular wire is excessively narrow, then, owing to fabrication tolerances, it may simply
𝐿
break or at least suffer from a large local resistance: 𝑅 = 𝜌
𝑊∗𝑇𝑤

So, in general, the thicker a layer, the greater its minimum allowable width.
Note: The thickness of the layers is not under the control of the layout designer.
* Minimum spacing:
different layers(masks) must be separated by a minimum spacing not to be shorted or
affected by neighbor’s fab step.

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* Minimum Enclosure:
In PMOS, the NWELL must surround the device with enough margin
given by the fab to guarantee that all parts in the well
despite of the margins through the fab steps.
Also, the contact should be surrounded by enough
enclosure of metal and poly.

* Minimum Extension:
Some geometries must extend beyond the edge of others by a minimum value.
To ensure proper transistor action at the edge, the gate polysilicon must have a
minimum extension beyond the active area.

Finally, modern CMOS technologies typically involve several hundred layout design rules
to solve more advanced problem like antenna damage and electromigration
Here, we can get some design rules to summarize them.

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In major of tools, they are smart enough to alarm in case that a design rule violation is
committed through the layout before we run DRC.
Concept of LVS Check.
An analysis of comparing the netlist of schematic to the netlist of layout to ensure the physical
implementation is express about what is designed.
The check consistence of
1) The devices parameters.
2) The nets connection between the devices.
3) The ports exist in the design.

Concept latch-up effect.

Unwanted low path resistance (RSub & RWell) leads to that there are two parasitics BJTs
in +ve feedback that leads to breakdown the substrate.
Through the inverter, we can explain the latch up:

Let’s assume there is a signal at node A = IBo:

because of RSub there will be sufficient voltage to turn the transistor (Q1) on
IB2=IC1=β*IBo
because of RWell there will be sufficient voltage to turn the transistor (Q2) on
IB1=IC2=𝛽 2 ∗ 𝐼𝐵𝑜
and so on till the 2 BJTs are in saturation forcing constant voltage
between VDD& GND
Here, let’s ask: Because which there is a signal at A?
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* Bounce at VDD & GND
* steep coupling signal edges
How can we solve latch up?
* Spacing: the larger spacing between devices, the bigger base size, the lower β
* Doping: increasing the doping of substrate leads to decrease RSub.
* Isolation: isolate between devices through any method (LOCOS or STI)
* Back gate connection: contacting the back gates (i.e., the n-wells and p-sub) with
metal as close as possible to the transistors to reduce RSub & RWell.

Concept of anntena rule.

The problem occurs through plasma etching of the connection between the output of
first stage and the gate of second stage.

Metal 1 will carry many charges when etched (plasma etching) these charges may lead
to break down the substrate.
How can we deal with this problem?
we can use jumpers of M2 to guarantee the quantity of charges not sufficient to break
down the substrate.

Note: metal1 between 2 M2 layers has a very large charges but they are floating that
will be earthed after CMP(chemical mechanical polishing).
Here, we should know how length should we route before using M2?
The fab puts “Antenna Design Rule” :
𝐴𝑟𝑒𝑎 𝑜𝑓 𝑚𝑒𝑡𝑎𝑙𝑠 𝑓𝑟𝑜𝑚 𝑀1 𝑡𝑜 𝑀𝑥 − 1
< 𝑣𝑎𝑙𝑢𝑒(𝑑𝑒𝑓𝑖𝑛𝑒𝑑 𝑏𝑦 𝑓𝑎𝑏)
𝐴𝑟𝑒𝑎 𝑜𝑓 𝑔𝑎𝑡𝑒

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another smart solution is to use PN junction Emergency in reverse bias mode not to
affect the normal operation .

When charges accumulated, they break down the diode to the GND rather than the
gate. But there are some constrains:
* 𝐴𝑟𝑒𝑎 𝑜𝑓 𝐷𝑖𝑜𝑑𝑒 > 𝐴𝑟𝑒𝑎 𝑜𝑓 𝑔𝑎𝑡𝑒 to be less resistive than the gate
*
𝐴𝑟𝑒𝑎 𝑜𝑓 𝑚𝑒𝑡𝑎𝑙𝑠 𝑓𝑟𝑜𝑚 𝑀1 𝑡𝑜 𝑀𝑥 − 1
< 𝑣𝑎𝑙𝑢𝑒(𝑑𝑒𝑓𝑖𝑛𝑒𝑑 𝑏𝑦 𝑓𝑎𝑏)
𝐴𝑟𝑒𝑎 𝑜𝑓 𝑑𝑖𝑜𝑑𝑒
Layout design of Differiental pairs amplifer.
The schematic that will be development is shown in Fig.1.

Figure 1: Schematic of differential amplifier with input M0 and M1 differential transistor with parameter

L=60n, W=500n, figures=2, and multiplier=8. Dummies devices with parameter L=60n, W=500n, figures=2, and
multiplier=4.

<< Create a cell view of layout for the above schematic << run the comments as shown in Fig.2 to
display the main spacing rules of PDK as shown in Fig.3 << change the option in the layout view as
shown in Fig.4 using E hotkey << using the icon of generate selected form source to generate the
devices and making the matching pattern as shown in Tabel.1 and Fig.5 Note the common diffusion is
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used as the two transistor are common in sources and the even figure lead to source ending devices
<< note that the parameters of top row as shown in Fig.6 (select them and Q hotkey) << note that the
parameters of bottom row as shown in Fig.7 (select them and Q hotkey) << the final placement will be
as shown in Fig.8 Note keep the spacing of 1.06u between the two rows << route the gate connection
and the shielding rout between the two rows as shown in Fig.9 Note the widths and spacing << route
the sources and drains of the top row as shown in Fig.10 << route the sources and drains of the bottom
row as shown in Fig.11 << rout the collect sources and drains of two rows with vertical route of M3 as
shown in Fig.12 << the layout before the guard ring will be as shown in Fig.13 << select all design and
then Shift+g hotkey to create a guard ring of parameters as shown in Fig.14 << routing the dummies
devices that exist at right corners for example as shown in Fig.15 << routing the dummies devices that
exist at left corners for example as shown in Fig.16 << the final layout will be as shown in Fig.17 <<
select the M2_CAD text layer to add the pins of Vin1, and Vin2 by creating label with names as shown
in Fig.18 << select the M3_CAD text layer to add the pins of S, D1, and D2 by creating label with names
as shown Fig.19 << select the M1_CAD text layer to add the pins of GND on the guard ring by creating
label with names as shown Fig.20 << run Caliber DRC and ensure that no error expect density error of
M1 and poly as shown in Fig.21 << run Caliber LVS and make sure that is clean as shown in Fig.22.

Figure 2: comments that read the technology file.

Figure 3: the display of spacing rules of PDK in the virtuoso window.

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 Figure 4: the display options of layout view to make the layout easier.

Dummy M0 M1 M0 M1 M0 M1 M0 M1 Dummy
Dummy M0 M1 M0 M1 M0 M1 M0 M1 Dummy

Tabel.1. the matching pattern of differential pairs transistors.

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 Figure 5: the interdigitation matching shown in layout with added dummies at the edges.

Figure 6: the parameters of the top row of devices.

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 Figure 7: the parameters of the bottom row of devices.

Figure 8: the placement of devices after modify the gate connection to easier the routing of gates.

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 qc

Figure 9: connection of every two gates that faced each other, shield box (red), and the collected gates (input)
(bule)

Figure 10: connection of the top row note that the first rout for source, second for drain of M1, and third for
the drain of M0 and keep the spacing and widths. The connection via is Via M1-M2 of 1 column and 1 row.

Figure 11: connection of the bottom row. note that the first rout for source, second for drain of M1, and third
for the drain of M0 and keep the spacing and widths. The connection via is Via M1-M2 of 1 column and 1 row.

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Figure 12: connection of collected routes for sources and drains. Note that using Via M2-M3 and keep it far as
possible from the M2 to avoid DRC. Note the labels for pin as will be illustrated below.

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 Figure 13: the layout before the guard ring.

Figure 14: guard ring of P-Tap type for N-MOS transistors with 0.3u enclosing and rectangular shape.

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Figure 15: dummies connection of right part. Note all terminals of source, drain, and gate are connected to
guard ring with M1.

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 Figure 16: dummies connection of left part. Note all terminals of source, drain, and gate are connected to
guard ring with M1.

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 Figure 17: the layout after the guard ring and dummies connection.

Figure 18: the label of input pins using M2_CAD text layer for Vin1, Vin2

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 Figure 19: the label of output pins using M3_CAD text layer for S, D1, and D2.

Figure 20: the label of ground pin using M1_CAD text layer for GND.

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Figure 21: the clean result of DRC check expect the density error that will be solved be filling stage of full chip.

Figure 22: the clean result of LVS.

In lab Task
<< Change the matching pattern to be cross quad as shown in Tabel 2. Note you should change the
positions of contact Vias and the routing of differential pair gate connection.

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Dummy M0 M1 M0 M1 M0 M1 M0 M1 Dummy
Dummy M1 M0 M1 M0 M1 M0 M1 M0 Dummy

Tabel.2. the matching pattern (cross quad) of differential pairs transistors.

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