Performance evaluation of N-well/P-sub

photodiodes in 65nm CMOS process

Waqas Ahmad, Markus Törmänen, and Henrik Sjöland
Department of Electrical and Information Technology (EIT), Lund University
Box 118, SE-22100, Lund, Sweden
Email:{Waqas.Ahmad, Markus.Tormanen, Henrik.Sjoland}@eit.lth.se

Abstract—This work explores the n-well/p-substrate lower reverse bias voltages increase the junction
photodiode in a deep submicron CMOS process. A CMOS capacitance, which limits the bandwidth of optical front-
chip is designed featuring different structures of the end. Furthermore in nanometer CMOS technologies more
photodiode. When characterized at a wavelength of 850nm metal layers are typically provided for compact layout of
DC responsivities between 0.12 and 0.16 A/W and 3-dB complex circuits, which results in a higher dielectric
bandwidths of about 6 MHz with a roll-off of about stack and reduced light propagation.
5.5dB/decade are measured. These investigations are very
Modeling photodiodes in nanometer CMOS processes
useful in designing the transimpedance amplifier and
equalizer for a fully integrated optical receiver. According is difficult since many of the technology parameters are
to the authors’ knowledge it is the first reported study on n- not disclosed by the foundries. In order to investigate the
well/p-sub photodiodes in a 65nm CMOS technology. performance we therefore fabricated different n-well/p-
sub photodiodes in STMicroelectronics 65nm CMOS
Keywords—photodiodes, optical communication, CMOS process and characterized them at 850nm wavelength.
technology, optical receivers, photodetectors
II. DESIGN
I. INTRODUCTION
In a standard CMOS process n-well/p-sub, n-well/p-
Optical receivers with integrated photodiode in well, n-well/p+ and p-well/n+ junctions can be used for
standard CMOS technology have clear advantages over light detection. The dopant concentration of n-well is
hybrid implementations when it comes to size and system relatively low compared to that of n+ and p+ diffusions.
cost. Although CMOS technology is not optimized for The depletion region of the n-well/p-sub and n-well/p-
photo detection, these benefits make it very attractive to well junction is thus wider than for the other junctions,
integrate the optical devices on a CMOS chip. However, making them the most suitable for light detection. The
the limited bandwidth offered by CMOS photodiodes is a responsivity of an n-well/p-sub photodiode is 0.378,
bottleneck when designing the fully integrated optical 0.306, 0.233 A/W in 180nm, 130nm, and 90nm
receivers. There has thus been a significant effort to technology, respectively [4], and the 3-dB bandwidth is
design fully integrated Gbit/s optical receivers in standard about 5MHz [1]. This should be compared to the
CMOS technologies, in which different schemes have responsivity of 0.03A/W and the bandwidth of 2.5MHz
been proposed to circumvent the limited bandwidth of for an n+/p-sub photodiode in 65nm CMOS technology
integrated photodiodes. In [1] equalization is used to that was reported in [5].
increase the bandwidth of the optical frontend. Spatially
modulated (SML) photodiodes are sometimes used to
provide higher bandwidth, but the responsivity is reduced
since half the light is blocked. In [2] and [3] SML
photodiodes together with equalization are used to realize
Gbit/s optical receivers. Avalanche photodiodes offer
high bandwidth and high responsivity, but require high
reverse bias voltage (~10V) leading to reliability issues.
Technology scaling brings many advantages in terms
of speed and size for optical receiver building blocks,
such as transimpedance amplifiers, equalizers, limiting
amplifiers, and clock and data recovery circuits.
Unfortunately, the effect of technology scaling is not
favorable for photodiodes. The increased dopant Fig. 1. Cross-section of the photodiodes a) n-well/p-sub PD b) deep n-
concentrations in advanced technology nodes result in well/p-sub/p-well PD c) n-well/p-sub PD with external electric field [6]
smaller depletion regions and also increase carrier
A CMOS chip was designed featuring different n-
recombination in the substrate. Nominal supply voltages
well/p-sub photodiode layouts. The diameter of each
are also reduced, resulting in lower reverse bias voltages
photodiode was 60um, suitable for light detection from a
of the PN junctions. Increased dopant levels together with
multi-mode fiber with a core diameter of 50um. To avoid
______________________________________________
This work has been performed within the project Distributed Antenna Systems, funded by the having silicide deposition over the photodiodes a silicide
Swedish Foundation for Strategic Research (SSF). Authors would like to thank
STMicroelectronics for chip fabrication.
blocking layer was used. In order to characterize the
photodiodes a transimpedance amplifier was integrated
on-chip with each photodiode. A standalone reference
TIA was also implemented on the chip to facilitate
accurate de-embedding of the TIA response. The TIA
was realized using a shunt-shunt feedback topology with
variable feedback resistor to control the gain.
Simplified cross-sections of the photodiodes are shown
in Fig. 1. Fig. 1a shows the classical n-well/p-sub
photodiode. In order to study the effect of photodiode
geometry on the performance two such photodiodes were
designed, one with 29 fingers (fw=1.5um) and one with
17 fingers (fw=3um). Fig. 1b shows a deep n-well/p-
sub/p-well photodiode which was implemented with 24
n-well fingers. An advantage of this structure is that there
are more n-well/p-sub junctions, but at the expense of
junctions present in the 29 finger diode. The bandwidth is
not affected by the photodiode geometry, since this is
mainly determined by the substrate current, which is
independent of n-well geometry. The deep n-well/p-
sub/p-well photodiode shows a higher responsivity of
about 0.15A/W due to more junctions. The n-well/p-sub
photodiode with external electric field has a responsivity
of 0.146A/W at vfield=0V and the responsivity is
increased slightly to 0.16 A/W at vfield=0.5V. The speed
of the photodiode changes a little. Voltages higher than
0.5V will eventually forward bias the PN junctions and
are thus not used. The results are summarized in Table I.
-14
-16

Responsivity [dB(A/W)]
-18
extra junction capacitance. Fig. 1c shows the cross-
-20
section of an n-well/p-sub photodiode, where an external
electric field can be applied to accelerate slowly diffusing -22 n-well/p-sub PD(29 fingers)
carriers in the substrate. This photodiode is divided into -24 n-well/p-sub PD(17 fingers)
deep n-well/p-sub/p-well PD
four n-well regions with six fingers each. The die photo is -26 n-well/p-sub PD (vfield=0V)
shown in Fig. 2. n-well/p-sub PD (vfield=0.5V)
-28 5 6 7 8
10 10 Frequency (Hz) 10 10
Fig. 3. Measured frequency response of the photodiodes
TABLE I
PERFORMANCE SUMMARY OF PHOTODIODES IN 65NM CMOS
Responsivity Bandwidth Roll-off
Photodiode
[A/W] [MHz] [dB/decade]
n-well/p-sub 0.121-0.126 6.25 6
Fig. 2. Die photo (650x500um2) deep n-well/p- 0.150 6.80 5
sub/p-well
III. MEASUREMENTS n-well/p-sub w. 0.146/0.16 6.25/5.7 5.5/6
electric field
For de-embedding purpose the gain of the reference (0V/0.5V)
TIA was first measured. A supply voltage of 1.2V was
then used, resulting in about 500mV reverse bias for the IV. CONCLUSIONS
photodiodes, and S-parameters of the TIA were measured
at different gain settings. The measured S-parameters Different n-well/p-sub photodiode structures have
were then used in Cadence simulations together with the been fabricated in 65nm CMOS technology and
corresponding extracted photodiode capacitance to characterized at 850nm wavelength. DC responsivities
accurately determine the in-circuit frequency response of between 0.121 and 0.16A/W were measured with 3-dB
the amplifiers. bandwidths of about 6MHz and a roll-off of about
In the optical measurements, light from Finisar’s 5.5dB/decade.
VCSEL (HFE4192-581) was coupled into a 2 meter long
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