micfo POWER INTELLECT uP1666Q 2-Phase Synchronous-Rectified Buck Controller General Description The uP16560 is a 2/1-phase synchronous-rectified buck controller specifically designed to work with 2.5V ~ 20V input voltage and deliver high quality output voltage for high performance graphic processor power. The uP1666Q adopts proprietary RCOT™ technology, providing flexible selection of outout LC fiter and excellent transient response to load and line change. ‘The uP'1666Q supports NVIDIA Open Voltage Regulator 2+ with PWMVID feature. The PWMVID input is buffered and ftered to generate accurate reference voltage, and the output voltage is precisely regulated to the reference input. The uP 1666Q uses MOSFET Roa. Current sensing for channel current balance. The uP 16660 also implements a ‘muttifunction pin (FS/OC) for switching frequency selection and OCP threshold setting Other features include power saving control input, and power good output. This part is available in WOFNSx3- 201 package. Ordering Information Order Number | Package “Top Marking uP1666Q0KF | WOFNS:3-20L | _uP16660 Note: (1) Please check the sample/production availabilty with UPI representatives. (2) uP products are compatible with the current IPC/JEDEC J-STD-020 requirements. They are halogen-free, ROHS compliant and 100% matte tin (Sn) plating thet are suit- able for use in SnPb or Pb-free soldering processes. Pin Configuration Oooo oa og cooogaqaa oa for Mobile GPU Power Features ‘Support NVIDIA Open VReg Type-2+ PWMVID Technology Wide Input Voltage Range 2.5V ~ 20V Robust Constant On-Time Control 2/1 Phase Operation ‘Two Integrated MOSFET Drivers with Shoot- Through Protection and Internal Bootstrap Schottky Diode Selectable Soft-Start Multi-Function Pin (FS!OC) for Linear OCP Threshold Setting and Switching Frequency Selection External Compensation Dynamic Output Voltage Adjustment Power Good Indication Over Voltage Protection Under Voltage Protection Over Temperature Protection RoHS Compliant and Halogen Free Applications Middle-High End GPU Core Power High End Desktop PC Memory Core Power Low Output Voltage, High Power Density DC-DC Converters Voltage Regulator Modules UP16660-DS-FO000, June 2017 www.upiesomi.coma micfo POWER INTELLECT Praia Ppa 1-Phase Mode uP1666Q Typical Application Circuit ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.com- MESSE. uP1666Q Typical Application Circuit 2-Phase Mode pia UP16660-DS-FO000, June 2017 3 www.upiesomi.comMESS. uP1666Q Typical Application Circuit Application for Output Above 2V 4 ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.commicro uP1666Q Functional Pin Description PinNo.| Name |Pin Function ; go0r1 [BOOT for Phase 4. Connect a capacitor from this pin to PHASE to form a bootstrap circuit for upper gate driver of the phase 1 2 | UGATE1 |Upper Gate Driver for Phase 1. Connect this pinto the gate of phase 1 upper MOSFET. 3 EN _|Enable. Chip enable 4 PSI _|Power Saving Input. Aninput pin receives power saving control signal from GPU, 5 ViD__|VID. PWMVID input pin. 3 | REFAD, [Reference Adjustment. PWMVDD oufput pin. Connect his pin with an RC integrator to generate REFIN votage. 7 REFN _ [Reference input. Comect this pin o an external reference voltage through a resistor or connect to the output ofthe REFADA circut. 3 Vrer _ [Reference Voltage. 2V LDO voltage output pin. Connect an at least 1uF decoupling capacitor between this pin and GND 9 | FSioc | Switching Frequency and OCP setting. Connect a resistive voltage divider fom VREF to GND to set OCP threshold and switching frequency. 10. | BRIN |Retum for the Reference Circuit. Connect this pin to the around point where output Yoliage is to be regulated " FB |Feedback Pin. This pinis the inverting input ofthe error ampiter. 12 | COMP | Compensation Output. Ths pin is the output ofthe error amplifier Power Good indication. Open-drain structure. Connect tis pin to a voltage source with 13 | _PS009 | a pulup resistor. 14 | UGATE2 [Upper Gate Driver for Phase 2. Connect this pin to the gate of phase 2 upper MOSFET 15 | BooTe [BOOT for Phase 2. Connect a capacitor from this pin to PHASE? to form a bootstrap circuit for upper gate diver ofthe phase 2. Phase Pin for Phase 2. Ths pin is the return path of upper gate driver for phase 2. 16 | PHASE2 |Connect a capacitor ftom this pin to BOOT? to form a bootstrap circuit for upper gate diver of the phase 2 17 | LGATE2 |Lower Gate Driver for Phase 2. Comect this pinto the gate of phase 2 lower MOSFET ta | pvoc _ |SUPPIV Input for the IC. Votlage power supply of the IC. Comet tis pin to @ SV supply and decouple using at least a TUF ceramic capacitor. 19 | LGATE1 |Lower Gate Driver for Phase 1. Comect this pinto the gate of phase 1 lower MOSFET. Phase Pin for Phase 4. This pin is the return path of upper gate driver for phase 1 20 | PHASE1 |Connect a capacitor from this pin to BOOT! to form a bootstrap circuit for upper gate diver of the phase 1 Exposed Pad | GFOUNd. Te this pin fo ground islandiplane through the lowest impedance connection Pos available. GP 19660-0S-F0000, June 2017 3 www.upiesomi.com. micro uP1666Q Functional Block Diagram sooo 8 . Puce: Power OK 00 GATE! prasen fa | cenercen oor cour ‘caret niece vuoare2 LoaTez Resa on ae st Vous Vases: Foy OAD | oe Fee vo 14 en: 6 ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.commicfo POWER INTELLECT uP1666Q ‘Supply Input and Power On Reset The uP 1666Q receives supply input from PVCC and EN pin to provide current to gate drivers and internal control circuit. The uP1666Q continuously monitors PVCC and EN voltages to ensure all power voltages are ready for normal operation. The PVC POR level is typically 4.1V. The EN high level is typically 4V. The uP16660 integrates floating MOSFET gate driver that ‘are powered from the PVCC pin. A bootstrep schottky diode is embedded to facilitate PCB design and reduce the total BOM cost. No external Schottky diode is required in real applications. An external Schottky diode with lower voltage rop can improve the power conversion efficiency. vos = Figure 1. Circuit of Power Ready Detection Voltage Control Loop and PWMVID Function Figure 2llustrates the voltage control loop of the uP 16660. FB and REFINare negative and positive inputs of the Error Amplifier respectively. The Error Amplifier modulates the COMP voltage V...... of buck converter to force FB voltage Vpp f0l10WS Veern~ Functional Description ‘The PWMVID signal from GPU is applied to the VID pin, Which is the input pin of the internal buffer. This buffer ays the role of level shifting, and the output of this buffer is injected into the external RC integrator to generate REFIN voltage, which can be calculated as: Veer v, y¢__R2U(R3-+ RA + RS) Ra+RS_ “ee RI+R2//(R3+R4+R8) R3+R4+R5 Visgs ve RIS + R4+R5) R4+R: We" R2+RI//(R3+R4+R5) R34R4+RS Where Veer i§ the DC voltage of REFIN. Vyger isthe voltage of VREF (typically 2V), and Dis the duty cycie of PWMVID input. The VREF pin s an intetnal LDO, therefore an output decoupling capacitors required. Recommend connecting atleast a 1uF capacitor from VREF pin to local GND. Boot Voltage and Standby Mode The new generation PWMVID structure includes two operation modes other than normal operation: boot mode ‘and standby mode, During boot mode, the GPU stops sending PWMVID signal end the input of the PWMVID buffer is floating, The REFAD\ pin enters high impedance state after the VID pin enters t-state region, and the REFIN voltage can than be calculated as: x R4+R5 R2+R3+R4+R5 During standby mode, other than GPU stopping the PWMVID transaction, an external system standby signal, additionally controls the entry of standby mode. An additional external switch should be connected in parallel with the original PWMVID resistors as shown in Figure 3, to generate the standby mode voltage: Vr. Vener Vase sor = (R34R44+RS)// Rerooy R4+RS Figure 2. Voltage Control Loop Vizee x R24 (R34 R4+RS)/ Reropy R3+RA+RS UP16660-DS-FO000, June 2017 www.upiesomi.commicfo POWER INTELLECT uP1666Q Functional Description Table 1. Controller Operation Frequency Table Figure 3. Standby Mode Configuration Operation Frequency Selection and OCP Setting ocr ta] or jure 4. FS/OC pin for Operation Frequency Selection and OCP Threshold Setting Figure 4 shows the multi-function FS/OC pin for operation, frequency selection and OCP threshold setting. After PVCC, POR, S1, and S2 switches tum on. Internal current source Iecunce flOWS out to FS/OC pin to generate a voltage V,., Then, S2 switch tums off, the FS/OC pin voltage Vea, IS determined by the external voltage divider. Controller samplesiholds the V,., and V,.. to calculate the AV,., and determine the controller operation frequency according to the following table. Level AV, Foy 1 omy 200kHz 2 120mV 300kH2 3 180mV 400kH2 4 240mV SOOkH2 5 300m 600ktZ 6 360mV 800kHZ After the operation frequency is determined, the uP 1666 tums off St and $2 switches and tums on S3 switch for OCP setting. When S3is tumed on, the FS/OC pin voltage: is determined by the external voltage divider, and the FS/ OC pin voltage is connect to the internal OCP circuit for OCP level V,, setting. Vacs the per-phase GND-PHASE voltage when the power stage lov-side MOSFETs are tured on. When per-phase leas’ Rosow ancy ®X08608 Vg, UP1666Q wil limit the phase current. Since the OC mechanism detects per phase current for inductor valley current limiting, the per- phase limited current can be calculated as: I =Moc 41a) hx er-shese hiow-ox) Rosion 2 And the total limited current can be calculated as: Vv. ys = oe ‘osjon) + fakin) ‘Where Nis the operating phase number, Ros.oy is the on- resistance of equivalent per-phase power stage low side MOSFET. If any phase current exceeds Ic seronge» Hh current limit protection is triggered, that phase current will be limited. UP16860's operation frequency and OC level setting is related to resistance of R1 and R2. Therefore, the proper resistance of R1 and R2 is needed. The following is the equation to calculate the value of R1 and R2. Vs wv 4UA” 0.6V +2xVoe wv oo Re loa RI -i fA ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.commicfo POWER INTELLECT uP1666Q Where V,.is the recommended AV, . for operating frequency select and the V,.is the OC level for each phase. Take 300kHz(V,.=120mV) operation frequency and 100mV per-phase OC level as an example, The resistance of Rt and R2 should be: 120mV wv —_V__ys Rl uA “Ov e2xtoomv ~ HS wv —-1| 75K = R: fw is SKQ = SOKO Operation Mode ‘The uP1666Q provides power saving features for platform designers to program platform specific power saving configuration. There are four operation modes: Full-phase CCM, Full-phase DCM, Single-phase CCM, and Single- phase DCM. The uP 1666Q switches between these four ‘operation modes according to the input voltage level of the PSI pin, Table 2 shows recommended PSI setting voltage level of four operation modes. In single-phase operation, the uP1666Q auto-selects phase 1 to be the operating phase. DCM operation mode is activated by two conditions 1. PSI Voltage stays at "Single-Phese” DCM or “Multi Phase DCM’ operation modes, 2. After PGOOD goss high, VID pin recieves a high or low input signal Once the DCM mode is activated, the uP1666Q automatically reduces switching frequency at ight load to maintain high efficiency. As the load current decreases, the rectifying MOSFET is turned off when zero inductor currentis detected, and the converter runs in discontinuous conduction mode. ‘uP16660's power saving feature is a non-latch-off function, the operation mode can be changed anytime after controller POR Table 2. Recommended V . Setting in Four Operation Functional Description MOSFET) Itis recommended to set Vpery,= Veep OF Provide affixed reference voltage for V,.,.,. The Output voltage can be programmed as: our = Vrerw X (1+ RAIR3) Where R1 and R2 are the resistors of the voltage divider on FB pin, The typical application circuit of output above 2V is shown in the section of Typical Application Circuit. ‘Over Voltage Protection (OVP) ‘The OVP is triggered if V,, > 1.5XxVpe,, Sustained 10us. When OVP is activated, the uP1666 turns on all low-side MOSFET and turns off all high-side MOSFET. The over voltage protection is a latch-off function and can only be reset by PVCC re-POR or EN restart. Under Voltage Protection (UVP) ‘The under voltage protection is triggered if V,, <0.5*Vper. sustained 10us. When UVP is activated, the uP16660 turns off all high-side and low-side MOSFET. The under voltage protection is a latch-off function and can only be reset by PVCC re-POR or EN restart, ‘Over Temperature Protection (OTP) The uP1666Q monitors the temperature of itself. If the temperature exceeds typical 150°C, the uP 1686Qis forced into shutdown mode. The over temperature protection is a latch-off function and can only be reset by PVCC re-POR or EN restart. ‘Output Ramp Up Time (T_ramp) The uP 16860 provides 150us, 450us, 900us, and 1.5 ms output ramp up time selection. The outout ramp up time is selected through an external resistor connected between LGATE2 toGND. To ensure LGATE2 functional setting to work normally, the total capacitance from LGATE2 toGND must NOT exceed 12nF (including C,,, capacitance of Low ‘Side MOSFET), The output ramp up time is determined and latched off before output soft-start cycle initiates. The Modes following table shows the four output ramp up time and its Operation Mode Recommended V,., recommended R,g.- FulPhase CoM Tav Table 3. Recommended Rg Setting h CubputRamp Up FultPhase DCM 1.2V Output Ramp Up Time | j__FubPhase OM _| Output Ramp Up Time Single-Phase CCM 0.6 (Tramp) Recommended R, 2 Single-Phase DCM GND 150us 30k22 450us 62k Application of Output Voltage Above 2V pplication of Output Voltage Above coos TD0Ka The uP1686Q supports the application of output voltage above 2V through a voltage divider at FB pin. To support 1500us Open this application, connect a 30k® resistor between LGATEt and GND. To ensure LGATE1 functional setting to work normally, the total capacitance from LGATE! to GND must NOT exceed 12nF (including C.”. capacitance of Low Side UP16660-DS-FO000, June 2017 www.upiesomi.commicro uP1666Q Functional Description Power Up Sequence A built-in softstart function is used to prevent surge current from power supply input during power on. Controller starts the soft-start process right on EN (soft-stert |) If EN asserts in the middle of POR initialization, soft-start process is waiting for PVCC_POR initialization to complete (soft-start Il) The error amplifier is a three-input device. Reference voltage (Vacq,) OF the intemal soft-start voltage (V,,) whichever is smaller dominates the behavior of the non-inverting inputs ofthe error amplifier. Internal soft-start voltage(V.,) starts to ramp up linearly with a slew rate determined by R, resistor after the soft-start cycle is initiated. The output voltage will follow the internal soft-start voltage(V..) and ramp Up lineariy. f there is no fault detected at the end of the soft-start, the controller then asserts PGOOD when the output voltage reaches its target level. The PWMVID signal is ignored before PGOOD goes high anc the output voltage might Not follow Vacen (which is generated by PWMVID network) during T_vid ime, Hence, itis recommended to lat PWMVID be toggled after T_vid time. The T_vid time can be calculated as { T_ramp } en soar )% { T _vid = Vesrae sae ~ "REF BOOT Where, Veer yx is the maximum voltage when PWMVID duty cycle=100%. V.cgx.eooy iS the boot voltage generated by PWMVID network. Tramp is the output voltage ramp up time determined by R, 5, resistor. The following graphs show the power up sequence of uP 16662. Soft Start Il Figure 5. Soft-Start Sequence 10 ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.commicro uP1666Q Absolute Maximum Rating (Note 1) ‘Supply Input Voltage, PVC xan nee OV 0 HEV BOOTs to PHASEX PHASEx to GND oc -0.7V10+28V 10018 $$$ $$$ 8V to 36v BOOTxtoGND oc 0.3Vto+34V $< 1009§ vio sae UGATEx to PHASEX De 02Vi0+8V $< 100793 Vig ry LGATExtoGND De 03Vio+8v 5 1QONS ananaen aman ann nnn cnn nnn cnnnnnnnnrnnnncnnaenccenemnnnceencccennnaene “BY 10 +7 Other Pins 0.3V to +8V ‘Storage Temperature Range a _$$$$$_$$_$ 65°C to +150°C Junction Temperature 1500 Lead Temperature Soldering, 10sec) — — 260°C ESD Rating (Note 2) HBM (Human Body Mode) MM (Machine Mode) —- Package Thermal Resistance (Note 3) WOFN3x3-20L.0,, — WOFNSx3 -201 8,- Power Dissipation, P, @ T, WOFN3X3 - 20 eeennenennnntnnennnnnnnnnntntnnnnnnenennttntnnnnnnes 1.47 Recommended Operation Conditions (Note 4) (Operating Junction Temperature Ran ge a AOC IO HIDES Operating Ambient Temperature Range ———_——- 40°0 10 +85 Input Voltage, V,, ann tcnnnnntnennnnnennnennnnnntnnnnnnnatnnannnnntnmnnenees 2.5Vt0 20) Control Voltage, V, 45Vt05.5V Note 4. Stresses listed as the above Absolute Maximum Ratings may cause permanent damage to the device. ‘These are for stress ratings. Functional operation of the device at these or any other conditions beyond those incicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating concitions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive, Handling precaution recommended. Note 3. 6,, is measured in the natural convection at T, = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 4. The device is not guaranteed to function outside its operating conditions. UP16660-DS-FO000, June 2017 1 www.upiesomi.coma micfo POWER INTELLECT uP1666Q (PVC = 5V, T,= 25°C, unless otherwise specified) Electrical Characteristics Parameter symbol Test Conditions, Min | Typ | Max | Units Supply Input Quiescent Current a iE Suing? DeM, ~ |a00} - | uv Shutdown Current yoy [EN=0V - [2 ][-[a PVCC POR Threshold Veveears | Veves Rising, 39 | 44] 43 |v PVCC POR Hysteresis Vevecis - [os] -[v \VREF Voltage Accuracy 198] 2 | 202] v REF Sourcing Current her io | - | = [ma Control Input: EN Logic Low Threshold Vous - | - [oat v Logic High Threshold Vous 12[-[- |v Internal Pull-down Resistance R, - | 200] - [ke On Time ‘One Shot Width Toy [METRY Noe = 0-8, ~ | 250) = | ns Minimum On Time. Tons - | 80 | - [ns Minimum Off Time Tore un - | 300] = | ns Error Amplifier Open Loop DC Gain ‘A, _ | Guaranteed by Design zo | 80 | - | 0B Trans-conductance om - | 800 | - [ww Maximum Current (Source & Sink) howe - |e] - [wa FERTN FBRTN Curent beam _[EN> 1.4V, no switching - | = [500] uw Soft Start hritialization Time at POR Trcrpon_| Refer to Figure § - | - | 350 [ us Initialization Time Tira _ [Refer to Figure 5 - | - | 250 [ ws Selectable Soft Start Time Tes__ [EN to PGOOD. 250 | — | 2000| us Psi 2-phase CCM 16 | - | - 2-phase DCM 1 | - | 14 Power Saving Mode Logic Vest v ‘phase CCM oa | - | o8 ‘phase DCM - | - | 02 2 ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.commicfo POWER INTELLECT uP1666Q Electrical Characteristics Parameter Symbol Test Conditions min | Typ | Max | Units PWMVID Buffer VID Input Low Level - | - [oelv VID Input High Level 1w2[-[- |v VID Ti-state Delay ~ | 100] - | 1s REFADJ Source Resistance -|2|-|e REFAD4 Sink Resistance -|2/]-/e Gate Drivers Upper Gate Source -[if2 fe Upper Gate Sink -|os/ 1] Lower Gate Source -~| 1) 2/2 Lower Gate Sink - | 04 [08] a Dead Time - || - | os Internal Bootstrap Schottky Diode Forward Voltage Vv, __ [Forward Bias Curent = 3.5mA ~ [oss[ - |v Zero Current Detection Threshold Zero Current Threshold Vc _[GND-PHASE ~ [os | - [aw Protection OCP Threshold Voc __ |GND-PHASE 40 | - | 400 | mv OVP Threshold Vous |VeeMcen - | 150[ - | % OVP Delay ~ | 0] - [os UVP Threshold Vive 4o[ - | 50 | % UVP Delay - | 0] - [os OTP Threshold - | 150[ - [ Power Good Indicator Power Good Indicator Veo - | - [os] v Power Good Leakage Current heen ~ | - [02 UP16660-DS-FO000, June 2017 www.upiesomi.com 13micro uP1666Q Typical Operation Characteristics Power On from EN Power Off from EN a ——— eN2vIDW [ EN 2viow uct 20vi0%7 Gt 20vi0W OUT soomvion vout 0m, 'PGOGO 2viDW - Time : 200us/DWv Time : 200us/Div V2 12V, our = 0.9% Jour = 1A, Rian = OPEN Vin T2V, Vour = 0.9V, Jour = A. Riga = OPEN 1 Phase DCM to 2 Phase CCM 4 Phase CCM to 2 Phase CCM faaaeeeeeenena paaheeeneieaer PS12ViDw i priv Led Vour to0mViOi . reo Fust ravi UGH 1OViOn use tevin use 1000 Time : 20us/Div Time : 20us/Div Vyi= 12V, Voyr = OV, hour = 1A, Vyg2 12V,Voys =O. lye ® 1A, 4 Phase DCM to 2 Phase DCM 4 Phase CCM to 2 Phase DCM ft a eeneenaaaer Psi2vbie » sa wos »| ‘Your 1oomvi0w ust 10V'0% ust tov use 10vibey Sz s0vIBi7 Time : 20us/Div Time : 20us/Div V2 12, Voy = O99. lug = 2A V2 12V,Vogy = OM, oy TA 4 ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.commicro uP1666Q Typical Operation Characteristics PWMIVID Duty Cycle 0% to 100% PWMVID Duty Cycle 100% to.0% VOUT 200mV/DW JOU 200 DW REFIN 200i vrais A viata Under Voltage Protection Over Voltage Protection nderWottge Protect over Voltage Protctos a UG120viiv Ut 20V/DIV 4 a ee wTTT I ott f Lat éviniv Tine usd Tine sud Uyet2 Ne, 88M ec UpetO Ne, 288M eC Over Current Protection PWIMVID: 50% PG000 2v'0m ens Your sonvibiv a) po ‘1 10n04" ‘VOUT S00niVOW vo2vee ist vio By) i aie WU va l Time :20us/Dv Time! tusDiv Vat 12V.Vg OF. 30OKHE, AV, * 40M, Vat TV 209% hg #0A Low Side MOSFET = GI3056 (Rogan 24.22), w= otha, R2 = a7 [Prose bS 0000, June 2017 7 www.upiesomi.commicfo POWER INTELLECT uP1666Q Efficiency (%) VOUT spon. Time : 20us/Div DV, Ve =O.N, ou = 1-50A, Fey 2 Phase CCM, 0 wo 028. Load (V) 5, 2 Phase CCM Operation Efficiency (2%) Typical Operation Characteristics 4 Phase DCM Effici ney 5 15 Load (A) Veq= 8V, 1 Phase DCM Operation 6 ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.commicfo uP1666Q POWER INTELLECT Package Information WOFN3x3 - 20L UUU OO TT p 2000 oaoace taf or-025 Pin tmark 4l_o nono Note 1.Package Outline Unit Description: BSC: Basic. Represents theoretical exact dimension or MIN: Minimum dimension specified MAX: Maximum dimension specified REF: Reference, Represents dimension for reference use only. This value is not a device specification. TYP. Typical. Provided as a general value. This value is not a device specification. 2,Dimensions in Millimeters. 3.Drawing not to scale. 4.These dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.5mm. ension target UP16660-DS-FO000, June 2017 www.upiesomi.com 7micro uP1666Q Important Notice UPI and its subsidiaries reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. UPI products are sold subject to the taerms and conditions of sale supplied at the time of order acknowledgment. However, no responsibilty is assumed by uPI or its subsidiaries for its use or application of any product or circuit; nor for any infringements of patents or other rights of third parties which may result from its use or application, including but not limited to any consequential or incidental damages. No uP components are designed, intended or authorized for use in military, eerospace, automotive applications nor in systems for surgical implantation or life-sustaining. No license is granted by implication or otherwise under any patent or patent rights of uP! or its subsidiaries. COPYRIGHT (c) 2015, UPI SEMICONDUCTOR CORP. uP! Semiconductor Corp. Headquarter Sales Branch Office 9F..No.5, Taiyuan 1st St. Zhubei City, 12F-5, No, 408, Ruiguang Rd. Neihu District, Hsinchu Taiwan, R.O.C. Taipei Taiwan, R.O.C. TEL: 886 3.560.166 FAX : 886.3.560.1888 TEL: 886.2.8751.2062 FAX : 886.2.8751.5064 18 ‘uP16660-DS-FO000, June 2017 \wwaw.upiesomi.com