DRV8320, DRV8320R

DRV8323, DRV8323R
SLVSDJ3D –FEBRUARY 2017 –REVISED MARCH 2022 www.ti.com

Functional Block Diagram (continued)

VM
VDRAIN VM
VM
VCP

GHA
VCP HS
1 µF
>10 µF 0.1 µF VCP SHA
CPH
Charge VGLS
Pump
47 nF
CPL GLA
LS

VGLS
VGLS Gate Driver
Linear
Regulator
VM
30 mA DVDD VCP
DVDD
1 µF Linear GHB
AGND HS
Regulator
Power SHB
PGND
VGLS

ENABLE Digital GLB

Core LS

INHA
Gate Driver

INLA VM
Smart Gate VCP
Drive GHC
INHB
HS
Protection
SHC
INLB
Control VGLS
Inputs
GLC
INHC LS

INLC VCC
Gate Driver
RPU
MODE
Fault Output nFAULT
IDRIVE

VDS

GAIN
VCC
SPC
VREF
AV RSEN
SNC
0.1 µF SOC
SPB
SOB Output
Offset AV RSEN
SNB
Bias
SOA
SPA
CAL
AV SNA RSEN

Figure 14. Block Diagram for DRV8323H

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