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EE/EC/CS & IT/IN CRASH COURSE-2023

Digital Electronics
DAC & CMOS Implementation of Logics DPP-13

1. Which of the following is FALSE for a CMOS 4. The DAC produces analog output corresponding to
Transmission Gate? digital signal in
(a) It has one NMOS and one PMOS connected in off set switch
0
Parallel + S2 –
0.5V 0.5V
(b) Control Input is connected to gate of NMOS and – +

complement of the control input to gate of PMOS Roff = R/7

(c) It has one NMOS and one PMOS connected in 1

S0 R
R
–
Series 0
1 S1 R/2 + V0
(d) It works as a controlled electronic switch
0
1 S2 R/4
2. The circuit shown in the following figure is a _______ 0
– +
gate. V(1) = 0.5V
+ –
V(0) = 0.5 V
VDD
Where S2 is MSB and S0 is LSB
(a) 1’s complement format
A B (b) 2’s complement format
(c) Straight binary format
Out (d) BCD format

5.
A off set switch
0
+ S2 –
0.5V 0.5V
– +

B Roff = R/7

1 R
S0 R
–
0 +
(a) AND (b) OR 1 S1 R/2 V0
(c) NAND (d) NOR 0
1 S2 R/4

– 0
3. What is the minimum number of CMOS required for V(1) = 0.5V
+
V(0) = 0.5 V
constructing a two input NOR logic gate? + –

Where S2 is MSB and S0 is LSB

The following changes are made in the circuit.
(i) Offset switch is removed.
(ii) Switch S2 is replaced by S2 and
(iii) Resistor R/4 is replaced by R/3
Now, the DAC produces analog output corresponding
to digital signal in
(a) 1’complement format
(b) 2’s complement format
(c) straight binary format
(d) BCD format
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6. In the CMOS inverter circuit shown below, if output

gets accidentally shorted, then
+VDD
T2

x y

T1

(a) T1 is at high risk of getting damaged.

(b) T2 is at high risk of geeting damaged.
(c) T1 and T2 both are at high risk of getting damaged.
(d) Neither T1 nor T2 is at risk of getting damaged
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Answer Key
1. (c)
2. (c)
3. (4)
4. (a)
5. (a)
6. (b)

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