Midterm Exam

Design of a Two-Stage Miller Compensated OTA

Mayar Magdy V23010005

Haneen Hossam V23010062
Nirvana Saleh V23010479

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Topology Selection

- Selected Topology is NMOS Based Two Stage Miller Compensated OTA.

- this topology was selected is to achieve the required specs.

- Schematic of the OTA:

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MOSFET Testbench
- NMOS testbench.

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 - PMOS Testbench.

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Design Charts
1. NMOS.
- 𝑔𝑚/𝑔𝑑𝑠 VS 𝑔𝑚/𝐼𝐷

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 𝐼𝐷/𝑊 VS 𝑔𝑚/𝐼𝐷

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 - 𝑉𝑔𝑠 VS 𝑔𝑚/𝐼𝐷

- 𝑉𝐷 𝑆𝑎𝑡 VS 𝑔𝑚/𝐼𝐷

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Design Steps and Calculations

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 2. PMOS.

- 𝑔𝑚/𝑔𝑑𝑠 VS 𝑔𝑚/𝐼𝐷

- 𝐼𝐷/𝑊 VS 𝑔𝑚/𝐼𝐷

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Design Steps and Calculations

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 - 𝑉𝑔𝑠 VS 𝑔𝑚/𝐼𝐷

- 𝑉𝐷 𝑆𝑎𝑡 VS 𝑔𝑚/𝐼𝐷

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 Design Steps and Calculations:

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Design Steps and Calculations

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 DC Analysis

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 - passives values.

𝐶𝑐 600f 𝐹

𝑅𝑧 2.415K Ω

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Simulation

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 - DC operating points (𝐼𝐷, 𝑉𝑔𝑠, 𝑔𝑚, Region) and DC node voltages clearly
annotated.

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 AC Analysis

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 - DC Gain = 63 dB, it achieves the specification.

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2) STB Analysis

- Testbench of the amplifier in closed loop configuration.

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 Loop Gain

- Phase Margin the amplifier is stable.

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3) Transient Analysis

- the input and output signals overlaid.

- SR value from the calculator.

- how the value of the slew rate be improved.

Answer: by increasing the biasing current, especially for the second stage.

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 - Apply a sudden change (vpulse) to the positive input of the amplifier and the
output voltage.

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4) Pole Splitting

Report the phase margin.

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 - the poles and zeros in the same graph.

6- Effect of Large Load Capacitance

high CL , low the Phase margin and slew rate

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