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Copyright 2018 Cengage Learning. All Rights Reserved. May not be copied, scanned, or duplicated, in whole or in part. WCN 02-200-202
Digital Logic and
Microprocessor Design
with Interfacing
Digital Logic and
with Interfacing
2nd Edition
Enoch O. Hwang
La Sierra University
Riverside, California, USA
Digital Logic and Microprocessor Design with © 2018, 2006 Cengage Learning®
Interfacing, Second Edition
ALL RIGHTS RESERVED. No part of this work covered by
Enoch O. Hwang
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Print Number: 01 Print Year: 2016
To my wife Windy,
the love of my life,
for her endless love and support.
CONTENTS
Preface................................................................................................................................... xv
About the Author................................................................................................................... xxi
CHAPTER 1
Introduction to Microprocessor Design 1
1.1 Overview of Microprocessor Design ................................................................................ 3
1.2 Design Abstraction Levels............................................................................................... 6
1.3 Examples of a 2-to-1 Multiplexer.................................................................................... 7
1.3.1 Behavioral Level ................................................................................................. 7
1.3.2 Gate Level........................................................................................................... 9
1.3.3 Transistor Level ................................................................................................ 11
1.4 Introduction to Hardware Description Language ........................................................... 11
1.5 Synthesis ...................................................................................................................... 15
1.6 Going Forward.............................................................................................................. 16
1.7 Problems ...................................................................................................................... 17
CHAPTER 2
Fundamentals of Digital Circuits 18
2.1 Binary Numbers............................................................................................................ 19
2.1.1 Counting in Binary ........................................................................................... 20
2.1.2 Converting between Binary and Decimal .......................................................... 20
2.1.3 Octal and Hexadecimal Notations .................................................................... 23
2.1.4 Binary Number Arithmetic ............................................................................... 25
2.2 Negative Numbers ........................................................................................................ 27
2.2.1 Two’s Complement Representation ................................................................... 27
2.2.2 Sign Extension .................................................................................................. 29
2.2.3 Signed Number Arithmetic ............................................................................... 30
2.3 Binary Switch ............................................................................................................... 32
2.4 Basic Logic Operators and Logic Expressions............................................................... 33
2.5 Logic Gates .................................................................................................................. 35
2.6 Truth Tables ................................................................................................................. 36
2.7 Boolean Algebra and Boolean Equations ....................................................................... 38
2.7.1 Boolean Algebra ............................................................................................... 38
2.7.2 Duality Principle............................................................................................... 41
2.7.3 Boolean Functions and Their Inverses .............................................................. 41
vii
viii Contents
2.8 Minterms and Maxterms .............................................................................................. 46

2.8.1 Minterms .......................................................................................................... 46
2.8.2 Maxterms ......................................................................................................... 49
2.9 Canonical, Standard, and Non-Standard Forms ............................................................ 52
2.10 Digital Circuits............................................................................................................. 53
2.11 Designing a Car Security System .................................................................................. 54
2.12 Verilog and VHDL Code for Digital Circuits ................................................................ 57
2.12.1 Verilog Code for a Boolean Function................................................................ 57
2.12.2 VHDL Code for a Boolean Function................................................................ 58
2.13 Problems ...................................................................................................................... 59
CHAPTER 3
Combinational Circuits 65
3.1 Analysis of Combinational Circuits............................................................................... 66
3.1.1 Using a Truth Table .......................................................................................... 67
3.1.2 Using a Boolean Function ................................................................................ 70
3.2 Synthesis of Combinational Circuits ............................................................................. 72
3.2.1 Using Only NAND Gates ................................................................................. 75
3.3 Minimization of Combinational Circuits ....................................................................... 76
3.3.1 Boolean Algebra ............................................................................................... 77
3.3.2 Karnaugh Maps................................................................................................ 78
3.3.3 Don’t-Cares ...................................................................................................... 85
3.3.4 Tabulation Method ........................................................................................... 86
3.4 Timing Hazards and Glitches........................................................................................ 89
3.4.1 Using Glitches .................................................................................................. 91
3.5 BCD to 7-Segment Decoder.......................................................................................... 92
3.6 Verilog and VHDL Code for Combinational Circuits .................................................... 95
3.6.1 Structural Verilog Code .................................................................................... 95
3.6.2 Structural VHDL Code .................................................................................... 97
3.6.3 Dataflow Verilog Code.....................................................................................101
3.6.4 Dataflow VHDL Code.....................................................................................102
3.6.5 Behavioral Verilog Code ..................................................................................103
3.6.6 Behavioral VHDL Code ..................................................................................104
3.7 Problems .....................................................................................................................106
CHAPTER 4
Standard Combinational Components 112
4.1 Signal Naming Conventions .........................................................................................113
4.2 Multiplexer..................................................................................................................114
4.3 Adder ..........................................................................................................................117
4.3.1 Full Adder .......................................................................................................117
4.3.2 Ripple-Carry Adder.........................................................................................118
4.3.3 Carry-Lookahead Adder .................................................................................120
Contents ix
4.4 Subtractor ...................................................................................................................123

4.5 Adder-Subtractor Combination ....................................................................................125
4.6 Arithmetic Logic Unit..................................................................................................129
4.7 Decoder.......................................................................................................................137
4.8 Tri-State Buffer...........................................................................................................140
4.9 Comparator .................................................................................................................142
4.10 Shifter .........................................................................................................................146
4.11 Multiplier ....................................................................................................................149
4.12 Problems .....................................................................................................................151
CHAPTER 5
Sequential Circuits 157
5.1 Bistable Element..........................................................................................................159
5.2 SR Latch.....................................................................................................................160
5.3 Car Security System—Version 2 ..................................................................................163
5.4 SR Latch with Enable..................................................................................................164
5.5 D Latch .......................................................................................................................164
5.6 D Latch with Enable ....................................................................................................166
5.7 Verilog and VHDL Code for Memory Elements ...........................................................166
5.7.1 VHDL Code for a D Latch with Enable ..........................................................168
5.7.2 Verilog Code for a D Latch with Enable ..........................................................169
5.8 Clock...........................................................................................................................169
5.9 D Flip-Flop..................................................................................................................171
5.9.1 Alternative Smaller Circuit ..............................................................................175
5.10 D Flip-Flop with Enable...............................................................................................176
5.10.1 Asynchronous Inputs.......................................................................................177
5.11 Description of a Flip-Flop............................................................................................180
5.11.1 Characteristic Table .........................................................................................180
5.11.2 Characteristic Equation ...................................................................................180
5.11.3 State Diagram ..................................................................................................180
5.12 Register .......................................................................................................................181
5.13 Register File ................................................................................................................182
5.14 Memories ....................................................................................................................188
5.14.1 ROM................................................................................................................190
5.14.2 RAM ...............................................................................................................192
5.15 Shift Registers .............................................................................................................197
5.15.1 Serial-to-Parallel Shift Register ........................................................................199
5.15.2 Serial-to-Parallel and Parallel-to-Serial Shift Register......................................200
5.15.3 Linear Feedback Shift Register ........................................................................202
5.16 Counters......................................................................................................................205
5.16.1 Binary Up Counter ..........................................................................................205
5.16.2 Binary Up Counter with Parallel Load ............................................................207
x Contents
5.17 Timing Issues...............................................................................................................210

5.18 Problems .....................................................................................................................211
CHAPTER 6
Finite-State Machines 215
6.1 Finite-State Machine Models.......................................................................................217
6.2 State Diagrams............................................................................................................221
6.3 Analysis of Finite-State Machines ...............................................................................224
6.3.1 Next-State Equations .......................................................................................225
6.3.2 Next-State Table ..............................................................................................226
6.3.3 Output Equations ............................................................................................228
6.3.4 Output Table....................................................................................................228
6.3.5 State Diagram ..................................................................................................229
6.3.6 Example...........................................................................................................230
6.4 Synthesis of Finite-State Machines ..............................................................................234
6.4.1 State Diagram ..................................................................................................235
6.4.2 Next-State Table ..............................................................................................236
6.4.3 Next-State Equations .......................................................................................237
6.4.4 Output Table and Output Equations................................................................237
6.4.5 FSM Circuit.....................................................................................................238
6.5 Optimizations for FSMs ..............................................................................................239
6.5.1 State Reduction................................................................................................239
6.5.2 State Encoding.................................................................................................240
6.5.3 Unused States ..................................................................................................243
6.6 FSM Construction Examples.......................................................................................243
6.6.1 Car Security System—Version 3.......................................................................243
6.6.2 Modulo-6 Up-Counter.....................................................................................245
6.6.3 One-Shot Circuit..............................................................................................249
6.6.4 Simple Microprocessor Control Unit ...............................................................251
6.6.5 Elevator Controller Using a Moore FSM ........................................................254
6.6.6 Elevator Controller Using a Mealy FSM .........................................................258
6.7 Verilog and VHDL Code for FSM Circuits ..................................................................261
6.7.1 Behavioral Verilog Code for a Moore FSM......................................................261
6.7.2 Behavioral Verilog Code for a Mealy FSM ......................................................265
6.7.3 Behavioral VHDL Code for a Moore FSM......................................................266
6.7.4 Behavioral VHDL Code for a Mealy FSM ......................................................269
6.8 Problems .....................................................................................................................270
CHAPTER 7
Dedicated Microprocessors 283
7.1 Need for a Datapath ....................................................................................................286
7.2 Constructing the Datapath...........................................................................................287
7.2.1 Selecting Registers ...........................................................................................293
7.2.2 Selecting Functional Units...............................................................................294
Contents xi
7.2.3 Data Transfer Methods....................................................................................295

7.2.4 Generating Status Signals ................................................................................297
7.3 Constructing the Control Unit......................................................................................302
7.3.1 Deriving the Control Signals............................................................................303
7.3.2 Deriving the State Diagram .............................................................................305
7.3.3 Timing Issues ...................................................................................................312
7.3.4 Deriving the FSM Circuit ................................................................................315
7.4 Constructing the Complete Microprocessor ..................................................................320
7.5 Dedicated Microprocessor Construction Examples.......................................................323
7.5.1 Greatest Common Divisor ...............................................................................323
7.5.2 High-Low Number Guessing Game.................................................................330
7.5.3 Traffic Light Controller....................................................................................337
7.6 Verilog and VHDL Code for Dedicated Microprocessors..............................................341
7.6.1 FSM1D Model ...............................................................................................342
7.6.2 FSMD Model ..................................................................................................351
7.6.3 Algorithmic Model ..........................................................................................354
7.7 Problems .....................................................................................................................356
CHAPTER 8
General-Purpose Microprocessors 363
8.1 Overview of the CPU Design .......................................................................................364
8.2 The EC-1 General-Purpose Microprocessor .................................................................366
8.2.1 Instruction Set .................................................................................................366
8.2.2 Datapath..........................................................................................................367
8.2.3 Control Unit ....................................................................................................369
8.2.4 Complete Circuit..............................................................................................373
8.2.5 Sample Program...............................................................................................373
8.2.6 Simulation........................................................................................................375
8.2.7 Hardware Implementation ...............................................................................375
8.3 The EC-2 General-Purpose Microprocessor .................................................................376
8.3.1 Instruction Set .................................................................................................376
8.3.2 Datapath..........................................................................................................377
8.3.3 Control Unit ....................................................................................................379
8.3.4 Complete Circuit..............................................................................................384
8.3.5 Sample Program...............................................................................................384
8.3.6 Hardware Implementation ...............................................................................387
8.4 Extending the EC-2 Instruction Set..............................................................................388
8.5 Using and Interfacing the EC-2....................................................................................391
8.6 Pipelining ....................................................................................................................395
8.6.1 Basic Pipelined Processor.................................................................................395
8.6.2 Pipeline Hazards ..............................................................................................397
8.7 Verilog and VHDL Code for General-Purpose Microprocessors ...................................399
8.7.1 FSM1D Model ...............................................................................................399
8.7.2 FSMD Model ..................................................................................................405
8.8 Problems .....................................................................................................................411
xii Contents
CHAPTER 9
Interfacing Microprocessors 415
9.1 Multiplexing 7-Segment LED Display .........................................................................416
9.1.1 Theory of Operation........................................................................................416
9.1.2 Controller Design ............................................................................................417
9.2 Issues with Interfacing Switches ...................................................................................420
9.3 3 3 4 Keypad Controller ..............................................................................................427
9.4 PS2 Keyboard and Mouse............................................................................................431
9.4.1 Theory of Operation—PS2 Keyboard .............................................................431
9.4.2 Controller Design—PS2 Keyboard ..................................................................432
9.4.3 Theory of Operation—PS2 Mouse ..................................................................436
9.4.4 Controller Design—PS2 Mouse .......................................................................438
9.5 RS-232 Controller for Bluetooth Communication .........................................................444
9.5.1 Theory of Operation—RS-232 ........................................................................445
9.5.2 Controller Design—RS-232 .............................................................................446
9.5.3 Implementation................................................................................................449
9.6 Liquid-Crystal Display Controller................................................................................450
9.7 VGA Monitor Controller .............................................................................................457
9.7.3 Implementation................................................................................................466
9.8 A/D Controller for Temperature Sensor........................................................................467
9.8.3 Implementation................................................................................................474
9.9 I2C Bus Controller for Real-Time Clock.......................................................................475
9.9.3 Implementation................................................................................................483
9.10 Problems .....................................................................................................................484
APPENDIX A
Xilinx Development Tutorial 486
A.1 Starting ISE ................................................................................................................486
A.1.1 Creating a New Project ....................................................................................486
A.1.2 Specifying the FPGA .......................................................................................489
Contents xiii
A.2 Creating a New Schematic Source File.........................................................................492

A.2.1 Drawing Your Schematic Circuit......................................................................493
A.2.2 Creating and Using a Schematic Symbol..........................................................495
A.2.3 Editing a Schematic Symbol ............................................................................497
A.2.4 Using a Schematic Symbol in Another Project.................................................500
A.3 Creating a New Verilog or VHDL Source File..............................................................500
A.4 Setting the Top-Level Module Design File ....................................................................500
A.5 Mapping the I/O Signals..............................................................................................500
A.5.1 Using PlanAhead for Mapping the Pins...........................................................501
A.5.2 Faster Alternative Method for Mapping the Pins.............................................503
A.6 Synthesis and Implementation......................................................................................503
A.7 Programming the Circuit to the FPGA.........................................................................505
A.8 Problems .....................................................................................................................509
APPENDIX B
Altera Development Tutorial 512
B.1 Starting Quartus .........................................................................................................512
B.1.1 Creating a New Project ....................................................................................512
B.1.2 Specifying the FPGA .......................................................................................514
B.2 Using the Graphic Editor .............................................................................................516
B.2.1 Starting the Graphic Editor .............................................................................516
B.2.2 Drawing Tools..................................................................................................516
B.2.3 Inserting Logic Symbols ..................................................................................517
B.2.4 Selecting, Moving, Copying, and Deleting Logic Symbols...............................518
B.2.5 Making and Naming Connections ...................................................................519
B.2.6 Selecting, Moving, and Deleting Connection Lines..........................................521
B.3 Managing Files in a Project .........................................................................................521
B.3.1 Design Files in a Project...................................................................................522
B.3.2 Creating a New Verilog or VHDL Source File .................................................522
B.3.3 Opening a Design File......................................................................................522
B.3.4 Adding Design Files to a Project......................................................................523
B.3.5 Deleting Design Files from a Project................................................................523
B.3.6 Setting the Top-Level Entity Design File .........................................................523
B.3.7 Saving the Project.............................................................................................523
B.4 Analysis and Synthesis.................................................................................................523
B.5 Creating and Using a Logic Symbol .............................................................................524
B.6 Mapping the I/O Signals..............................................................................................525
B.6.1 Faster Alternative Method for Mapping the Pins.............................................527
B.7 Fitting the Netlist and Pins to the FPGA......................................................................527
B.8 Programming the Circuit to the FPGA.........................................................................528
B.9 Problems .....................................................................................................................529
xiv Contents
APPENDIX C
Verilog Summary 533
C.1 Basic Language Elements ............................................................................................533
C.1.1 Keywords.........................................................................................................533
C.1.2 Comments........................................................................................................534
C.1.3 Identifiers.........................................................................................................534
C.1.4 Signals .............................................................................................................534
C.1.5 Numbers and Strings .......................................................................................534
C.1.6 Constants.........................................................................................................535
C.1.7 Data Types.......................................................................................................536
C.1.8 Data Operators ................................................................................................536
C.1.9 Module ............................................................................................................537
C.1.10 Module Parameter ...........................................................................................539
C.2 Behavioral Model ........................................................................................................540
C.2.1 Assignment ......................................................................................................540
C.2.2 initial................................................................................................................541
C.2.3 always ..............................................................................................................542
C.2.4 Event Control ..................................................................................................542
C.2.5 begin-end .........................................................................................................544
C.2.6 if-then-else .......................................................................................................545
C.2.7 case, casex, casez ..............................................................................................545
C.2.8 for ....................................................................................................................546
C.2.9 while ................................................................................................................547
C.2.10 function..........................................................................................................547
C.2.11 Behavioral Model Example ............................................................................548
C.3 Dataflow Model...........................................................................................................548
C.3.1 Continuous Assignment...................................................................................549
C.3.2 Conditional Assignment ..................................................................................549
C.3.3 Dataflow Model Example................................................................................550
C.4 Structural Model .........................................................................................................550
C.4.1 Built-in Gates...................................................................................................550
C.4.2 User-Defined Module ......................................................................................551
C.4.3 Structural Model Example...............................................................................552
APPENDIX D
VHDL Summary 553
D.1 Basic Language Elements ............................................................................................553
D.1.1 Keywords.........................................................................................................553
D.1.2 Comments........................................................................................................554
D.1.3 Identifiers.........................................................................................................554
D.1.4 Data Objects ....................................................................................................554
D.1.5 Data Types.......................................................................................................554
D.1.6 Data Operators ................................................................................................557
D.1.7 ENTITY ..........................................................................................................558
Contents xv
D.1.8 ARCHITECTURE..........................................................................................559
D.1.9 GENERIC.......................................................................................................560
D.1.10 PACKAGE ....................................................................................................562
D.2 Behavioral Model—Sequential Statements...................................................................564
D.2.1 PROCESS........................................................................................................564
D.2.2 Sequential Signal Assignment ..........................................................................564
D.2.3 Variable Assignment ........................................................................................565
D.2.4 WAIT...............................................................................................................565
D.2.5 IF-THEN-ELSE..............................................................................................565
D.2.6 CASE...............................................................................................................566
D.2.7 NULL..............................................................................................................566
D.2.8 FOR ................................................................................................................567
D.2.9 WHILE............................................................................................................567
D.2.10 LOOP ............................................................................................................567
D.2.11 EXIT .............................................................................................................567
D.2.12 NEXT............................................................................................................567
D.2.13 FUNCTION..................................................................................................568
D.2.14 PROCEDURE ..............................................................................................569
D.2.15 Behavioral Model Example............................................................................570
D.3 Dataflow Model—Concurrent Statements....................................................................570
D.3.1 Concurrent Signal Assignment ........................................................................570
D.3.2 Conditional Signal Assignment........................................................................571
D.3.3 Selected Signal Assignment..............................................................................571
D.3.4 Dataflow Model Example................................................................................572
D.4 Structural Model—Concurrent Statements ..................................................................573
D.4.1 COMPONENT Declaration ............................................................................573
D.4.2 PORT MAP .....................................................................................................574
D.4.3 OPEN ..............................................................................................................574
D.4.4 GENERATE ...................................................................................................575
D.4.5 Structural Model Example...............................................................................575
D.5 Conversion Routines.....................................................................................................576
D.5.1 CONV_INTEGER( )......................................................................................576
D.5.2 CONV_STD_LOGIC_VECTOR( , )...............................................................577
Index .....................................................................................................................................578
P R E FA C E
This book is about the digital logic design of microprocessors, and is intended to
provide both an understanding of the basic principles of digital logic design, and how
these fundamental principles are applied in the building of complex microproces-
sor circuits using current technologies. Although the basic principles of digital logic
design have not changed, the design process and the implementation of the circuits
have. With the advances in fully integrated modern hardware computer-aided design
(CAD) tools for logic synthesis, simulation, and the implementation of digital circuits
in field-programmable gate arrays (FPGAs), it is now possible to design and imple-
ment complex digital circuits very easily and quickly
quickly.
Many excellent books on digital logic design have followed the traditional approach
of introducing the basic principles and theories of digital logic design and the building
of separate standard combinational and sequential components. However, students
are left to wonder about the purpose of these individual components and how they
are used in the building of more complex digital circuits, such as microcontrollers
and microprocessors that are used in controlling real-world electronic devices. The
primary goal of this book is to fill in this gap by going beyond the logic principles and
the building of basic standard components. The book discusses in detail how the basic
components are combined together to form datapaths, how control units are designed,
and how these two main components (datapath and control unit) are connected
together to produce actual dedicated custom microprocessors and general-purpose
microprocessors. The book ends with an entire chapter containing many examples on
how microprocessors are interfaced with real-world devices.
Many texts on digital logic design and implementation techniques mainly focus on
the logic gate level. At this low level, it is difficult to discuss larger and more complex
circuits that are beyond the standard combinational and sequential circuits. However,
with the introduction of the register-transfer technique for designing datapaths and
the concept of a finite-state machine for control units, we can easily design a dedicated
microprocessor for any arbitrary algorithm and then implement it on a FPGA chip
to execute that algorithm. The book uses an easy-to-understand ground-up approach
with complete circuit diagrams, and both Verilog and VHDL codes, starting with the
building of basic digital components. These components are then used in the build-
ing of more complex components, and finally the building of the complete dedicated
microprocessor circuit. The construction of a general-purpose microprocessor then
comes naturally as a generalization of a dedicated microprocessor. At the end, stu-
dents will have a complete understanding of how to design, construct, and implement
fully working custom microprocessors.
xvii
xviii PReFACe
Design of Circuits using Verilog and VHDL

Although this book provides coverage on both Verilog and VHDL for all of the
circuits, this information can be omitted entirely while gaining an understanding of
digital circuits and their design. For an introductory course in digital logic design,
learning the basic principles is more important than learning how to use a hardware
description language (HDL). In fact, instructors may find that students can get lost
in learning the principles while trying to learn the language at the same time. With
this in mind, the Verilog and VHDL code in the text is totally independent of the
presentation of each topic and may be skipped without any loss of continuity
continuity.
On the other hand, by studying the HDL codes, the student can not only learn
the use of a hardware description language but also learn how digital circuits can be
designed automatically using a synthesizer. This book provides an introduction to
both Verilog and VHDL and uses the “learn-by-examples” approach. In writing either
Verilog or VHDL code at the dataflow and behavioral levels, the student will see the
power and usefulness of a state-of-the-art hardware CAD synthesis tool.
New to This Edition

In this newly revised second edition, a new chapter on interfacing microprocessors
with external devices has been added. Just knowing how to design and implement a
microprocessor is not sufficient. The main purpose and usage of a microprocessor is
to control external devices. This entire chapter contains many real-world examples on
interfacing microprocessors with external devices. Students can use these examples to
help them in doing their final projects.
Throughout the book, many new examples have been added and old examples
updated. This new edition also covers the usage of both Verilog and VHDL, the two
industry standard hardware description languages for describing digital circuits. All
circuit examples, in addition to having schematic diagrams, also include codes written
in both VHDL and Verilog.
In addition to the Altera FPGA development software, a new section in the
Appendix is added for using the Xilinx FPGA development software. Using either
the Altera or the Xilinx FPGA development software and their respective FPGA
hardware development boards, students can actually implement these microprocessor
circuits and see them execute, both in software simulation and in hardware. The book
contains many interesting examples with complete schematic diagrams and Verilog
and VHDL codes for implementing them in hardware. With the hands-on exercises,
students will learn not only the principles of digital logic design but, also in practice,
how circuits are implemented using current technologies.
To actually see your own microprocessor come to life in real hardware and being
able to control real-world external devices is an exciting experience. Hopefully, this
will help students to not only remember what they have learned but will also get them
interested in the world of microprocessor controllers and digital circuit design.
PReFACe xix
Using This Book

This book can be used in either an introductory or a more advanced course in digital
logic design. For an introductory course with no previous background in digital logic,
Chapters 1 and 2 are intended to provide the fundamental basic concepts in digital
logic design, while Chapters 3 and 4 cover the design of combinational circuits and
standard combinational components. Chapter 5 on the design of sequential circuits
can be introduced and lightly covered.
An advanced digital logic design course will start with sequential circuits in
Chapter 5, and the design of finite-state machines in Chapter 6. Chapters 7 and 8
cover the design of datapaths and control units, and the building of dedicated and
general-purpose microprocessors. Finally, Chapter 9 concludes with the interfacing of
microprocessors with the external world.
It is strongly recommended that a lab component be fully integrated with the lecture.
With an integrated lab, students can have a hands-on learning experience alongside the
theoretical concepts that they have learned in class. In fact, many teachers find that too
often not enough hours are given to the lab. As we probably know, it is often easier to
understand the theory, but to actually implement a circuit and to get it to work requires
much more detail and time. Ready-to-use labs that complement the lecture are available
for download from the teachers’ resource website at https://login.cengage.com.
Chapter 1—Introduction to Microprocessor Design gives an overview of the var-
ious components of a microprocessor circuit and the different abstraction levels in
which digital circuits can be designed.
Chapter 2—Fundamentals of Digital Circuits provides the basic principles and
theories for designing digital logic circuits by introducing binary numbers, the use of
truth tables, Boolean algebra, and how the theories get translated into logic gates and
circuit diagrams. Also a brief introduction to Verilog and VHDL is given.
Chapter 3—Combinational Circuits shows how combinational circuits are ana-
lyzed, synthesized, and optimized.
Chapter 4—Standard Combinational Components discusses the standard combi-
national components that are used as building blocks for larger digital circuits. These
components include the adder, subtractor, arithmetic logic unit, decoder, multiplexer,
tri-state buffer, comparator, shifter, and multiplier. In a hierarchical design, these com-
ponents will be used in the building of the datapath used in the microprocessor.
Chapter 5—Sequential Circuits introduces latches and flip-flops as basic storage
elements and then continues with larger storage components such as registers, register
files, and memories. Special sequential components such as shift registers and counters
are also covered.
Chapter 6—Finite-State Machines shows how finite-state machines are analyzed,
synthesized, and optimized.
Chapter 7—Dedicated Microprocessors first introduces the need for a datapath,
and then explains how a control unit, in the form of a finite-state machine, is used to
xx PReFACe
control the datapath. The chapter expands further showing how dedicated micropro-
cessors are constructed by connecting the datapath and the control unit together as
one coherent circuit.
Chapter 8—General-Purpose Microprocessors continues on from Chapter 7 to
suggest that a general-purpose microprocessor is really a dedicated microprocessor
that is dedicated to only read, decode, and execute instructions. The chapter discusses
the complete design and construction of two simple general-purpose microprocessors
with their own custom instruction set, and how programs written in machine language
are executed on them. The highlight of this chapter and this book is that these two
fully-working general-purpose microprocessors can be implemented in hardware and
have programs executed by them.
Chapter 9—Interfacing Microprocessors provides several complete examples on
how to interface microprocessors with real-world external devices. Examples include
interfacing with a real-time clock IC using the I2C protocol, Bluetooth communication
using RS-232, and drawing graphics on a VGA monitor.
The Appendixes provide tutorials on using both the Altera and Xilinx software
development tools, and summaries on the Verilog and VHDL hardware description
languages.
Supplements
Resources for the book can be found at https://login.cengage.com/. The instructor site
is password protected and requires a verified instructor login to access the site.
Student Resources
● Chapter on Implementation Technologies
● Labs for each chapter
● All of the example codes from the book in VHDL and Verilog
● Altera FPGA development software download
● Xilinx FPGA development software download
Instructor Resources
● Chapter on Implementation Technologies
● Labs for each chapter
● PowerPoint lecture slides
● Solutions to problems at the end of each chapter
● All of the example codes from the book in VHDL and Verilog
● Altera FPGA development software download
● Xilinx FPGA development software download
PReFACe xxi
Acknowledgments
I want to thank Professor Zhiguo Shi, Ph.D., and many of his graduate students from
Zhejiang University, Hangzhou, China, for translating this book into Chinese. In the
process, we have become lasting friends.
I also want to thank the following reviewers for their constructive feedback:
Christopher Doss, North Carolina A&T State University
Eric Durant, Milwaukee School of Engineering
Rajiv JJ. Kapadia, Minnesota State University, Mankato
Emma Regentova, University of Nevada, Las Vegas
Darrin Rothe, Milwaukee School of Engineering
I wish to acknowledge and thank the Global Engineering team at Cengage Learn-
ing for their dedication to this new book:
Timothy Anderson, Product Director; Ashley Kaupert, Associate Media Content
Developer; Kim Kusnerak, Senior Content Project Manager; Kristin Stine, Mar-
keting Manager; Elizabeth Brown, Learning Solutions Specialist; and Alexander
Sham, Product Assistant. They have skillfully guided every aspect of this text’s
development and production to successful completion.
I also want to thank the College of Information Science and Electronic Engineer-
ing at Zhejiang University for inviting me as a visiting professor to teach their Digital
Systems Design course (in English) using the contents of this book. During this time, I
was able to gather many valuable ideas and feedbacks from the bright and enthusiastic
students on how to make the book better. As a result, numerous changes have been
made. This book truly is field-tested.
I also want to thank my school, La Sierra University in sunny California, for giv-
ing me the time off to be at Zhejiang University and to work on this book. It would
have been extremely difficult without this extra time.
Finally, I want to thank my wife, Windy, for her support and giving me the time
to focus and to finish this book.
Enoch O. Hwang, Ph.D.

Riverside, California
ABOUT THE AUTHOR
Enoch Hwang has a Ph.D. in Computer Science from the University

of California, Riverside. He is currently a professor of computer sci-
ence at La Sierra University in Southern California teaching digital
logic and microprocessor design. In 2015, he was invited as a visit-
ing professor to Zhejiang University in Hangzhou, China, where he
taught their Digital Systems Design course. Many new ideas from
that class have been incorporated into this edition of the book.
Even from his childhood days, he has been fascinated with elec-
tronic circuits. In one of his first experiments, he attempted to connect
a microphone to the speaker inside a portable radio through the ear-
phone plug. Instead of hearing sound from the microphone through
the speaker, smoke was seen coming out of the radio. Thus ended that
experiment and his family’s only radio. He now continues his interest
in digital circuits with research in embedded microprocessor systems,
controller automation, power optimization, and robotics.
xxiii
CHAPTER 1
Introduction to
Control Data
Inputs Microprocessor Inputs
'0'
Control Unit 8 Datapath
MUX
ff
Output
Next- State ALU
state Memory
Logic Control 8
Logic Register Signals ff
Register
Status 8
Signals
Control Data
Outputs Outputs
2 CHAPTER 1 IntroductIon to MIcroprocessor desIgn
Electronic devices are an integral part of our lives. Every day and everywhere we
see and use electronic devices, from cellular telephones to electronic billboards, cars,
toys, TVs, elevators, musical greeting cards, personal computers, traffic lights, and
many more. Inside each and every one of them, there is a microprocessor that controls
their operations. Microprocessors are at the heart of all of these “smart” devices.
Their smartness is a direct result of the work of the microprocessor, without which
none of these electronic devices would be able to operate as they do.
There are generally two types of microprocessors: general-purpose microprocessors
and dedicated microprocessors. General-purpose microprocessors, such as the Intel
Core™ i7 CPU shown in Figure 1.1(a) can perform different tasks under the control
of different software programs. General-purpose microprocessors typically are much
more powerful in terms of processing power and speed. However, they usually require
external components for their memory and supporting input/output (I/O) peripherals.
They are used in all personal computers.
Dedicated microprocessors, also known as microcontrollers or application-specific
integrated circuits (ASICs), on the other hand, are designed to perform just one specific
task. For example, inside your cell phone is a dedicated microcontroller that does noth-
ing else but control its entire operation. Microcontrollers therefore are usually not as
powerful (because they do not need to perform so many tasks) as a microprocessor and
are much smaller in size. However, they usually will have the memory and supporting
I/O peripherals included inside the chip, hence the entire system can be on a single chip.
For example, the Atmel ATtiny13A microcontroller shown in Figure 1.1(b) has built-in
flash memory, electrically erasable programmable read-only memory (EEPROM), static
random-access memory (SRAM), general-purpose I/Os, timers, serial interface, and ana-
log-to-digital converters (ADC). Dedicated microcontrollers are used in almost all smart
electronic devices. Although the small dedicated microcontrollers are not as powerful
and are slower in speed as compared to general-purpose microprocessors, they are being
sold much more and are used in a lot more places than general-purpose microprocessors.
© Oleksiy Maksymenko Photography /
Dmitry S. Gordienko /
Alamy Stock Photo
Shutterstock.com
(a) (b)
FIGURE 1.1 Microprocessors: (a) General-purpose Intel Core™ i7 CPU; (b) Dedicated
Atmel ATtiny13A microcontroller.
1.1 overvIew of MIcroprocessor desIgn 3
In this book, I will show you in detail how to design, implement, and interface a
microprocessor. At the end, you will be able to design your own custom microproces-
sor and use it to control your own electronic device. I will use a hands-on approach to
guide you step-by-step through the entire design process with complete circuits that
you actually can implement in hardware. The exciting part is that at the end, you can
actually, very easily and inexpensively, implement your own custom microprocessor in
a real integrated circuit (IC) and see that it really can execute software programs, make
lights flash, or do whatever you have designed it to do.
We will start with the fundamentals of digital logic circuit design in Chapter 2, which
will provide you with a good foundation and basic building blocks for creating larger and
more complex digital circuits. Chapters 3 and 4 will discuss the design of simple digital
circuits and common circuits that are used as building blocks for larger circuits. Chapter
5 talks about the design of memory circuits. Typically, an introduction to digital logic
design course will cover the materials from Chapters 1 to 5 only. Moving on to more
advanced digital logic design, Chapter 6 talks about control unit circuits. Chapter 7 talks
about the datapath and how to connect it with the control unit to produce a dedicated
microcontroller. Chapter 8 extends the dedicated microcontroller from Chapter 7 to
produce a general-purpose microprocessor. Finally, Chapter 9 concludes with examples
of how to interface these microprocessors and microcontrollers in the real world.
1.1 Overview of Microprocessor Design

The microprocessor or microcontroller is an electronic digital logic circuit that is imple-
mented inside an IC chip. Any digital electronic circuit at the lowest physical level
understands only whether there is electricity or no electricity, which is typically rep-
resented by the use of a 1 or a 0. The question is how do we design a microprocessor
so that it can understand the 1s and 0s, and then do something meaningful with that
understanding? To design a microprocessor is to design its logic circuit to do whatever
it is intended to do. To implement the microprocessor is to put the logic circuit of the
microprocessor onto an IC chip.
Previously, making an IC chip with any circuit was a long and expensive pro-
cess. With the advance of large-capacity field-programmable gate array (FPGA) chips,
digital circuits of almost any size can be implemented in a chip easily and quickly.
Moreover, because FPGA chips are erasable, you can use the same FPGA chip over and
over again to implement different circuits. If you put an adder circuit in the FPGA chip,
that chip will be an adder, and if you put a traffic light controller circuit in the FPGA
chip, that chip will be a traffic light controller. So implementing any digital circuit in a
FPGA chip is quite simple. The challenge now is how to design the circuit; how do we
design the adder circuit or the traffic light controller circuit?
A block diagram of a microprocessor circuit is shown in Figure 1.2. As you can
see, it is divided into two main parts: the control unit and the datapath. The datap-
ath is responsible for the execution of all of the microprocessor’s data operations,
such as the addition of two numbers inside the arithmetic logic unit (ALU). The dat-
apath also includes registers for the temporary storage of data and comparators for
testing data values. These and many other functional units are connected together
Control Data
Inputs Inputs
'0'
MUX
ff
Output
Next- State ALU
state Memory
Logic Control 8
Register
Status 8
Signals
Control Data
Outputs Outputs
FIGURE 1.2 Internal parts of a microprocessor.
with multiplexers and data signal lines. The data signal lines are for transferring data
between two functional units. Sometimes, several data signal lines are grouped together
to form a bus. The width of the bus (i.e., the number of data signal lines in the group) is
annotated next to the bus line. In the figure, the bus lines are thicker and are 8-bit wide.
Multiplexers, also known as MUXs, are for selecting data from two or more sources to
go to one destination. In the figure, a 2-to-1 multiplexer is used to select between the
input data and the constant “0” to go to the left operand of the ALU. The output of the
ALU is connected to the input of the register. The output of the register is connected
to three different destinations: (1) the right operand of the ALU; (2) an OR gate used
as a comparator for the test “not equal to 0”; and (3) a tri-state buffer, which is used to
control the output of the data from the register.
Even though the datapath is capable of performing all of the microprocessor’s data
operations, it cannot, however, do it on its own. In order for the datapath to execute the
operations automatically and correctly, a control unit is required. The control unit, also
known as the controller, controls all of the operations of the datapath and therefore,
the operations of the entire microprocessor. The control unit is also called a finite-state
machine (FSM) because it is a machine that executes by going from one state to another,
and there are only a finite number of states for the machine to go to. The control unit is
made up of three parts: (1) the next-state logic; (2) the state memory; and (3) the output
logic. The purpose of the state memory is to remember the current state that the FSM
is in. The next-state logic is the circuit that determines what the machine’s next state
should be. The output logic is the circuit that generates the actual control signals for
controlling the datapath and/or external devices.
Every digital logic circuit, regardless of whether it is part of the control unit or
the datapath, is categorized as either a combinational circuit or a sequential circuit.
1.1 overvIew of MIcroprocessor desIgn 5
A combinational circuit is one where the output of the circuit is dependent only on the
current inputs to the circuit, and therefore has no memory about what has happened
before. For example, an adder is a combinational circuit because it will produce a sum
when given any two input numbers.
A sequential circuit, on the other hand, is dependent not only on the current inputs,
but also on all of the previous inputs. In other words, a sequential circuit has to remem-
ber its past history. For example, a register is a sequential circuit because it can remember
a value indefinitely. Because sequential circuits are dependent on the history, they must
contain memory elements to remember that history. Combinational circuits, on the other
hand, do not need to remember the history, and so they do not have memory elements.
An analogy of the difference between a combinational circuit and a sequential cir-
cuit is the combination lock that we are familiar with. There are actually two different
types of combination locks as shown in Figure 1.3. For the lock in Figure 1.3(a), you
just turn the three number dials in any order you like to the correct number and the lock
will open. For the lock in Figure 1.3(b), you also have three numbers that you need to
turn to, but you need to turn to these three numbers in the correct sequence. If you turn
to these three numbers in the wrong sequence the lock will not open even if you have
the numbers correct. The lock in Figure 1.3(a) is like a combinational circuit where the
order in which the inputs are entered into the circuit does not matter, whereas, a sequen-
tial circuit is like the lock in Figure 1.3(b) where the sequence of the inputs does matter.
Examples of combinational circuits inside the microprocessor include the ALU,
multiplexers, tri-state buffers, and comparators in the datapath, and the next-state logic
and output logic circuits in the control unit. Examples of sequential circuits include
the register for the state memory in the control unit and the registers in the datapath.
Nattawat Kaewjirasit / Shutterstock.com
Cloud7Days / Shutterstock.com
(a) (b)
FIGURE 1.3 Two types of combination locks: (a) the order in which you enter the
numbers does not matter; (b) the order in which you enter the numbers does matter.
All digital logic circuits, whether they are combinational or sequential, are made up of
the three basic logic gates: AND, OR, and NOT gates. From these three basic gates, the most
powerful computer can be made. Furthermore, these basic gates are built using transis-
tors—the fundamental building blocks for all digital logic circuits. Transistors are simply
electronic binary switches that can be turned on and off. The 1s and 0s that we, as com-
puter scientists, often talk about are used to represent the on and off states of a transistor.
To summarize, transistors, as the lowest-level building blocks, are used to build
the basic logic gates. Logic gates are connected together to form either combinational
circuits or sequential circuits. The difference between these two types of circuits is only
in the way the logic gates are connected together. Certain combinational circuits and
sequential circuits are used as standard building blocks for larger circuits and so are
kept in standard libraries. These standard combinational and sequential components
are connected together to form either the datapath or the control unit. Finally, com-
bining the datapath and the control unit together will produce the circuit for either a
dedicated or a general-purpose microprocessor.
1.2 Design Abstraction Levels

Digital circuits can be designed at any one of several abstraction levels. When designing
a circuit at the transistor level, which is the lowest level, you are dealing with discrete
transistors and connecting them together to form the circuit. The next level up in the
abstraction is the gate level. At this level, you are working with logic gates to build the
circuit. In using logic gates, a designer usually creates standard combinational and
sequential components for building larger circuits. In this way, a very large circuit, such
as a microprocessor, can be built in a hierarchical fashion. Design methodologies have
shown that solving a problem hierarchically is always easier than trying to solve the
entire problem as a whole from the ground up. These combinational and sequential
components are used at the register-transfer level to build the datapath and the control
unit in the microprocessor. At the register-transfer level, we are concerned with how the
data is transferred between the various registers and functional units to realize or solve
the problem at hand. Finally, at the highest level, called the behavioral level, we can
describe the behavior or operation of the circuit using a high-level hardware description
language, and we can use a synthesizer, which is equivalent to a compiler, to automati-
cally generate the logic circuit for it. Designing at this level does not require knowledge
of the underlying logic gates and circuits because the synthesizer will automatically
create the logic circuit for you. This is very similar to writing a computer program
using a high-level programming language, and then using the compiler to automatically
translate the program into machine language that the computer can execute.
An important point to realize is that there are many different ways to create
the same functional circuit. Although they are all functionally equivalent, they are
different in other respects, such as the actual circuit (how the transistors or gates
are connected together), size (how big the circuit is or how many transistors or gates
it uses), speed (how long it takes for the output result to be valid), cost (how much
it costs to manufacture), and power usage (how much power it uses). Hence, when
designing a circuit, in addition to being functionally correct, we also should consider
1.3 exaMples of a 2-to-1 MultIplexer 7
the economic versus performance tradeoffs. In this book, we will focus mainly on how
to design a functionally correct circuit with some discussion about how to optimize
the circuit size.
1.3 Examples of a 2-to-1 Multiplexer

As an introduction example, let us look at the design of the 2-to-1 multiplexer from
different abstraction levels. At this point, don’t worry too much if you don’t understand
the details of how all of these circuits are built. This example is intended just to give
you an idea of what the circuit looks like at the different abstraction levels. We will get
to the details in the rest of the book.
The multiplexer is a component that is used a lot in the datapath. An analogy for
the operation of the 2-to-1 multiplexer is similar in principle to a railroad switch in
which two railroad tracks are to be merged onto one track. The switch controls which
one of the two trains on the two separate tracks will move onto the one track. Similarly,
the 2-to-1 multiplexer has two data inputs, d1 and d0, and a select input, s. The select
input determines which data from the two data inputs will pass to the output, y.
Figure 1.4 shows the graphical symbol, also referred to as the logic symbol, for the
2-to-1 multiplexer. From looking at the logic symbol, you can tell how many signal lines
the 2-to-1 multiplexer has, and the name or function designated for each line. For the
2-to-1 multiplexer, there are two data input signals, d1 and d0, a select input signal, s,
and an output signal, y.
d1 d0
1.3.1 Behavioral Level

s 1 0
We can describe the operation of the 2-to-1 multiplexer simply
(using the same names as in the logic symbol) by saying that
y
if s 5 0 then d0 passes to y,
FIGURE 1.4 Logic
otherwise symbol for the
2-to-1 multiplexer.
d1 passes to y
Or more precisely, the value that is at d0 passes to y if s 5 0, and the value that is
at d1 passes to y if s 5 1.
We use a hardware description language (HDL), which is quite similar to many
high-level computer programming languages, to describe the circuit at the behavioral
level. When describing a circuit at this level, you would write basically the same thing
as in the description, except that you have to use the correct syntax required by the
hardware description language. Figure 1.5 shows the description of the 2-to-1 multi-
plexer using the hardware description language called Verilog, and Figure 1.6 shows
the description of the same 2-to-1 multiplexer using another hardware description
language called VHDL, which stands for VHSIC Hardware Description Language
(VHSIC, in turn, stands for Very High Speed Integrated Circuit). Verilog and VHDL
are two standard hardware description languages used for digital logic design.
module multiplexer (
input s,
input d0,
input d1,
output reg y
);
always @ (s or d0 or d1) begin
if (s == 0) begin
y = d0;
end else begin
y = d1;
end
end
endmodule
FIGURE 1.5 Behavioral Verilog code for a 2-to-1 multiplexer.
In the Verilog code shown in Figure 1.5, the declaration of the component begins
with the keyword module followed by the name of the component, which in the exam-
ple, is the user identifier multiplexer. All of the words used in Verilog are case sen-
sitive. The input and output interface signals are listed next using the keywords input
and output. For ease of reference, the user-defined names used for these signals match
those shown earlier in the logic symbol. The always block is followed by its sensitivity
list of signals inside the parentheses. The always block is executed each and every time
when any one of the signals in the sensitivity list changes value. The statements inside
the always block (bracketed by the begin and end keywords) are executed sequen-
tially. In the example, there is only one if-then-else statement inside the block.
Like any if statement in other programming languages, the assignment statement y
= d0 is executed when the condition “s equals to 0” is true, otherwise the assignment
statement y = d1 is executed. For the two assignment statements, the value for the
expression on the right side of the equal sign is assigned to the signal on the left side
of the equal sign. Notice that the output signal y on the left side of the equal sign is
declared as a reg because assignment statements inside the always block cannot
drive a wire data type, but can only drive a register or an integer data type. Finally,
the module is terminated with the keyword endmodule. A summary of the Verilog
language can be found in Appendix C.
In the VHDL code shown in Figure 1.6, the LIBRARY and USE statements are simi-
lar to the “#include” and “using namespace” preprocessor commands in C11. None
of the words used in VHDL is case sensitive, however, in the examples, the keywords
are shown in upper case. The IEEE library contains the definition for the STD_LOGIC
type used in the declaration of signals. The ENTITY section declares the interface for
the circuit by specifying the input and output signals of the circuit. In this example,
there are three input signals of type STD_LOGIC and one output signal also of type
STD_LOGIC. Again, the names used for these signals match those shown earlier in the
logic symbol. The ARCHITECTURE section defines the actual operation of the circuit.
1.3 exaMples of a 2-to-1 MultIplexer 9
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY multiplexer IS PORT (
s, d0, d1: IN STD_LOGIC;
y: OUT STD_LOGIC);
END multiplexer;
ARCHITECTURE Behavioral OF multiplexer IS
BEGIN
PROCESS(s, d0, d1)
BEGIN
IF (s = '0') THEN
y <= d0;
ELSE
y <= d1;
END IF;
END PROCESS;
END Behavioral;
FIGURE 1.6 Behavioral VHDL code for a 2-to-1 multiplexer.
The ARCHITECTURE keyword is followed by a user identifier name and the entity that
it is for. The PROCESS block with its sensitivity list is like the always block in Verilog.
The operation of the multiplexer is defined in the conditional IF-THEN-ELSE statement.
The two signal assignment statements, which use the symbol ,5 to denote the signal
assignment, in conjunction with the IF-THEN-ELSE statement, says that the signal y gets
the value of d0 if s is equal to 0; otherwise, y gets the value of d1. The PROCESS block is
terminated by the END PROCESS statement, and the ARCHITECTURE block is terminated by
the END keyword followed by the name of this architecture. A summary of the VHDL
language can be found in Appendix D.
Having written the behavioral code, either in Verilog or VHDL, we will use a syn-
thesizer to automatically construct the netlist (which is the circuit connections) that
will operate according to the description of the code. As you can see, when designing
circuits at the behavioral level, we do not need to know what logic gates are needed or
how they are connected together. We only need to know their interface and functional
operation, and then describe it using an HDL.
1.3.2 Gate Level

At the gate level, you can draw a schematic diagram or circuit diagram, which shows
how the logic gates are connected together. Two different schematic diagrams of a
2-to-1 multiplexer circuit are shown in Figures 1.7(a) and (b). In Figure 1.7(a), the
circuit uses three NOT gates ( ), four 3-input AND gates ( ), and one 4-input OR gate
( ). In Figure 1.7(b), only one NOT gate, two 2-input AND gates, and one 2-input OR
gate are needed. Although one circuit is larger (in terms of the number of gates needed)
than the other, both of these circuits realize the same 2-to-1 multiplexer function.
Therefore, when we want to actually implement a 2-to-1 multiplexer circuit, we will
want to use the second, smaller circuit rather than the first.
s d1 d0
d0
y s y
d1
(a) (b)
FIGURE 1.7 Gate level circuit diagram for the 2-to-1 multiplexer: (a) circuit using
eight gates; (b) circuit using four gates.
At the gate level, you also can describe the 2-to-1 multiplexer using a truth table or
with a Boolean equation as shown in Figures 1.8(a) and (b), respectively. For the truth
table, we list all possible combinations of the binary values for the three inputs, s, d0,
and d1, and then determine what the output value y should be based on the functional
description of the circuit. We see that for the first four rows of the table when s 5 0,
y has the same values as d0; whereas, in the last four rows when s 5 1, y has the same
values as d1.
The Boolean equation in Figure 1.8(b) can be derived from either the schematic
diagram or the truth table. The first equality in Figure 1.8(b) matches the truth table
in Figure 1.8(a) and also the schematic diagram in Figure 1.7(a). The second equality
in Figure 1.8(b) matches the schematic diagram in Figure 1.7(b). To derive the first
equality equation from the truth table, we look at all of the rows where the output y is
a 1. Each of these rows results in a term in the equation. For each term, the variable is
primed 1 r 2 when the value of the variable is a 0, and unprimed when the value of the
variable is a 1. For example, the first term s rd1rd0 in the equation is obtained from the
first row in the truth table where y is a 1, since s is a 0, d1 is a 0 and d0 is a 1.
s d1 d0 y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
y 5 s rd1rd0 1 s rd1d0 1 sd1d0r 1 sd1d0
1 1 1 1 5 s rd0 1 sd1
(a) (b)
FIGURE 1.8 Gate level description of the 2-to-1 multiplexer: (a) using a truth table;
(b) using a Boolean equation.
1.4 IntroductIon to Hardware descrIptIon language 11
d0
Vcc
s y
d1
FIGURE 1.9 Transistor circuit for the 2-to-1 multiplexer.
1.3.3 Transistor Level

The 2-to-1 multiplexer circuit at the transistor level is shown in Figure 1.9. It contains
six transistors, three of which are P-type metal-oxide semiconductor (PMOS) transis-
tors ( ), and three are N-type metal-oxide semiconductor (NMOS) transistors ( ).
The pair of transistors on the left forms a NOT gate for the signal s, while the two pairs
of transistors on the right form two transmission gates. The transmission gate allows
or disallows the data signal d0 or d1 to pass through, depending on the control signal s.
The top transmission gate is turned on when s is a 0, and the bottom transmission gate
is turned on when s is a 1. Hence, when s is 0, the value at d0 is passed to y, and when
s is 1, the value at d1 is passed to y.
A more detailed discussion about how to design digital circuits at the transistor
level can be found in the online chapter on Implementation Technologies.
1.4 Introduction to Hardware Description Language

The popularity of using hardware description languages (HDL) to design digital cir-
cuits began in the mid-1990s when commercial synthesis tools became available. Two
popular HDLs used by many engineers today are VHDL and Verilog. VHDL was
sponsored and developed jointly by the U.S. Department of Defense and the Institute
of Electrical and Electronic Engineers (IEEE) in the mid-1980s. It was standardized by
the IEEE in 1987 (VHDL-87), and later extended in 1993 (VHDL-93). Verilog, on the
other hand, was first introduced in 1984, and again later in 1988, as a proprietary hard-
ware description language by two companies: Synopsys and Cadence Design Systems.
Both Verilog and VHDL, in many respects, are similar to a regular computer
programming language, such as C. For example, it has constructs for variable assign-
ments, conditional statements, loops, and functions (just to name a few). In a computer
programming language, a compiler is used to translate the high-level source code to
machine code. In HDL, however, a synthesizer is used to translate the source code
to a description of the actual hardware circuit that implements the code. From this
description, which we call a netlist, the actual, physical digital device that realizes the
source code can be made automatically. Accurate functional and timing simulation of
the code is also possible in order to test the correctness of the circuit.
We saw in the previous section how we used Verilog and VHDL to describe the
2-to-1 multiplexer at the behavioral level. HDL also can be used to describe a circuit at
other levels. Figure 1.10 shows the VHDL code for the multiplexer written at the data-
flow level. The main difference between the behavioral VHDL code shown in Figure 1.6
and the dataflow VHDL code is that, in the behavioral code, there is a PROCESS block
statement; whereas, in the dataflow code, there is no PROCESS statement. Statements
within a PROCESS block are executed sequentially as in a computer program, while state-
ments outside a PROCESS block (including the PROCESS block itself) are executed concur-
rently or in parallel. The signal assignment statement, using the symbol <=, is derived
directly from the Boolean equation for the multiplexer, as shown in Figure 1.8(b), using
the built-in VHDL operators: AND, OR, and NOT.
The corresponding Verilog version of the 2-to-1 multiplexer written at the dataflow
level is shown in Figure 1.11. For Verilog, the assign keyword is used for the signal
assignment, and the symbols &, 0 , and , are used for the logical operators AND, OR,
and NOT, respectively.
In addition to the behavioral and dataflow levels, we also can write HDL code at
the structural level. Figure 1.13 shows the Verilog code for the multiplexer written at
the structural level and Figure 1.14 shows the VHDL code. The code is based on the
circuit shown in Figure 1.7(b) and duplicated here in Figure 1.12.
LIBRARY IEEE;
ENTITY multiplexer IS PORT(
y: OUT STD_LOGIC);
END multiplexer;
ARCHITECTURE Dataflow OF multiplexer IS
BEGIN
y <= ((NOT s) AND d0) OR (s AND d1);
END Dataflow;
FIGURE 1.10 Dataflow level VHDL description of the 2-to-1 multiplexer.
input s, d0, d1,
output y
);
assign y = ((~s) & d0) | (s & d1);
endmodule
FIGURE 1.11 Dataflow level Verilog description of the 2-to-1 multiplexer.
1.4 IntroductIon to Hardware descrIptIon language 13
d0 snd0
U2
U1
sn
s U4 y
U3
d1 sd1
FIGURE 1.12 2-to-1 multiplexer circuit.
input s, d0, d1,
output y
);
wire sn,snd0,sd1;
// first parameter is the output;
// remaining parameters are the inputs
not U1(sn,s);
and U2(snd0,sn,d0);
and U3(sd1,s,d1);
or U4(y,snd0,sd1);
endmodule
FIGURE 1.13 Structural Verilog code for the 2-to-1 multiplexer.
----------------- NOT gate -----------------------

LIBRARY IEEE;
ENTITY notgate IS PORT(
i: IN STD_LOGIC;
o: OUT STD_LOGIC);
END notgate;
ARCHITECTURE Dataflow OF notgate IS
BEGIN
o <= NOT i;
END Dataflow;
----------------- 2-input AND gate ---------------
LIBRARY IEEE;
ENTITY and2gate IS PORT(
i1, i2: IN STD_LOGIC;
o: OUT STD_LOGIC);
END and2gate;
FIGURE 1.14 Structural VHDL code for the 2-to-1 multiplexer.

(continued on next page)
ARCHITECTURE Dataflow OF and2gate IS

BEGIN
o <= i1 AND i2;
END Dataflow;
----------------- 2-input OR gate ----------------
LIBRARY IEEE;
ENTITY or2gate IS PORT(
o: OUT STD_LOGIC);
END or2gate;
ARCHITECTURE Dataflow OF or2gate IS
BEGIN
o <= i1 OR i2;
END Dataflow;
----------------- 2-to-1 multiplexer ------------
LIBRARY IEEE;
ENTITY multiplexer IS PORT(
y: OUT STD_LOGIC);
END multiplexer;
ARCHITECTURE Structural OF multiplexer IS
COMPONENT notgate PORT(
i: IN STD_LOGIC;
o: OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2gate PORT(
o: OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2gate PORT(
o: OUT STD_LOGIC);
END COMPONENT;
SIGNAL sn, snd0, sd1: STD_LOGIC;
BEGIN
U1: notgate PORT MAP(s, sn);
U2: and2gate PORT MAP(d0, sn, snd0);
U3: and2gate PORT MAP(d1, s, sd1);
U4: or2gate PORT MAP(snd0, sd1, y);
END Structural;
FIGURE 1.14 Structural VHDL code for the 2-to-1 multiplexer.
In the structural Verilog code shown in Figure 1.13, the keywords (not, and, or) for
the various gates are used. The first parameter for these gate statements is the output from
the gate. The remaining parameters in the statements are the inputs to the gate. The wire
1.5 sYntHesIs 15
keyword defines user identifiers using the wire data type for connecting the gates together
based on the schematic diagram. For example, looking at the schematic diagram, the NOT
gate labeled U1 has s as the input and sn as the output. Hence in the corresponding code,
we have the statement not U1(sn, s). The user-identifier name U1 in the statement
is optional, and is added only for easy identification of the gate in the circuit.
The structural VHDL code shown in Figure 1.14 looks more complicated than
the Verilog code, but it actually does the same thing. The three different gates (notgate,
and2gate, and or2gate) used in the circuit are declared and defined first using the ENTITY
and ARCHITECTURE statements, respectively. After this, the multiplexer is declared (also
with the ENTITY statement). The actual, structural definition of the multiplexer is in the
ARCHITECTURE section for multiplexer. First of all, the COMPONENT statements specify
what components are used in the circuit. The SIGNAL statement declares the three inter-
nal signals (sn, snd0, and sd1) that will be used in the connection of the circuit. Finally,
the PORT MAP statements declare the instances of the gates used in the circuit and specify
how they are connected using the external and internal signals. So if you ignore all of
the preliminary declaration stuff, the last few statements in the VHDL code matches
the statements in the Verilog code.
The focus of this book is not to teach the details of how to write Verilog or VHDL
codes. Because these two hardware description languages are quite similar to high-level
computer languages such as C, which you already should be familiar with, we will take the
approach of learning by examples. Throughout the book, there are Verilog and VHDL
codes for all of the circuits discussed, and in the appendix there is a syntax summary of the
two languages for your reference. By looking at the examples and the summary references,
you should be able to write codes using these languages to describe your digital circuits.
1.5 Synthesis
Given a gate-level circuit diagram, such as the one shown in Figure 1.7, you actually
can get some discrete logic gates and manually connect them together with wires on
a breadboard. Traditionally, this is how electronic engineers actually designed and
implemented digital logic circuits. However, this is not how electronic engineers design
circuits anymore. They write programs, such as the one in Figure 1.6, just like what
computer programmers do. The question is how does the program that describes the
operation of the circuit actually get converted to the physical circuit?
The problem here is similar to translating a computer program written in a high-
level language to machine language for a particular computer to execute. For a computer
program, we use a compiler to do the translation. For translating a digital logic circuit,
we use a synthesizer. Instead of using a high-level computer language to describe a
computer program, we use a hardware description language (HDL) to describe the oper-
ations of a digital logic circuit. Writing a description of a digital logic circuit is similar to
writing a computer program except that a different language is used. A synthesizer then
is used to translate the HDL program into the circuit netlist. A netlist is a description of
how a circuit actually is realized or connected using basic gates. This translation process
from an HDL description of a circuit to its netlist is referred to as synthesis.
The netlist from the output of the synthesizer can be used directly to implement
the actual circuit in a FPGA IC chip. With this final step, the creation of a digital
circuit that is implemented fully in an IC chip can be done easily. The appendices
give a tutorial of the complete process: from writing the Verilog or VHDL code to
synthesizing the circuit and uploading the netlist to a FPGA chip using an FPGA
development board.
1.6 Going Forward

We will now embark upon a journey that will take you from a simple transistor to the
construction of a microprocessor. Figure 1.2 will serve as our guide and map. If you
get lost on the way, and do not know where a particular component fits in the overall
picture, just refer to this map. At the end, you will be able to design your own custom
microprocessor. The exciting part is that this is not just talk and theories. You will be
able to implement and try out all of the circuits on a real FPGA chip. You will be able
to make lights flash, motors run, and execute your own software program on your own
custom microprocessor.
Figure 1.15 is an actual picture of the circuitry inside an Intel Pentium 4 CPU.
When you reach the end of this book, you still may not be able to design the cir-
cuit for the P4 because of lack of resources, but you certainly will know how it is
designed, because you actually will have designed and implemented a real working
microprocessor yourself.
Getty Images / Handout
FIGURE 1.15 The internal circuitry of the Intel Pentium 4 CPU.
1.7 probleMs 17
1.7 PROBLEMS
1.1. Find out the approximate number of general-purpose microprocessors
sold in your country in the most recent year versus the number of dedi-
cated microprocessors sold.
1.2. Compile a list of devices controlled by a microprocessor that you use
during one regular day.
1.3. Describe what your regular daily routine would be like if no electrical
power (including battery power) were available.
1.4. What are the inputs and outputs for the following systems?
a) Traffic light
b) Heart pacemaker
c) Microwave oven
d) Musical greeting card
e) Hard disk drive (not the entire personal computer)
1.5. The speed of a microprocessor is often measured by its clock frequency.
What is the clock frequency of the fastest general-purpose microprocessor
available today?
1.6. Compare some typical clock speeds between general-purpose micropro-
cessors and dedicated microprocessors.
1.7. Summarize the mainstream generations of the Intel general-purpose
microprocessors used in personal computers, starting with the 8086 CPU.
List the year introduced, the clock speed, and the number of transistors in
each.
1.8. The first-generation PC uses the Intel 8088 with approximately 29,000
transistors. Approximately how many transistors are in the Intel Core
i7 (Quad) CPU? Approximately how many transistors are in the Xilinx
Virtex-7 FPGA? Approximately how many transistors are in the Altera
Stratix V FPGA?
1.9. Using Figure 1.11 as a template, write the dataflow Verilog code for the
2-to-1 multiplexer circuit shown in Figure 1.7(a).
1.10. Using Figure 1.13 as a template, write the structural Verilog code for the
1.11. Using Figure 1.10 as a template, write the dataflow VHDL code for the
1.12. Using Figure 1.14 as a template, write the structural VHDL code for the
1.13. Do the Xilinx ISE tutorial in Appendix A.
1.14. Do the Altera Quartus tutorial in Appendix B.
CHAPTER 2
Fundamentals of Digital Circuits
Control Data
Inputs Microprocessor Inputs
'0'
MUX
ff
Output
Next- State ALU
state Memory
Logic Control 8
Register
Status 8
Signals
Control Data
Outputs Outputs
18
2.1 BInARY nUMBeRs 19
Our world is an analog world. Measurements that we make of the physical objects
around us are never in discrete units, but rather in a continuous range. We talk about
physical constants such as 2.718281828. . . or 3.141592. . . . To build analog devices
that can process these values accurately is next to impossible. Even building a simple
analog radio requires very accurate adjustments of frequencies, voltages, and currents
at each part of the circuit. If we were to use voltages to represent the constant 3.14, we
would have to build a component that will give us exactly 3.14 volts every time. This is
again impossible because the manufacturing process is imperfect, and each component
produced will be slightly different from the others. Even if the manufacturing process
could be made as perfect as we can get, we still would not be able to get 3.14 volts from
this component every time we use it. The reason is that the physical elements used in
producing the component behave differently in different environments, such as tem-
perature, pressure, and gravitational force, just to name a few. Therefore, even if the
manufacturing process is perfect, using this component in different environments will
not give us exactly 3.14 volts every time.
To make things simpler, we work with a digital abstraction of our analog world.
Instead of working with an infinite continuous range of values, we use just two values,
1 and 0, to represent the two states, on and off, in a digital electronic circuit. It cer-
tainly is much easier to control and work with two values rather than an infinite range
of values. We call these two values binary values because there are only two of them.
A single 0 or a single 1 is a binary digit or bit for short (where “bi” comes from the first
two letters of the word “binary,” and “t” comes from the last letter of the word “digit”).
This sounds great, but we have to remember that the underlying building block for our
digital circuits is still based on an analog world.
This chapter provides the theoretical foundations for building digital logic circuits
using logic gates, the basic building blocks for all digital circuits. We start with an intro-
duction on working with binary numbers and performing simple arithmetic in binary.
We then will introduce the basic logic gates for building digital circuits. Next, we cover
the basic theory of Boolean algebra, Boolean functions, and how to use and manipulate
them. Many students may find these theories to be boring and difficult to understand,
but let me encourage you to grind through it patiently. The good news is that I will
try to keep them as short and simple as possible. You also will find that many of the
Boolean theorems are very familiar, because they are similar to the algebra theorems
that you already learned in your high school math class. Finally, we conclude with an
example of building a simple digital circuit.
2.1 Binary Numbers

Because digital circuits deal with binary values, we will begin with an introduction to
binary numbers. A bit, having a value of either 0 or 1, can represent only two things
or two pieces of information. It is, therefore, necessary to group together many bits to
represent more pieces of information. A string of n bits can represent 2n different pieces
of information. For example, a string of two bits can represent four different things
20 CHAPTER 2 FUnDAMentALs oF DIGItAL CIRCUIts
using the four unique combinations: 00, 01, 10, and 11. By using different encoding
techniques, a group of bits can be used to represent different information, such as a
number, a letter of the alphabet, a character symbol, or a command for the micropro-
cessor to execute.
Instead of working with the more familiar decimal numbers that consist of decimal
digits, we work with binary numbers, which consist of a string of bits. However, the
use of binary numbers is just a convenient form of representation for a string of bits,
because we can just as well use octal, decimal, or hexadecimal numbers to represent
this group of bits. In fact, you will find that hexadecimal numbers often are used as a
shorthand notation for binary numbers.
2.1.1 Counting in Binary

The decimal number system that we all are familiar with is a positional system. In
other words, the value of the digit is dependent on the position of the digit within the
number. For example, in the decimal number 48, the decimal digit 4 has a greater value
than the decimal digit 8 because it is in the tens position, whereas the digit 8 is in the
unit position.
The binary number system is also a positional system, with the only difference
between the two systems being that the binary system is a base-2 system, using only two
digits, 0 and 1, instead of a base-10 system, using ten digits, 0 to 9. So for the binary
number 101, the leftmost 1 has a larger value than the rightmost 1.
Counting in binary is just like counting in decimal. When we count in decimal, we
count from 0 to 9. After reaching 9 (the last digit) we go back to 0, and have a carry of
a 1 by incrementing the next digit to the left by 1, giving us 10. Doing the same thing in
binary, we count from 0 to 1 (which is the last digit in the binary system). After reach-
ing 1, we go back to 0, and increment the next bit to the left by 1, giving us 10. Although
we use the number 10 in both systems, they are different because one is in base ten and
the other is in base two, and so they have different values. To avoid confusion, we will
use a subscript to denote what base the number is in, for example, 102 is the number
10 in base 2, and 1010 is the same number, but in base 10. Continuing with the count in
binary, the next few numbers in sequence are 11, 100, 101, 110, 111, and 1000.
The binary numbers from 0 to 15 (decimal) are shown in Figure 2.1. The range
from 0 to 15 has 16 different combinations. We need a 4-bit binary number (i.e., a string
of four bits) to represent this range because 24 5 16. The count from 0 to 15 in binary
is shown in the second column. The corresponding octal (base 8) and hexadecimal
(base 16) numbers also are shown in the figure. We will discuss them further in later
sections.
2.1.2 Converting between Binary and Decimal

The decimal value of a binary number can be found just like that for a decimal number,
except that we raise the base number 2 to a power rather than the base number 10 to
a power. The rightmost digit or bit is raised to the power 0, the next digit or bit to the
left is raised to the power 1, then the next one to the power 2, and so on. For example,
the value for the decimal number 658 is
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station, a porter roused himself from his afternoon nap and strolled
slowly down the platform calling "Whitsea! Change here for
Whitsea," in a melancholy sing-song. Guy picked up his stick and
alighted. Would Meriel come herself to meet him? He had asked the
question of himself a hundred times on the journey, and a hundred
times had told himself that he expected far too much.
But Meriel was there, and the delight in his heart showed in his
eyes as he went forward with outstretched hand to welcome her. Her
eyes dropped under his ardent glance, and the colour flushed her
cheek. Guy had seen no one but Meriel. Another voice recalled his
wandering faculties.
"I am just as delighted to welcome you to Whitsea, Mr. Hora, as
Meriel can be."
It was Guy's turn to flush, as he half turned to meet Mrs.
Marven's kindly glance.
"I only saw Miss Challys," he remarked simply.
"That was quite obvious," replied Mrs. Marven, as she took
Guy's hand, "and I am inclined to think that if I had been in your
place I shouldn't have seen anyone else, either. She is a pretty
picture, isn't she?" There was a tender inflection in her voice which
put Guy at his ease.
"There can be no two opinions about that," he answered
heartily.
"Auntie would make me vain, if I were not so already," said the
girl demurely, as she thrust her arm in Mrs. Marven's. "If you'll just
tell the porter which is your luggage, he will see that it is sent on. We
are not more than half a mile from the station, and we thought you
would like to walk to the Hall."
"Nothing could suit me better," declared Guy.
They strolled along the platform talking. Guy's kit bag and
dressing case were tossed out on the platform, and Jessel was
already mounting guard over them. Guy did not recognise his
servant until he was close to him. His surprise was apparent in the
tone of his voice.
"Hullo, Jessel!" he said. "What on earth are you doing here?"
The man touched his hat. "Beg your pardon, sir," he said. "Didn't
you intend me to come? You said nothing, so of course——"
Guy interrupted him. "I thought I had told you! But it doesn't
matter. Just see that the porter has my luggage all right. You can get
the next train back."
He turned away. Cornelius touched his hat. His face expressed
disappointment. Mrs. Marven observed his fallen countenance and
came to the rescue.
"I ought to have told you to bring your man with you," she
remarked to Guy, "and unless you have something you want him to
do for you, you had better let him come to the Hall. I know that the
Captain's man will be delighted that you have brought him, for I don't
mind telling you now, that he detests valeting anyone but his own
master."
With a word of thanks Guy dismissed the subject from his
thoughts. He was supremely indifferent to Jessel's presence. Meriel
was beside him. Nothing else mattered.
CHAPTER XVII
STAR-DUST
Whitsea lies on the estuary of one of those Essex rivers which

flow into the North Sea through a wilderness of shallows. The visitor
who goes to it expecting to find any one of the ordinary attractions of
the average seaside watering-place may make up his mind to be
wofully disappointed. But the visitor with a delight in the
unconventional and the unhackneyed need not fear boredom. The
salt marshes which border the river for miles have a wild beauty
entirely their own. Flowers grow there as if the sea were no enemy to
them. Then the six miles of sheltered water which lie between
Whitsea and the sea give protection from wild weather, which the
yachtsman is not slow to appreciate. So when the days begin to
lengthen the Whitsea River begins to be alive with sailing craft, and
when the summer days really come, it has a population which lives
entirely upon the water.
At Whitsea the Hall was the most prominent residence, even as
Captain Marven was the most distinguished inhabitant. It was just a
simple, kindly English house, at one with its simple, kindly English
inhabitants. The life there was a revelation to Guy. Never before had
he known what it was to be an inmate of a pure unpretentious
English country home.
"You will find us dull, I am afraid," had been Mrs. Marven's
warning when she had invited him, "for excepting some sailing and
later in the year a little rough shooting Whitsea has no attractions."
Dull! Guy had never found a life so full. Every moment of the
day provided a new item of interest.
The house itself was a haven of peace. The long, low white
stone structure stood on a little knoll looking with all its many eyes in
the face of the southing sun. It was girt about with an old garden
where the scent of roses disputed with the perfume of carnations for
supremacy, a garden where tall white lilies stood sentinel over
serried ranks of sweet peas, and gazed down unmoved upon the riot
of colours that filled the borders. Beyond the garden a meadow
dropped down into the saltings, and beyond the saltings the sea wall
kept the tides at bay, and ever the sweet fresh breezes dinted the
surface of the water and lifted the petals of the roses and whispered
stories of the ocean in the ears of those who walked in the garden,
tempting them to venture forth in search of the places where they
were born.
Daily two of the inmates of the Hall responded to the temptation.
Meriel loved the sea. Guy was equally fervent in his adoration, and
there, ever before them, was the means of gratifying their desires in
the shape of the graceful ten-ton cutter Witch lying at her moorings
opposite the house, or the rightly christened little eighteen-footer
Dainty, which ever seemed to chafe at the chain which saved her
from going adrift. Oftentimes Captain Marven made one of the party,
more occasionally Mrs. Marven accompanied them, but there were
occasions when Meriel and Guy found themselves alone. Then when
the breeze sang in Guy's ears, and the spray tasted salt on his lips,
he felt a mad impulse to sail on and on with his precious cargo right
away out of the old life into a totally new one.
The two young people were drawn very close together in those
days. Meriel took no pains to conceal the pleasure she found in
Guy's companionship. Guy made no effort to disguise the fact that
life held only one hope for him. If there was a doubt at the back of his
mind that the hope was foredoomed to be disappointed, he put it
away. He would be happy while he might. Sorrow was for the sad
days of autumn. There was only one jarring note in the symphony. It
was a trifling one and did not affect Meriel. On the first day they went
for a sail they passed an excellently appointed steam yacht lying at
anchor in the fairway of the river. A figure immaculately clad in blue
jacket and white flannels raised a bridge-cap as they passed.
"Hildebrand Flurscheim, by all that's holy," remarked Guy.
"Still searching for his missing pictures," said Meriel laughing.
The thought was an unpleasant one. But Guy was not allowed
to forget it. Flurscheim found out that the Marvens were at their
house and he called, and, undeterred by a cool reception, called
again. Guy could not help but realise that if his host and hostess had
been aware that he was the burglar who had raided the
connoisseur's treasure-house, the coolness accorded Flurscheim
would be nothing to the reception he might expect.
But Captain and Mrs. Marven would have both been horrified at
the mere suggestion that Guy could be guilty of such a deed. They
were fully cognisant of the love-story developing under their eyes,
acquiescing smilingly. They anticipated an idyll. They had watched
Guy carefully, and they had seen no fault in him. He had an
unblemished university career and was apparently sufficiently
endowed with this world's goods. He seemed chivalrous,
honourable, and, above all, deeply in love. Thinking of the days of
their own wooing, they anticipated a happy union.
A week passed, the second week was near its end, when a
shadow was cast on the sunlight of Guy's happiness, and again the
gloom was produced by a letter from Hora, forwarded to him from his
chambers.
"We shall be home on the Monday," wrote the Commandatore.
"Please come and see me on the Tuesday at latest, for I have now
completed my plans, and nothing remains but to put them into
execution. Again let me remind you to do your best to cultivate the
Marven people, if the opportunity arises. Any knowledge you may
acquire concerning them is likely to prove useful."
Guy took the letter with him into the open, where he tore it into
tiny fragments and scattered them to the breeze. Cornelius Jessel
from Guy's bedroom window watched the flying fragments longingly.
So also did another man who, seated on the sea wall some hundred
yards away, was just near enough to realise what Guy was doing.
But neither Cornelius nor the stranger made any efforts to recover
the fragments. Detective Inspector Kenly had no desire to call
attention in so pointed a fashion to the fact that he was visiting
Whitsea.
Guy was unaware of the dual observation, even as Jessel was
unaware that his late landlord was so near to him. His action was
merely prompted by an outbreak of anger at the despicable part he
was expected to play. He did not at first remember that he had not
told the Commandatore of his projected visit. His anger passed, for
he thought that the expectation was founded on a misapprehension.
But the reiteration of Hora's intention, his renewal of the belief that
he, Guy, would be as ready as heretofore to participate in the
carrying out of his plans warned Guy that he must no longer delay
coming to an explanation with the Commandatore. Hora had named
a date. That date would suit Guy as well as another. It would not be
fair to his father to delay any longer.
Guy was unusually silent that morning, and when Meriel joined
him she was surprised that he should be so preoccupied. She feared
to rally him on the subject, for she suspected a reason for his
preoccupation which she would not name to herself.
They went aboard the Witch about nine o'clock. There was a fair
wind from the north, the tide had just begun to ebb and there was
every promise of an ideal day. Gradually Guy's preoccupation melted
away. It was impossible to remain preoccupied on a brilliant summer
morning in Meriel's presence. By the time they had cast off their
moorings he was chattering away freely as ever. Hora was forgotten
for a while. He was remembered later.
"I must be going back to town on Tuesday," Guy said in reply to
a suggestion of some proposed trip for the ensuing week.
"Going back to town," remarked Meriel. There was more than
surprise, there was regret in her tone.
"I shall hate to do so," said Guy, "but I had a letter from my
father this morning and he particularly wishes to see me."
Guy's voice had unconsciously hardened as he spoke. His brow
was knitted and his lips were compressed. He looked up and he
caught sight of a something in her eyes which chased away the
frown.
"Of course, you must go then," said Meriel.
Guy responded to the regretful note in the girl's voice.
"You will be sorry to lose me?" he asked eagerly.
The ghost of a blush fluttered for a moment on her cheeks.
"We shall all be very sorry," she answered equivocally. Guy was
about to press the personal question home, but the sails shivered.
Meriel glanced upward. "Give me the tiller," she said. "You are
steering awfully badly this morning. Why, you've let the Witch run
right up into the wind."
Guy laughed as he vacated his post at the helm. For the
moment he was satisfied. He had seen an answer in Meriel's eyes to
his unspoken question which set his mind at rest. Before the day
was out that question should be answered, but the time was not yet.
The Witch flew along, bending over to the breeze. The river
widened and the banks fell away. The cutter begun to curtsey to the
waves, and now and again a spatter of spray was tossed high in the
air. Guy took the tiller again and Meriel unpacked the luncheon
basket. With appetites sharpened by the breeze they picnicked on
deck. They still pressed onward until the houses on the white cliff
before them begun to be plainly visible. Meriel looked at her watch.
"We are very near Clacton, and it is two o'clock," she remarked.
"Isn't it time we thought about returning?" she added regretfully.
The summer breeze began to show a disposition to change,
veering to the east. Guy put the helm down and went about. The
wind veered still more, though it still held. Guy gave the mainsail
more sheet, and the Witch ran merrily before the breeze over the
slackening tide. An hour passed and the wind became perceptibly
lighter. The afternoon sun shone down from a cloudless sky, while a
purple heat haze gathered on the horizon.
"Luckily we turned back when we did," said Meriel. "We shall
hardly get home on the tide even now. Hadn't we better set the
spinnaker?"
Guy acceded to the request. The breeze freshened again, and
for another hour the water rippled musically under their bows. Then
the breeze died away completely.
Guy shrugged his shoulders. "There's nothing for it but a policy
of masterly inaction," he said. "Don't you think it is time for a cup of
tea?"
He relinquished the tiller to his companion and dived below to
light the stove, and place the kettle upon it. By the time the kettle
boiled an absolute calm had fallen, the sea might have served as a
mirror, the sails hung straight and still, the heat had become almost
oppressive.
Neither Meriel nor Guy were troubled. They were together, and
although the boat seemed motionless they were drifting homewards.
Guy especially was in no anxiety to return. Tea drunk and the cups
washed and put away, Guy brought cushions from the cabin and
made a comfortable couch on deck for Meriel, while he sat by the
helm looking down upon her.
Their talk became personal. Meriel's confidences were those of
a pure-hearted girl, and Guy, listening, longed to repay confidence
with confidence. If he only dared! But his risks were too great. How
could this pure girl be brought to comprehend his point of view? Yet
he knew that some day he must make the effort. Perhaps if she
cared enough for him she might strive to understand. If she cared
enough! Yes, that was the whole question. Her views were so totally
opposed to those which he had imbibed from his earliest youth,
those which he knew now to be hopelessly wrong—not through any
intellectual conviction, but merely by his intuition of what would be
his companion's attitude towards them. He would make her
understand how he came to have held such views and where they
had led him. But not if she did not care. He could not win her under
false pretences. She must know all about him, exactly what he was,
the hidden life which none save Lynton Hora and Myra knew. Yet first
he must know if she did care for him, otherwise such confidence
would be treachery to Hora. His thoughts constrained him to silence.
When his replies became monosyllabic Meriel looking up saw that
his countenance had become overcast. She, too, became silent.
The boat drifted.
Meriel lay back on the cushions. Her eyes half-closed. She
wondered what thought could be troubling her companion. She
glanced up again and met his eyes.
"Something is troubling you," she demanded suddenly.
"Yes, something is troubling me," answered Guy moodily. With
an impulsive gesture the girl held out her hand. Guy grasped it. The
little sunbrowned hand was not withdrawn.
"Can I help?" she asked quietly.
"I cannot tell," he replied. "Until——" The moment had arrived
when he felt that he must give utterance to his thoughts or remain
forever silent. He braced himself to the effort. His voice was almost
harsh.
"Meriel," he said. She started at the sound of her name on his
lips. "Meriel——" He paused.
There was no coquetry in her nature. She understood the
unspoken thought as clearly as if it had been vocalised in a flood of
eloquence.
"Guy," she answered shyly.
The one musical syllable was sufficient. Their glances met.
Each read in the other's eyes the words they longed to hear. Lips
closed on lips.
The sun shone down fiercely. The boat drifted.
"Then you do care for me?" Guy asked presently.
"Do I care?" Meriel looked happily into his face. "If anyone were
to tell you that the sea had become dry you might sooner believe the
tale than that I should have ceased to care for you."
"That is love," said Guy. "I know, for my love for you is also
greater than the ocean."
She was seated beside him. One hand was on the tiller, the
other encircled her waist and she leaned her head on his shoulder
with a sigh of content. The westering sun was dropping to the
horizon, and on the path of gold it painted on the waters the boat still
drifted. Was this to be the omen of their future lot? In his rapture Guy
thrust away all disturbing memories. He loved and he was beloved.
Nothing could alter that one fact. The whole world was transformed
for him. The sun dropped lower still. A rosy flush crept into the sky.
The sea, unflecked by a single ripple, glowed with opal fires. Nothing
broke the stillness. Meriel, too, lived her brief hour in love's fairyland.
The boat still drifted. The mouth of the Whitsea River was
narrowing in upon them. The sea wall stood up blackly against the
pellucid sky. The sun went down behind the purple bank of mist. The
colours faded. The sweet grey calm of summer twilight spread its
mantle over the water. From somewhere on the shore a sandpiper
called to his mate.
Meriel awoke to reality with a start.
"We shall never make our moorings to-night, Guy," she cried. "It
must be eight o'clock, and we are quite four miles from home."
"I should be quite content, dear," he answered, "to drift along
forever."
"You would tell another tale when you came to examine our
store of provisions," she answered merrily.
Guy looked at his watch. "The tide will run for another half hour,"
he said. "No, unless a breeze should spring up the Witch will never
make Whitsea to-night."
"We shall have to leave her," answered Meriel promptly.
"Why not wait for the next tide?" urged Guy.
"No, Auntie will be so anxious," the girl replied. "If we drop
anchor here and stow away comfortably we can easily row home in
the dingey."
Guy stood up and glanced around the horizon. The air was
perfectly still. There was not a movement in the sails.
"We'll let her drift so long as the tide makes, and meanwhile I'll
make things snug," said Guy. The blocks creaked musically as he
gathered in foresail and jib. The topsail fluttered to the deck. It was
warmer work getting in the mainsail and darkness was gathering
rapidly. But the canvas was stowed away at last, the halliards made
fast, every rope coiled away in its place.
"The tide is on the turn," said Meriel. "If we can edge in a little
nearer the south shore the Witch will lie as safely as she would on
her moorings."
Guy hauled up the chain and cast the anchor loose. "When you
are ready, dear," he said.
"You may let go," she cried a minute later. The anchor dropped
with a heavy splash and the rattle of the chain as Guy paid it out
seemed almost a desecration of the silence. When the anchor held,
Guy once more went below to trim and light the riding lamp. By the
time his job was finished and the lamp was swung, the sky had
gained a deeper tint of blue and the stars had begun to sparkle. He
drew the dingey alongside and held out his hand to Meriel.
"You must let me take one oar," she said as she stepped into the
boat. "It will be a stiff pull against the tide."
"When I am tired I'll tell you," he answered. He looked regretfully
at the cutter as he dipped his oars.
"It seems ungracious to leave her," he said, "since the happiest
moments of my life have been passed aboard her."
"Good old Witch," replied Meriel softly.
Night's mantle of darkness and silence enwrapped them. The
stars studded the moonless sky, the plunk of the oars in the rowlocks
and the drip of the water from the blades alone disturbed the perfect
stillness. The boat drove onwards, leaving a trail of light in its wake.
The darkness had made yet another of nature's marvels manifest.
The water was full of phosphorescent light. Guy rested on his oars.
Meriel lifted a handful of water and poured it back into the sea. It was
as if she had poured out a handful of gems. She threw a handful of
the diamonds in the air, and every gem as it fell again into the water
struck gleams of light from the surface. They leaned over the side of
the boat, and here and there in the blackness the lights sparkled for
a moment and were hidden again.
"The water is full of star-dust," said Meriel. "See!" she added
eagerly. Guy followed the direction of her outstretched finger.
A phantom form lighting its way beneath the surface sailed by, a
myriad of the sparkling points accompanying it.
"Even the sea has its spirits," she remarked.
"On a night like this it is possible to idealise even a jelly fish," he
answered whimsically.
He took again to the oars. Few words were spoken between
them.
They came at last to their landing place. Guy made the boat fast
and joined Meriel on the bank. He clasped her lightly in his arms.
"Tell me you love me, Meriel," he demanded almost fiercely.
Her assurance was whispered only, but Guy recognised an
intensity as great as his own. He held her closely to him.
"I have something to—say," he told her. "I cannot ask you to
marry me,"—the words were wrung from him—"until I have told you
something about myself which you do not suspect."
She did not move in his embrace. He could see her eyes shining
in the darkness.
"Nothing you could tell me would make any difference, Guy,"
she answered.
A sharp pain stabbed his heart. "I am not worthy, Meriel," he
said. "And I fear that to-morrow you will tell me so."
"As if it were possible," she answered.
"I have been very happy to-day," he continued. "Such happiness
cannot last. When you know what I am in reality you will be glad to
forget me."
This was more than the detraction of the ardent lover. Meriel
realised that there was the note of real suffering in his voice. She
waited almost with dread for him to continue. And Guy was upon the
point of pouring out his whole story. But the chance passed. A voice
hailed them from the lawn of the Hall.
"Is that you, Meriel?"
"Auntie is watching for our return," she said shyly. "Come."
Guy followed her along the path to the house.
"To-morrow," he said and she understood.
CHAPTER XVIII
CORNELIUS JESSEL DREAMS OF A FORTUNE
The morning was heavy with an almost unnatural calm. By nine

o'clock the sun's rays glowed with the intensity of noon. The flowers
drooped their heads and the leaves hung listlessly. Cornelius Jessel,
passing out of the back way from the Hall, on his way to the
postoffice, had not covered a dozen yards before he paused to mop
his brow with his handkerchief. He bore with him the letter in which
Guy announced to Hora his intention of returning to town. It was the
briefest of notes, disclosing nothing of the intention of the writer. But
it was not the only letter which Jessel carried. In the other envelope
was the report which the shadow man had penned to the Master.
The envelope was stamped and sealed, but Cornelius took it from
his pocket and looked at it and frowned. He replaced it in his pocket
and proceeded on his way. He did not know whether to post it or not.
For the first time since he had undertaken the part of spy upon Guy's
actions he had wilfully suppressed an item of information which had
come into his possession concerning Guy. It was such an important
item of information, too. So important that he had gasped for breath
when he realised what the discovery he had made really meant.
On the previous afternoon and evening he had taken advantage
of Guy's absence to make a careful examination of his master's
property. He had frequently done so before, but without discovering
anything of any interest. But on this occasion he was more fortunate.
He had long been curious concerning the contents of a little silver-
bound box which reposed in a corner of Guy's dressing case. He
had oftentimes made discreet attempts to pick the lock but without
success, and he dared not venture on forcing it lest by damaging the
box he should excite suspicion. He guessed that sooner or later he
would get the opportunity he desired for examining the contents of
the little casket, and the occasion had arrived at last. Guy had left his
keys on the dressing table and one of the bunch fitted the lock.
When the lid was opened, Cornelius, at first sight of its contents,
gave a sniff indicative of disgust. He saw a little lace handkerchief, a
glove, an opera programme, a few withered rose leaves, and an
infinite contempt for the young man he served swept over him. There
was no trace of sentiment hidden away in the heart of Cornelius. But
when he tossed the trumpery aside he drew a long breath of
surprise. Beneath the valueless trifles was concealed an article of
price—a little golden frame enclosing an exquisite miniature on ivory
of a girl with a wealth of fair hair, the painting surrounded with a
circlet of brilliants. At first he did not grasp the significance of the
discovery. The likeness of the miniature to Meriel Challys seemed to
him a full explanation as to why it should be in his employer's
possession. But as he turned the frame over in his hand, counting
the stones in the setting, weighing the trinket delicately on two
fingers to estimate the weight of the gold, he remembered that
somewhere he had seen a description of some such article. Where?
He had not to rack his brain very long before he was able to recall
where he had seen the miniature described. Like many another
person who longs for the prize without incurring the attendant risks,
Cornelius had assimilated every detail which had been made public
concerning the Flurscheim robbery. His mouth had watered at the
published descriptions of the stolen articles and now here—if he was
not greatly mistaken—was one of them in his own hand.
At the heels of this thought came another which almost made
his heart cease beating. Five thousand pounds reward! Five
thousand pounds had been offered for such information as would
lead to the conviction of the thief and to the recovery of the stolen
property. Five—thousand—pounds! Five thousand pounds was lying
waiting for him, Cornelius Jessel. Yet, dazzled as he was by the
prospect of the acquisition of such wealth, he hesitated a long while
before he could persuade himself to make use of the information
which had come into his possession. It was the thought of the Master
which gave him pause. In view of the discovery which he had made
he began to be timorous. He could no longer believe that the
Master's interest in Guy Hora was the interest of the hawk in the
pigeon. Dimly he began to comprehend that unknowingly he was
being used as pawn in a game which he did not comprehend.
Supposing then that any effort of his own to secure that five
thousand pounds should run counter to any plan of the Master's? He
shivered at the thought, for he had a very real fear of the Master's
capacity for mischief. He had locked the miniature and the glove and
the rose leaves away again and set his wits to work to discover a
plan by which he might obtain the five thousand pounds without the
fact that he was the informer being disclosed to anybody. The more
he pondered upon the subject the more convinced he became that
fortune was within his grasp. He could not have made the discovery
at a more opportune moment. He was in the country surrounded by
a lot of simple country folk, and within reach was the victim of the
burglary, who had offered the reward. What better plan could be
conceived than that of taking his information straight to the fountain
head? He would then be able to make his own terms. But he saw
that it would be necessary to have some proof of the correctness of
his statements. He paid another visit to Guy's dressing case after
providing himself with a pencil and oiled paper. With these he made
a series of tracings of the miniature, and, clumsy as they were, yet
he trusted that they might be clear enough for identification. Thus
provided, he determined to take the first opportunity afforded him of
communicating with Mr. Hildebrand Flurscheim.
The determination carried with it as a necessary corollary the
decision to keep his discovery concealed from everybody,
particularly from the Master. He would have felt quite easy in his
mind if he could have assured himself that the Master was not
already acquainted with the fact that Guy possessed the miniature.
On the other hand, Cornelius argued that it was quite possible that
the man who was paying him to keep a watch upon Guy might be
actuated by dread of a confederate playing him false. That was a
strong reason why he should not postpone communicating with
Flurscheim. The reward would go to the first in the field with the
information. Then if the Master were implicated, and if he should be
captured, Cornelius saw safety for himself. Therefore when he wrote
his daily report to the Master of Guy's movements he entirely omitted
to mention the momentous discovery he had made, and yet so
terrified was he that he should bring his employer's vengeance upon
himself by his failure to report it, that a dozen times on the way to the
postoffice he drew the letter from his pocket and looked at it and
considered whether he should not reopen the envelope and add the
information which he had suppressed.
Even when he had dropped the letter into the box he nearly
entered the postoffice to ask for it back again, and only prevented
himself from doing so by declaring to himself that it would be easy to
give the information thereafter if circumstances pointed to the
desirability of his doing so. But once the letter was posted Cornelius
became bolder. The posting of the letter was in the nature of a
definite act committing him to a definite policy. It was no use looking
back, especially with the prospect of five thousand pounds to be
earned by merely speaking a few words. He forgot the heat. He
walked briskly away from the postoffice towards the little
embankment which Whitsea village proudly designated "The Front."
It seemed hotter than ever there. The tide was low and the air
shimmered in the heat reflected from the silvery banks of mud. He
placed his hand on the stone parapet of the low wall and drew it
back hastily. The stone was nearly hot enough to have blistered his
hand. He looked out on the river. Almost opposite him was Mr.
Hildebrand Flurscheim's yacht, and if Cornelius's eyes were to be
trusted Mr. Hildebrand Flurscheim himself was reclining beneath an
awning on the deck. The opportunity was too good to be missed.
Cornelius looked around for a boatman to put him aboard. There
was none visible, and he could not muster up courage to hail the
yacht. The Whitsea hotel showed an inviting open door just handy.
Cornelius felt suddenly thirsty. He accepted the invitation of the open
door, and while he quenched his thirst with a bottle of iced ginger
beer with something in it, he made known his desire to be put aboard
Mr. Flurscheim's yacht to the barmaid.
Before the words were well out of his mouth a man who had
followed Cornelius into the hotel remarked, "I'll put you aboard the
boat with pleasure, Mr. Jessel."
Jessel's first impulse was to fly. To be suddenly accosted by
name when so far as he knew there was no one in Whitsea except
the servants at the Hall who could be aware of his identity, was
disconcerting to say the least. He stifled the impulse as best he
could, and, turning on his heel, faced the speaker. He saw a
pleasant, open-faced man of fifty or thereabouts holding out his
hand.
"Didn't expect to see me here, eh, any more than I expected to
have the pleasure of meeting you? But the world's a little place, and
this sort of weather, if one is likely to knock up against old
acquaintances, there's no spot more likely than where you find a
pretty girl mixing long drinks with a lot of ice in 'em. That's right, isn't
it, miss?"
The barmaid giggled.
"A slice of lemon, a bottle of Schweppe, a lump of ice, and a
suspicion of white satin, if you please," he said before turning again
to Jessel and continuing volubly. "You don't recognise me, eh? Well,
I'm not surprised, for now I come to think of it we haven't exchanged
more than a dozen words in our lives. My name's Kenly."
"Oh!" Cornelius remembered and immediately felt easy in his
mind. He had no reason for dreading his late landlord. He took the
proffered hand.
"This is a surprise," he said. "Who would ever have expected to
meet you here?"
"The same to you," said Kenly. He pointed to Jessel's glass.
"Drink up and have another and tell how you are getting on," he said.
"The missis will be pleased to hear, for she's always telling me that
she's never likely to have such a nice gent in the house to do for,
and she's always cracking on about your being obliged to leave, and
how certain she is never to get another like you."
Cornelius smiled and emptied his glass. "Well, as you insist
——" he said.
"Another of the same," said Kenly affably.
"And what brings you down here?" asked Cornelius.
"Taking my holiday," remarked Kenly expansively. "This is just
the sort of a place that suits me. No sand, no niggers. Plenty of fresh
air and sunshine, a boat to potter about in, and some of the real sort
to drink when you're thirsty, that's the place that suits me down to the
ground, so I'm here. I suppose you're down for a change, too?"
"Not exactly," replied Cornelius. "I have to combine business
and pleasure, too." He took a long draught of the fresh brew which
the barmaid handed to him, and, assuming his most important air, he
changed the topic.
"I suppose Mrs. Kenly is with you?"
"Not much," answered the detective with a broad wink. "I know a
bit too much to bring the missis on a holiday, and, if you are married,
you'd understand."
Cornelius laughed and glanced at the barmaid. "You can't tell
me anything," he said.
"No," answered Kenly. "Half the bachelors to-day know more
than the married people, and that's a fact, ain't it, miss?"
The barmaid giggled again. "You're a caution," she said. The
conversation progressed swimmingly, and ten minutes later
Cornelius embarked on a dingey, having graciously allowed Kenly to
put him aboard Mr. Flurscheim's yacht. He lounged in the stern,
assuming his most important air, while Kenly pulled away at the oars.
He was fully alive to the fact that he would create a much better
impression going aboard thus than if he had been compelled to
borrow a boat and pull himself out to the yacht.
Kenly ran him up alongside, steadied the boat by the side of the
ladder, and then let his dingey drop astern to a sufficient distance to
allow him to observe Cornelius introduce himself to Flurscheim. He
saw that the two men were strangers, and he gathered that the
connoisseur was annoyed at Jessel's invasion of his privacy. He saw
the connoisseur jump up suddenly at something which was said and
begin to pace the deck in manifest agitation. He saw Jessel standing
unmoved, and then after a brief conference both men went down the
companion into the saloon.
The detective immediately realised that there was a chance of
his learning what errand had taken Jessel to the yacht. Half a dozen
strokes took him alongside again, and, making his painter fast to the
yacht's anchor chain, he stood up in the dingey as it drifted level with
an open port. As he had suspected the porthole gave upon the
saloon, and as the dingey came opposite he could hear two voices in
excited colloquy. One was easily recognised as Jessel's, and the
other Kenly had just as little difficulty in recognising as Flurscheim's.
"Is that anything like the face on one of your miniatures?" said
Jessel.
"I could swear to it," said Flurscheim.
"And the portrait—is it like anyone you know?" asked the valet.
"You've seen it," cried the Jew eagerly. "You must have done, for
the miniature is so like Miss Challys that she might have sat for the
portrait."
"I have seen it and I can tell you where it is at the present
moment," answered the valet.
"Where? Where?" cried the Jew eagerly.
"You don't expect me to tell you straight away, do you?" asked
Jessel in an injured tone.
The Jew took no notice. "And the other boxes and the pictures
—can you tell me where my Greuze is?"
"No, I can't, at least not at present," said the valet coolly, "but I
reckon that if once I put you on the track of one of the things that has
been stolen it won't be my fault if you don't find out where the rest of
'em are."
"Well, well," said Flurscheim, impatiently, "tell me where the
miniature is?"
There was silence and the detective listened impatiently.
"Have you lost your tongue?" demanded Flurscheim angrily.
"What about the reward you offered?" said Jessel. "Five
thousand pounds, wasn't it, for such information as shall lead to the
conviction of the thieves or the recovery of the stolen property?"
"You shall have the reward, all right," said Flurscheim
impatiently.
"I'm not misdoubting your word," said Jessel, "but in cases like
this it's better to 'ave everything in black and white. 'Ave it in black
and white, that's my motto."
Kenly heard the connoisseur give a grunt of disgust, and he
smiled. He could even hear the scratching of a pen on paper. Then
Flurscheim's voice remarked sharply:
"Mind, I'll give nothing to any confederate in the robbery. If you
have had anything to do with it and will make a clean breast of the
matter, I'll do my best for you, but I'm not going to be blackmailed by
any d——d thief."
The detective smiled again at the injured tone of Jessel's reply.
"I'm a respectable man, Mr. Flurscheim, though I am a poor one, an'
the hinformation 'as come to me quite unexpected like. If I was rich
I'd be 'appy to tell you all I know for the cause of justice, but being
only poor, I've my old age to think of."
"Well, I only warned you, that's all," grumbled Flurscheim.
"Which there was no need," answered Cornelius with dignity.
"And there's another matter," he added, and now the detective could
detect a note of anxiety in his voice. "There's them as is connected
with this job that won't stick at nothing to get even with them as gives
'em away, if they has so much as a hint as to who done it. You'll have
to give me your word of honour as a gentleman as you'll not so much
as mention my name, or my life'll not be worth two pennorth of gin."
This time Flurscheim was silent a while before he replied.
"If I don't know your name it is not possible for me to mention it."
"You can easy find out," answered Jessel, "when I tell you what I
have to tell you."
"I promise," replied Flurscheim shortly.
Jessel dropped his voice, but, low as it was, the detective's keen
ears overheard every word of the information which was imparted.
He was thunderstruck at the intelligence that a part of the stolen
property was in the possession of Guy Hora. He could not conceive
the motive which had prompted Jessel to disclose the fact, even if it
were true. He wanted time to arrange his ideas on the subject. But
he listened eagerly to every word that passed. He missed not a word
of the long conversation that ensued when Jessel had imparted the
information he possessed. He drank in all Flurscheim's questions
and all the valet's answers, and was so anxious to lose nothing of
what passed that he had barely time to cast the boat loose and drift
astern when he heard them rise to leave the saloon. Still he
presented a picture of perspiring innocence when he pulled up
alongside to take his late lodger back to the quay.
Cornelius was obviously elated. "Sorry to 'ave kept you so long,
Kenly," he remarked. "But I 'ad to wait for an answer to something.
We must have another drink."
They had it and the detective learned that Cornelius was
expecting to return to town the following day.
CHAPTER XIX
INSPECTOR KENLY REPORTS
Although Cornelius had been entirely unaware of the fact, his

late landlord had arrived at Whitsea by the same train as himself,
and had been keeping a sharp eye on him, and if it were possible, a
still sharper eye on Guy Hora. But Kenly's observation had been
unproductive until the time when he obeyed the impulse to make
himself known to Jessel. He had been impelled to do so by sheer
desperation at having passed, from a professional point of view, one
of the most unprofitable fortnights of his life. He had not anticipated
any remarkable revelations when he had followed Cornelius into the
hotel bar, and when he finally bade his old tenant good-bye, he had
no need to force a spice of heartiness into the greeting.
Directly after Jessel left him he felt the necessity for rearranging
all his theories, but at the same time he was equally alive to the
desirability of getting to work upon the new clue which was in his
possession. There was now nothing to keep him in Whitsea. He had
learned of Guy's intention to return to London the following day, and
he determined to be in town before him. There would be plenty of
time to decide upon the best course to pursue during the journey.
He went into the hotel, packed his bag, and paid his bill in a
desperate hurry, for the hotel omnibus was at the door.
He caught his train and was thankful to find so few people
travelling that he could get a compartment to himself. He could
marshal his ideas better in solitude. Still, arrange them and
rearrange them as he might, he could get no nearer a reasonable
explanation of the relationship of the various parties who had
become objects of his suspicion. The only theory which seemed at
all tenable was that the Horas, father and son, Cornelius Jessel and
Captain Marven were all members of a gang of criminals who
operated in perfect safety by reason of the social position of the
principals. But in such case Kenly could not understand the motive of
the elaborate plot by means of which Cornelius had secured for
himself his place in Guy's service. Nor could he comprehend why
Captain Marven's name should have been used in regard to the
stock exchange operations which had followed upon the acquisition
of the knowledge contained in the despatches. To Kenly, that
seemed such a gratuitous piece of folly, as to be entirely unworthy of
the audacious person who had planned and carried out the
Flurscheim coup.
Like a wise man, he ceased after a while to trouble himself with
inventing explanations to fit theories. He knew very well that once all
the facts were in his hands an explanation would be easy to find, and
he was anxious to get some additional facts. Was not that the motive
which had made him decide to leave Whitsea in such a hurry? He
knew very well that Guy was not carrying the stolen picture about
with him, and he had learned quite enough about Whitsea Hall to be
quite assured in his own mind that the picture was not likely to be
reposing there. He had, however, become sufficiently acquainted
with Lynton Hora's mode of life from his friend the hall porter of
Westminster Mansions, to warrant the assumption that the Greuze
was hidden somewhere in Lynton Hora's flat. If he could only get an
opportunity to verify his suspicion before any of the persons he
suspected were alarmed, he saw an opportunity of bringing off a
coup which would provide a startling denouement to the sensational
Flurscheim burglary. The thought ran away with him to such an
extent that he allowed himself to taste the sweets of success. He
imagined himself reading the references in the newspapers to "the
smart work of that able officer, Detective Inspector Kenly." He
imagined himself listening to the commendations of the Judge when
the prisoners at the bar had been sentenced to various terms of
penal servitude, and—— He awoke to the bustle of Liverpool Street
railway station, limp with perspiration, still undecided as to the best
manner of setting about getting the evidence he needed, and
perforce compelled to leave circumstances to guide his course of
action.
He permitted himself the luxury of a cab to Scotland Yard, where
he proposed to deposit his bag and report himself. He had another
reason for calling at headquarters. He foresaw that very shortly the
moment might arrive when he would not be able to deal with the
situation single-handed. If all the parties whom he expected to be
implicated in the two affairs were to be kept under surveillance, he
would need assistance, and he was not quite certain whether that
moment had not already arrived when some such steps were
necessary. Then Mr. Hildebrand Flurscheim might at any moment
communicate with the Yard, and Inspector Kenly did not want
anyone else to be put on the job without his knowledge. He knew
that as he had previously had the investigation in hand, if he
reported himself back in town he would be communicated with in the
event of any fresh information coming to hand, even though he was
detailed for special service on the Foreign Office affair, and thereby
relieved of the obligation to render daily reports of his work to his
own department.
He was glad that he had determined to report himself, for he
found awaiting him a pressing message from the Permanent
Secretary, asking him to call at the Foreign Office, as the Great Man
was anxious to know the result of his investigations.
Inspector Kenly looked at his watch. The afternoon was young.
The Permanent Secretary could be kept waiting for an hour or two
longer. The detective, leaving his bag behind him, strolled out into
the sun-scorched streets. He had even forgotten that he had eaten
no lunch, so eager was he on his quest. He walked briskly towards
Westminster Mansions, and could have shouted with delight when
he observed his old comrade standing at the open door. "Hello,
looking for a breeze," he remarked.
The porter chuckled.
"If you've been locking any up lately, the sooner you let 'em
loose again the better I shall be pleased," he remarked.
"It looks cooler inside than out here," said Kenly, with meaning.
The porter winked and led the way inside. Two lift attendants
were seated languidly interesting themselves in the cricket
intelligence of the latest evening papers.
Kenly glanced at them while he asked in a low tone: "Is there
any chance of a private chat?"
His old comrade nodded, and after talking for a few moments on
the burning topic of the weather, managed to send both the youths
on an errand. Kenly grunted his relief. Directly he was alone with the
porter he went straight to the point.
"I want to go over Mr. Lynton Hora's flat," he announced
abruptly.
The porter gazed at him in silent astonishment.
"Yes, I mean exactly what I say," he continued, "and the sooner I
can do so the better I shall be pleased. I suppose some of your
people have a key?"
The hall porter regained his power of speech. "It can't possibly
be managed, Kenly," he spluttered. "There's nothing I wouldn't do for
you in reason, but——"
Kenly cut him short. "It's got to be done," he remarked
decisively. "I've come to you, because I know I can trust you to say
nothing, and the fewer people who know what I am doing the better I
shall be pleased."
"It can't be done," remarked the hall porter. "It would be as much
as my place is worth."
"Pooh!" said the detective. "It is easy enough to make some
excuse. You can say I'm the electric light man or that I have orders to
clean out the cisterns."
"There ain't no cisterns that want cleaning," objected the hall
porter. "Now if you had come and asked me two days ago there
wouldn't have been any difficulty, but to-day——"
"Why is it impossible to-day?" demanded the detective.
"Well, Mr. Hora and Miss Myra have been away at Scarborough
for the past fortnight, and I could have let you in to their place, but
I'm expecting them to return at any minute now."
"Then we mustn't lose any time talking about it," said Kenly
briskly. "I suppose you have some means of communicating with the
flat from here."
"There's the telephone," said the porter.
"Take me straight up," said Kenly, "and if Mr. Hora should arrive
before I come down again just give two rings at the telephone bell. I
shall have plenty of time to let myself out before Mr. Hora returns."
He caught hold of the porter's arm and hurried him away in the
direction of the lift. Protesting all the while that it would be impossible
and entreating Kenly to postpone his visit to a more convenient
occasion, he yet allowed himself to be carried away by the
detective's impetuosity. He protested while the lift went steadily
upward, he protested even while he inserted a key in the lock, and
Kenly left him outside the door still protesting.
Fortune seemed to be favouring the detective. From previous
conversations he had gained a fairly accurate knowledge of the
geography of the interior of Hora's residence, and he wasted no time
in searching the residential portion of the flat. He went directly to the
door where Hora kept his pictures and his books. But here he
experienced a rebuff. The door was locked, and the lock was a
patent one. Kenly had with him a bunch of skeleton keys, but a very
slight trial proved that the lock was unpickable.
He began to cast around for some other means of gaining
access, but he saw none within the flat. He passed through all the
rooms, glancing round each. He was impressed by the luxury of the
furnishing, but there was nothing which could cause anyone to
suspect the occupant of anything but highly refined tastes. Kenly had
just completed his hasty survey when the telephone bell rang twice.
"D——n!" said the Inspector. He opened the outer door and
walked out into the passage outside. He knew that he must not be
seen, and he hastily descended the flight of stairs to the floor below,
and as he did so the lift passed him ascending upwards. He caught a
glimpse of Hora's face.
Kenly waited until the lift descended. The hall porter himself was
in charge. He stopped the lift. Kenly entered in silence.
"Find what you wanted?" asked the porter curiously.
"No time," grunted the detective. "I must have a look round
another time. If I had only known yesterday what I learned to-day
——" He groaned at the thought of what might be hidden beyond
that locked door. Still he was not disheartened. He had noted the
number of the lock and the name of the maker, and he knew that the
next time he called the locked door would prove no barrier to his
investigations. Still, days might pass before the opportunity he
desired would recur, and it was annoying to feel that opportunity had
been lost by so narrow a margin. He bade his friend good-bye and
went away at once to the Foreign Office.
The sky had become overcast and the atmosphere was hotter
than ever. Visions of a long drink, with cool translucent lumps of ice
tinkling against the steamy glass, sorely tempted the detective, but
he banished them, and, perspiring himself, he was at last ushered by
a perspiring attendant into the presence of a perspiring Permanent
Secretary who had wheeled his chair on to a line between the open
door and the open window, and sat there in his shirt sleeves in the
pathetic belief that a draught of cool air might be tempted to pass
that way.
"What is it? What is it?" he snapped at the attendant who
entered to announce Inspector Kenly. Then looking up he recognised
his visitor standing at the open door.
"Oh, it's you, Kenly. Come in." The attendant withdrew. "And,
yes, you had better shut the door." He sighed as if he had thereby
ordered the door to be shut on his own salvation.
"Sit down, Inspector, and tell me what you have found out," he
added.
He looked round for his cigar case, and not finding it
immediately made confusion of the pile of papers which covered his
table.
"I think, Sir Everard, you will find your cigar case in your coat
pocket," observed the detective blandly.
The Permanent Secretary smiled as he thrust his hand into the
breast pocket of his discarded coat.
"The heat always makes me irritable," he apologised. "No man
ought to work when the thermometer reaches the eighties." He
selected a cigar. "By the way," he remarked, "by what process of
reasoning did you arrive at the deduction that my cigar case was in
my pocket?"
"I saw the corner of it sticking out," remarked the detective
equably.
"H—m," said the Permanent Secretary, laughing, "the proper
use of the eyes may on occasion be more valuable than any amount
of deduction."
He lit his cigar and stretched himself lazily in his chair.
"Now fire away, Kenly. I can see that you have something to tell
me about those stolen despatches."
Without unnecessary beating about the bush Kenly began the
result of his investigations. The narration did not take long, for,
though he had already spent a month on the investigation, the facts
he had discovered could be described in a very few words. But few
as those facts were they were sufficiently startling to make the
Permanent Secretary forget the heat.
"By Jove!" he remarked, when Kenly had finished. "And I would
have pledged my life on Captain Marven's absolute honour. Yet, from
what you have told me, he appears to be hand-in-glove with a gang
of thieves, one of them living in his own house and likely at any
moment to become engaged to his daughter."
"Certainly appearances are very much against him," remarked
Kenly cautiously, "but I never trust to appearances myself. I have
seen too many cases, where perfectly innocent persons have been
on the most intimate terms with scoundrels, to allow that one fact to
weigh with me. If it was only a question of the burglary, I should
expect Captain Marven to be the next victim of the gang, and it is
only the fact that it seems impossible for the contents of the
despatches to have become known to the Horas without Marven's
assistance which leads me to suspect him with the rest of the
crowd."
The Permanent Secretary puffed meditatively at his cigar.
"Things look very black against Marven," he said. "Very black
indeed," he repeated, after a lengthy pause; then he asked, "Who
are these Horas?" Kenly shook his head.
"I should like to know their history myself," he answered. "All I
have heard hitherto is that the elder man has occupied a first-class
flat in Westminster for the past ten years at a rent of three hundred
and fifty pounds a year, and passes as a very retired gentleman
indeed. He spends only about six months of the year in London, and
they say he has estates in Italy. That may or may not be the case,
but, anyhow, he calls himself the Commandatore, which I'm told is
an Italian title given him by the King of Italy for something or other
he's done over there. The young one was at Oxbridge and made
quite a name amongst his set, and lived at home till a few weeks
ago, when he took some chambers in the Albany. Then there's a girl
named Myra, who passes as the old man's daughter, though there's
reason to think that she's only an adopted child."
"What are you proposing to do?" asked the Permanent
Secretary, after another pause.
Inspector Kenly coughed. "That depends——" he remarked, and
paused. "That depends on circumstances. You see, Sir Everard, my
hand may be forced before I shall have obtained all the evidence I
want. That communication which has been made to Mr. Flurscheim
may lead at any moment to the younger Hora's arrest, and then
good-bye to the hope of obtaining any more evidence. What I was
going to suggest was that you should allow me to continue to
investigate your affair. It will leave me more free to look after things
than if I have to turn in a report to headquarters. I'm so afraid," he
added in a burst of confidence, "that they might put some man on to

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Digital Logic & Microprocessor Design

With Interfacing, 2nd Edition Enoch O.

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2.8 Minterms and Maxterms .............................................................................................. 46

4.4 Subtractor ...................................................................................................................123

5.17 Timing Issues...............................................................................................................210

7.2.3 Data Transfer Methods....................................................................................295

A.2 Creating a New Schematic Source File.........................................................................492

Design of Circuits using Verilog and VHDL

New to This Edition

Using This Book

Enoch O. Hwang, Ph.D.

Enoch Hwang has a Ph.D. in Computer Science from the University

1.1 Overview of Microprocessor Design

FIGURE 1.2 Internal parts of a microprocessor.

1.2 Design Abstraction Levels

1.3 Examples of a 2-to-1 Multiplexer

1.3.1 Behavioral Level

FIGURE 1.5 Behavioral Verilog code for a 2-to-1 multiplexer.

1.3.2 Gate Level

FIGURE 1.9 Transistor circuit for the 2-to-1 multiplexer.

1.3.3 Transistor Level

1.4 Introduction to Hardware Description Language

FIGURE 1.10 Dataflow level VHDL description of the 2-to-1 multiplexer.

FIGURE 1.11 Dataflow level Verilog description of the 2-to-1 multiplexer.

FIGURE 1.12 2-to-1 multiplexer circuit.

FIGURE 1.13 Structural Verilog code for the 2-to-1 multiplexer.

----------------- NOT gate -----------------------

FIGURE 1.14 Structural VHDL code for the 2-to-1 multiplexer.

ARCHITECTURE Dataflow OF and2gate IS

1.6 Going Forward

Getty Images / Handout

FIGURE 1.15 The internal circuitry of the Intel Pentium 4 CPU.

Fundamentals of Digital Circuits

2.1 Binary Numbers

2.1.1 Counting in Binary

2.1.2 Converting between Binary and Decimal

Whitsea lies on the estuary of one of those Essex rivers which

The morning was heavy with an almost unnatural calm. By nine

Although Cornelius had been entirely unaware of the fact, his

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