European Journal of Electrical Engineering and Computer Science

Vol 7 | Issue 6 | December 2023

ISSN 2736-5751

RESEARCH ARTICLE

Design of a Vending Machine Using Verilog HDL

and Implementation in Genus & Encounter
Mahamudul Hassan Fuad1, * , Rahbaar Yeassin1 , K. M. Mehedi Hassan1 ,
Md Mahamudunnobi Sykot2 , and Md Faysal Nayan1

ABSTRACT
This paper proposes the design, implementation, and verification of a Submitted: November 21, 2023
vending machine using the Finite State Machine (FSM) methodology Published: December 29, 2023
in Verilog HDL. The FSM is used to manage the multiple states of the
vending machine, including “idle,” “accepting coins,” “dispensing item,” 10.24018/ejece.2023.7.6.595
and “returning change.” The implementation of the vending machine is
done in Verilog HDL, and the FSM is implemented as a state diagram. The 1 Department
design is then synthesized using the Genus synthesis tool and implemented of Electrical & Electronic
Engineering, Ahsanullah University of Sci-
using the Encounter implementation tool. The Genus tool uses advanced ence & Technology, Bangladesh.
optimization techniques, such as timing-driven placement and clock tree 2 Daffodil International University,
synthesis, to improve the design’s performance and area. The Encounter Bangladesh.
tool performs physical design, including placement and routing, to meet
the design’s timing, power, and area constraints. To validate the design’s *Corresponding Author:
correctness and functionality, a test bench is created to simulate the e-mail: fuadhassan5598@gmail.com
behavior of the vending machine. The simulation results are then used to
verify that the design meets the required specifications and that the FSM
behaves as expected. The proposed design is then can be implemented on a
Field Programmable Gate Array (FPGA) to demonstrate its effectiveness
in a real-world scenario. The results of the implementation are presented
and analyzed to validate the design’s performance, power consumption,
and area. Overall, the vending machine using FSM in Verilog HDL,
implemented in Genus and Encounter, provides a reliable and efficient
solution for users to purchase items from the machine. The proposed
design and implementation demonstrate the feasibility and effectiveness
of this approach, and the results show that the design meets the required
specifications and performs well in a real-world scenario.

Keywords: FSM, Physical verification, Placement, State diagram.

1. Introduction machines. The FSM model describes the system’s behav-

Vending machines are widely used in various settings,
such as schools, offices, and public places, to provide users
with convenient access to a variety of products. A vend-
ing machine typically consists of a coin slot, a selection
panel, and an item dispenser. The user selects an item,
inserts coins, and receives the selected item along with any
change due. A vending machine needs to operate reliably
and efficiently to provide a good user experience. FSM
stands for Finite state machine, is a model of compu-
tation used to design sequential logic circuits [1]. Finite
State Machine (FSM) is a mathematical model used to
describe the behavior of sequential systems, and it can
be applied to a wide range of systems, including vending
ior as a set of states and transitions between the states
based on inputs and internal events. The FSM method-
ology provides a structured and systematic approach to
designing and implementing sequential systems, such as
vending machines [2]. In order to increase their adaptabil-
ity, vending machines can serve as an advertising medium
by utilising various advanced programming skills [3]. Ver-
ilog Hardware Description Language (HDL) is a popular
language for describing digital circuits and systems. Verilog
HDL is used to design and implement the vending machine
using the FSM methodology. The FSM technique provides
a structured and methodical way to build and execute
sequential systems like vending machines. There are mainly
two types of machine-mealy and Moore [4].

Copyright: © 2023 Fuad et al. This is an open access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and
reproduction in any medium, provided the original source is cited.

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Fuad et al. Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter

The FSM is implemented as a state diagram in Verilog

HDL. Verilog HDL provides a high-level abstraction of
the hardware, making it easy to simulate, synthesize, and
implement the design. Synthesis and implementation tools,
such as Genus and Encounter, are used to optimize and
implement the design. The synthesis tool optimizes the
design for timing, area, and power, while the implemen-
tation tool performs physical design, including placement Fig. 1. State diagram for 10-taka product.
and routing, to meet the design’s timing, power, and area
constraints. The proposed design and implementation are
verified using a testbench, which simulates the behavior
of the vending machine. The simulation results are used
to verify that the design meets the required specifications,
and that the FSM behaves as expected. The proposed
design is implemented on an FPGA to demonstrate its
effectiveness in a real-world scenario [5]. The results of
the implementation are presented and analyzed to validate
the design’s performance, power consumption & area. The
proposed design and implementation demonstrate the fea-
sibility and effectiveness of using FSM in Verilog HDL
and implementing the design in Genus and Encounter for Fig. 2. State diagram for 15-taka product.
vending machine applications.

2. State Table
2.1. State Diagram
This is the state diagram for the 10TK state where two
states are present (Fig. 1). Where S0 represents the 0-taka
state & S1 represents the 10-taka state. Now if no coin/taka
is inserted then the machine will remain in the S0 state, and
no product will be dispensed. Now in another clock cycle if
the consumer inserts 10-taka, then the machine will remain
in the S0 state, but the purchase pin will be high, but the
money return pin will remain low in those two cases. Now
if the consumer inserts 20-taka in the vending machine for Fig. 3. State diagram for 20-taka product.
the product of 10-taka, then the purchase pin will be high,
and the money return pin also will be high and immediately
return 10-taka to the consumer. But in the first step if the money change. Tables I and II show the state table and
consumer inserts more than 5-taka for the product of 10- state transition table for three different states in terms of
taka then the machine will go to the S1 state but as the 15-taka product purchase issue. Where, S0, S1 & S2 are the
product is for 10-taka, but consumer inserts only 5-taka three different states.
as results in the purchase pin & money return pin will be Here, Tables III–VII show us the Kmap diagram for Y1,
working as an active low pin. Now if the consumer again Y2, C1, C2 & Z respectively. As a result, we can easily
inserts 5-taka then the total taka will be inserted is 10 now optimize the logic gates numbers which will simplify our
the purchase pin will be high & similarly if the consumer synthesis process and require a small area for the physical
inserts 20-taka then the purchase pin & money return pin design purposes.
both will be high [6], [7].
Figs. 2 and 3 respectively show us the state diagram for
the 15-taka product and 20-taka product. There are three 4. Simulation Results & Discussion
states are present for the 15-taka products and four states Table VIII shows the Synopsys design constraints and
for the 20-taka products. Where S0 denotes there is no taka Table IX shows the Design constraints for the design.
inserted or 0-taka state, S1 denotes 5-taka state, and S2- Table X shows the Result after the physical design.
denote the 10-taka state for the 15-taka product. But for Fig. 4 shows the synthesized circuit according to the
the 20-taka product, there is one more state that is required state diagram and Fig. 5 shows the Floor plan for the
that’s denoted as S3 state in the 20-taka state. synthesized circuit.
Fig. 6 shows the full power plan for the chip using VDD
& VSS. Fig. 7 shows the I/O pin placement for the chip.
3. State Table & Kmap
Fig. 8 shows the optimized version of the area after pin
Here the state table from the FSM is given where Z placement. The filler cell added to the rest of the space of
denotes the purchase and C1C2 denotes the amount of the chip is shown in Fig. 9. After routing Fig. 10 shows the

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Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter Fuad et al.

TABLE I: State Table

Present Next state Output

state Y2 Y1 Z C2 C1

(W2 W1 ) (W2 W1 ) C(W2 W1 )

(Y2 Y1 ) 00 01 10 11 00 01 10 11 00 01 10 11
S0 S0 S1 S2 S0 0 0 0 1 00 00 00 01
S1 S0 S2 S0 S0 0 0 1 1 01 00 00 10
S2 S0 S0 S0 S0 0 1 1 1 10 00 01 11

TABLE II: State Transition Table

Present Next state Output

state Y2 Y1 Z C2 C1

(W2 W1 ) (W2 W1 ) C(W2 W1 )

(Y2 Y1 ) 00 01 10 11 00 01 10 11 00 01 10 11
00 00 01 00 00 0 0 0 1 00 00 00 01
01 00 10 00 00 0 0 1 1 01 00 00 10
10 00 00 00 00 0 1 1 1 10 00 01 11
11 D D D D D D D D D D D D

TABLE III: Kmap for Y1 TABLE VI: Kmap for C2

W2 W1 W2 W1

Y2 Y1 00 01 11 10 Y2 Y1 00 01 11 10
00 0 1 0 0 00 0 0 0 0
01 0 0 0 0 01 0 0 1 0
11 D D D D 11 D D D D
10 0 0 0 0 10 1 0 1 1
Note: Expression of Y1 = W2 ’ W1 Y2 ’Y1 . Note: Expression of C2 = W2 ’ W1 ’ Y2 ’ + W2 W1 Y2 + W2 W1 Y1 .

TABLE VII: Kmap for Z

TABLE IV: Kmap for Y2
W2 W1
W2 W1
Y2 Y1 00 01 11 10
Y2 Y1 00 01 11 10
00 0 0 1 0
00 0 0 0 1
01 0 0 1 1
01 0 1 0 0
11 D D D D
11 D D D D
10 0 1 1 1
10 0 0 0 0
Note: Expression of Z = W2 W1 + W2 Y1 + W2 Y2 + W1 Y2 .
Note: Expression of Y2 = W2 ’ W1 Y1 + W2 W1 ’Y2 ’Y1 ’.

TABLE VIII: SDC Constraints

TABLE V: Kmap for C1 Initial Maximum Driving Operating Output Max
W2 W1 clock transition cell condi- delay (ns) fanout
frequency (ns) tions
Y2 Y1 00 01 11 10 (MHz)
00 0 0 1 0 66.67 3 BUFX16 Slow 0.6 18
01 1 0 0 0
11 D D D D
10 0 0 1 1
Fig. 14 shows that there are 0 violations in the Pre-CTS
Note: Expression of C1 = W2 ’ W1 ’ Y1 ’ + W2 W1 Y1 ’ + W2 Y2 . design summary so after doing optimization, we did not
get any changes.
Figs. 15 & 16 show that after routing we found hold
routed version of the chip design. Then we have to use the violations where the worst negative slack is −0.416 and
metal filler cell which is adapted in Fig. 11. Finally after the total negative slack is −2.646 & the violating path is 8
physical verification and power analysis the final GDS which means in total 8 paths input is giving those delays.
version is shown in Fig. 12. Fig. 17 shows after doing the optimization in the hold
From Fig. 13 the time design summary, we found mode the worst negative slack is decreased.
that there are no violations available. From the DRV Fig. 18 shows that there are 0 violations get in the Pre-
max_cap,max_tran,max_fanout, and max_length all them CTS design summary so after doing optimization, we did
is zero. not get any changes.

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Fuad et al. Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter

TABLE IX: Design Constraints

Distance Ring (Width, Stripe Initial Offset
between die distance) (Number of placement
and core sets) density
11 3.2 3 50 1

TABLE X: Result
Parameter Value
Initial density (%) 85.944
Final density (%) 95.183
Total placed cells 33
Dynamic power (nW) 44527.045
Leakage power (nW) 5.860
Total power (nW) 44532.905 Fig. 5. Floor plan.
Initial DRV violations (max_cap,max_tran,max_fan
,max_length) = 0
Remaining DRV violations 0
Initial timing violation 0
Final timing violation (Hold WNS = −0.416 ns,
mode before optimized) TNS = −2.646 ns
Final timing violation (Hold WNS = −0.385 ns,
mode after optimized) TNS = −2.469 ns
Total number DRC violations 8
Total number geometry 8
violations
Total number ProcessAntena 0
violations
Total number connectivity 10
violations
Total number Aclmit violations 0
Total number PG_SHORT 8 Fig. 6. Power plan.
violations
Total number power_via 0
violations

Fig. 7. Pin placement.

limit verifications. For Geometry verifications there are 8

violations and for connectivity verifications there the 10
violations present. But there is 0 power via violations found
though there are 8 PG_short violations present.

Fig. 4. Synthesized circuit. 5. Future Aspects

Fig. 19 shows there is 1 main clock source present and 7
clocks for the flipflops shown.
Figs. 20–26 show different types of physical verifications
which show after DRC verifications we found 8 violations
but there are 0 violations present for process antenna & AC
1. Security features: Including security elements in the
design of vending machines is one possible area for further
research and development. Other security measures to
stop theft or fraudulent activity might also be used, such
as biometric authentication such as fingerprint or facial
recognition [8], [9].

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Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter Fuad et al.

Fig. 8. Placement optimized.

Fig. 11. Metal filler added.

Fig. 9. Filler cell added.

Fig. 12. Final design after STA, physical verification, and power
analysis.

2. Wireless connectivity: Including wireless connectivity

in vending machine designs is another area that could
see development in the future. With real-time inventory
management and sales tracking possible thanks to this, the
vending machine may be able to connect to a central server
[10].
3. User interface: Touch screens or other interactive
displays could be added to the vending machine’s user
Fig. 10. Placement (post route).
interface to make the purchasing process simpler and more
user-friendly.

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Fuad et al. Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter

Fig. 16. Post-route time design summary before optimization

(Hold violations).

Fig. 13. Pre-CTS time design summary (DRV and setup violations).

Fig. 17. Post-route time design summary after optimization

(Hold violations).

Fig. 14. Optimized Pre-CTS time design summary (DRV and

setup violations).

Fig. 18. Post route time design summary after optimization

Fig. 15. Post route time design summary before optimization (DRV and setup violations).
(DRV and setup violations).

5. Data analysis: Vending machine operators could

4. Multiple payment alternatives: The vending machine choose products and set prices based on data-driven judg-
could be improved to accept a variety of payments, includ- ments by analyzing the data supplied by the vending
ing credit cards, mobile payments, and other electronic machine to acquire insights into consumer behavior and
payment options [11], [12]. preferences [13].

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Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter Fuad et al.

Fig. 19. Clock tree diagram.

Fig. 24. Connectivity violations verification.

Fig. 20. DRC violations verification.

Fig. 25. PG_SHORT violations verification.

Fig. 21. Process antenna violations verification.

Fig. 22. AC limit verification.

Fig. 26. Power via violations verification.

machine learning and artificial intelligence into it. Based

on their past purchases and interests, this might offer
consumers personalized recommendations, improving the
user experience. The vending machine employing FSM in
Verilog HDL and implemented in Genus and Encounter
has a wide range of possible areas for future improvement
and optimization. The vending machine can be made even
more effective, user-friendly, and economical by combining
new technologies and methods, giving clients a wonderful
user experience [14]–[16].

Fig. 23. Geometry violations verification.

6. Conclusion
6. Smart vending machine: The vending machine could In this paper, we presented the design, implementation,
be upgraded to a smart vending machine by incorporating and verification of a vending machine using Finite State

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Fuad et al. Design of a Vending Machine Using Verilog HDL and Implementation in Genus & Encounter
Machine (FSM) methodology in Verilog HDL, imple-
mented in Genus and Encounter. The proposed design and
implementation provide a reliable and efficient solution
for users to purchase items from the vending machine.
The FSM model is used to manage the multiple states of
the vending machine, including “idle,” “accepting coins,”
“dispensing item,” and “returning change.” The FSM is
implemented as a state diagram in Verilog HDL, which
provides a high-level abstraction of the hardware and
makes it easy to simulate, synthesize, and implement the
design. The implementation of the vending machine is
done using the Genus synthesis tool and the Encounter
implementation tool. The Genus tool optimizes the design
for timing, area, and power, while the Encounter tool per-
forms physical design, including placement and routing,
to meet the design’s timing, power, and area constraints.
The proposed design is validated using a testbench, which
simulates the behavior of the vending machine.
The simulation results are used to verify that the design
meets the required specifications, and that the FSM
behaves as expected. The proposed design is also can be
implemented on an FPGA to demonstrate its effectiveness
in a real-world scenario. The results of the implementation
show that the proposed design meets the required speci-
fications and performs well in a real-world scenario. The
design’s performance, power consumption, and area are
analyzed, and the results show that the design is efficient
and reliable. In conclusion, the proposed vending machine
design using FSM in Verilog HDL and implemented in
Genus and Encounter provides a reliable and efficient solu-
tion for users to purchase items from the vending machine.
The proposed design and implementation demonstrate the
feasibility and effectiveness of using FSM in Verilog HDL
and implementing the design in Genus and Encounter for
vending machine applications. The proposed design can be
further extended and optimized for more complex vending
machines, and it can also be used as a basis for other digital
systems that require FSM-based designs.
Conflict of Interest
Authors declare that they do not have any conflict of
interest.
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