IC Packaging

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 1. GENERAL DATA

Course : IC Packaging Code :

Workload : 9 hours (theoretical lectures) Period : semester I/II / <year>

Professor : Contact :

Description :

IC Packaging Introduction, First Level Interconnect, Package Characteristics, Packaging Design

Flow, Substrate Assembly, Package Reliability and Failure Analysis.

2. OBJETIVES

SCOPE DESCRIPTION

 Understanding of the multidisciplinary characteristic of IC design

General  Understanding the relevance of a suitable package selection over the design
features and feasibility.

 Identify the kinds of packaging for determining the suitable fitting with the design
features
 Identify the differences involving the several packaging interconnect technologies
 Identify new packaging technologies: 3D die, SiP, and PoP.
 Determine the bond pull strength of a wire bond
Especific
 Determine characteristic impedance for stripline and microstrip transmission lines
 Determine propagation delay for transmission lines
 Understand and describe the package design flow
 Describe the three types of MCM.
 Understand topics associated to packaging reliability and failure analysis.
 3. CONTEXT and MOTIVATION

DESCRIPTION

In the last years, the electronics market has demonstrated a rising demand for portable electronic

devices for wireless communication, signal processing, monitoring and control systems (by applying

digital, mixed signal and analog and RF radiofrequency technologies). In this context, the need for

building and operating features like high portability, low cost, low power consumption and high

performance has stimulated the implementation of these technologies through integrated circuit IC design.

Once designed to provide physical support for mechanical protection, heat dissipation, and signal

and power distribution for the chip, the several packaging technologies demonstrates different physical

and geometrical features, to comprise the several categories of electronic systems. As a result, this

condition implies on different interaction patterns between the packaging model and the chip-based

system. This operating condition leads to the need for a packaging technology based-design requiring a

suitable interaction between packaging and system models to ensure the required working for the

physically implemented final integrated circuit IC.

Thus, the set of topics to be considered for IC design training have to include this packaging

technologies based-approach. The set of available packaging technologies includes the following options:

- DIP (Dual Inline Package): rectangular format, few pins, and different materials.

- SOP (Small Outline Package): less thickness, grater routing density, and different materials.

- QFP (Quad Flat Package) : increased pin number, increased routing density.

- BGA (Ball Grid Array) : very high I/O density, very low pin inductance.
 4. PROGRAM

CLASS MODULES DESCRIPTION

IC Packaging definition, hierarchy of packaging, function of the package, package

1 - IC Packaging disciplines (electrical, mechanical, materials), package types (PGA, BGA and
Introduction QFP), advanced packaging technologies (chip scale packaging, 3D high density
packaging, PoP, System in package), package efficiency, Rent’s Rule.

 Packaging technologies - wire bond (wedge bonding and ball stitch bonding) and
2 - First Level flip chip (advantages, assembly and die bump functions)
Interconnect  Wirebond pull strength
 Expansion differentials.

 Electrical characteristics – impedance and transmission line models (stripline,

microstrip, and buried stripline), propagation delay models, Lattice diagrams for
reflection analysis.
 Thermal characteristics - thermal transport modes. (conduction, convection and
3 - Packaging radiation, newton’s law of cooling).
Characteristics
Kinds of available packaging technologies: DIP (Dual Inline Packages), SOP (Small
Outline Packages), QFP (Quad Flat Pack), BGA (Ball Grid Array), CSP (Chip Scale
Packages), WLP (Wafer Level Packages), MCP (Multichip Packages).

Packaging design flow (package modeling, IC modeling, wirebonding, dynamic

4 - Packaging Design
manufacturing constraints, package interconnect and routing, manufacturing data
Flow
creation)

5 - Substrate MCM types (MCM-D, MCM-C, MCM-L), Manufacturing challenges (etch factor,
Assembly planarization), assembly techniques

6 - Package Overstress failures and wearout failures, electrical failures mechanisms,

Reliability and thermomechanical failure mechanisms, chemically induced failure mechanisms,
Failure Analysis multi-chip module yelds.
 1. ACTIVITIES SCHEDULE

WEEK CLASS DATE DESCRIPTION

1
2

Week 1 3
4

--

2. EVALUATION SYSTEM

The set of activities to be proposed for evaluating trainee performance are described as follows:

EVALUATON DESCRIPTION

 Theoretical activity to be developed at home through the application of the

Homeworks (H)
concepts presented in the class.

Final Exam (FE)  Theoretical verification of the acquired knowledge.

 P1 - Homeworks (20 %)
 P2 - Final Exam (80 %)

Final Grade (FG)

Final grade will be determined through the following expression:

 FG = P1*H + P2*FP
 3. BIBLIOGRAPHY

SOURCE PACKAGING REFERENCE BOOKS

Title:
Title: Title:
Electronic Title: Title:
Integrated Semiconductor
Packaging and Area Array Advanced
Circuit Packaging
Interconnection Packaging Electronic
Packaging, Author:
Handbook Handbook Packaging
Assembly and Andrea Chen
Author: Authors: Author:
Interconnections Randy Hsiao-Yu
Charles A. Ken Gilleo Frank Ellinger
Complementary

Author: Lo
Harper
William Craig

Title:
System-on- Title: Title: Title:
Title:
Package (SOP) Flip Chip Ball Grid Array Chip Scale
Chip on Board
Author: Technologies Technology Package
Author:
- Rao R. Author: Author: Author:
John H. Lau
Tummala John H. Lau John H. Lau John H. Lau
- Madhavan
Swaminathan