MODULE-I

SLNO QUESTIONSs MARKS KTU,YEAR

Draw the amplitude and phase responses of an RC low pass filter. Mark the| Jul-21
cut off frequency point on both.

2 Explain working of a self bias circuit 3 Jul-21

3 Explain the hybrid-rt parameters of BJT in CE configuration. 6 Sep-20

ACE amplifier with voltage divider bias has VRE =

1.5v, VRC 6V, VCC
= =

3 Jul-21
15V,ICQ=3mA and B= 200. Find R1, R2, Qpoint
Design a high pass filter for a cut off frequency of 5kHz. Plot the frequency
8 Jul-21
response indicating roll off rate in terms of dB/octave.

6 Explain the concept of operating point with the help of dc and ac load 6 Jul-21
lines. Why is voltage divider biasing superior to other biasing circuits.
Design a clamper circuit to clamp a 10Vpp sine wave so that its negative
7 peak is clamped at +2V. Assume diode drop is 0.7V. Draw and explain the 5 Ju-21

output waveform and transfer characteristics.

8 périve the stability factor of a voltage divider bias circuit. 6 Sep-20

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Berive an expression for current stability factor of collector to base bias.

101Derive 3-dB frequency of a high pass RC circuit.

6

4
Sep-20

Sep-20

Show how an RC circuit can behave as an integrator. 5 Sep-20

oraw an RC differentiator circuit. Give the conditions for an RC circuit to

4 Dec-19
behave as adifferentiator.
13
Design an integrator for an input frequency of 1KHz 3 Dec-19

For a fixed bias.circuit with RB 300KN, RC = 2K0, B = 50, VCC = 9V, find Q-
14 Dec-19
point and stability factor.
15 |Design and draw an RC differentiator circuit for a given input frequency of Dec-20

|Define stability factor, Derive an expresslon for the stability factor for
16
leakage current of a voltage divider blas clrcuit. How does the voltage 8 Dec-20
divider bias improve the stablity of an amplifler circult.
With neat circuit diagrams, derlve the design criterla for an RC clreult to
functions as
17 Dec-20
() Differentiator
(i) Low passfilter
 1.5K0,
For a voltage divider bias circuit using VCC 12V, RC 2.2KQ, RE
= =
=

SLN
7
18
R1 7.2KQ, R2 2.2K0, RL 1K0, draw AC and DC load lines and locate Q
= = Dec-20
point. Assume values for parameters that are not given.
19
Explain the concept of AC and Dc load lines. 4 Jan-22

20Determinethe
20 stability factor of a fixed bias CE- BJT amplifier with VCC =
4
12V, RC =10K, RB =5K and ß=120. Sep-20

TRACE KTU
 MODULE-I

SL NO QUESTIONS MARKS KTU,YEAR

|1. For the given circuit B= 100 for silicon transistor. Calculate the
operating points. Assume data that are not given.

KA Rc

Jan-22
Vi
5KAg
0o Ce

Explain the small signal hybrid-t model of transistor in

CE
configuration with neat schematics. Derive the expression
for 5 Dec-18
voltage gain without by pass capacitor.
Draw high frequency equivalent circuits of BJT and discuss Miller
6 Dec-20
effect
Determine the upper cut off frequency of a common emitter
Dec-19
amplifier configuration using hybrid-t equivalent circuit.

TRACE KTU
Draw the small signal low frequency hybrid-T model for common
emitter configuration. Derive the expression for voltage gain, input 5 Dec-18
impedance and output impedance.

Usinghybrid-t model, obtain the expression for input impedance, Dec-18

output impedance and midband voltage gain of a CE amplifier.
For aRCCoupled amplifier with by pass capacitors, the circuit
components are R1= 35.2K0, R2 5.83KQ, RC = 10KO, RE = 1K and
6 Dec-19
RS 0. Transistor parameters are VBE{ON) = 0.7V, VA =100V, B=
100. Determine Q-point and smallsignal voltage gain (VCC =5V))
8
Explain the hybrid-T parameters of BJT in CE configuration. 3 Jul-21
Three stages of individual RC coupled amplifier having midband gain
9 of 80 with lower cut-off frequency of 100OHz and upper cut off
3 Jul-21
frequency of 300 MHz are cascaded. Find the resulatant gain anfd
cut off frequencies.
10 Derive Ri, Ro, Ai and Av using hybrid- t parameters for CE
10 Jul-21
|configurationat low and mid frequencies.
11 Find mid frequency voltage gain and output impedance of a CE
Jan-22
amplifier without by pass capacitor using hybrid-T model.
 MODULE-

MARKS KTU,YEAR
SL NO QUESTIONS

4 Jan-22
Draw the circuit diagram of cascode amplifier.
for midband voltage
Draw the circuit diagram and derive an expression 9 Dec-19
gain of cascode amplifier.
and
Analyze a common source amplifier with source resistance bypassed
impedance and voltage 4 Dec-19
3 derive expressions for input impedance, output
gain using small signal equivalent circuit.
sketch. Dec-20
4 Write short notes on cascade amplifiers with neat

MOSFET amplifiers. 8 Sep-20

Explain various types of biasing methods of

Draw the small signal equivalent of MOSFET. Dec-20

6

circuit
Determine drain to source voltage of a MOSFETcommon source
Given that 8. Dec-18
using voltage divider bias and source is directly grounded.
TRACE KTU
7
VDD 10V, R1 10MQ, R2 10KO, RD 2KQ, Vt 3V, and ID 2mA
= = =
= = =

3V, and it is biased at VGSQ

Determine gm for E-MOSFET if VGS(Th)
= =

3 Dec-18
BV. Assume k= 0.3x10-3 mA/N2

9 Explain any two biasing techniques for E-MOSFET. 8 Sep-20

Draw a CS MOSFET amplifier. With the help of small signal equivalent

10 10 Jul-21
circuit, compute its voltage and current gain.

11 How can you increase the gain of this single stage without additional Jul-21
stages
12 How does cascode attain large bandwidth without comprimising on 10 Jul-21
volatge or current gain.
 Calculate the drain current if unCox = 100uA/V2, VTH = 0.5V and A =0 in
the following circuit.
Vpo /:6V

20 IK Kp 1K
13 Dec-19

o.1F

14 How wide bandwidth is obtained in cascode amplifier. Dec-19

Draw the CS stage with current source load and deduce the expression for
15 14 Dec-19
voltage gain of the amplifier.

3 Dec-19
16 What are the effects of cascading in gain and bandwidth of an amplifier.

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 MODULE-IV

NO QUESTIONS MARKS KTU,YEAR

Draw the circuit diagram of Hartley oscillator. In Hartley

1
oscllator,Ll = 0.3mH, L2 0.3mH
= and C= 0.003uF. Calculate the Jan-22

2 |What are the dfferent feedback topologies. Explain how the

current series feedback effect the input and output impedances. Jan-22
3 What are the conditions for sustained oscillations. Jan-22

Draw the circuit diagram of Wienbridge oscillator. Explain how

4
Barkhausen criterion for oscillation is satisfied by the circuit and
derive an expression for the frequency of oscillation.
8 Dec-19

5
Draw circuit diagrams of feedback amplifier circuits using voltage
series feedback and current series feedback. Dec-20

6
Explain shunt-shunt feedback topology with neat diagram.
Derive the expression for input and output impedance.
Dec-20
Discuss any two feedback topology.

8 lnspite TRACE KTU

of reduction in gain, negative feedback is
amplifiers. Justify the statement.
preferred for

|State Barkhausen criteria. How is it achieved in Wienbridge

6
Sep-20

Jul-21

9
oscillators. Jul-21

10 Derive the input resistance, outputresistance and gain of

voltage series feedback amplifiers. 10 Jul-21

11 Design an oscillator to obtain sinusoidal waveform of 1MHz.

Jul-21

12 Draw the equivalent circuit of a crystal. Explain crystal osillator.

8 Jul-21
How does negative feedback affect input and output
13
impedances in feedback amplifiers. b Jul-21
llustrate the effect of negative feedback on bandwidth and gain
14
of the amplifier. 3 Dec-19
15 Explain the criteria for an oscillator to oscillate.
Dec-19

16 Explain the working principle of crystal oscllator.

Dec-19
 MODULE-V
SL NO
QUESTIONS
MARKS KTU,YEAR
1
A Class- B push pull amplifier working
peak signal to a 80 load. Calculate with Vcc 25V provides a 22 V
isinatisa the amplifier effeciency and power 5 Jan-22
2 |With à neat circuit diagram,
regulator with error amplifierexplain
the working of a series voltage
Jul-22
|What is cross over distortion in
amplifiers. How is it avoided? 5 Dec-19

Differentiate between line and load regulations.

6 Jan-22
Classify power amplifiers based on collector current
waveforms
conduction angle. and
5 Dec-19
Draw the circuit diagram of Class A series fed
power amplifier 10 Dec-19
7 With a neat circuit
diagram, explain the working of a transistor based
shunt voltage regulator 9 Dec-19
8 How is short circuit protection provided in series
voltage regulator.
Explain with neat circuit diagram. 5 Dec-20
Explain the working of transformer coupled Class A
with a neat circuit diagram and collector waveforms.power amplifier 10 Dec-20

11
TRACE KTU
19 With the help of V-I characteristics, explain foldback
What do you mean by harmonic distortion in power
protection.
amplifier. How is
Jul-21

lit reduced in push pull amplifier

circuit. 6 Jul-21
12 what is line regulation and load regulation in the context
of voltage
regulators. Dec-19
13 llustrate the working principle of complementary-
power amplifiers and deduce the maximum symmetry Class B
14
effeciency of the circuit. Dec-19
14 Design a discrete series voltage regulator with short circuit
for regulated output voltage 10V and maximum current protection
100mA. 14 Dec-19
15
What do you mean by conversion effeciency of a
power amplifier. Sep-20
16 Draw the circuit diagram of Class AB push pull
working. amplifier and explain its
6 Jan-22