Date: December 07, 2020 filter.

bdf Project: filter

Parameter Value
INCLOCK_PERIOD 20000
INCLOCK_SETTINGS "USED"
VALID_LOCK_CYCLES 1
INVALID_LOCK_CYCLES 1
VALID_LOCK_MULTIPLIER 1
INVALID_LOCK_MULTIPLIER 1
OPERATION_MODE "NORMAL"
CLOCK0_BOOST 1
CLOCK0_DIVIDE 1
CLOCK0_SETTINGS "UNUSED"
CLOCK0_TIME_DELAY "0"
CLOCK1_BOOST 1
CLOCK1_DIVIDE 1
CLOCK1_SETTINGS "UNUSED"
CLOCK1_TIME_DELAY "0"
CLOCK2_BOOST 1
CLOCK2_DIVIDE 1
CLOCK2_SETTINGS "UNUSED"
11.2896MHz codec clock
CLOCK2_TIME_DELAY "0"
CLOCK_EXT_BOOST 4 May deviate due to discrete multipliers/dividers
CLOCK_EXT_DIVIDE 18 44.1kHz 16bit sampling 256fs
CLOCK_EXT_SETTINGS "USED"
Using Audio CD sampling settings,
CLOCK_EXT_TIME_DELAY "0"
which gives us 2 options for the codec clock AUD_XCLK: 256fs and 384fs
OUTCLOCK_PHASE_SHIFT 0
(read the manual) altclklock
50MHz master clock
CLOCK_50 INPUT
VCC
inclock OUTPUT AUD_XCK
PIN_G7
PIN_AF14

clock_ext
Starts with 0 and rises long after PLL stabilises
inst (used as power on reset)
sync
PIN_H7
Digital Audio interface, master mode clk Ds Synchronous parallel interfaces
PIN_K7 Da s2p_adaptor fir
64x44.1kHz
AUD_BCLK INPUT
AUD_BCLK ADCDAT[15..0] ADCdat[15..0]
VCC
inst5 ADCstb ADCstb
AUD_ADCDAT INPUT
AUD_ADCDAT
PIN_K8 VCC ADCrdy ADCrdy
AUD_ADCLRCK INPUT
AUD_ADCLRCK
VCC

AUD_DACDAT
AUD_DACDAT OUTPUT
PIN_J7 AUD_DACLRCK INPUT
VCC
sync AUD_DACLRCK
DACDAT[15..0] DACdat[15..0]
clk Ds CLOCK_50 DACstb DACstb
Da RST_N DACrdy DACrdy
PIN_H8
inst1
inst6 CLOCK_50
RST_N

inst3
Synchronizers "sync" are
codec_init
used with all asynchronous
sync
inputs that are sampled CLOCK_50 SCLK OUTPUT FPGA_I2C_SCLK
PIN_J12
very close to their change. clk Ds RES_N SDIN OUTPUT FPGA_I2C_SDAT
KEY[0] INPUT
VCC Da 2-wire MPU interface
PIN_AA14 (i2c compatible) PIN_K12
inst2
inst4

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