Lecture 07 AVR Module 1

CSE234: Embedded System
Instructor:
Dr. Ahmed Shalaby
http://bu.edu.eg/staff/ahmedshalaby14#
Course Book
Embedded Systems
www. Micro Digital Ed. com
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Introduction to Computing
Chapter 0
The AVR microcontroller

and embedded
systems
using assembly and c
AVR Microcontroller and Embedded System Using Assembly and C © 2011 Pearson Higher Education,
Mazidi, Naimi, and Naimi Upper Saddle River, NJ 07458. • All Rights Reserved.
Topics
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• Internal organization of computers

– The different parts of a computer
• I/O
• Memory
• CPU
– Connecting the different parts
• Connecting memory to CPU
• Connecting I/Os to CPU
– How computers work
Internal organization of computers
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• CPU
• Memory
• I/O
– Input
• E.g. Keyboard, Mouse, Sensor
– Output
• E.g. LCD, printer, hands of a robot
Memory
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• Everything that can store, retain, and recall

information.
– E.g. hard disk, a piece of paper, etc.
Memory characteristics
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• Capacity
– The number of bits that a memory can store.
• E.g. 128 Kbits, 256 Mbits
• Organization
4 bits
– How the locations are organized 0
128 locations
1
• E.g. a 128 x 4 memory has 128 locations, 2
4 bits each
…
127
• Access time
– How long it takes to get data from memory
Semiconductor memories
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• ROM • RAM
– Mask ROM – SRAM (Static RAM)
– PROM (Programmable – DRAM (Dynamic RAM)
ROM) – NV-RAM (Nonvolatile
– EPROM (Erasable RAM)
PROM)
– EEPROM (Electronic
Erasable PROM)
– Flash EPROM
Memory\ROM\ Mask ROM
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• Programmed by the IC manufacturer
Memory\ROM\ PROM (Programmable ROM)
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• OTP (One-Time Programmable)

– You can program it only once
Memory\ROM\ EPROM (Erasable Programmable ROM)
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• UV-EPROM
– You can shine ultraviolet (UV) radiation
to erase it
– Erasing takes up to 20 minutes
– The entire contents of ROM are erased
2764
Memory\ROM\ EEPROM (Electrically Erasable
Programmable ROM) BIHE university
• Erased Electrically RDY/BSY

A12
VCC
WE
A7 NC
– Erased instantly A6 8K x 8 A8
A5 A9
– Each byte can be erased separately A4

A3
A11
OE
A2 A10
A1 CE
A0 I/O7
I/O0 I/O6
I/O1 I/O5
I/O2 I/O4
VSS I/O3
Memory\ROM\ Flash ROM
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• Erased in a Flash
• the entire device is erased at once
Semiconductor memories
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• ROM • RAM
– Mask ROM – SRAM (Static RAM)
– PROM (Programmable – DRAM (Dynamic RAM)
ROM) – NV-RAM (Nonvolatile
– EPROM (Erasable RAM)
PROM)
– EEPROM (Electronic
Erasable PROM)
– Flash EPROM
Memory\RAM\ SRAM (Static RAM)
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• Made of flip-flops (Transistors)

• Advantages: 2K x 8
– Faster SRAM
– No need for refreshing

• Disadvantages:
– High power consumption
– Expensive
Memory\RAM\ DRAM (Dynamic RAM)
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• Made of capacitors
• Advantages:
– Less power consumption
– Cheaper
– High capacity
• Disadvantages:
– Slower
– Refresh needed
Memory\RAM\ NV-RAM (Nonvolatile RAM)
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• Made of SRAM, Battery, control circuitry

• Advantages:
– Very fast
– Infinite program/erase cycle
– Non-volatile
• Disadvantage:
– Expensive
Internal parts of computers\CPU
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• Tasks:
– It should execute instructions
• It should recall the instructions one after another
and execute them
Connecting memory to CPU
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• Memory pin out
VCC
GND VCC
8
D0-D7
n
A0-An-1
WE
OE
CS
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VCC
GND VCC
8
D0-D7
CPU n
A0-An-1
WE
OE
CS
Writing to memory
Address
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CS
Data
WE
Time
VCC
GND VCC
8
D0-D7
CPU n
A0-An-1
WE
OE
CS
Connecting memory
Writing
Reading memory to CPU
to memory
from
Address
Address
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CS
CS
OE
Data
Data
WE
WE
Time
Time
VCC
GND VCC
8
D0-D7
CPU n
A0-An-1
WE
OE
CS
Connecting I/Os to CPU
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• CPU should have

lots of pins! Mouse
Network
CPU Keyboard
Sound Card
Graphic Card
Connecting I/Os to CPU using bus
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Address bus
Data bus
Write
Control bus Read
CPU
I/O 0 I/O 1 I/O 2 I/O n
Connecting I/Os and Memory to CPU
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Address bus
Data bus
Write
Control bus Read
CPU I/O 0 I/O 1 I/O 2 I/O n

VCC
GND VCC
n
A0-An-1
8
D0-D7
WE
OE
CS
Connecting I/Os and memory to CPU using bus
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VCC
1
2
3
A0-An-1
GND
D0-D7
WE
OE
CS
Address bus
Data bus
Write
Control bus Read
CPU
I/O 0 I/O 1 I/O 2 I/O n
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VCC
1
2
3
A0-An-1
GND
D0-D7
WE
OE
CS
0
Address bus
Data bus
Write
Control bus Read
CPU
I/O 0 I/O 1 I/O 2 I/O n
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VCC
1
2
3
A0-An-1
GND
D0-D7
WE
OE
CS
0
Address bus
Data bus
Write
Control bus Read
CPU
I/O 0 I/O 1 I/O 2 I/O n
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VCC
1
How could we manage it? 2

3
A0-An-1
GND
D0-D7
WE
OE
CS
0
Address bus
Data bus
Write
Control bus Read
CPU
I/O 0 I/O 1 I/O 2 I/O n
Connecting I/Os and Memory to CPU using bus
(Peripheral I/O) BIHE university
VCC
0
1
..
63
A0-An-1
GND
D0-D7
WE
OE
CS
Address bus
Data bus
Write
Control bus Read
IO/MEM
CPU
I/O 0 I/O 1 I/O 2 I/O n
(Memory Mapped I/O) BIHE university
The logic circuit
VCC
0
1 enables CS
..
15
when address is
between 0 and
A0-An-1
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Write
Control bus Read
CPU
I/O 16 I/O 17 I/O 18 I/O n
The logic circuit
VCC
0
1 enables CS
How could we make the logic ..
15
when address is
between 0 and
A0-An-1
circuit?
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Write
Control bus Read
CPU
I/O 16 I/O 17 I/O 18 I/O n
The logic circuit
VCC
0
1 enables CS
15
when address is
between 0 and
A0-An-1
circuit?
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Write
Control bus Read
CPU
I/O 16 I/O 17 I/O 18 I/O n
The logic circuit
VCC
0
1 enables CS
15
when address is
between 0 and
A0-An-1
circuit?
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Solution
Control 1.
bus Write
Write the address range in binary
Read
CPU
I/O 16 I/O 17 I/O 18 I/O n
The logic circuit
VCC
0
1 enables CS
15
when address is
between 0 and
A0-An-1
circuit?
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Solution
Control 1.
bus Write
Read
CPU
From address 0 ➔ 0 0 0 0 0 0 0 0
I/O 16 I/O 17 I/O 18 I/O n
To address15 ➔ 0 0 0 0 1 1 1 1
The logic circuit
VCC
0
1 enables CS
15
when address is
between 0 and
A0-An-1
circuit?
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Solution
Control 1.
bus Write
Read
2. Separate the fixed part of address
CPU
a7 a6 a5 a4 a3 a2 a1 a0
From address 0 ➔ 0 0 0 0 0 0 0 0
I/O 16 I/O 17 I/O 18 I/O n
To address15 ➔ 0 0 0 0 1 1 1 1
The logic circuit
VCC
0
1 enables CS
15
when address is
between 0 and
A0-An-1
circuit?
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Solution
Control 1.
bus Write
Read
CPU
3. Using a NAND, design a logic circuit whose output
activates when the fixed address is given to it.
a7 a6 a5 a4 a3 a2 a1 a0
From address 0 ➔ 0 0 0 0 0 0 0 0
I/O 16 I/O 17 I/O 18 I/O n
To address15 ➔ 0 0 0 0 1 1 1 1
The logic circuit
VCC
0
1 enables CS
15
when address is
between 0 and
A0-An-1
circuit?
GND
D0-D7
WE
OE
CS
15
Logic circuit
Address bus
Data bus
Solution
Control 1.
bus Write
Read
CPU
3. Using a NAND, design a logic circuit whose output
activates when the fixed address is given to it.
a7 a6 a5 a4 a3 a2 a1 a0
From address 0 ➔ 0 0 0 0 0 0 0 0 a4
I/O 16 I/O 17 I/O a5
18
a6
I/OCS
n
To address15 ➔ 0 0 0 0 1 1 1 1 a7
Another example for address decoder
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• Design an address decoder for address of 300H

to 3FFH.
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to 3FFH.
Solution
1. Write the address range in binary
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to 3FFH.
Solution
a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
From address 300H ➔ 0 0 1 1 0 0 0 0 0 0 0 0
To address 3FFH ➔ 001111111111
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to 3FFH.
Solution
a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
From address 300H ➔ 0 0 1 1 0 0 0 0 0 0 0 0
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to 3FFH.
Solution
3. Design the logic circuit.
a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0
From address 300H ➔ 0 0 1 1 0 0 0 0 0 0 0 0
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to 3FFH.
Solution
a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a8
a9
From address 300H ➔ 0 0 1 1 0 0 0 0 0 0 0 0 a10 CS
a11
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to 3FFH.
Solution
a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a8
a9
a11
An easy way of
designing
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to 3FFH.
Solution
a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a8
a9
a11
An easy way of
designing
Inside the CPU
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• PC (Program Counter)
• Instruction decoder
• ALU (Arithmetic Logic Unit)
• Registers
PC A
ALU B
CPU C
D
Instruction decoder registers
How computers work 0 31h
31
1 C4h A [17]
BA
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2 26h
VCC
3 81h A  [6]
EAh
AA+B
4
[7]A
5 0h
A0-An-1
5h
GND
6
D0-D7
7
WE
OE
CS
Logic circuit
Address bus
Data bus
Write
Control bus Read
ALU
CPU A
B
PC: 0 C
D I/O 16 I/O 17 I/O 18 I/O n
Inst. Dec. registers
How Instruction decoder works
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Opcode Operand Opcode Operand
Instruction
Instruction
Operation Code Meaning

000 Ax
0011 0001 0 31h
1100 0100 1 C4h A [17] 001 A  [x]
0010 0110 BA
2 26h 010 A  A – register (x)
1000 0001 3 81h A  [6]
1110 1010 4 EAh
AA+B 011 AA+x
0000 0000
[7]A
5 0h 100 A  A + register (x)
0000 0101 6 5h
7
101 AA–x
110 Register (xH)  Register (xL)
111 [x]  A
Von Neumann vs. Harvard architecture
Harvard architecture has separate data and
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instruction busses, allowing transfers to be

• Harvard architecture performed simultaneously on both busses.
Data bus Data bus

Code Data
Memory Address bus CPU Address bus Memory
Control bus Control bus
• Von Neumann architecture

A von Neumann architecture
Code Data has only one bus which is used
Memory Memory
for both data transfers and
Data bus instruction fetches, and
CPU
therefore data transfers and
Address bus instruction fetches must be
Control bus scheduled
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Introduction to AVR
Chapter 1

and embedded
systems
Topics
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• Microcontrollers vs. Microprocessors

• Most common microcontrollers
• AVR Features
• AVR members
General Purpose Microprocessors vs.
Microcontrollers BIHE university
• General Purpose Microprocessors

Data BUS
General Serial
IO
Purpose RAM ROM Timer COM
Port
Micro Port
processor Address BUS
Control BUS
• Microcontrollers
CPU RAM ROM
Serial
Timer I/O
Port
Most common microcontrollers
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• 8-bit microcontrollers
– AVR
– PIC
– HCS12
– 8051
• 32-bit microcontrollers
– ARM
– PIC32
AVR internal architecture
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RAM EEPROM Timers
PROGRAM
ROM
Program
Bus Bus
CPU
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
AVR internal architecture
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40 PIN DIP
(XCK/T0) PB0 1 40 PA0 (ADC0)
(T1) PB1 2 RAM 39 EEPROM
PA1 (ADC1) Timers
(INT2/AIN0) PB2 3 38 PA2 (ADC2)
(OC0/AIN1) PB3 4 MEGA32 37 PA3 (ADC3)
PROGRAM (SS) PB4 5 36 PA4 (ADC4)
ROM (MOSI) PB5 6 35 PA5 (ADC5)
(MISO) PB6 7 34 PA6 (ADC6)
Program (SCK) PB7 8 33 PA7 (ADC7)
RESET 9 32 AREF
Bus Bus
VCC 10 31 AGND
CPU GND 11 30 AVCC
XTAL2 12 29 PC7 (TOSC2)
XTAL1 13 28 PC6 (TOSC1)
(RXD) PD0 14 27 PC5 (TDI)
(TXD) PD1 15 26 PC4 (TDO)
(INT0) PD2 16 25 PC3 (TMS)
(INT1) PD3 17 24 PC2 (TCK)
(OC1B) PD4 18
Interrupt 23 PC1 (SDA)
Other
OSC (OC1A) PD5 19 22 Ports
PC0 (SCL)
(ICP) PD6 20 Unit 21 PD7 (OC2) Peripherals
I/O
PINS
AVR different groups
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• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
– e.g. ATmega8, ATmega32, ATmega128
• Tiny
– e.g. ATtiny13, ATtiny25
• Special Purpose AVR
– e.g. AT90PWM216,AT90USB1287
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• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
• Tiny
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• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
• Tiny
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• Classic AVR
– e.g. AT90S2313, AT90S4433
• Mega
• Tiny
Let’s get familiar with the AVR part numbers
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ATmega128
Atmel group
Flash =128K
ATtiny44 AT90S4433
Atmel
Tiny Flash =4K Atmel Classic
Flash =4K
group group
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Introduction to Assembly
Chapter 2

and embedded
systems
Topics
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• AVR’s CPU
– Its architecture
– Some simple programs
• Data Memory access
• Program memory RAM EEPROM Timers
• RISC architecture PROGRAM

Flash ROM
Program Data
Bus Bus
CPU
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
AVR’s CPU
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• AVR’s CPU
– ALU
– 32 General Purpose
R0
registers (R0 to R31) R1
ALU
– PC register R2
…
– Instruction decoder SREG: I T H S V N Z C
R15
CPU R16
R17
…
PC
R30
Instruction decoder
R31
Instruction Register
registers
Some simple instructions
1. Loading values into the general purpose registers
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LDI (Load Immediate)

• LDI Rd, k
– Its equivalent in high level languages:
Rd = k
• Example: R0
ALU R1
– LDI R16,53 R2
…
• R16 = 53 SREG: I T H S V N Z C
CPU
R15
– LDI R19,132 R16
R17
– LDI R23,0x27 PC
…
• R23 = 0x27 Instruction decoder
R30
R31
registers
2. Arithmetic calculation
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• There are some instructions for doing Arithmetic

and logic operations; such as:
ADD, SUB, MUL, AND, etc.
• ADD Rd,Rs
– Rd = Rd + Rs R0
ALU R1
– Example: R2
…
– ADD R25, R9 SREG: I T H S V N Z C
CPU
R15
• R25 = R25 + R9 R16
R17
– ADD R17,R30 PC
…
• R17 = R17 + R30 Instruction decoder
R30
R31
registers
A simple program
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• Write a program that calculates 19 + 95
R0
ALU R1
R2
…
SREG: I T H S V N Z C
CPU
R15
R16
R17
PC
…
R30
Instruction decoder
R31
registers
A simple program
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• Write a program that calculates 19 + 95
LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20
R0
ALU R1
R2
…
CPU
R15
R16
R17
PC
…
R30
Instruction decoder
R31
registers
A simple program
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• Write a program that calculates 19 + 95 + 5
A simple program
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LDI R16, 19 ;R16 = 19
LDI R20, 95 ;R20 = 95
LDI R21, 5 ;R21 = 5
ADD R16, R20 ;R16 = R16 + R20
ADD R16, R21 ;R16 = R16 + R21
A simple program
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LDI R16, 19 ;R16 = 19
LDI R20, 95 ;R20 = 95
LDI R21, 5 ;R21 = 5
ADD R16, R20 ;R16 = R16 + R20
ADD R16, R21 ;R16 = R16 + R21
LDI R16, 19 ;R16 = 19

LDI R20, 95 ;R20 = 95
ADD R16, R20 ;R16 = R16 + R20
LDI R20, 5 ;R20 = 5
ADD R16, R20 ;R16 = R16 + R20
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• SUB Rd,Rs
– Rd = Rd - Rs
• Example:
– SUB R25, R9
• R25 = R25 - R9 R0
ALU R1
– SUB R17,R30 R2
…
• R17 = R17 - R30 SREG: I T H S V N Z C
CPU
R15
R16
R17
PC
…
R30
Instruction decoder
R31
registers
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• INC Rd
– Rd = Rd + 1
• Example:
– INC R25
• R25 = R25 + 1 R0
ALU R1
R2
…
• DEC Rd SREG: I T H S V N Z C
CPU
R15
– Rd = Rd - 1 R16
R17
• Example: PC
…
R30
– DEC R23 Instruction decoder
R31
• R23 = R23 - 1 registers
Data Address Space
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General RAM EEPROM Timers

Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus
8 bit
Data Address
Space R0
R1
R2
$0000 Interrupt Other
$0001 General OSC Ports
Unit Peripherals
...
Purpose
...
Registers R31
$001F I/O Address I/O
$0020 TWBR $00 PINS
TWSR $01
Standard I/O
...
...
Registers
SPH $3E
$005F SREG $3F
$0060
General
purpose
...
RAM
(SRAM)
$FFFF
Data Address Space
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Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
Space R0
R1
R2
Unit Peripherals
...
Purpose
...
Registers R31
$0020 TWBR $00 PINS
TWSR $01
Standard I/O
...
...
Registers
SPH $3E
$005F SREG $3F
$0060
General
purpose
...
RAM
(SRAM)
AVR Tutorials - Working With I/O Registers (rjhcoding.com)

$FFFF
Address
I/O
$00
Mem.
$20
Name
TWBR
Address
I/O
$16
Data Address Space
Mem.
$36
Name
PINB
Address
I/O
$2B
Mem.
$4B
Name
OCR1AH
$01 $21 TWSR $17 $37 DDRB $2C $4C TCNT1L
$02 $22 TWAR $18 $38 PORTB $2D $4D TCNT1H BIHE university
$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B

$04 $24 ADCL $1A $3A DDRA $2F $4F TCCR1A
$05 $25 ADCH $1B $3B PORTA $30 $50 SFIOR
$06 $26 ADCSRA $1C $3C EECR OCDR
$07 $27 ADMUX $1D $3D EEDR $31 $51 General RAM EEPROM Timers
OSCCAL
$08 $28 ACSR $1E $3E EEARL $32 $52 Purpose
TCNT0
$1F $3F PROGRAM
EEARH
$09 $29 UBRRL $33 $53 Registers
TCCR0
$0A $2A UCSRB UBRRCROM $34 $54 MCUCSR
$20 $40
$0B $2B UCSRA UBRRH $35 $55 MCUCR
Program
$0C $2C UDR $21 $41 WDTCR $36 $56CPUTWCRData
$0D $2D SPCR $22 $42 ASSR Bus
$37 $57 SPMCRBus address bus
$0E $2E SPSR $23 $43 OCR2 $38 $58 TIFR data bus
control bus
$0F $2F SPDR $24 $44 TCNT2 $39 $59 TIMSK Data
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
$12 $32 PORTD $27R0 $47 ICR1H $3C $5C OCR0
Space
$13 $33 PINC $28R1 $48 OCR1BL $3D $5D SPL
$14
$0000 $34 DDRC $29R2 $49 OCR1BH $3E $5E SPH Interrupt Other
General
$0001 $35
$15 PORTC OSC Ports
$2A $4A OCR1AL $3E $5E SREG Unit Peripherals
...
Purpose
...
Registers R31
$0020 TWBR $00 PINS
TWSR $01
Standard I/O
LDS (Load direct from data space)
...
...
Registers
SPH $3E
$005F SREG
LDS Rd, addr ;Rd = [addr]
$3F
$0060
General
purpose
...
RAM
(SRAM) Example:
LDS R1, 0x60
$FFFF
Address
I/O
$00
Mem.
$20
Name
TWBR
Address
I/O
$16
Data Address Space
Mem.
$36
Name
PINB
Address
I/O
$2B
Mem.
$4B
Name
OCR1AH

OSCCAL
TCNT0
$1F $3F PROGRAM
EEARH
TCCR0
$20 $40
Program
control bus
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
Space
$14
General
$0001 $35
$15 PORTC OSC Ports
...
Purpose
...
Registers R31
$0020 TWBR $00 PINS
TWSR $01
Standard I/O
LDS
STS(Load
(Storedirect
directfrom dataspace)
to data space)
...
...
Registers
SPH $3E
$005F SREG
LDS
STS Rd, addr ;Rd = [addr]
$3F
$0060 addr,Rd ;[addr]=Rd
General
purpose
...
RAM
(SRAM) Example:
LDS
STS R1, 0x60
0x60,R15 ; [0x60] = R15
$FFFF
Address
I/O
$00
Mem.
$20
Name
TWBR
Address
I/O
$16
Data Address Space
Mem.
$36
Name
PINB
Address
I/O
$2B
Mem.
$4B
Name
OCR1AH

OSCCAL
TCNT0
$1F $3F PROGRAM
EEARH
TCCR0
$20 $40
Program
control bus
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
Space
$14
General
$0001 $35
$15 PORTC OSC Ports
...
Purpose
...
Registers R31
$0020 TWBR $00 PINS
TWSR $01
Standard I/O
LDS
STS
Example: Write a program (Load
(Store
that direct
55from
direct
stores data
to data
into space)
space)
location 0x80 of RAM.
...
...
Registers
SPH $3E
$005F SREG
LDS
STS Rd, addr ;Rd = [addr]
$3F
$0060 addr,Rd ;[addr]=Rd
General
purpose Solution:
...
RAM
(SRAM) LDI R20, 55 Example:
;R20 = 55
STS 0x80, R20 LDS
STS R1,
;[0x80] =0x60
0x60,R15 ; [0x60] = R15
R20 = 55
$FFFF
Address
I/O
$00
Mem.
$20
Name
TWBR
Address
I/O
$16
Data Address Space
Mem.
$36
Name
PINB
Address
I/O
$2B
Mem.
$4B
Name
OCR1AH

OSCCAL
TCNT0
$1F $3F PROGRAM
EEARH
TCCR0
$20 $40
Program
control bus
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
Space
$14
General
$0001 $35
$15 PORTC OSC Ports
...
Purpose
...
Registers R31
$0020 TWBR $00 PINS
TWSR $01
Standard I/O
Example: Write LDS
STS
Write aa program
program (Load
(Store
that direct
stores 55from
direct to
into data
data space)
space)
...
Example: that copies the contents of location 0x80

...
Registers
SPH $3E
$005F
$0060
of RAM $3F
SREG
into location 0x81.
LDS
STS Rd, addr ;[addr]=Rd
addr,Rd ;Rd = [addr]
General
purpose Solution:
...
RAM
(SRAM) Solution:
LDI R20, 55 Example:
;R20 = 55
STS
LDS 0x80, R20
R20, 0x80 LDS
STS R1,
;[0x80] =0x60
0x60,R15
;R20 R20 ; [0x60] = R15
= 55
= [0x80]
STS 0x81, R20 ;[0x81] = R20 = [0x80]
$FFFF
Address
I/O
$00
Mem.
$20
Name
TWBR
Address
I/O
$16
Data Address Space
Mem.
$36
Name
PINB
Address
I/O
$2B
Mem.
$4B
Name
OCR1AH

OSCCAL
TCNT0
$1F $3F PROGRAM
EEARH
TCCR0
$20 $40
Program
control bus
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
Space
$14
General
$0001 $35
$15 PORTC OSC Ports
...
Purpose
...
Registers R31
$0020 Example:
TWBR
TWSR
$00 Add contents of location 0x90 to contents
$01
PINS of location 0x95
Standard I/O and store the result in location
LDS 0x313.
(Load direct
Example: Write a STS
program (Store
that stores 55from
direct to
into data
data space)
space)
...
Example: Write a program that copies the contents of location 0x80

...
Registers
Solution:
SPH $3E
$005F
$0060
of RAM
SREG
into location 0x81.
$3F
LDS
General LDS R20, 0x90 ;R20 = [0x90]
purpose Solution:
...
RAM
(SRAM)
LDS R20,
Solution:
0x95 ;R20 =;R21
55 = [0x95]
ADD R20, R21
R20 LDS ;R20 = R20 + R21
STS
LDS 0x80,
R20, 0x80 STS R1,
;[0x80] =0x60
0x60,R15
;R20 R20 ; [0x60] = R15
= 55
= [0x80]
STS 0x313, R20 ;[0x313] = R20
STS 0x81, R20 ;[0x81] = R20 = [0x80]
$FFFF
Address
I/O
$00
Mem.
$20
Name
TWBR
Address
I/O
$16
Data Address Space
Mem.
$36
Name
PINB
Address
I/O
$2B
Mem.
$4B
Name
OCR1AH

OSCCAL
TCNT0
$1F $3F PROGRAM
EEARH
TCCR0
$20 $40
Program
control bus
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
Space
$14
General
$0001 $35
$15 PORTC OSC Ports
...
Purpose
...
Registers R31
$0020 Example:
TWBR
TWSR
$00 Add contents of location 0x90 to contents
$01
PINS of location 0x95
Standard I/O Example:
and store What doesinthe
the result following
location
LDS
STS (Load
(Store instruction
0x313.
direct from
direct to do?space)
data
data space)
Example: Write a program that stores 55 into location 0x80 of RAM.
...

...
Registers
Solution:
LDS R20,2
SPH $3E
$005F
$0060
of RAM
SREG
into location 0x81.
$3F
LDS
General LDS R20, 0x90 ;R20 = [0x90]
purpose Solution:
Answer:
...
RAM
(SRAM)
LDS R20,
Solution:
0x95 ;R20 =;R21
55 = [0x95]
It copies
ADD the contents
R20, R21 of R2 ;R20
into R20;
= R20as+ 2R21
is the address of R2.
LDS R20, 0x80 LDS
STS 0x80, R20 STS R1,
;[0x80] =0x60
0x60,R15
;R20 R20 = ; [0x60] = R15
55
= [0x80]
STS 0x313, R20 ;[0x313] = R20
STS 0x81, R20 ;[0x81] = R20 = [0x80]
$FFFF
Address
I/O
$00
Mem.
$20
Name
TWBR
Address
I/O
$16
Data Address Space
Mem.
$36
Name
PINB
Address
I/O
$2B
Mem.
$4B
Name
OCR1AH

OSCCAL
TCNT0
$1F $3F PROGRAM
EEARH
TCCR0
$20 $40
Program
control bus
$10 $30 PIND $25 $45 TCCR2 $3A $5A GIFR
$11 $31 DDRD 8 bit
$26 $46 ICR1L $3B $5B GICR
Bus
Data Address
Space
$14
General
$0001 $35
$15 PORTC OSC Ports
...
Purpose
...
Registers R31
$0020 Example:
TWBR
TWSR
$00 Add contents
$01
of location
Example: 0x90
Store to contents
0x53 into PINS of location
the SPH 0x95
register.
Standard I/O Example:
and store What doesinthe
the result following
location
The
LDS
STS (Load
(Store instruction
0x313.
address of SPH
direct do?space)
isdata
from
direct to 0x5E
data space)
Example: Write a program that stores 55 into location 0x80 of RAM.
...

...
Registers
Solution:
LDS R20,2
SPH $3E
$005F
$0060
of RAM
SREG
into location 0x81.
$3F
LDS
General LDS R20, 0x90 Solution: ;R20 = [0x90]
purpose Solution:
Answer:
...
RAM
(SRAM)
LDS R20,
Solution:
0x95 LDI =;R21
;R20 R20,= 0x53
55 [0x95] ;R20 = 0x53
It copies
ADD the contents
R20, R21 of
STSR2 ;R20
into R20;
0x5E,= R20
R20as+ 2R21
is the;SPH
address
= R20of R2.
LDS R20, 0x80 LDS
STS 0x80, R20 STS R1,
;[0x80] =0x60
0x60,R15
;R20 R20 = ; [0x60] = R15
55
= [0x80]
STS 0x313, R20 ;[0x313] = R20
STS 0x81, R20 ;[0x81] = R20 = [0x80]
$FFFF
Data Address Space
BIHE university

Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
Space R0
R1
R2
Unit Peripherals
...
Purpose
...
Registers R31
$0020 TWBR $00 PINS
TWSR $01
Standard I/O
...
...
Registers
SPH $3E
$005F SREG $3F
$0060
General
purpose
...
RAM
(SRAM)
$FFFF
Data Address Space
BIHE university

Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
Space R0
R1
R2
Unit Peripherals
IN (IN from IO location)
...
Purpose
...
Registers R31
TWBR $00 PINS
IN Rd,IOaddress ;Rd = [addr]
$0020
TWSR $01
Standard I/O
...
...
Registers
SPH $3E
$005F SREG $3F
$0060
General
purpose
Example:
...
RAM
(SRAM) IN R1, 0x3F ;R1 = SREG
IN R17,0x3E ;R17 = SPH
$FFFF
Data Address Space
BIHE university

Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
Space R0
R1
R2
Unit Peripherals
OUT (OUT
IN (IN toIO
from IOlocation)
location)
...
Purpose
...
Registers R31
TWBR $00 PINS
$0020
Standard I/O
TWSR $01
OUT IOAddr,Rd ;Rd
IN Rd,IOaddress ;[addr]=Rd
= [addr]
...
...
Registers
SPH $3E
$005F SREG $3F
$0060
General Example:
purpose
...
RAM
(SRAM) OUT 0x3F,R12
IN R1, ;SREG
0x3F ;R1 = R12
= SREG
OUT 0x3E,R15;R17
IN R17,0x3E ;SPH = R15
= SPH
$FFFF
Data Address Space
BIHE university

Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
Space R0
R1
R2
Unit Peripherals
OUT (OUT
IN (IN toIO
from IOlocation)
location)
...
Purpose
...
Registers R31
TWBR $00 PINS
$0020
Standard I/O
TWSR $01
OUT IOAddr,Rd
IN Rd,IOaddress
Using ;[addr]=Rd
Names of;Rd
IO = [addr]
registers
...
...
Registers
SPH $3E
$005F SREG $3F
$0060
General Example:
Example:
purpose
...
RAM
(SRAM)
OUTOUT
IN SPH,R12
0x3F,R12
R1, ;OUT
0x3F ;R1;SREG0x3E,R12
= R12
= SREG
IN R15,SREG ;IN R15,0x3F
OUT 0x3E,R15;R17
= SPH
$FFFF
Data Address Space
BIHE university

Purpose
PROGRAM
Registers
ROM
Program CPU Data

Bus Bus address bus
data bus
control bus
Data
8 bit Bus
Data Address
Space
Example:
R0
R1
R2
Write a program that adds the contents of the PINC IO
$0001 General register to the contents of
OSCPIND and stores the result
Unit
Ports in location 0x90
Peripherals
OUT
IN (IN(OUT toIO
from IOlocation)
location)
...
Purpose of the SRAM

...
Registers R31
TWBR
Solution:
$00
OUT IOAddr,Rd
PINS
;[addr]=Rd
IN Rd,IOaddress
Names of;Rd = [addr]
$0020
TWSR $01
Standard I/O Using IO registers
...
...
Registers IN R20,PINC ;R20 = PINC

SPH $3E
$005F SREG $3F
$0060
IN R21,PIND Example:
;R21 = PIND
General Example:
purpose
...
RAM ADD R20,R21 ;R20 SPH,R12

OUT = R20 + R21;OUT 0x3E,R12
(SRAM) OUT
IN R1,0x3F,R12
0x3F ;R1 ;SREG = R12
= SREG
STS 0x90,R20 ;[0x90]
IN = R20
R15,SREG ;IN R15,0x3F
OUT 0x3E,R15;R17
= SPH
$FFFF
Status Register (SREG)
BIHE university
Carry
Interrupt oVerflow Zero
Temporary Negative
Sign
Data Address
Half carry N+V Space
$0000
$0001 General
Purpose
...
Registers
R0 $001F IO Address
ALU R1 $0020 TWBR $00
TWSR $01
R2 Standard IO
...
...
Registers
…
SPH
SREG: I T H S V N Z C $005F SREG
$3E
$3F
CPU
R15 $0060
R16 General
R17 purpose
...
RAM
PC
…
(SRAM)
R30
Instruction decoder
R31
registers
$FFFF
BIHE university
Carry
Temporary Negative
Sign
Data Address
Example: Show the status of the C, H,$0000

and Z flags after the addition
$0001 General
of 0x38 and 0x2F in the following instructions:
Purpose
...
LDI R16, 0x38R0 0x38 Registers
;R16 = $001F
IO Address
ALU R1 TWBR $00
LDI R17, 0x2F ;R17 = $0020
0x2F TWSR $01
R2 Standard IO
ADD R16, R17 ;add R17 to Registers
R16
...
...
…
SPH
$3E
$3F
CPU
Solution: R15 1 $0060
R16
$38 0011 1000 General
R17 purpose
...
+ $2F 0010 1111 RAM
PC
…
$67 0110 0111 R16 (SRAM)

= 0x67
C = 0 decoder R30
because there is no carry beyond the D7 bit.
Instruction
H = 1 because there isR31
a carry from the D3 to the D4 bit.
Z = 0 because the R16 (the result) has a value other than 0 after the addition.
registers
$FFFF
BIHE university
Carry
Temporary Negative
Sign
Data Address
Example:
Example: Show
Show the
the status
status of
of the
the C,
C, H, and
and ZZ flags
H,$0000 flags after
after the
the addition
addition
$0001 General
of
of 0x9C 0x64 in the following instructions:
0x38 and 0x2F Purpose
...
LDI LDI R20,
R0 0x9C
R16, 0x38 0x38 Registers
;R16 = $001F
IO Address
ALU LDI R1 0x64
R21, TWBR $00
LDI R17, 0x2F ;R17 = $0020
0x2F TWSR $01
R2 Standard IO
ADD ADD
R16, R17R20, R21;add R17;add R21 to R20
to Registers
R16
...
...
…
SPH
$3E
$3F
CPU
Solution:
R16
$38
$9C 0011
1001 1000
1100 General
R17 purpose
...
+ +$64
$2F 0010 0100
0110 1111 RAM
PC
…
$67 1 0000
$100 01100000
0111 R16 (SRAM)
R20 == 00
0x67
C = 1 because there isR30
C = 0 decoder a carry beyond the D7 bit.
because there is no carry beyond the D7 bit.
Instruction
H = 1 because there is a carry from the D3 to the D4 bit.
H = 1 because there isR31a carry from the D3 to the D4 bit.
ZZ = 0 because the R16 (the result)
= 1
Instruction because
Register the R20 (the result) has
has aa value
value 0other
in it after
than 0the addition.
after the addition.
registers
$FFFF
BIHE university
Carry
Temporary Negative
Sign
Data Address
Example:
Example: Show
Example: Show the
Show the status
the status of
status of the
of the C,
the C, H,
C, H, and
and
H,$0000
and ZZ
Z flags
flags
flags after
after
after the
the
the addition
addition
subtraction of 0x23 from 0xA5 in the $0001 General
following instructions:
of
...
LDI
LDI LDI
R16, 0x38 R20, 0x9C
R20, 0xA5;R16 = 0x38 Registers
R0 $001F IO Address
ALU LDI
LDI R1 0x64
R21,
R21, 0x23 TWBR $00
LDI R17, 0x2F ;R17 = $0020
0x2F TWSR $01
R2 Standard IO
ADD SUB
ADD R20, R21
R16, R17R20, R21;add R17;add
;subtract
R21 toR21
to Registers
R16 R20from R20
...
...
…
SPH
$3E
$3F
CPU
Solution:
$A5 R16 0101
1010
$38
$9C 0011
1001 1000
1100 General
R17 purpose
...
+- +$64
$23
$2F 0010 0100
0110 0011
1111 RAM
PC
…
$82 1000
$67 1 0000
$100 0010
01100000
0111 R20 == 00
$82
R16 (SRAM)
R20 0x67
CC == 10 because
because there
R21 isisnot bigger
a carry
R30 than R20
beyond andbit.
the D7 there is no borrow from D8 bit.
C == 1
Instruction
Z= 00 decoder
because the
because there
R20is no carry beyond the D70 bit.
H H because
= 1 there
because is ahas
there
a value
carry
is fromother
R31
a
than
the D3 after
to the the subtraction.
D4 bit.
ZH = 0 because there is nocarry from
borrow the D4
from D3 to
to D3.
the D4 bit.
Z = 0 because the R16 (the result) has a value 0other
= 1 because
Instruction Register the R20 (the result)
registers
has a value in it after
than 0the addition.
after the addition.
$FFFF
BIHE university
Carry
Temporary Negative
Sign
Data Address
Example:
Example:
Example: Show
Example:Show
Show the
Showthe
the status
thestatus
status of
statusof
of the
ofthe
the C,
theC,
C, H,
C,H, and
andZZ
H,$0000
H, and
and flags
Zflags
Z after
flagsafter
flags the
afterthe
after theaddition
the addition
subtraction
subtraction of
of 0x23
0x73 from
from 0xA5
0x52 in the $0001 General
following instructions:
of
...
LDI
LDI LDILDI 0x38
R16, R20,
R20, 0xA5
R20, 0x9C
0x52;R16 = 0x38 Registers
R0 $001F IO Address
ALU LDI
LDI R1 0x64
R21,
LDI 0x2F
R21,
R21, 0x23
0x73 TWBR $00
LDI R17, ;R17 = $0020
0x2F TWSR $01
R2 Standard IO
ADD SUB
ADD
R16, R20,
SUB R17R20, R21
R20, R21 ;subtract
R21;add R17;add R21 toR21
;subtract
to Registers
R16 R20from
R21 from R20
R20
...
...
…
SPH
SREG: I T H S V N Z C $3E
Solution: $005F SREG $3F
CPU
Solution:
$52
$A5 0101
R16 0010
1010 0101
$38
$9C 0011
1001 1000
1100 General
- $23
$73 0111
R17 0011 purpose
...
+- +$64
$2F 0010 0100
0110 0011
1111 RAM
PC $DF 1101 1111 R20 = $DF
…
$82
$67
$100 1 1000
0110
0000 0010
0111
0000 R20
R16
R20 == 00
$82
0x67
(SRAM)
C = 1 because R21 is bigger than R20 and there is a borrow from D8 bit.
CC == 10 because
because there
R21 isisnot bigger
a carry
R30 than R20
beyond andbit.
the D7 there is no borrow from D8 bit.
Z
C == 00 decoder
because
because the R20
there is has a value
no carry otherthe
beyond than
D7zero after the subtraction.
Instruction
Z=
H =1 0 because
because the R20
there is ahas a value
carry fromother than
the D3 0 bit.
to theafter the subtraction.
D4 bit.
H = 1 because there isR31 a borrow
carry from
from D4D3
the toto
D3.
the D4 bit.
ZH = 0 because there is no borrow from D4 to D3.
= 1 because
registers
than 0the addition.
after the addition.
$FFFF
BIHE university
Carry
Temporary Negative
Sign
Data Address
Example:Show
Example:
Example:
Example: Showthe
Show
Show thestatus
the
the status of
status
status ofthe
of
of theC,
the
the C,H,
C,
C, H,$0000
H,
H, andZZ
and
and
and ZZflags
flagsafter
flags
flags afterthe
after
after theaddition
the
the addition
subtraction
subtraction
of
of 0x9C of
of 0x9C
0x23
0x73 from
from
from 0x9C
0xA5
0x52 in
in the
the following
$0001
following
0x64 in the following instructions:
0x38 and 0x2F instructions:
General
instructions:
Purpose
...
LDI LDILDI 0x38
LDI
R16, R20, 0x9C
R20,
R20, 0x9C
0xA5
R0 $001F IO Address
ALU LDI 0x2F
LDI
LDI R1 0x64
R21,
R21,
R21, 0x9C
0x23
0x73 TWBR $00
LDI R17, ;R17 = $0020
0x2F TWSR $01
R2 Standard IO
ADD SUB R17R20,
SUB
ADD
R16, R20, R21
R20, R21;add R17;add
R21 ;subtract
;subtract
R21 toR21
to Registers
R16 R21 from R20
R20from R20
...
...
…
SPH
Solution:
Solution:
$005F SREG $3F
CPU
Solution:
$52
$9C
$A5 0101
R16 0010
1001 1100
1010 1100
0101
$38
$9C 0011
1001 1000 General
- $23
$73 0111
R17 0011 purpose
+-- +$64
$9C 10010100
1100
...
$2F 0010
0110 0011
1111 RAM
PC $DF 1101 1111 R20 = $DF
…
$00
$82
$67
$100 1 0000
1000
0110
0000 0000
0010
0111
0000 R20
R20
R16
R20 == $00
= 00
$82
0x67
(SRAM)
CC===100because
C becausethere
because R21 is
R21 is not
isnot bigger
bigger
a carry
R30 than R20
than
beyond R20 andbit.
and
the D7 there is
there is no
no borrow
borrow from
from D8
D8 bit.
bit.
Z
C == 00 decoder
because
because the
thereR20
is has
no a value
carry otherthe
beyond than
Instruction
ZZ =
H == 1
01 because
because there
because the R20
the R20 iscarry
is ahaszero after
a value
from the D3
other
the than 0 bit.
subtraction.
D4 bit.
carry from
from D4D3
the toto
D3.
the D4 bit.
ZH
H =
= 00 because
because there
there is
is no
no borrow
borrow from
from D4
D4 to
to D3.
D3.
= 1 because
registers
than 0the addition.
after the addition.
$FFFF
BIHE university
Carry
Temporary Negative
Sign
Data Address
Example:Show
Example:
Example:
Example: Showthe
Show
Show thestatus
the
the status of
status
status ofthe
of
of theC,
the
the C,H,
C,
C, H,$0000
H,
H, andZZ
and
and
and ZZflags
flagsafter
flags
flags afterthe
after
after theaddition
the
the addition
subtraction
subtraction
of
of 0x9C of
of 0x9C
0x23
0x73 from
from
from 0x9C
0xA5
0x52 in
in the
the following
$0001
following
0x64 in the following instructions:
0x38 and 0x2F instructions:
General
instructions:
Purpose
...
LDI LDILDI 0x38
LDI
R16, R20, 0x9C
R20,
R20, 0x9C
0xA5
R0 $001F IO Address
ALU LDI 0x2F
LDI
LDI R1 0x64
R21,
R21,
R21, 0x9C
0x23
0x73 TWBR $00
LDI R17, ;R17 = $0020
0x2F TWSR $01
R2 Standard IO
ADD SUB R17R20,
SUB
ADD
R16, R20, R21
R20, R21;add R17;add
R21 ;subtract
;subtract
R21 toR21
to Registers
R16 R21 from R20
R20from R20
...
...
…
SPH
Solution:
Solution:
$005F SREG $3F
CPU
Solution:
$52
$9C
$A5 0101
R16 0010
1001 1100
1010 1100
0101
$38
$9C 0011
1001 1000 General
- $23
$73 0111
R17 0011 purpose
+-- +$64
$9C 10010100
1100
...
$2F 0010
0110 0011
1111 RAM
PC $DF 1101 1111 R20 = $DF
…
$00
$82
$67
$100 1 0000
1000
0110
0000 0000
0010
0111
0000 R20
R20
R16
R20 == $00
= 00
$82
0x67
(SRAM)
CC===100because
C becausethere
because R21 is
R21 is not
isnot bigger
bigger
a carry
R30 than R20
than
beyond R20 andbit.
and
the D7 there is
there is no
no borrow
borrow from
from D8
D8 bit.
bit.
Z
C == 00 decoder
because
because the
thereR20
is has
no a value
carry otherthe
beyond than
Instruction
ZZ =
H == 1
01 because
because there
because the R20
the R20 iscarry
is ahaszero after
a value
from the D3
other
the than 0 bit.
subtraction.
D4 bit.
carry from
from D4D3
the toto
D3.
the D4 bit.
ZH
H =
= 00 because
because there
there is
is no
no borrow
borrow from
from D4
D4 to
to D3.
D3.
= 1 because
registers
than 0the addition.
after the addition.
$FFFF
Assembler Directives
.EQU and .SET
BIHE university
• .EQU name = value

– Example:
.EQU COUNT = 0x25
LDI R21, COUNT ;R21 = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
• .SET name = value

– Example:
.SET COUNT = 0x25
LDI R22, COUNT + 3 ;R22 = 0x28
.SET COUNT = 0x19
.INCLUDE
BIHE university
• .INCLUDE “filename.ext”
.INCLUDE
BIHE university
• .INCLUDE “filename.ext”
M32def.inc
.equ SREG = 0x3f
.equ SPL = 0x3d
.equ SPH = 0x3e
....
.equ INT_VECTORS_SIZE = 42 ; size in words
Program.asm
.INCLUDE “M32DEF.INC”
LDI R20, 10
OUT SPL, R20
.ORG
BIHE university
• .ORG address
00 E205
01 0000
Program.asm 02 0000
.ORG 0 03 0000
LDI R16, 0x25 04 0000

.ORG 0x7
assembler 05 0000
LDI R17, 0x34 06 0000
LDI R18, 0x31 07 E314
08 E321
09 0000
0A 0000
Assembler
BIHE university
Assembly
EDITOR
PROGRAM assembler
myfile.asm
ASSEMBLER
PROGRAM Machine
Language
myfile.eep myfile.hex myfile.map myfile.lst myfile.obj
DOWNLOAD TO DOWNLOAD TO
AVR’s EEPROM AVR ’s FLASH
Flash memory and PC register
BIHE university
16-bit
RAM EEPROM Timers
PROGRAM
Flash ROM ALU
PC: Data
CPU Bus
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
BIHE university
16-bit
RAM EEPROM Timers
PROGRAM
Flash ROM ALU
PC: Data
16bit
16bit CPU Bus

Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
BIHE university
00 E205
01 E314
02 E321
03 0F01
04 0F02
0516-bit
E01B
06 0F01
07 9300
08 0300 RAM EEPROM Timers
09 940C
PROGRAM
0A
Flash0009
ROM ALU
PC: Data
16bit
16bit CPU Bus

Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
BIHE university
00 E205
E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
HERE:JMP HERE 07 9300
09 940C
PROGRAM
0A
Flash0009
ROM ALU
16bit
PC: 0 Data
16bit CPU Bus
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
BIHE university
00 E205
E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
09 940C
PROGRAM
0A
Flash0009
ROM ALU
16bit
PC: 0 Data
16bit CPU Bus
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
BIHE university
00 E205
E205
LDI R16, 0x25 01 E314
LDI R17, $34 02 E321
LDI R18, 0x31
03 0F01
ADD R16, R17
ADD R16, R18 04 0F02
LDI R17, 11 0516-bit
E01B
ADD R16, R17
06 0F01
STS SUM, R16
9300
08 0300
0300 RAM EEPROM Timers
09 940C
940C
PROGRAM
0A
Flash0009
0009
ROM ALU
16bit
PC: 3
0
1
5
2
4 Data
16bit CPU Bus
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
Fetch and execute
BIHE university
00 E205
• Old Architectures 01 E314
02 E321
Instruct 4
03 0F01
Instruct 3
04 0F02
Instruct 2
0516-bit
E01B
Instruct 1
06 0F01
07 9300
Fetch
09 940C
PROGRAM
0A
Flash0009
ROM ALU
PC: Data
CPU Bus
Execute
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
Pipelining
BIHE university
00 E205
• Pipelining 01 E314
02 E321
Instruct 4 03 0F01
Instruct 3 04 0F02
Instruct 2 0516-bit
E01B
Instruct 1 06 0F01
07 9300
Fetch 09 940C
PROGRAM
0A
Flash0009
ROM ALU
PC: Data
CPU Bus
Execute Program Instruction dec.
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
How to speed up the CPU
BIHE university
• Increase the clock frequency

– More frequency ➔ More power consumption &
more heat
– Limitations
• Change the architecture
– Pipelining
– RISC
Changing the architecture
RISC vs. CISC BIHE university
• CISC (Complex Instruction Set Computer)

– Put as many instruction as you can into the CPU
• RISC (Reduced Instruction Set Computer)
– Reduce the number of instructions, and use your
facilities in a more proper way.
RISC architecture
BIHE university
• Feature 1
– RISC processors have a fixed instruction size. It
makes the task of instruction decoder easier.
• In AVR the instructions are 2 or 4 bytes.
– In CISC processors instructions have different
lengths
• E.g. in 8051
– CLR C ; a 1-byte instruction
– ADD A, #20H ; a 2-byte instruction
– LJMP HERE ; a 3-byte instruction
RISC architecture
BIHE university
• Feature 2: reduce the number of instructions

– Pros: Reduces the number of used transistors
– Cons:
• Can make the assembly programming more difficult
• Can lead to using more memory
RISC architecture
BIHE university
• Feature 3: limit the addressing mode

– Advantage
• hardwiring
– Disadvantage
• Can make the assembly programming more difficult
RISC architecture
BIHE university
• Feature 4: Load/Store
LDS R20, 0x200
LDS R21, 0x220
ADD R20, R21
STS 0x230, R20
RAM EEPROM Timers
PROGRAM
Flash ROM ALU
PC: Data
CPU Bus
Instruction dec.
Program
Bus
Interrupt Other
OSC Ports
Unit Peripherals
I/O
PINS
RISC architecture
BIHE university
• Feature 5 (Harvard architecture): separate buses for

opcodes and operands
– Advantage: opcodes and operands can go in and out of the CPU
together.
– Disadvantage: leads to more cost in general purpose computers.

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus
RISC architecture
BIHE university
• Feature
LDS R20, 5 (Harvard
0x100 ; R20 = architecture):
[0x100] separate buses for
ADD R20, R21
opcodes and operands
ADD R20,R21 ; R20 = R20 + R21
LDS R20, 0x100
– Advantage: opcodes and operands can go in and out of the CPU
together.
– Disadvantage: leads to more cost in generalFetch
purpose computers.
Execute

Code Data
Memory Data bus CPU Data bus Memory
Address bus Address bus
RISC architecture
BIHE university
• Feature 6: more than 95% of instructions are

executed in 1 machine cycle
RISC architecture
BIHE university
• Feature 7
– RISC processors have at least 32 registers.
Decreases the need for stack and memory
usages.
• In AVR there are 32 general purpose registers (R0
to R31)

Lecture 07 AVR Module 1

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Lecture 07 AVR Module 1

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CSE234: Embedded System

The AVR microcontroller

• Internal organization of computers

• Everything that can store, retain, and recall

• Programmed by the IC manufacturer

• OTP (One-Time Programmable)

• Erased Electrically RDY/BSY

– Each byte can be erased separately A4

• Made of flip-flops (Transistors)

– No need for refreshing

• Made of SRAM, Battery, control circuitry

• Memory pin out

• CPU should have

CPU I/O 0 I/O 1 I/O 2 I/O n

How could we manage it? 2

The logic circuit

The logic circuit

The logic circuit

The logic circuit

The logic circuit

The logic circuit

The logic circuit

The logic circuit

• Design an address decoder for address of 300H

• Design an address decoder for address of 300H

• Design an address decoder for address of 300H

• Design an address decoder for address of 300H

• Design an address decoder for address of 300H

• Design an address decoder for address of 300H

• Design an address decoder for address of 300H

• Design an address decoder for address of 300H

Opcode Operand Opcode Operand

Operation Code Meaning

instruction busses, allowing transfers to be

Data bus Data bus

• Von Neumann architecture

The AVR microcontroller

• Microcontrollers vs. Microprocessors

• General Purpose Microprocessors

CPU RAM ROM

RAM EEPROM Timers

The AVR microcontroller

• RISC architecture PROGRAM

LDI (Load Immediate)

• There are some instructions for doing Arithmetic

• Write a program that calculates 19 + 95

• Write a program that calculates 19 + 95

LDI R16, 19 ;R16 = 19

• Write a program that calculates 19 + 95 + 5

• Write a program that calculates 19 + 95 + 5

• Write a program that calculates 19 + 95 + 5

LDI R16, 19 ;R16 = 19

General RAM EEPROM Timers

Program CPU Data

General RAM EEPROM Timers

Program CPU Data

AVR Tutorials - Working With I/O Registers (rjhcoding.com)

$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B

$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B

$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B

$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B

Example: that copies the contents of location 0x80

$03 $23 TWDR $19 $39 PINA $2E $4E TCCR1B

Example: Write a program that copies the contents of location 0x80