BSC105N15LS5

MOSFET
OptiMOSTM5Power-Transistor,150V SuperSO8

8 5
6
Features 7
6 7
8
5
•N-channel,logiclevel
•Verylowon-resistanceRDS(on)
•Superiorthermalresistance
•100%avalanchetested
•Pb-freeleadplating;RoHScompliant 1 4
3
•Halogen-freeaccordingtoIEC61249-2-21 2
3
2
1
4

Productvalidation
FullyqualifiedaccordingtoJEDECforIndustrialApplications
Drain
Pin 5-8
Table1KeyPerformanceParameters
Parameter Value Unit Gate *1

Pin 4
VDS 150 V
Source
RDS(on),max 10.5 mΩ *1: Internal body diode Pin 1-3

ID 76 A
Qoss 81 nC
QG(0V...10V) 34 nC

Type/OrderingCode Package Marking RelatedLinks

BSC105N15LS5 PG-TDSON-8 105N15LS -

Final Data Sheet 1 Rev.2.0,2023-12-13

 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

TableofContents
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Final Data Sheet 2 Rev.2.0,2023-12-13

 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

1Maximumratings
atTA=25°C,unlessotherwisespecified

Table2Maximumratings
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
- - 76 VGS=10V,TC=25°C
- - 48 VGS=10V,TC=100°C
Continuous drain current 1)
ID A
- - 41 VGS=4.5V,TC=100°C
- - 10.7 VGS=10V,TA=25°C,RthJA=50°C/W2)
Pulsed drain current3) ID,pulse - - 304 A TC=25°C
Avalanche energy, single pulse 4)
EAS - - 62 mJ ID=50A,RGS=25Ω
Gate source voltage VGS -20 - 20 V -
- - 125 TC=25°C
Power dissipation Ptot W
- - 2.5 TA=25°C,RTHJA=50°C/W2)
Operating and storage temperature Tj,Tstg -55 - 150 °C -

2Thermalcharacteristics

Table3Thermalcharacteristics
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Thermal resistance, junction - case,
RthJC - - 1.0 °C/W -
bottom
Thermal resistance, junction - case,
RthJC - - 20 °C/W -
top
Thermal resistance, junction - ambient,
RthJA - - 50 °C/W -
6 cm² cooling area2)

1)
Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature
as specified. For other case temperatures please refer to Diagram 2. De-rating will be required based on the actual
environmental conditions.
2)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
3)
See Diagram 3 for more detailed information
4)
See Diagram 13 for more detailed information
Final Data Sheet 3 Rev.2.0,2023-12-13
 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

3Electricalcharacteristics
atTj=25°C,unlessotherwisespecified

Table4Staticcharacteristics
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Drain-source breakdown voltage V(BR)DSS 150 - - V VGS=0V,ID=1mA
Gate threshold voltage VGS(th) 1.3 1.8 2.3 V VDS=VGS,ID=91µA
- 0.1 1.0 VDS=120V,VGS=0V,Tj=25°C
Zero gate voltage drain current IDSS µA
- 10 100 VDS=120V,VGS=0V,Tj=125°C
Gate-source leakage current IGSS - 10 100 nA VGS=20V,VDS=0V
- 8.8 10.5 VGS=10V,ID=40A
Drain-source on-state resistance RDS(on) mΩ
- 10.9 14 VGS=4.5V,ID=20A
Gate resistance RG - 0.9 1.35 Ω -
Transconductance gfs - 70 - S |VDS|≥2|ID|RDS(on)max,ID=40A

Table5Dynamiccharacteristics
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Input capacitance Ciss - 2300 3000 pF VGS=0V,VDS=75V,f=1MHz
Output capacitance1) Coss - 580 750 pF VGS=0V,VDS=75V,f=1MHz
Reverse transfer capacitance 1)
Crss - 17 30 pF VGS=0V,VDS=75V,f=1MHz
VDD=75V,VGS=10V,ID=40A,
Turn-on delay time td(on) - 6.4 - ns
RG,ext=1.6Ω
VDD=75V,VGS=10V,ID=40A,
Rise time tr - 2.3 - ns
RG,ext=1.6Ω
VDD=75V,VGS=10V,ID=40A,
Turn-off delay time td(off) - 17.8 - ns
RG,ext=1.6Ω
VDD=75V,VGS=10V,ID=40A,
Fall time tf - 3.4 - ns
RG,ext=1.6Ω

Table6Gatechargecharacteristics2)
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Gate to source charge Qgs - 7.5 - nC VDD=75V,ID=40A,VGS=0to4.5V
Gate charge at threshold Qg(th) - 4.1 - nC VDD=75V,ID=40A,VGS=0to4.5V
Gate to drain charge 1)
Qgd - 6.9 10.4 nC VDD=75V,ID=40A,VGS=0to4.5V
Switching charge Qsw - 10.3 - nC VDD=75V,ID=40A,VGS=0to4.5V
Gate charge total 1)
Qg - 18.1 23.0 nC VDD=75V,ID=40A,VGS=0to4.5V
Gate plateau voltage Vplateau - 3.3 - V VDD=75V,ID=40A,VGS=0to4.5V
Gate charge total1) Qg - 34 43 nC VDD=75V,ID=40A,VGS=0to10V
Output charge 1)
Qoss - 81 108 nC VDS=75V,VGS=0V

1)
Defined by design. Not subject to production test.
2)
See ″Gate charge waveforms″ for parameter definition
Final Data Sheet 4 Rev.2.0,2023-12-13
 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

Table7Reversediode
Values
Parameter Symbol Unit Note/TestCondition
Min. Typ. Max.
Diode continuous forward current IS - - 76 A TC=25°C
Diode pulse current IS,pulse - - 304 A TC=25°C
Diode forward voltage VSD - 0.83 1.2 V VGS=0V,IF=38A,Tj=25°C
Reverse recovery time 1)
trr - 24.3 48.6 ns VR=75V,IF=40A,diF/dt=100A/µs
Reverse recovery charge 1)
Qrr - 15.7 31.4 nC VR=75V,IF=40A,diF/dt=100A/µs

1)
Defined by design. Not subject to production test.
Final Data Sheet 5 Rev.2.0,2023-12-13
 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

4Electricalcharacteristicsdiagrams

Diagram1:Powerdissipation Diagram2:Draincurrent
140 80

70
120

60
100

50
80
Ptot[W]

ID[A]
40

60
30

40
20

20
10

0 0
0 25 50 75 100 125 150 0 25 50 75 100 125 150
TC[°C] TC[°C]
Ptot=f(TC) ID=f(TC);VGS≥10V

Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance
3
10 101
single pulse
1 µs 0.01
0.02
0.05
102 0.1
10 µs 0.2
100 0.5

100 µs
101
ZthJC[K/W]
ID[A]

1 ms 10-1

100

DC
10 ms
10-2
-1
10

10-2 10-3
100 101 102 103 10-6 10-5 10-4 10-3 10-2 10-1 100
VDS[V] tp[s]
ID=f(VDS);TC=25°C;D=0;parameter:tp ZthJC=f(tp);parameter:D=tp/T

Final Data Sheet 6 Rev.2.0,2023-12-13

 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance
320 28
10 V

280
24
3V 4V
240
20
5V
4.5 V
200
16 3.5 V

RDS(on)[mΩ]
ID[A]

160
4.5 V
12 5V
120

4V 10 V
8
80

3.5 V
4
40 3V

2.8 V
0 0
0 1 2 3 4 5 0 20 40 60 80 100 120 140 160
VDS[V] ID[A]
ID=f(VDS),Tj=25°C;parameter:VGS RDS(on)=f(ID),Tj=25°C;parameter:VGS

Diagram7:Typ.transfercharacteristics Diagram8:Typ.drain-sourceonresistance
240 28
25 °C

24
200

150 °C
20
160

150 °C
16
RDS(on)[mΩ]
ID[A]

120

12

80
8
25 °C

40
4

0 0
0 1 2 3 4 5 0 2 4 6 8 10 12 14 16
VGS[V] VGS[V]
ID=f(VGS),|VDS|>2|ID|RDS(on)max;parameter:Tj RDS(on)=f(VGS),ID=40A;parameter:Tj

Final Data Sheet 7 Rev.2.0,2023-12-13

 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

Diagram9:Normalizeddrain-sourceonresistance Diagram10:Typ.gatethresholdvoltage
2.4 2.4

2.0 2.0
RDS(on)(normalizedto25°C)

1.6 1.6

VGS(th)[V]
910 µA
1.2 1.2

91 µA
0.8 0.8

0.4 0.4

0.0 0.0
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
Tj[°C] Tj[°C]
RDS(on)=f(Tj),ID=40A,VGS=10V VGS(th=f(Tj),VGS=VDS;parameter:ID

Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode
4
10 103
25 °C
25 °C, max
150 °C
150 °C, max

Ciss
103

102

Coss
C[pF]

IF[A]

2
10

101

101
Crss

100 100
0 25 50 75 100 125 150 0.0 0.5 1.0 1.5 2.0 2.5
VDS[V] VSD[V]
C=f(VDS);VGS=0V;f=1MHz IF=f(VSD);parameter:Tj

Final Data Sheet 8 Rev.2.0,2023-12-13

 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge
2
10 10
30 V
75 V
120 V

101

6
25 °C

VGS[V]
IAV[A]

100 °C
125 °C
4
0
10

10-1 0
10-1 100 101 102 103 0 5 10 15 20 25 30 35 40
tAV[µs] Qgate[nC]
IAS=f(tAV);RGS=25Ω;parameter:Tj,start VGS=f(Qgate),ID=40Apulsed,Tj=25°C;parameter:VDD

Diagram15:Min.drain-sourcebreakdownvoltage Diagram Gate charge waveforms

160

158

156

154
VBR(DSS)[V]

152

150

148

146

144
-75 -50 -25 0 25 50 75 100 125 150 175
Tj[°C]
VBR(DSS)=f(Tj);ID=1mA

Final Data Sheet 9 Rev.2.0,2023-12-13

 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

5PackageOutlines

DOCUMENT NO.
Z8B00003332
REVISION
08
MILLIMETERS
DIMENSION
MIN. MAX. SCALE 10:1
A 0.90 1.20
A1 0.15 0.35 0 1 2 3mm
b 0.34 0.54
D 4.80 5.35
D1 3.90 4.40
EUROPEAN PROJECTION
D2 0.00 0.22
E 5.70 6.10
E1 5.90 6.42
E2 3.88 4.31
e 1.27
L 0.45 0.71 ISSUE DATE
M 0.45 0.69 05.11.2019

Figure1OutlinePG-TDSON-8,dimensionsinmm

Final Data Sheet 10 Rev.2.0,2023-12-13

 OptiMOSTM5Power-Transistor,150V
BSC105N15LS5

PG-TDSON-8: RecommenGHd BoDrdpads & Apertures

1.905 1.905

1.27 0.6 1.27 0.5

3x 0.8
3x

0.75
3.325

0.2
2.9
4.455

1.5
2.863

2.863
1.6

0.875

0.825
0.2 1.5
0.925

1.27 0.5 1.27 0.4

3x 3x
1.905 1.905

copper solder mask stencil apertures all dimensions in mm

Figure 2 Outline Boardpads (TDSON-8), dimensions in mm

Final Data Sheet 11 Rev.2.0,2023-12-13

 OptiMOS TM5 Power-Transistor , 150 V
BSC105N15LS5

Revision History
BSC105N15LS5

Revision: 2023-12-13, Rev. 2.0

Previous Revision
Revision Date Subjects (major changes since last revision)
2.0 2023-12-13 Release of final version

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Final Data Sheet 12 Rev. 2.0, 2023-12-13

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